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debug EQM...
pellion -
r570:0b1aedcd4196 JC
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1 LIBRARY IEEE;
2 USE IEEE.STD_LOGIC_1164.ALL;
3 USE IEEE.NUMERIC_STD.ALL;
4
5 ENTITY fine_time_max_value_gen IS
6
7 PORT (
8 clk : IN STD_LOGIC;
9 rstn : IN STD_LOGIC;
10 tick : IN STD_LOGIC;
11 fine_time_add : IN STD_LOGIC;
12 fine_time_max_value : OUT STD_LOGIC_VECTOR(8 DOWNTO 0)
13 );
14
15 END fine_time_max_value_gen;
16
17 ARCHITECTURE beh OF fine_time_max_value_gen IS
18
19 SIGNAL count_even : STD_LOGIC;
20 SIGNAL count_first : STD_LOGIC;
21 SIGNAL count_modulo_33 : STD_LOGIC;
22
23
24 SIGNAL count_33 : INTEGER range 0 TO 32;
25
26 BEGIN -- beh
27
28 fine_time_max_value <= STD_LOGIC_VECTOR(to_unsigned(381,9)) WHEN count_first = '1' ELSE
29 STD_LOGIC_VECTOR(to_unsigned(380,9)) WHEN count_even = count_modulo_33 ELSE
30 STD_LOGIC_VECTOR(to_unsigned(381,9)) WHEN count_even = '1' ELSE
31 STD_LOGIC_VECTOR(to_unsigned(379,9)) WHEN count_modulo_33 = '1' ELSE
32 STD_LOGIC_VECTOR(to_unsigned(380,9));
33
34
35
36 PROCESS (clk, rstn)
37 BEGIN -- PROCESS
38 IF rstn = '0' THEN -- asynchronous reset (active low)
39 count_first <= '1';
40 count_even <= '0';
41 count_modulo_33 <= '0';
42 count_33 <= 0;
43 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
44 IF tick = '1' THEN
45 count_even <= '0';
46 count_first <= '1';
47 count_modulo_33 <= '0';
48 count_33 <= 0;
49 ELSE
50 IF fine_time_add = '1' THEN
51 count_first <= '0';
52 IF count_even = '1' THEN
53 count_even <= '0';
54 ELSE
55 count_even <= '1';
56 END IF;
57 IF count_33 = 31 THEN
58 count_modulo_33 <= '1';
59 ELSE
60 count_modulo_33 <= '0';
61 END IF;
62
63 IF count_33 = 32 THEN
64 count_33 <= 0;
65 ELSE
66 count_33 <= count_33 + 1;
67 END IF;
68 END IF;
69 END IF;
70 END IF;
71 END PROCESS;
72
73 END beh;
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@@ -1,38 +1,41
1 # use glob syntax.
1 # use glob syntax.
2 syntax: glob
2 syntax: glob
3
3
4 *.tex
4 *.tex
5 *.html
5 *.html
6 *log*
6 *log*
7 *.png
7 *.png
8 *.dot
8 *.dot
9 *.css
9 *.css
10 *.md5
10 *.md5
11 *.eps
11 *.eps
12 *.pdf
12 *.pdf
13 *.toc
13 *.toc
14 *.map
14 *.map
15 *.sty
15 *.sty
16 *.3
16 *.3
17 *.js
17 *.js
18 *.aux
18 *.aux
19 *.idx
19 *.idx
20 *doc*
20 *doc*
21 *Doc*
21 *Doc*
22 *vhdlsyn.txt
22 *vhdlsyn.txt
23 *dirs.txt
23 *dirs.txt
24 *.orig
24 *.orig
25 *.o
25 *.o
26 *.a
26 *.a
27 *.bin
27 *.bin
28 *~
28 *~
29 apb_devices_list.h
29 apb_devices_list.h
30 apb_devices_list.vhd
30 apb_devices_list.vhd
31 twiddle.vhd
31 twiddle.vhd
32 primitives.vhd
32 primitives.vhd
33 fftSm.vhd
33 fftSm.vhd
34 fftDp.vhd
34 fftDp.vhd
35 fft_components.vhd
35 fft_components.vhd
36 CoreFFT.vhd
36 CoreFFT.vhd
37 actram.vhd
37 actram.vhd
38 actar.vhd No newline at end of file
38 actar.vhd
39 *.bak
40 *.pdc.ce
41 *.zip
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@@ -1,124 +1,124
1 #set_io clk49_152MHz -pinname D5 -fixed yes -DIRECTION Inout
1 #set_io clk49_152MHz -pinname D5 -fixed yes -DIRECTION Inout
2 set_io clk50MHz -pinname B3 -fixed yes -DIRECTION Inout
2 set_io clk50MHz -pinname B3 -fixed yes -DIRECTION Inout
3 set_io reset -pinname R4 -fixed yes -DIRECTION Inout
3 set_io reset -pinname R4 -fixed yes -DIRECTION Inout
4
4
5 set_io {address[0]} -pinname U3 -fixed yes -DIRECTION Inout
5 set_io {address[0]} -pinname U3 -fixed yes -DIRECTION Inout
6 set_io {address[1]} -pinname V14 -fixed yes -DIRECTION Inout
6 set_io {address[1]} -pinname V14 -fixed yes -DIRECTION Inout
7 set_io {address[2]} -pinname V13 -fixed yes -DIRECTION Inout
7 set_io {address[2]} -pinname V13 -fixed yes -DIRECTION Inout
8 set_io {address[3]} -pinname V16 -fixed yes -DIRECTION Inout
8 set_io {address[3]} -pinname V16 -fixed yes -DIRECTION Inout
9 set_io {address[4]} -pinname N9 -fixed yes -DIRECTION Inout
9 set_io {address[4]} -pinname N9 -fixed yes -DIRECTION Inout
10 set_io {address[5]} -pinname T11 -fixed yes -DIRECTION Inout
10 set_io {address[5]} -pinname T11 -fixed yes -DIRECTION Inout
11 set_io {address[6]} -pinname U13 -fixed yes -DIRECTION Inout
11 set_io {address[6]} -pinname U13 -fixed yes -DIRECTION Inout
12 set_io {address[7]} -pinname R5 -fixed yes -DIRECTION Inout
12 set_io {address[7]} -pinname R5 -fixed yes -DIRECTION Inout
13 set_io {address[8]} -pinname U2 -fixed yes -DIRECTION Inout
13 set_io {address[8]} -pinname U2 -fixed yes -DIRECTION Inout
14 set_io {address[9]} -pinname N11 -fixed yes -DIRECTION Inout
14 set_io {address[9]} -pinname N11 -fixed yes -DIRECTION Inout
15 set_io {address[10]} -pinname R13 -fixed yes -DIRECTION Inout
15 set_io {address[10]} -pinname R13 -fixed yes -DIRECTION Inout
16 set_io {address[11]} -pinname R12 -fixed yes -DIRECTION Inout
16 set_io {address[11]} -pinname R12 -fixed yes -DIRECTION Inout
17 set_io {address[12]} -pinname M15 -fixed yes -DIRECTION Inout
17 set_io {address[12]} -pinname M15 -fixed yes -DIRECTION Inout
18 set_io {address[13]} -pinname T12 -fixed yes -DIRECTION Inout
18 set_io {address[13]} -pinname T12 -fixed yes -DIRECTION Inout
19 set_io {address[14]} -pinname M13 -fixed yes -DIRECTION Inout
19 set_io {address[14]} -pinname M13 -fixed yes -DIRECTION Inout
20 set_io {address[15]} -pinname T13 -fixed yes -DIRECTION Inout
20 set_io {address[15]} -pinname T13 -fixed yes -DIRECTION Inout
21 set_io {address[16]} -pinname L13 -fixed yes -DIRECTION Inout
21 set_io {address[16]} -pinname L13 -fixed yes -DIRECTION Inout
22 set_io {address[17]} -pinname V17 -fixed yes -DIRECTION Inout
22 set_io {address[17]} -pinname V17 -fixed yes -DIRECTION Inout
23 set_io {address[18]} -pinname V15 -fixed yes -DIRECTION Inout
23 set_io {address[18]} -pinname V15 -fixed yes -DIRECTION Inout
24
24
25 set_io {data[0]} -pinname V4 -fixed yes -DIRECTION Inout
25 set_io {data[0]} -pinname V4 -fixed yes -DIRECTION Inout
26 set_io {data[1]} -pinname V3 -fixed yes -DIRECTION Inout
26 set_io {data[1]} -pinname V3 -fixed yes -DIRECTION Inout
27 set_io {data[2]} -pinname V2 -fixed yes -DIRECTION Inout
27 set_io {data[2]} -pinname V2 -fixed yes -DIRECTION Inout
28 set_io {data[3]} -pinname T3 -fixed yes -DIRECTION Inout
28 set_io {data[3]} -pinname T3 -fixed yes -DIRECTION Inout
29 set_io {data[4]} -pinname N6 -fixed yes -DIRECTION Inout
29 set_io {data[4]} -pinname N6 -fixed yes -DIRECTION Inout
30 set_io {data[5]} -pinname P6 -fixed yes -DIRECTION Inout
30 set_io {data[5]} -pinname P6 -fixed yes -DIRECTION Inout
31 set_io {data[6]} -pinname R6 -fixed yes -DIRECTION Inout
31 set_io {data[6]} -pinname R6 -fixed yes -DIRECTION Inout
32 set_io {data[7]} -pinname T4 -fixed yes -DIRECTION Inout
32 set_io {data[7]} -pinname T4 -fixed yes -DIRECTION Inout
33 set_io {data[8]} -pinname T1 -fixed yes -DIRECTION Inout
33 set_io {data[8]} -pinname T1 -fixed yes -DIRECTION Inout
34 set_io {data[9]} -pinname R1 -fixed yes -DIRECTION Inout
34 set_io {data[9]} -pinname R1 -fixed yes -DIRECTION Inout
35 set_io {data[10]} -pinname P1 -fixed yes -DIRECTION Inout
35 set_io {data[10]} -pinname P1 -fixed yes -DIRECTION Inout
36 set_io {data[11]} -pinname N2 -fixed yes -DIRECTION Inout
36 set_io {data[11]} -pinname N2 -fixed yes -DIRECTION Inout
37 set_io {data[12]} -pinname R3 -fixed yes -DIRECTION Inout
37 set_io {data[12]} -pinname R3 -fixed yes -DIRECTION Inout
38 set_io {data[13]} -pinname P4 -fixed yes -DIRECTION Inout
38 set_io {data[13]} -pinname P4 -fixed yes -DIRECTION Inout
39 set_io {data[14]} -pinname N4 -fixed yes -DIRECTION Inout
39 set_io {data[14]} -pinname N4 -fixed yes -DIRECTION Inout
40 set_io {data[15]} -pinname N3 -fixed yes -DIRECTION Inout
40 set_io {data[15]} -pinname N3 -fixed yes -DIRECTION Inout
41 set_io {data[16]} -pinname G12 -fixed yes -DIRECTION Inout
41 set_io {data[16]} -pinname G12 -fixed yes -DIRECTION Inout
42 set_io {data[17]} -pinname G15 -fixed yes -DIRECTION Inout
42 set_io {data[17]} -pinname G15 -fixed yes -DIRECTION Inout
43 set_io {data[18]} -pinname H15 -fixed yes -DIRECTION Inout
43 set_io {data[18]} -pinname H15 -fixed yes -DIRECTION Inout
44 set_io {data[19]} -pinname F17 -fixed yes -DIRECTION Inout
44 set_io {data[19]} -pinname F17 -fixed yes -DIRECTION Inout
45 set_io {data[20]} -pinname F18 -fixed yes -DIRECTION Inout
45 set_io {data[20]} -pinname F18 -fixed yes -DIRECTION Inout
46 set_io {data[21]} -pinname G17 -fixed yes -DIRECTION Inout
46 set_io {data[21]} -pinname G17 -fixed yes -DIRECTION Inout
47 set_io {data[22]} -pinname H18 -fixed yes -DIRECTION Inout
47 set_io {data[22]} -pinname H18 -fixed yes -DIRECTION Inout
48 set_io {data[23]} -pinname J18 -fixed yes -DIRECTION Inout
48 set_io {data[23]} -pinname J18 -fixed yes -DIRECTION Inout
49 set_io {data[24]} -pinname R18 -fixed yes -DIRECTION Inout
49 set_io {data[24]} -pinname R18 -fixed yes -DIRECTION Inout
50 set_io {data[25]} -pinname N18 -fixed yes -DIRECTION Inout
50 set_io {data[25]} -pinname N18 -fixed yes -DIRECTION Inout
51 set_io {data[26]} -pinname P17 -fixed yes -DIRECTION Inout
51 set_io {data[26]} -pinname P17 -fixed yes -DIRECTION Inout
52 set_io {data[27]} -pinname N17 -fixed yes -DIRECTION Inout
52 set_io {data[27]} -pinname N17 -fixed yes -DIRECTION Inout
53 set_io {data[28]} -pinname T18 -fixed yes -DIRECTION Inout
53 set_io {data[28]} -pinname T18 -fixed yes -DIRECTION Inout
54 set_io {data[29]} -pinname M17 -fixed yes -DIRECTION Inout
54 set_io {data[29]} -pinname M17 -fixed yes -DIRECTION Inout
55 set_io {data[30]} -pinname U18 -fixed yes -DIRECTION Inout
55 set_io {data[30]} -pinname U18 -fixed yes -DIRECTION Inout
56 set_io {data[31]} -pinname L18 -fixed yes -DIRECTION Inout
56 set_io {data[31]} -pinname L18 -fixed yes -DIRECTION Inout
57
57
58 set_io nSRAM_MBE -pinname E4 -fixed yes -DIRECTION Inout
58 set_io nSRAM_MBE -pinname E4 -fixed yes -DIRECTION Inout
59 set_io nSRAM_E1 -pinname D1 -fixed yes -DIRECTION Inout
59 set_io nSRAM_E1 -pinname D1 -fixed yes -DIRECTION Inout
60 set_io nSRAM_E2 -pinname C1 -fixed yes -DIRECTION Inout
60 set_io nSRAM_E2 -pinname C1 -fixed yes -DIRECTION Inout
61 #set_io nSRAM_SCRUB -pinname C2 -fixed yes -DIRECTION Inout
61 #set_io nSRAM_SCRUB -pinname C2 -fixed yes -DIRECTION Inout
62 set_io nSRAM_W -pinname D4 -fixed yes -DIRECTION Inout
62 set_io nSRAM_W -pinname D4 -fixed yes -DIRECTION Inout
63 set_io nSRAM_G -pinname E1 -fixed yes -DIRECTION Inout
63 set_io nSRAM_G -pinname E1 -fixed yes -DIRECTION Inout
64 set_io nSRAM_BUSY -pinname F4 -fixed yes -DIRECTION Inout
64 set_io nSRAM_BUSY -pinname F4 -fixed yes -DIRECTION Inout
65
65
66 set_io spw1_en -pinname G4 -fixed yes -DIRECTION Inout
66 set_io spw1_en -pinname G4 -fixed yes -DIRECTION Inout
67 set_io spw1_din -pinname D13 -fixed yes -DIRECTION Inout
67 set_io spw1_din -pinname D13 -fixed yes -DIRECTION Inout
68 set_io spw1_sin -pinname D14 -fixed yes -DIRECTION Inout
68 set_io spw1_sin -pinname D14 -fixed yes -DIRECTION Inout
69 set_io spw1_dout -pinname C16 -fixed yes -DIRECTION Inout
69 set_io spw1_dout -pinname C16 -fixed yes -DIRECTION Inout
70 set_io spw1_sout -pinname C4 -fixed yes -DIRECTION Inout
70 set_io spw1_sout -pinname C4 -fixed yes -DIRECTION Inout
71
71
72 set_io spw2_en -pinname G3 -fixed yes -DIRECTION Inout
72 set_io spw2_en -pinname G3 -fixed yes -DIRECTION Inout
73 set_io spw2_din -pinname E6 -fixed yes -DIRECTION Inout
73 set_io spw2_din -pinname E6 -fixed yes -DIRECTION Inout
74 set_io spw2_sin -pinname C15 -fixed yes -DIRECTION Inout
74 set_io spw2_sin -pinname C15 -fixed yes -DIRECTION Inout
75 set_io spw2_dout -pinname B7 -fixed yes -DIRECTION Inout
75 set_io spw2_dout -pinname B7 -fixed yes -DIRECTION Inout
76 set_io spw2_sout -pinname D7 -fixed yes -DIRECTION Inout
76 set_io spw2_sout -pinname D7 -fixed yes -DIRECTION Inout
77
77
78 set_io TAG1 -pinname J12 -fixed yes -DIRECTION Inout
78 set_io TAG1 -pinname J12 -fixed yes -DIRECTION Inout
79 set_io TAG2 -pinname K12 -fixed yes -DIRECTION Inout
79 set_io TAG2 -pinname K12 -fixed yes -DIRECTION Inout
80 set_io TAG3 -pinname K13 -fixed yes -DIRECTION Inout
80 set_io TAG3 -pinname K13 -fixed yes -DIRECTION Inout
81 set_io TAG4 -pinname L16 -fixed yes -DIRECTION Inout
81 set_io TAG4 -pinname L16 -fixed yes -DIRECTION Inout
82 #set_io TAG5 -pinname L15 -fixed yes -DIRECTION Inout
82 #set_io TAG5 -pinname L15 -fixed yes -DIRECTION Inout
83 #set_io TAG6 -pinname M16 -fixed yes -DIRECTION Inout
83 set_io TAG6 -pinname M16 -fixed yes -DIRECTION Inout
84 #set_io TAG7 -pinname J14 -fixed yes -DIRECTION Inout
84 set_io TAG7 -pinname J14 -fixed yes -DIRECTION Inout
85 set_io TAG8 -pinname K15 -fixed yes -DIRECTION Inout
85 set_io TAG8 -pinname K15 -fixed yes -DIRECTION Inout
86 #set_io TAG9 -pinname J17 -fixed yes -DIRECTION Inout
86 #set_io TAG9 -pinname J17 -fixed yes -DIRECTION Inout
87
87
88 set_io bias_fail_sw -pinname A3 -fixed yes -DIRECTION Inout
88 set_io bias_fail_sw -pinname A3 -fixed yes -DIRECTION Inout
89
89
90 set_io {ADC_OEB_bar_CH[0]} -pinname A10 -fixed yes -DIRECTION Inout
90 set_io {ADC_OEB_bar_CH[0]} -pinname A10 -fixed yes -DIRECTION Inout
91 set_io {ADC_OEB_bar_CH[1]} -pinname B10 -fixed yes -DIRECTION Inout
91 set_io {ADC_OEB_bar_CH[1]} -pinname B10 -fixed yes -DIRECTION Inout
92 set_io {ADC_OEB_bar_CH[2]} -pinname B12 -fixed yes -DIRECTION Inout
92 set_io {ADC_OEB_bar_CH[2]} -pinname B12 -fixed yes -DIRECTION Inout
93 set_io {ADC_OEB_bar_CH[3]} -pinname A11 -fixed yes -DIRECTION Inout
93 set_io {ADC_OEB_bar_CH[3]} -pinname A11 -fixed yes -DIRECTION Inout
94 set_io {ADC_OEB_bar_CH[4]} -pinname B13 -fixed yes -DIRECTION Inout
94 set_io {ADC_OEB_bar_CH[4]} -pinname B13 -fixed yes -DIRECTION Inout
95 set_io {ADC_OEB_bar_CH[5]} -pinname C6 -fixed yes -DIRECTION Inout
95 set_io {ADC_OEB_bar_CH[5]} -pinname C6 -fixed yes -DIRECTION Inout
96 set_io {ADC_OEB_bar_CH[6]} -pinname A13 -fixed yes -DIRECTION Inout
96 set_io {ADC_OEB_bar_CH[6]} -pinname A13 -fixed yes -DIRECTION Inout
97 set_io {ADC_OEB_bar_CH[7]} -pinname A14 -fixed yes -DIRECTION Inout
97 set_io {ADC_OEB_bar_CH[7]} -pinname A14 -fixed yes -DIRECTION Inout
98
98
99 set_io ADC_smpclk -pinname A15 -fixed yes -DIRECTION Inout
99 set_io ADC_smpclk -pinname A15 -fixed yes -DIRECTION Inout
100
100
101 set_io HK_smpclk -pinname R11 -fixed yes -DIRECTION Inout
101 set_io HK_smpclk -pinname R11 -fixed yes -DIRECTION Inout
102 set_io ADC_OEB_bar_HK -pinname D6 -fixed yes -DIRECTION Inout
102 set_io ADC_OEB_bar_HK -pinname D6 -fixed yes -DIRECTION Inout
103 set_io {HK_SEL[0]} -pinname C3 -fixed yes -DIRECTION Inout
103 set_io {HK_SEL[0]} -pinname C3 -fixed yes -DIRECTION Inout
104 set_io {HK_SEL[1]} -pinname A2 -fixed yes -DIRECTION Inout
104 set_io {HK_SEL[1]} -pinname A2 -fixed yes -DIRECTION Inout
105
105
106 #set_io {ADC_data[0]} -pinname G13 -fixed yes -DIRECTION Inout
106 #set_io {ADC_data[0]} -pinname G13 -fixed yes -DIRECTION Inout
107 #set_io {ADC_data[1]} -pinname G16 -fixed yes -DIRECTION Inout
107 #set_io {ADC_data[1]} -pinname G16 -fixed yes -DIRECTION Inout
108 #set_io {ADC_data[2]} -pinname F16 -fixed yes -DIRECTION Inout
108 #set_io {ADC_data[2]} -pinname F16 -fixed yes -DIRECTION Inout
109 #set_io {ADC_data[3]} -pinname E15 -fixed yes -DIRECTION Inout
109 #set_io {ADC_data[3]} -pinname E15 -fixed yes -DIRECTION Inout
110 #set_io {ADC_data[4]} -pinname F13 -fixed yes -DIRECTION Inout
110 #set_io {ADC_data[4]} -pinname F13 -fixed yes -DIRECTION Inout
111 #set_io {ADC_data[5]} -pinname F15 -fixed yes -DIRECTION Inout
111 #set_io {ADC_data[5]} -pinname F15 -fixed yes -DIRECTION Inout
112 #set_io {ADC_data[6]} -pinname D16 -fixed yes -DIRECTION Inout
112 #set_io {ADC_data[6]} -pinname D16 -fixed yes -DIRECTION Inout
113 #set_io {ADC_data[7]} -pinname D15 -fixed yes -DIRECTION Inout
113 #set_io {ADC_data[7]} -pinname D15 -fixed yes -DIRECTION Inout
114 #set_io {ADC_data[8]} -pinname B17 -fixed yes -DIRECTION Inout
114 #set_io {ADC_data[8]} -pinname B17 -fixed yes -DIRECTION Inout
115 #set_io {ADC_data[9]} -pinname A17 -fixed yes -DIRECTION Inout
115 #set_io {ADC_data[9]} -pinname A17 -fixed yes -DIRECTION Inout
116 #set_io {ADC_data[10]} -pinname A16 -fixed yes -DIRECTION Inout
116 #set_io {ADC_data[10]} -pinname A16 -fixed yes -DIRECTION Inout
117 #set_io {ADC_data[11]} -pinname B16 -fixed yes -DIRECTION Inout
117 #set_io {ADC_data[11]} -pinname B16 -fixed yes -DIRECTION Inout
118 #set_io {ADC_data[12]} -pinname C12 -fixed yes -DIRECTION Inout
118 #set_io {ADC_data[12]} -pinname C12 -fixed yes -DIRECTION Inout
119 #set_io {ADC_data[13]} -pinname C13 -fixed yes -DIRECTION Inout
119 #set_io {ADC_data[13]} -pinname C13 -fixed yes -DIRECTION Inout
120
120
121 set_io DAC_SDO -pinname A4 -fixed yes -DIRECTION Inout
121 set_io DAC_SDO -pinname A4 -fixed yes -DIRECTION Inout
122 set_io DAC_SCK -pinname A5 -fixed yes -DIRECTION Inout
122 set_io DAC_SCK -pinname A5 -fixed yes -DIRECTION Inout
123 set_io DAC_SYNC -pinname B6 -fixed yes -DIRECTION Inout
123 set_io DAC_SYNC -pinname B6 -fixed yes -DIRECTION Inout
124 set_io DAC_CAL_EN -pinname A6 -fixed yes -DIRECTION Inout
124 set_io DAC_CAL_EN -pinname A6 -fixed yes -DIRECTION Inout
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@@ -1,39 +1,40
1 # Top Level Design Parameters
1 # Top Level Design Parameters
2
2
3 # Clocks
3 # Clocks
4
4
5 create_clock -period 20.000000 -waveform {0.000000 10.000000} clk50MHz
5 create_clock -period 20.000000 -waveform {0.000000 10.000000} clk50MHz
6 create_clock -period 40.000000 -waveform {0.000000 20.000000} clk_25
6 create_clock -period 20.344999 -waveform {0.000000 10.172500} clk49_152MHz
7
7
8
9
10 #create_clock -period 40.000000 -waveform {0.000000 20.000000} clk_25
8 #create_generated_clock -name{clk_domain_25} -divide_by 2 -source{clk_25_int:CLK}{clk_25_int:Q}
11 #create_generated_clock -name{clk_domain_25} -divide_by 2 -source{clk_25_int:CLK}{clk_25_int:Q}
9
10 #create_clock -period 20.344999 -waveform {0.000000 10.172500} clk49_152MHz
11 #create_clock -period 40.690000 -waveform {0.000000 20.345100} clk_24:Q
12 #create_clock -period 40.690000 -waveform {0.000000 20.345100} clk_24:Q
12 #create_clock -name SPW_CLOCK -period 100.000000 -waveform {0.000000 50.000000} {spw1_din spw1_sin spw2_din spw2_sin}
13 #create_clock -name SPW_CLOCK -period 100.000000 -waveform {0.000000 50.000000} {spw1_din spw1_sin spw2_din spw2_sin}
13
14
14
15
15 # False Paths Between Clocks
16 # False Paths Between Clocks
16
17
17
18
18 # False Path Constraints
19 # False Path Constraints
19
20
20
21
21 # Maximum Delay Constraints
22 # Maximum Delay Constraints
22
23
23 # Multicycle Constraints
24 # Multicycle Constraints
24
25
25
26
26 # Virtual Clocks
27 # Virtual Clocks
27 # Output Load Constraints
28 # Output Load Constraints
28 # Driving Cell Constraints
29 # Driving Cell Constraints
29 # Wire Loads
30 # Wire Loads
30 # set_wire_load_mode top
31 # set_wire_load_mode top
31
32
32 # Other Constraints
33 # Other Constraints
33
34
34
35
35 ## GRSPW constraints
36 ## GRSPW constraints
36 create_clock -period 100.00 {spw_inputloop.1.spw_phy0/rxclki_RNO:Y}
37 create_clock -period 100.00 {spw_inputloop.1.spw_phy0/rxclki_RNO:Y}
37 create_clock -period 100.00 {spw_inputloop.0.spw_phy0/rxclki_RNO:Y}
38 create_clock -period 100.00 {spw_inputloop.0.spw_phy0/rxclki_RNO:Y}
38 set_max_delay 4.00 -from [all_inputs] -to [get_clocks spw_inputloop.0.spw_phy0/rxclki_RNO:Y]
39 set_max_delay 4.00 -from [all_inputs] -to [get_clocks spw_inputloop.0.spw_phy0/rxclki_RNO:Y]
39 set_max_delay 4.00 -from [all_inputs] -to [get_clocks spw_inputloop.1.spw_phy0/rxclki_RNO:Y]
40 set_max_delay 4.00 -from [all_inputs] -to [get_clocks spw_inputloop.1.spw_phy0/rxclki_RNO:Y]
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@@ -1,465 +1,468
1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
18 -------------------------------------------------------------------------------
19 -- Author : Jean-christophe Pellion
19 -- Author : Jean-christophe Pellion
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 -------------------------------------------------------------------------------
21 -------------------------------------------------------------------------------
22 LIBRARY IEEE;
22 LIBRARY IEEE;
23 USE IEEE.numeric_std.ALL;
23 USE IEEE.numeric_std.ALL;
24 USE IEEE.std_logic_1164.ALL;
24 USE IEEE.std_logic_1164.ALL;
25 LIBRARY grlib;
25 LIBRARY grlib;
26 USE grlib.amba.ALL;
26 USE grlib.amba.ALL;
27 USE grlib.stdlib.ALL;
27 USE grlib.stdlib.ALL;
28 LIBRARY techmap;
28 LIBRARY techmap;
29 USE techmap.gencomp.ALL;
29 USE techmap.gencomp.ALL;
30 LIBRARY gaisler;
30 LIBRARY gaisler;
31 USE gaisler.memctrl.ALL;
31 USE gaisler.memctrl.ALL;
32 USE gaisler.leon3.ALL;
32 USE gaisler.leon3.ALL;
33 USE gaisler.uart.ALL;
33 USE gaisler.uart.ALL;
34 USE gaisler.misc.ALL;
34 USE gaisler.misc.ALL;
35 USE gaisler.spacewire.ALL;
35 USE gaisler.spacewire.ALL;
36 LIBRARY esa;
36 LIBRARY esa;
37 USE esa.memoryctrl.ALL;
37 USE esa.memoryctrl.ALL;
38 LIBRARY lpp;
38 LIBRARY lpp;
39 USE lpp.lpp_memory.ALL;
39 USE lpp.lpp_memory.ALL;
40 USE lpp.lpp_ad_conv.ALL;
40 USE lpp.lpp_ad_conv.ALL;
41 USE lpp.lpp_lfr_pkg.ALL; -- contains lpp_lfr, not in the 206 rev of the VHD_Lib
41 USE lpp.lpp_lfr_pkg.ALL; -- contains lpp_lfr, not in the 206 rev of the VHD_Lib
42 USE lpp.lpp_top_lfr_pkg.ALL; -- contains top_wf_picker
42 USE lpp.lpp_top_lfr_pkg.ALL; -- contains top_wf_picker
43 USE lpp.iir_filter.ALL;
43 USE lpp.iir_filter.ALL;
44 USE lpp.general_purpose.ALL;
44 USE lpp.general_purpose.ALL;
45 USE lpp.lpp_lfr_management.ALL;
45 USE lpp.lpp_lfr_management.ALL;
46 USE lpp.lpp_leon3_soc_pkg.ALL;
46 USE lpp.lpp_leon3_soc_pkg.ALL;
47
47
48 library proasic3l;
48 library proasic3l;
49 use proasic3l.all;
49 use proasic3l.all;
50
50
51 ENTITY LFR_EQM IS
51 ENTITY LFR_EQM IS
52 GENERIC (
53 Mem_use : INTEGER := use_RAM);
52
54
53 PORT (
55 PORT (
54 clk50MHz : IN STD_ULOGIC;
56 clk50MHz : IN STD_ULOGIC;
55 clk49_152MHz : IN STD_ULOGIC;
57 clk49_152MHz : IN STD_ULOGIC;
56 reset : IN STD_ULOGIC;
58 reset : IN STD_ULOGIC;
57
59
58 -- TAG --------------------------------------------------------------------
60 -- TAG --------------------------------------------------------------------
59 TAG1 : IN STD_ULOGIC; -- DSU rx data
61 TAG1 : IN STD_ULOGIC; -- DSU rx data
60 TAG3 : OUT STD_ULOGIC; -- DSU tx data
62 TAG3 : OUT STD_ULOGIC; -- DSU tx data
61 -- UART APB ---------------------------------------------------------------
63 -- UART APB ---------------------------------------------------------------
62 TAG2 : IN STD_ULOGIC; -- UART1 rx data
64 TAG2 : IN STD_ULOGIC; -- UART1 rx data
63 TAG4 : OUT STD_ULOGIC; -- UART1 tx data
65 TAG4 : OUT STD_ULOGIC; -- UART1 tx data
64 -- RAM --------------------------------------------------------------------
66 -- RAM --------------------------------------------------------------------
65 address : OUT STD_LOGIC_VECTOR(18 DOWNTO 0);
67 address : OUT STD_LOGIC_VECTOR(18 DOWNTO 0);
66 data : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0);
68 data : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0);
67
69
68 nSRAM_MBE : INOUT STD_LOGIC; -- new
70 nSRAM_MBE : INOUT STD_LOGIC; -- new
69 nSRAM_E1 : OUT STD_LOGIC; -- new
71 nSRAM_E1 : OUT STD_LOGIC; -- new
70 nSRAM_E2 : OUT STD_LOGIC; -- new
72 nSRAM_E2 : OUT STD_LOGIC; -- new
71 -- nSRAM_SCRUB : OUT STD_LOGIC; -- new
73 -- nSRAM_SCRUB : OUT STD_LOGIC; -- new
72 nSRAM_W : OUT STD_LOGIC; -- new
74 nSRAM_W : OUT STD_LOGIC; -- new
73 nSRAM_G : OUT STD_LOGIC; -- new
75 nSRAM_G : OUT STD_LOGIC; -- new
74 nSRAM_BUSY : IN STD_LOGIC; -- new
76 nSRAM_BUSY : IN STD_LOGIC; -- new
75 -- SPW --------------------------------------------------------------------
77 -- SPW --------------------------------------------------------------------
76 spw1_en : OUT STD_LOGIC; -- new
78 spw1_en : OUT STD_LOGIC; -- new
77 spw1_din : IN STD_LOGIC;
79 spw1_din : IN STD_LOGIC;
78 spw1_sin : IN STD_LOGIC;
80 spw1_sin : IN STD_LOGIC;
79 spw1_dout : OUT STD_LOGIC;
81 spw1_dout : OUT STD_LOGIC;
80 spw1_sout : OUT STD_LOGIC;
82 spw1_sout : OUT STD_LOGIC;
81 spw2_en : OUT STD_LOGIC; -- new
83 spw2_en : OUT STD_LOGIC; -- new
82 spw2_din : IN STD_LOGIC;
84 spw2_din : IN STD_LOGIC;
83 spw2_sin : IN STD_LOGIC;
85 spw2_sin : IN STD_LOGIC;
84 spw2_dout : OUT STD_LOGIC;
86 spw2_dout : OUT STD_LOGIC;
85 spw2_sout : OUT STD_LOGIC;
87 spw2_sout : OUT STD_LOGIC;
86 -- ADC --------------------------------------------------------------------
88 -- ADC --------------------------------------------------------------------
87 bias_fail_sw : OUT STD_LOGIC;
89 bias_fail_sw : OUT STD_LOGIC;
88 ADC_OEB_bar_CH : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
90 ADC_OEB_bar_CH : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
89 ADC_smpclk : OUT STD_LOGIC;
91 ADC_smpclk : OUT STD_LOGIC;
90 ADC_data : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
92 ADC_data : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
91 -- DAC --------------------------------------------------------------------
93 -- DAC --------------------------------------------------------------------
92 DAC_SDO : OUT STD_LOGIC;
94 DAC_SDO : OUT STD_LOGIC;
93 DAC_SCK : OUT STD_LOGIC;
95 DAC_SCK : OUT STD_LOGIC;
94 DAC_SYNC : OUT STD_LOGIC;
96 DAC_SYNC : OUT STD_LOGIC;
95 DAC_CAL_EN : OUT STD_LOGIC;
97 DAC_CAL_EN : OUT STD_LOGIC;
96 -- HK ---------------------------------------------------------------------
98 -- HK ---------------------------------------------------------------------
97 HK_smpclk : OUT STD_LOGIC;
99 HK_smpclk : OUT STD_LOGIC;
98 ADC_OEB_bar_HK : OUT STD_LOGIC;
100 ADC_OEB_bar_HK : OUT STD_LOGIC;
99 HK_SEL : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
101 HK_SEL : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
100 ---------------------------------------------------------------------------
102 ---------------------------------------------------------------------------
101 TAG8 : OUT STD_LOGIC
103 TAG8 : OUT STD_LOGIC
102 );
104 );
103
105
104 END LFR_EQM;
106 END LFR_EQM;
105
107
106
108
107 ARCHITECTURE beh OF LFR_EQM IS
109 ARCHITECTURE beh OF LFR_EQM IS
108
110
109 SIGNAL clk_25 : STD_LOGIC := '0';
111 SIGNAL clk_25 : STD_LOGIC := '0';
110 SIGNAL clk_24 : STD_LOGIC := '0';
112 SIGNAL clk_24 : STD_LOGIC := '0';
111 -----------------------------------------------------------------------------
113 -----------------------------------------------------------------------------
112 SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
114 SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
113 SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0);
115 SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0);
114
116
115 -- CONSTANTS
117 -- CONSTANTS
116 CONSTANT CFG_PADTECH : INTEGER := inferred;
118 CONSTANT CFG_PADTECH : INTEGER := inferred;
117 CONSTANT NB_APB_SLAVE : INTEGER := 11; -- 3 = grspw + waveform picker + time manager, 11 allows pindex = f
119 CONSTANT NB_APB_SLAVE : INTEGER := 11; -- 3 = grspw + waveform picker + time manager, 11 allows pindex = f
118 CONSTANT NB_AHB_SLAVE : INTEGER := 1;
120 CONSTANT NB_AHB_SLAVE : INTEGER := 1;
119 CONSTANT NB_AHB_MASTER : INTEGER := 2; -- 2 = grspw + waveform picker
121 CONSTANT NB_AHB_MASTER : INTEGER := 2; -- 2 = grspw + waveform picker
120
122
121 SIGNAL apbi_ext : apb_slv_in_type;
123 SIGNAL apbi_ext : apb_slv_in_type;
122 SIGNAL apbo_ext : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5) := (OTHERS => apb_none);
124 SIGNAL apbo_ext : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5) := (OTHERS => apb_none);
123 SIGNAL ahbi_s_ext : ahb_slv_in_type;
125 SIGNAL ahbi_s_ext : ahb_slv_in_type;
124 SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3) := (OTHERS => ahbs_none);
126 SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3) := (OTHERS => ahbs_none);
125 SIGNAL ahbi_m_ext : AHB_Mst_In_Type;
127 SIGNAL ahbi_m_ext : AHB_Mst_In_Type;
126 SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1) := (OTHERS => ahbm_none);
128 SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1) := (OTHERS => ahbm_none);
127
129
128 -- Spacewire signals
130 -- Spacewire signals
129 SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
131 SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
130 SIGNAL stmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
132 SIGNAL stmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
131 SIGNAL spw_rxclk : STD_LOGIC_VECTOR(1 DOWNTO 0);
133 SIGNAL spw_rxclk : STD_LOGIC_VECTOR(1 DOWNTO 0);
132 SIGNAL spw_rxtxclk : STD_ULOGIC;
134 SIGNAL spw_rxtxclk : STD_ULOGIC;
133 SIGNAL spw_rxclkn : STD_ULOGIC;
135 SIGNAL spw_rxclkn : STD_ULOGIC;
134 SIGNAL spw_clk : STD_LOGIC;
136 SIGNAL spw_clk : STD_LOGIC;
135 SIGNAL swni : grspw_in_type;
137 SIGNAL swni : grspw_in_type;
136 SIGNAL swno : grspw_out_type;
138 SIGNAL swno : grspw_out_type;
137
139
138 --GPIO
140 --GPIO
139 SIGNAL gpioi : gpio_in_type;
141 SIGNAL gpioi : gpio_in_type;
140 SIGNAL gpioo : gpio_out_type;
142 SIGNAL gpioo : gpio_out_type;
141
143
142 -- AD Converter ADS7886
144 -- AD Converter ADS7886
143 SIGNAL sample : Samples14v(8 DOWNTO 0);
145 SIGNAL sample : Samples14v(8 DOWNTO 0);
144 SIGNAL sample_s : Samples(8 DOWNTO 0);
146 SIGNAL sample_s : Samples(8 DOWNTO 0);
145 SIGNAL sample_val : STD_LOGIC;
147 SIGNAL sample_val : STD_LOGIC;
146 SIGNAL ADC_OEB_bar_CH_s : STD_LOGIC_VECTOR(8 DOWNTO 0);
148 SIGNAL ADC_OEB_bar_CH_s : STD_LOGIC_VECTOR(8 DOWNTO 0);
147
149
148 -----------------------------------------------------------------------------
150 -----------------------------------------------------------------------------
149 SIGNAL observation_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
151 SIGNAL observation_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
150
152
151 -----------------------------------------------------------------------------
153 -----------------------------------------------------------------------------
152 SIGNAL rstn_25 : STD_LOGIC;
154 SIGNAL rstn_25 : STD_LOGIC;
153 SIGNAL rstn_24 : STD_LOGIC;
155 SIGNAL rstn_24 : STD_LOGIC;
154
156
155 SIGNAL LFR_soft_rstn : STD_LOGIC;
157 SIGNAL LFR_soft_rstn : STD_LOGIC;
156 SIGNAL LFR_rstn : STD_LOGIC;
158 SIGNAL LFR_rstn : STD_LOGIC;
157
159
158 SIGNAL ADC_smpclk_s : STD_LOGIC;
160 SIGNAL ADC_smpclk_s : STD_LOGIC;
159
161
160 SIGNAL nSRAM_CE : STD_LOGIC_VECTOR(1 DOWNTO 0);
162 SIGNAL nSRAM_CE : STD_LOGIC_VECTOR(1 DOWNTO 0);
161
163
162 SIGNAL clk50MHz_int : STD_LOGIC := '0';
164 SIGNAL clk50MHz_int : STD_LOGIC := '0';
163 SIGNAL clk_25_int : STD_LOGIC := '0';
165 SIGNAL clk_25_int : STD_LOGIC := '0';
164
166
165 component clkint port(A : in std_ulogic; Y :out std_ulogic); end component;
167 component clkint port(A : in std_ulogic; Y :out std_ulogic); end component;
166
168
167 BEGIN -- beh
169 BEGIN -- beh
168
170
169 -----------------------------------------------------------------------------
171 -----------------------------------------------------------------------------
170 -- CLK
172 -- CLK
171 -----------------------------------------------------------------------------
173 -----------------------------------------------------------------------------
172 rst_domain25 : rstgen PORT MAP (reset, clk_25, '1', rstn_25, OPEN);
174 rst_domain25 : rstgen PORT MAP (reset, clk_25, '1', rstn_25, OPEN);
173 rst_domain24 : rstgen PORT MAP (reset, clk_24, '1', rstn_24, OPEN);
175 rst_domain24 : rstgen PORT MAP (reset, clk_24, '1', rstn_24, OPEN);
174
176
175 --clk_pad : clkint port map (A => clk50MHz, Y => clk50MHz_int );
177 --clk_pad : clkint port map (A => clk50MHz, Y => clk50MHz_int );
176 clk50MHz_int <= clk50MHz;
178 clk50MHz_int <= clk50MHz;
177
179
178 PROCESS(clk50MHz_int)
180 PROCESS(clk50MHz_int)
179 BEGIN
181 BEGIN
180 IF clk50MHz_int'EVENT AND clk50MHz_int = '1' THEN
182 IF clk50MHz_int'EVENT AND clk50MHz_int = '1' THEN
181 --clk_25_int <= NOT clk_25_int;
183 --clk_25_int <= NOT clk_25_int;
182 clk_25 <= NOT clk_25;
184 clk_25 <= NOT clk_25;
183 END IF;
185 END IF;
184 END PROCESS;
186 END PROCESS;
185 --clk_pad_25 : clkint port map (A => clk_25_int, Y => clk_25 );
187 --clk_pad_25 : clkint port map (A => clk_25_int, Y => clk_25 );
186
188
187 PROCESS(clk49_152MHz)
189 PROCESS(clk49_152MHz)
188 BEGIN
190 BEGIN
189 IF clk49_152MHz'EVENT AND clk49_152MHz = '1' THEN
191 IF clk49_152MHz'EVENT AND clk49_152MHz = '1' THEN
190 clk_24 <= NOT clk_24;
192 clk_24 <= NOT clk_24;
191 END IF;
193 END IF;
192 END PROCESS;
194 END PROCESS;
193
195
194 -----------------------------------------------------------------------------
196 -----------------------------------------------------------------------------
195 --
197 --
196 leon3_soc_1 : leon3_soc
198 leon3_soc_1 : leon3_soc
197 GENERIC MAP (
199 GENERIC MAP (
198 fabtech => apa3e,
200 fabtech => apa3e,
199 memtech => apa3e,
201 memtech => apa3e,
200 padtech => inferred,
202 padtech => inferred,
201 clktech => inferred,
203 clktech => inferred,
202 disas => 0,
204 disas => 0,
203 dbguart => 0,
205 dbguart => 0,
204 pclow => 2,
206 pclow => 2,
205 clk_freq => 25000,
207 clk_freq => 25000,
206 IS_RADHARD => 0,
208 IS_RADHARD => 0,
207 NB_CPU => 1,
209 NB_CPU => 1,
208 ENABLE_FPU => 1,
210 ENABLE_FPU => 1,
209 FPU_NETLIST => 0,
211 FPU_NETLIST => 0,
210 ENABLE_DSU => 1,
212 ENABLE_DSU => 1,
211 ENABLE_AHB_UART => 1,
213 ENABLE_AHB_UART => 1,
212 ENABLE_APB_UART => 1,
214 ENABLE_APB_UART => 1,
213 ENABLE_IRQMP => 1,
215 ENABLE_IRQMP => 1,
214 ENABLE_GPT => 1,
216 ENABLE_GPT => 1,
215 NB_AHB_MASTER => NB_AHB_MASTER,
217 NB_AHB_MASTER => NB_AHB_MASTER,
216 NB_AHB_SLAVE => NB_AHB_SLAVE,
218 NB_AHB_SLAVE => NB_AHB_SLAVE,
217 NB_APB_SLAVE => NB_APB_SLAVE,
219 NB_APB_SLAVE => NB_APB_SLAVE,
218 ADDRESS_SIZE => 19,
220 ADDRESS_SIZE => 19,
219 USES_IAP_MEMCTRLR => 1)
221 USES_IAP_MEMCTRLR => 1,
222 BYPASS_EDAC_MEMCTRLR => '1')
220 PORT MAP (
223 PORT MAP (
221 clk => clk_25,
224 clk => clk_25,
222 reset => rstn_25,
225 reset => rstn_25,
223 errorn => OPEN,
226 errorn => OPEN,
224
227
225 ahbrxd => TAG1,
228 ahbrxd => TAG1,
226 ahbtxd => TAG3,
229 ahbtxd => TAG3,
227 urxd1 => TAG2,
230 urxd1 => TAG2,
228 utxd1 => TAG4,
231 utxd1 => TAG4,
229
232
230 address => address,
233 address => address,
231 data => data,
234 data => data,
232 nSRAM_BE0 => OPEN,
235 nSRAM_BE0 => OPEN,
233 nSRAM_BE1 => OPEN,
236 nSRAM_BE1 => OPEN,
234 nSRAM_BE2 => OPEN,
237 nSRAM_BE2 => OPEN,
235 nSRAM_BE3 => OPEN,
238 nSRAM_BE3 => OPEN,
236 nSRAM_WE => nSRAM_W,
239 nSRAM_WE => nSRAM_W,
237 nSRAM_CE => nSRAM_CE,
240 nSRAM_CE => nSRAM_CE,
238 nSRAM_OE => nSRAM_G,
241 nSRAM_OE => nSRAM_G,
239 nSRAM_READY => nSRAM_BUSY,
242 nSRAM_READY => nSRAM_BUSY,
240 SRAM_MBE => nSRAM_MBE,
243 SRAM_MBE => nSRAM_MBE,
241
244
242 apbi_ext => apbi_ext,
245 apbi_ext => apbi_ext,
243 apbo_ext => apbo_ext,
246 apbo_ext => apbo_ext,
244 ahbi_s_ext => ahbi_s_ext,
247 ahbi_s_ext => ahbi_s_ext,
245 ahbo_s_ext => ahbo_s_ext,
248 ahbo_s_ext => ahbo_s_ext,
246 ahbi_m_ext => ahbi_m_ext,
249 ahbi_m_ext => ahbi_m_ext,
247 ahbo_m_ext => ahbo_m_ext);
250 ahbo_m_ext => ahbo_m_ext);
248
251
249
252
250 nSRAM_E1 <= nSRAM_CE(0);
253 nSRAM_E1 <= nSRAM_CE(0);
251 nSRAM_E2 <= nSRAM_CE(1);
254 nSRAM_E2 <= nSRAM_CE(1);
252
255
253 -------------------------------------------------------------------------------
256 -------------------------------------------------------------------------------
254 -- APB_LFR_TIME_MANAGEMENT ----------------------------------------------------
257 -- APB_LFR_TIME_MANAGEMENT ----------------------------------------------------
255 -------------------------------------------------------------------------------
258 -------------------------------------------------------------------------------
256 apb_lfr_management_1 : apb_lfr_management
259 apb_lfr_management_1 : apb_lfr_management
257 GENERIC MAP (
260 GENERIC MAP (
258 tech => apa3e,
261 tech => apa3e,
259 pindex => 6,
262 pindex => 6,
260 paddr => 6,
263 paddr => 6,
261 pmask => 16#fff#,
264 pmask => 16#fff#,
262 FIRST_DIVISION => 374, -- ((49.152/2) /2^16) - 1 = 375 - 1 = 374
265 --FIRST_DIVISION => 374, -- ((49.152/2) /2^16) - 1 = 375 - 1 = 374
263 NB_SECOND_DESYNC => 60) -- 60 secondes of desynchronization before CoarseTime's MSB is Set
266 NB_SECOND_DESYNC => 60) -- 60 secondes of desynchronization before CoarseTime's MSB is Set
264 PORT MAP (
267 PORT MAP (
265 clk25MHz => clk_25,
268 clk25MHz => clk_25,
266 resetn_25MHz => rstn_25, -- TODO
269 resetn_25MHz => rstn_25, -- TODO
267 clk24_576MHz => clk_24, -- 49.152MHz/2
270 --clk24_576MHz => clk_24, -- 49.152MHz/2
268 resetn_24_576MHz => rstn_24, -- TODO
271 --resetn_24_576MHz => rstn_24, -- TODO
269
272
270 grspw_tick => swno.tickout,
273 grspw_tick => swno.tickout,
271 apbi => apbi_ext,
274 apbi => apbi_ext,
272 apbo => apbo_ext(6),
275 apbo => apbo_ext(6),
273
276
274 HK_sample => sample_s(8),
277 HK_sample => sample_s(8),
275 HK_val => sample_val,
278 HK_val => sample_val,
276 HK_sel => HK_SEL,
279 HK_sel => HK_SEL,
277
280
278 DAC_SDO => DAC_SDO,
281 DAC_SDO => DAC_SDO,
279 DAC_SCK => DAC_SCK,
282 DAC_SCK => DAC_SCK,
280 DAC_SYNC => DAC_SYNC,
283 DAC_SYNC => DAC_SYNC,
281 DAC_CAL_EN => DAC_CAL_EN,
284 DAC_CAL_EN => DAC_CAL_EN,
282
285
283 coarse_time => coarse_time,
286 coarse_time => coarse_time,
284 fine_time => fine_time,
287 fine_time => fine_time,
285 LFR_soft_rstn => LFR_soft_rstn
288 LFR_soft_rstn => LFR_soft_rstn
286 );
289 );
287
290
288 -----------------------------------------------------------------------
291 -----------------------------------------------------------------------
289 --- SpaceWire --------------------------------------------------------
292 --- SpaceWire --------------------------------------------------------
290 -----------------------------------------------------------------------
293 -----------------------------------------------------------------------
291
294
292 ------------------------------------------------------------------------------
295 ------------------------------------------------------------------------------
293 -- \/\/\/\/ TODO : spacewire enable should be controled by the SPW IP \/\/\/\/
296 -- \/\/\/\/ TODO : spacewire enable should be controled by the SPW IP \/\/\/\/
294 ------------------------------------------------------------------------------
297 ------------------------------------------------------------------------------
295 spw1_en <= '1';
298 spw1_en <= '1';
296 spw2_en <= '1';
299 spw2_en <= '1';
297 ------------------------------------------------------------------------------
300 ------------------------------------------------------------------------------
298 -- /\/\/\/\ --------------------------------------------------------- /\/\/\/\
301 -- /\/\/\/\ --------------------------------------------------------- /\/\/\/\
299 ------------------------------------------------------------------------------
302 ------------------------------------------------------------------------------
300
303
301 --spw_clk <= clk50MHz;
304 --spw_clk <= clk50MHz;
302 --spw_rxtxclk <= spw_clk;
305 --spw_rxtxclk <= spw_clk;
303 --spw_rxclkn <= NOT spw_rxtxclk;
306 --spw_rxclkn <= NOT spw_rxtxclk;
304
307
305 -- PADS for SPW1
308 -- PADS for SPW1
306 spw1_rxd_pad : inpad GENERIC MAP (tech => inferred)
309 spw1_rxd_pad : inpad GENERIC MAP (tech => inferred)
307 PORT MAP (spw1_din, dtmp(0));
310 PORT MAP (spw1_din, dtmp(0));
308 spw1_rxs_pad : inpad GENERIC MAP (tech => inferred)
311 spw1_rxs_pad : inpad GENERIC MAP (tech => inferred)
309 PORT MAP (spw1_sin, stmp(0));
312 PORT MAP (spw1_sin, stmp(0));
310 spw1_txd_pad : outpad GENERIC MAP (tech => inferred)
313 spw1_txd_pad : outpad GENERIC MAP (tech => inferred)
311 PORT MAP (spw1_dout, swno.d(0));
314 PORT MAP (spw1_dout, swno.d(0));
312 spw1_txs_pad : outpad GENERIC MAP (tech => inferred)
315 spw1_txs_pad : outpad GENERIC MAP (tech => inferred)
313 PORT MAP (spw1_sout, swno.s(0));
316 PORT MAP (spw1_sout, swno.s(0));
314 -- PADS FOR SPW2
317 -- PADS FOR SPW2
315 spw2_rxd_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
318 spw2_rxd_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
316 PORT MAP (spw2_din, dtmp(1));
319 PORT MAP (spw2_din, dtmp(1));
317 spw2_rxs_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
320 spw2_rxs_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
318 PORT MAP (spw2_sin, stmp(1));
321 PORT MAP (spw2_sin, stmp(1));
319 spw2_txd_pad : outpad GENERIC MAP (tech => inferred)
322 spw2_txd_pad : outpad GENERIC MAP (tech => inferred)
320 PORT MAP (spw2_dout, swno.d(1));
323 PORT MAP (spw2_dout, swno.d(1));
321 spw2_txs_pad : outpad GENERIC MAP (tech => inferred)
324 spw2_txs_pad : outpad GENERIC MAP (tech => inferred)
322 PORT MAP (spw2_sout, swno.s(1));
325 PORT MAP (spw2_sout, swno.s(1));
323
326
324 -- GRSPW PHY
327 -- GRSPW PHY
325 --spw1_input: if CFG_SPW_GRSPW = 1 generate
328 --spw1_input: if CFG_SPW_GRSPW = 1 generate
326 spw_inputloop : FOR j IN 0 TO 1 GENERATE
329 spw_inputloop : FOR j IN 0 TO 1 GENERATE
327 spw_phy0 : grspw_phy
330 spw_phy0 : grspw_phy
328 GENERIC MAP(
331 GENERIC MAP(
329 tech => apa3e,
332 tech => apa3e,
330 rxclkbuftype => 1,
333 rxclkbuftype => 1,
331 scantest => 0)
334 scantest => 0)
332 PORT MAP(
335 PORT MAP(
333 rxrst => swno.rxrst,
336 rxrst => swno.rxrst,
334 di => dtmp(j),
337 di => dtmp(j),
335 si => stmp(j),
338 si => stmp(j),
336 rxclko => spw_rxclk(j),
339 rxclko => spw_rxclk(j),
337 do => swni.d(j),
340 do => swni.d(j),
338 ndo => swni.nd(j*5+4 DOWNTO j*5),
341 ndo => swni.nd(j*5+4 DOWNTO j*5),
339 dconnect => swni.dconnect(j*2+1 DOWNTO j*2));
342 dconnect => swni.dconnect(j*2+1 DOWNTO j*2));
340 END GENERATE spw_inputloop;
343 END GENERATE spw_inputloop;
341
344
342 -- SPW core
345 -- SPW core
343 sw0 : grspwm GENERIC MAP(
346 sw0 : grspwm GENERIC MAP(
344 tech => apa3e,
347 tech => apa3e,
345 hindex => 1,
348 hindex => 1,
346 pindex => 5,
349 pindex => 5,
347 paddr => 5,
350 paddr => 5,
348 pirq => 11,
351 pirq => 11,
349 sysfreq => 25000, -- CPU_FREQ
352 sysfreq => 25000, -- CPU_FREQ
350 rmap => 1,
353 rmap => 1,
351 rmapcrc => 1,
354 rmapcrc => 1,
352 fifosize1 => 16,
355 fifosize1 => 16,
353 fifosize2 => 16,
356 fifosize2 => 16,
354 rxclkbuftype => 1,
357 rxclkbuftype => 1,
355 rxunaligned => 0,
358 rxunaligned => 0,
356 rmapbufs => 4,
359 rmapbufs => 4,
357 ft => 0,
360 ft => 0,
358 netlist => 0,
361 netlist => 0,
359 ports => 2,
362 ports => 2,
360 --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1
363 --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1
361 memtech => apa3e,
364 memtech => apa3e,
362 destkey => 2,
365 destkey => 2,
363 spwcore => 1
366 spwcore => 1
364 --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1
367 --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1
365 --output_type => CFG_SPW_OUTPUT, -- not used byt the spw core 1
368 --output_type => CFG_SPW_OUTPUT, -- not used byt the spw core 1
366 --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1
369 --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1
367 )
370 )
368 PORT MAP(rstn_25, clk_25, spw_rxclk(0),
371 PORT MAP(rstn_25, clk_25, spw_rxclk(0),
369 spw_rxclk(1),
372 spw_rxclk(1),
370 clk50MHz_int,
373 clk50MHz_int,
371 clk50MHz_int,
374 clk50MHz_int,
372 -- spw_rxtxclk, spw_rxtxclk, spw_rxtxclk, spw_rxtxclk,
375 -- spw_rxtxclk, spw_rxtxclk, spw_rxtxclk, spw_rxtxclk,
373 ahbi_m_ext, ahbo_m_ext(1), apbi_ext, apbo_ext(5),
376 ahbi_m_ext, ahbo_m_ext(1), apbi_ext, apbo_ext(5),
374 swni, swno);
377 swni, swno);
375
378
376 swni.tickin <= '0';
379 swni.tickin <= '0';
377 swni.rmapen <= '1';
380 swni.rmapen <= '1';
378 swni.clkdiv10 <= "00000100"; -- 50 MHz / (4 + 1) = 10 MHz
381 swni.clkdiv10 <= "00000100"; -- 50 MHz / (4 + 1) = 10 MHz
379 swni.tickinraw <= '0';
382 swni.tickinraw <= '0';
380 swni.timein <= (OTHERS => '0');
383 swni.timein <= (OTHERS => '0');
381 swni.dcrstval <= (OTHERS => '0');
384 swni.dcrstval <= (OTHERS => '0');
382 swni.timerrstval <= (OTHERS => '0');
385 swni.timerrstval <= (OTHERS => '0');
383
386
384 -------------------------------------------------------------------------------
387 -------------------------------------------------------------------------------
385 -- LFR ------------------------------------------------------------------------
388 -- LFR ------------------------------------------------------------------------
386 -------------------------------------------------------------------------------
389 -------------------------------------------------------------------------------
387 LFR_rstn <= LFR_soft_rstn AND rstn_25;
390 LFR_rstn <= LFR_soft_rstn AND rstn_25;
388
391
389 lpp_lfr_1 : lpp_lfr
392 lpp_lfr_1 : lpp_lfr
390 GENERIC MAP (
393 GENERIC MAP (
391 Mem_use => use_RAM,
394 Mem_use => Mem_use,
392 nb_data_by_buffer_size => 32,
395 nb_data_by_buffer_size => 32,
393 --nb_word_by_buffer_size => 30,
396 --nb_word_by_buffer_size => 30,
394 nb_snapshot_param_size => 32,
397 nb_snapshot_param_size => 32,
395 delta_vector_size => 32,
398 delta_vector_size => 32,
396 delta_vector_size_f0_2 => 7, -- log2(96)
399 delta_vector_size_f0_2 => 7, -- log2(96)
397 pindex => 15,
400 pindex => 15,
398 paddr => 15,
401 paddr => 15,
399 pmask => 16#fff#,
402 pmask => 16#fff#,
400 pirq_ms => 6,
403 pirq_ms => 6,
401 pirq_wfp => 14,
404 pirq_wfp => 14,
402 hindex => 2,
405 hindex => 2,
403 top_lfr_version => X"020144") -- aa.bb.cc version
406 top_lfr_version => X"020144") -- aa.bb.cc version
404 -- AA : BOARD NUMBER
407 -- AA : BOARD NUMBER
405 -- 0 => MINI_LFR
408 -- 0 => MINI_LFR
406 -- 1 => EM
409 -- 1 => EM
407 -- 2 => EQM (with A3PE3000)
410 -- 2 => EQM (with A3PE3000)
408 PORT MAP (
411 PORT MAP (
409 clk => clk_25,
412 clk => clk_25,
410 rstn => LFR_rstn,
413 rstn => LFR_rstn,
411 sample_B => sample_s(2 DOWNTO 0),
414 sample_B => sample_s(2 DOWNTO 0),
412 sample_E => sample_s(7 DOWNTO 3),
415 sample_E => sample_s(7 DOWNTO 3),
413 sample_val => sample_val,
416 sample_val => sample_val,
414 apbi => apbi_ext,
417 apbi => apbi_ext,
415 apbo => apbo_ext(15),
418 apbo => apbo_ext(15),
416 ahbi => ahbi_m_ext,
419 ahbi => ahbi_m_ext,
417 ahbo => ahbo_m_ext(2),
420 ahbo => ahbo_m_ext(2),
418 coarse_time => coarse_time,
421 coarse_time => coarse_time,
419 fine_time => fine_time,
422 fine_time => fine_time,
420 data_shaping_BW => bias_fail_sw,
423 data_shaping_BW => bias_fail_sw,
421 debug_vector => OPEN,
424 debug_vector => OPEN,
422 debug_vector_ms => OPEN); --,
425 debug_vector_ms => OPEN); --,
423 --observation_vector_0 => OPEN,
426 --observation_vector_0 => OPEN,
424 --observation_vector_1 => OPEN,
427 --observation_vector_1 => OPEN,
425 --observation_reg => observation_reg);
428 --observation_reg => observation_reg);
426
429
427
430
428 all_sample : FOR I IN 7 DOWNTO 0 GENERATE
431 all_sample : FOR I IN 7 DOWNTO 0 GENERATE
429 sample_s(I) <= sample(I) & '0' & '0';
432 sample_s(I) <= sample(I) & '0' & '0';
430 END GENERATE all_sample;
433 END GENERATE all_sample;
431 sample_s(8) <= sample(8)(13) & sample(8)(13) & sample(8);
434 sample_s(8) <= sample(8)(13) & sample(8)(13) & sample(8);
432
435
433 -----------------------------------------------------------------------------
436 -----------------------------------------------------------------------------
434 --
437 --
435 -----------------------------------------------------------------------------
438 -----------------------------------------------------------------------------
436 top_ad_conv_RHF1401_withFilter_1 : top_ad_conv_RHF1401_withFilter
439 top_ad_conv_RHF1401_withFilter_1 : top_ad_conv_RHF1401_withFilter
437 GENERIC MAP (
440 GENERIC MAP (
438 ChanelCount => 9,
441 ChanelCount => 9,
439 ncycle_cnv_high => 13,
442 ncycle_cnv_high => 13,
440 ncycle_cnv => 25,
443 ncycle_cnv => 25,
441 FILTER_ENABLED => 16#FF#)
444 FILTER_ENABLED => 16#FF#)
442 PORT MAP (
445 PORT MAP (
443 cnv_clk => clk_24,
446 cnv_clk => clk_24,
444 cnv_rstn => rstn_24,
447 cnv_rstn => rstn_24,
445 cnv => ADC_smpclk_s,
448 cnv => ADC_smpclk_s,
446 clk => clk_25,
449 clk => clk_25,
447 rstn => rstn_25,
450 rstn => rstn_25,
448 ADC_data => ADC_data,
451 ADC_data => ADC_data,
449 ADC_nOE => ADC_OEB_bar_CH_s,
452 ADC_nOE => ADC_OEB_bar_CH_s,
450 sample => sample,
453 sample => sample,
451 sample_val => sample_val);
454 sample_val => sample_val);
452
455
453 ADC_OEB_bar_CH <= ADC_OEB_bar_CH_s(7 DOWNTO 0);
456 ADC_OEB_bar_CH <= ADC_OEB_bar_CH_s(7 DOWNTO 0);
454
457
455 ADC_smpclk <= ADC_smpclk_s;
458 ADC_smpclk <= ADC_smpclk_s;
456 HK_smpclk <= ADC_smpclk_s;
459 HK_smpclk <= ADC_smpclk_s;
457
460
458 TAG8 <= nSRAM_BUSY;
461 TAG8 <= nSRAM_BUSY;
459
462
460 -----------------------------------------------------------------------------
463 -----------------------------------------------------------------------------
461 -- HK
464 -- HK
462 -----------------------------------------------------------------------------
465 -----------------------------------------------------------------------------
463 ADC_OEB_bar_HK <= ADC_OEB_bar_CH_s(8);
466 ADC_OEB_bar_HK <= ADC_OEB_bar_CH_s(8);
464
467
465 END beh;
468 END beh;
Show file before | Show file after | Hide comments
@@ -1,55 +1,55
1 #GRLIB=../..
1 #GRLIB=../..
2 VHDLIB=../..
2 VHDLIB=../..
3 SCRIPTSDIR=$(VHDLIB)/scripts/
3 SCRIPTSDIR=$(VHDLIB)/scripts/
4 GRLIB := $(shell sh $(VHDLIB)/scripts/lpp_relpath.sh)
4 GRLIB := $(shell sh $(VHDLIB)/scripts/lpp_relpath.sh)
5 TOP=LFR_EQM
5 TOP=LFR_EQM
6 BOARD=LFR-EQM
6 BOARD=LFR-EQM
7 include $(VHDLIB)/boards/$(BOARD)/Makefile.inc
7 include $(VHDLIB)/boards/$(BOARD)/Makefile.inc
8 DEVICE=$(PART)-$(PACKAGE)$(SPEED)
8 DEVICE=$(PART)-$(PACKAGE)$(SPEED)
9 UCF=$(GRLIB)/boards/$(BOARD)/$(TOP).ucf
9 UCF=$(GRLIB)/boards/$(BOARD)/$(TOP).ucf
10 QSF=$(GRLIB)/boards/$(BOARD)/$(TOP).qsf
10 QSF=$(GRLIB)/boards/$(BOARD)/$(TOP).qsf
11 EFFORT=high
11 EFFORT=high
12 XSTOPT=
12 XSTOPT=
13 SYNPOPT="set_option -pipe 0; set_option -retiming 0; set_option -write_apr_constraint 0"
13 SYNPOPT="set_option -pipe 0; set_option -retiming 0; set_option -write_apr_constraint 0"
14 #VHDLSYNFILES=config.vhd ahbrom.vhd leon3mp.vhd
14 #VHDLSYNFILES=config.vhd ahbrom.vhd leon3mp.vhd
15 #VHDLSYNFILES=config.vhd leon3mp.vhd
15 #VHDLSYNFILES=config.vhd leon3mp.vhd
16 VHDLSYNFILES=LFR-EQM.vhd
16 VHDLSYNFILES=LFR-EQM.vhd
17 VHDLSIMFILES=testbench.vhd
17 VHDLSIMFILES=testbench.vhd
18 #SIMTOP=testbench
18 #SIMTOP=testbench
19 PDC=$(VHDLIB)/boards/$(BOARD)/LFR_EQM_A3PE3000.pdc
19 PDC=$(VHDLIB)/boards/$(BOARD)/LFR_EQM_A3PE3000.pdc
20 SDCFILE=$(VHDLIB)/boards/$(BOARD)/LFR_EQM_synthesis.sdc
20 SDCFILE=$(VHDLIB)/boards/$(BOARD)/LFR_EQM_synthesis.sdc
21 SDC=$(VHDLIB)/boards/$(BOARD)/LFR_EQM_place_and_route.sdc
21 SDC=$(VHDLIB)/boards/$(BOARD)/LFR_EQM_place_and_route.sdc
22
22
23 BITGEN=$(VHDLIB)/boards/$(BOARD)/default.ut
23 BITGEN=$(VHDLIB)/boards/$(BOARD)/default.ut
24 CLEAN=soft-clean
24 CLEAN=soft-clean
25
25
26 TECHLIBS = proasic3e
26 TECHLIBS = proasic3l
27
27
28 LIBSKIP = core1553bbc core1553brm core1553brt gr1553 corePCIF \
28 LIBSKIP = core1553bbc core1553brm core1553brt gr1553 corePCIF \
29 tmtc openchip hynix ihp gleichmann micron usbhc
29 tmtc openchip hynix ihp gleichmann micron usbhc
30
30
31 DIRSKIP = b1553 pcif leon2 leon2ft crypto satcan ddr usb ata i2c \
31 DIRSKIP = b1553 pcif leon2 leon2ft crypto satcan ddr usb ata i2c \
32 pci grusbhc haps slink ascs pwm coremp7 spi ac97 \
32 pci grusbhc haps slink ascs pwm coremp7 spi ac97 \
33 ./amba_lcd_16x2_ctrlr \
33 ./amba_lcd_16x2_ctrlr \
34 ./general_purpose/lpp_AMR \
34 ./general_purpose/lpp_AMR \
35 ./general_purpose/lpp_balise \
35 ./general_purpose/lpp_balise \
36 ./general_purpose/lpp_delay \
36 ./general_purpose/lpp_delay \
37 ./lpp_bootloader \
37 ./lpp_bootloader \
38 ./dsp/lpp_fft_rtax \
38 ./dsp/lpp_fft_rtax \
39 ./lpp_uart \
39 ./lpp_uart \
40 ./lpp_usb \
40 ./lpp_usb \
41 ./lpp_sim/CY7C1061DV33 \
41 ./lpp_sim/CY7C1061DV33 \
42
42
43 FILESKIP = i2cmst.vhd \
43 FILESKIP = i2cmst.vhd \
44 APB_MULTI_DIODE.vhd \
44 APB_MULTI_DIODE.vhd \
45 APB_MULTI_DIODE.vhd \
45 APB_MULTI_DIODE.vhd \
46 Top_MatrixSpec.vhd \
46 Top_MatrixSpec.vhd \
47 APB_FFT.vhd\
47 APB_FFT.vhd\
48 CoreFFT_simu.vhd \
48 CoreFFT_simu.vhd \
49 lpp_lfr_apbreg_simu.vhd
49 lpp_lfr_apbreg_simu.vhd
50
50
51 include $(GRLIB)/bin/Makefile
51 include $(GRLIB)/bin/Makefile
52 include $(GRLIB)/software/leon3/Makefile
52 include $(GRLIB)/software/leon3/Makefile
53
53
54 ################## project specific targets ##########################
54 ################## project specific targets ##########################
55
55
Show file before | Show file after | Hide comments
@@ -1,740 +1,757
1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
18 -------------------------------------------------------------------------------
19 -- Author : Jean-christophe Pellion
19 -- Author : Jean-christophe Pellion
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 -------------------------------------------------------------------------------
21 -------------------------------------------------------------------------------
22 LIBRARY IEEE;
22 LIBRARY IEEE;
23 USE IEEE.numeric_std.ALL;
23 USE IEEE.numeric_std.ALL;
24 USE IEEE.std_logic_1164.ALL;
24 USE IEEE.std_logic_1164.ALL;
25 LIBRARY grlib;
25 LIBRARY grlib;
26 USE grlib.amba.ALL;
26 USE grlib.amba.ALL;
27 USE grlib.stdlib.ALL;
27 USE grlib.stdlib.ALL;
28 LIBRARY techmap;
28 LIBRARY techmap;
29 USE techmap.gencomp.ALL;
29 USE techmap.gencomp.ALL;
30 LIBRARY gaisler;
30 LIBRARY gaisler;
31 USE gaisler.memctrl.ALL;
31 USE gaisler.memctrl.ALL;
32 USE gaisler.leon3.ALL;
32 USE gaisler.leon3.ALL;
33 USE gaisler.uart.ALL;
33 USE gaisler.uart.ALL;
34 USE gaisler.misc.ALL;
34 USE gaisler.misc.ALL;
35 USE gaisler.spacewire.ALL;
35 USE gaisler.spacewire.ALL;
36 LIBRARY esa;
36 LIBRARY esa;
37 USE esa.memoryctrl.ALL;
37 USE esa.memoryctrl.ALL;
38 LIBRARY lpp;
38 LIBRARY lpp;
39 USE lpp.lpp_memory.ALL;
39 USE lpp.lpp_memory.ALL;
40 USE lpp.lpp_ad_conv.ALL;
40 USE lpp.lpp_ad_conv.ALL;
41 USE lpp.lpp_lfr_pkg.ALL; -- contains lpp_lfr, not in the 206 rev of the VHD_Lib
41 USE lpp.lpp_lfr_pkg.ALL; -- contains lpp_lfr, not in the 206 rev of the VHD_Lib
42 USE lpp.lpp_top_lfr_pkg.ALL; -- contains top_wf_picker
42 USE lpp.lpp_top_lfr_pkg.ALL; -- contains top_wf_picker
43 USE lpp.iir_filter.ALL;
43 USE lpp.iir_filter.ALL;
44 USE lpp.general_purpose.ALL;
44 USE lpp.general_purpose.ALL;
45 USE lpp.lpp_lfr_management.ALL;
45 USE lpp.lpp_lfr_management.ALL;
46 USE lpp.lpp_leon3_soc_pkg.ALL;
46 USE lpp.lpp_leon3_soc_pkg.ALL;
47
47
48 ENTITY MINI_LFR_top IS
48 ENTITY MINI_LFR_top IS
49
49
50 PORT (
50 PORT (
51 clk_50 : IN STD_LOGIC;
51 clk_50 : IN STD_LOGIC;
52 clk_49 : IN STD_LOGIC;
52 clk_49 : IN STD_LOGIC;
53 reset : IN STD_LOGIC;
53 reset : IN STD_LOGIC;
54 --BPs
54 --BPs
55 BP0 : IN STD_LOGIC;
55 BP0 : IN STD_LOGIC;
56 BP1 : IN STD_LOGIC;
56 BP1 : IN STD_LOGIC;
57 --LEDs
57 --LEDs
58 LED0 : OUT STD_LOGIC;
58 LED0 : OUT STD_LOGIC;
59 LED1 : OUT STD_LOGIC;
59 LED1 : OUT STD_LOGIC;
60 LED2 : OUT STD_LOGIC;
60 LED2 : OUT STD_LOGIC;
61 --UARTs
61 --UARTs
62 TXD1 : IN STD_LOGIC;
62 TXD1 : IN STD_LOGIC;
63 RXD1 : OUT STD_LOGIC;
63 RXD1 : OUT STD_LOGIC;
64 nCTS1 : OUT STD_LOGIC;
64 nCTS1 : OUT STD_LOGIC;
65 nRTS1 : IN STD_LOGIC;
65 nRTS1 : IN STD_LOGIC;
66
66
67 TXD2 : IN STD_LOGIC;
67 TXD2 : IN STD_LOGIC;
68 RXD2 : OUT STD_LOGIC;
68 RXD2 : OUT STD_LOGIC;
69 nCTS2 : OUT STD_LOGIC;
69 nCTS2 : OUT STD_LOGIC;
70 nDTR2 : IN STD_LOGIC;
70 nDTR2 : IN STD_LOGIC;
71 nRTS2 : IN STD_LOGIC;
71 nRTS2 : IN STD_LOGIC;
72 nDCD2 : OUT STD_LOGIC;
72 nDCD2 : OUT STD_LOGIC;
73
73
74 --EXT CONNECTOR
74 --EXT CONNECTOR
75 IO0 : INOUT STD_LOGIC;
75 IO0 : INOUT STD_LOGIC;
76 IO1 : INOUT STD_LOGIC;
76 IO1 : INOUT STD_LOGIC;
77 IO2 : INOUT STD_LOGIC;
77 IO2 : INOUT STD_LOGIC;
78 IO3 : INOUT STD_LOGIC;
78 IO3 : INOUT STD_LOGIC;
79 IO4 : INOUT STD_LOGIC;
79 IO4 : INOUT STD_LOGIC;
80 IO5 : INOUT STD_LOGIC;
80 IO5 : INOUT STD_LOGIC;
81 IO6 : INOUT STD_LOGIC;
81 IO6 : INOUT STD_LOGIC;
82 IO7 : INOUT STD_LOGIC;
82 IO7 : INOUT STD_LOGIC;
83 IO8 : INOUT STD_LOGIC;
83 IO8 : INOUT STD_LOGIC;
84 IO9 : INOUT STD_LOGIC;
84 IO9 : INOUT STD_LOGIC;
85 IO10 : INOUT STD_LOGIC;
85 IO10 : INOUT STD_LOGIC;
86 IO11 : INOUT STD_LOGIC;
86 IO11 : INOUT STD_LOGIC;
87
87
88 --SPACE WIRE
88 --SPACE WIRE
89 SPW_EN : OUT STD_LOGIC; -- 0 => off
89 SPW_EN : OUT STD_LOGIC; -- 0 => off
90 SPW_NOM_DIN : IN STD_LOGIC; -- NOMINAL LINK
90 SPW_NOM_DIN : IN STD_LOGIC; -- NOMINAL LINK
91 SPW_NOM_SIN : IN STD_LOGIC;
91 SPW_NOM_SIN : IN STD_LOGIC;
92 SPW_NOM_DOUT : OUT STD_LOGIC;
92 SPW_NOM_DOUT : OUT STD_LOGIC;
93 SPW_NOM_SOUT : OUT STD_LOGIC;
93 SPW_NOM_SOUT : OUT STD_LOGIC;
94 SPW_RED_DIN : IN STD_LOGIC; -- REDUNDANT LINK
94 SPW_RED_DIN : IN STD_LOGIC; -- REDUNDANT LINK
95 SPW_RED_SIN : IN STD_LOGIC;
95 SPW_RED_SIN : IN STD_LOGIC;
96 SPW_RED_DOUT : OUT STD_LOGIC;
96 SPW_RED_DOUT : OUT STD_LOGIC;
97 SPW_RED_SOUT : OUT STD_LOGIC;
97 SPW_RED_SOUT : OUT STD_LOGIC;
98 -- MINI LFR ADC INPUTS
98 -- MINI LFR ADC INPUTS
99 ADC_nCS : OUT STD_LOGIC;
99 ADC_nCS : OUT STD_LOGIC;
100 ADC_CLK : OUT STD_LOGIC;
100 ADC_CLK : OUT STD_LOGIC;
101 ADC_SDO : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
101 ADC_SDO : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
102
102
103 -- SRAM
103 -- SRAM
104 SRAM_nWE : OUT STD_LOGIC;
104 SRAM_nWE : OUT STD_LOGIC;
105 SRAM_CE : OUT STD_LOGIC;
105 SRAM_CE : OUT STD_LOGIC;
106 SRAM_nOE : OUT STD_LOGIC;
106 SRAM_nOE : OUT STD_LOGIC;
107 SRAM_nBE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
107 SRAM_nBE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
108 SRAM_A : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
108 SRAM_A : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
109 SRAM_DQ : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0)
109 SRAM_DQ : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0)
110 );
110 );
111
111
112 END MINI_LFR_top;
112 END MINI_LFR_top;
113
113
114
114
115 ARCHITECTURE beh OF MINI_LFR_top IS
115 ARCHITECTURE beh OF MINI_LFR_top IS
116
117 --==========================================================================
118 -- USE_IAP_MEMCTRL allow to use the srctrle-0ws on MINILFR board
119 -- when enabled, chip enable polarity should be reversed and bank size also
120 -- MINILFR -> 1 bank of 4MBytes -> SRBANKSZ=9
121 -- LFR EQM & FM -> 2 banks of 2MBytes -> SRBANKSZ=8
122 --==========================================================================
123 CONSTANT USE_IAP_MEMCTRL : integer := 1;
124 --==========================================================================
125
116 SIGNAL clk_50_s : STD_LOGIC := '0';
126 SIGNAL clk_50_s : STD_LOGIC := '0';
117 SIGNAL clk_25 : STD_LOGIC := '0';
127 SIGNAL clk_25 : STD_LOGIC := '0';
118 SIGNAL clk_24 : STD_LOGIC := '0';
128 SIGNAL clk_24 : STD_LOGIC := '0';
119 -----------------------------------------------------------------------------
129 -----------------------------------------------------------------------------
120 SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
130 SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
121 SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0);
131 SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0);
122 --
132 --
123 SIGNAL errorn : STD_LOGIC;
133 SIGNAL errorn : STD_LOGIC;
124 -- UART AHB ---------------------------------------------------------------
134 -- UART AHB ---------------------------------------------------------------
125 -- SIGNAL ahbrxd : STD_ULOGIC; -- DSU rx data
135 -- SIGNAL ahbrxd : STD_ULOGIC; -- DSU rx data
126 -- SIGNAL ahbtxd : STD_ULOGIC; -- DSU tx data
136 -- SIGNAL ahbtxd : STD_ULOGIC; -- DSU tx data
127
137
128 -- UART APB ---------------------------------------------------------------
138 -- UART APB ---------------------------------------------------------------
129 -- SIGNAL urxd1 : STD_ULOGIC; -- UART1 rx data
139 -- SIGNAL urxd1 : STD_ULOGIC; -- UART1 rx data
130 -- SIGNAL utxd1 : STD_ULOGIC; -- UART1 tx data
140 -- SIGNAL utxd1 : STD_ULOGIC; -- UART1 tx data
131 --
141 --
132 SIGNAL I00_s : STD_LOGIC;
142 SIGNAL I00_s : STD_LOGIC;
133
143
134 -- CONSTANTS
144 -- CONSTANTS
135 CONSTANT CFG_PADTECH : INTEGER := inferred;
145 CONSTANT CFG_PADTECH : INTEGER := inferred;
136 --
146 --
137 CONSTANT NB_APB_SLAVE : INTEGER := 11; -- 3 = grspw + waveform picker + time manager, 11 allows pindex = f
147 CONSTANT NB_APB_SLAVE : INTEGER := 11; -- 3 = grspw + waveform picker + time manager, 11 allows pindex = f
138 CONSTANT NB_AHB_SLAVE : INTEGER := 1;
148 CONSTANT NB_AHB_SLAVE : INTEGER := 1;
139 CONSTANT NB_AHB_MASTER : INTEGER := 2; -- 2 = grspw + waveform picker
149 CONSTANT NB_AHB_MASTER : INTEGER := 2; -- 2 = grspw + waveform picker
140
150
141 SIGNAL apbi_ext : apb_slv_in_type;
151 SIGNAL apbi_ext : apb_slv_in_type;
142 SIGNAL apbo_ext : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5); -- := (OTHERS => apb_none);
152 SIGNAL apbo_ext : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5); -- := (OTHERS => apb_none);
143 SIGNAL ahbi_s_ext : ahb_slv_in_type;
153 SIGNAL ahbi_s_ext : ahb_slv_in_type;
144 SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3); -- := (OTHERS => ahbs_none);
154 SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3); -- := (OTHERS => ahbs_none);
145 SIGNAL ahbi_m_ext : AHB_Mst_In_Type;
155 SIGNAL ahbi_m_ext : AHB_Mst_In_Type;
146 SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1); -- := (OTHERS => ahbm_none);
156 SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1); -- := (OTHERS => ahbm_none);
147
157
148 -- Spacewire signals
158 -- Spacewire signals
149 SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
159 SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
150 SIGNAL stmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
160 SIGNAL stmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
151 SIGNAL spw_rxclk : STD_LOGIC_VECTOR(1 DOWNTO 0);
161 SIGNAL spw_rxclk : STD_LOGIC_VECTOR(1 DOWNTO 0);
152 SIGNAL spw_rxtxclk : STD_ULOGIC;
162 SIGNAL spw_rxtxclk : STD_ULOGIC;
153 SIGNAL spw_rxclkn : STD_ULOGIC;
163 SIGNAL spw_rxclkn : STD_ULOGIC;
154 SIGNAL spw_clk : STD_LOGIC;
164 SIGNAL spw_clk : STD_LOGIC;
155 SIGNAL swni : grspw_in_type;
165 SIGNAL swni : grspw_in_type;
156 SIGNAL swno : grspw_out_type;
166 SIGNAL swno : grspw_out_type;
157 -- SIGNAL clkmn : STD_ULOGIC;
167 -- SIGNAL clkmn : STD_ULOGIC;
158 -- SIGNAL txclk : STD_ULOGIC;
168 -- SIGNAL txclk : STD_ULOGIC;
159
169
160 --GPIO
170 --GPIO
161 SIGNAL gpioi : gpio_in_type;
171 SIGNAL gpioi : gpio_in_type;
162 SIGNAL gpioo : gpio_out_type;
172 SIGNAL gpioo : gpio_out_type;
163
173
164 -- AD Converter ADS7886
174 -- AD Converter ADS7886
165 SIGNAL sample : Samples14v(7 DOWNTO 0);
175 SIGNAL sample : Samples14v(7 DOWNTO 0);
166 SIGNAL sample_s : Samples(7 DOWNTO 0);
176 SIGNAL sample_s : Samples(7 DOWNTO 0);
167 SIGNAL sample_val : STD_LOGIC;
177 SIGNAL sample_val : STD_LOGIC;
168 SIGNAL ADC_nCS_sig : STD_LOGIC;
178 SIGNAL ADC_nCS_sig : STD_LOGIC;
169 SIGNAL ADC_CLK_sig : STD_LOGIC;
179 SIGNAL ADC_CLK_sig : STD_LOGIC;
170 SIGNAL ADC_SDO_sig : STD_LOGIC_VECTOR(7 DOWNTO 0);
180 SIGNAL ADC_SDO_sig : STD_LOGIC_VECTOR(7 DOWNTO 0);
171
181
172 SIGNAL bias_fail_sw_sig : STD_LOGIC;
182 SIGNAL bias_fail_sw_sig : STD_LOGIC;
173
183
174 SIGNAL observation_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
184 SIGNAL observation_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
175 SIGNAL observation_vector_0 : STD_LOGIC_VECTOR(11 DOWNTO 0);
185 SIGNAL observation_vector_0 : STD_LOGIC_VECTOR(11 DOWNTO 0);
176 SIGNAL observation_vector_1 : STD_LOGIC_VECTOR(11 DOWNTO 0);
186 SIGNAL observation_vector_1 : STD_LOGIC_VECTOR(11 DOWNTO 0);
177 -----------------------------------------------------------------------------
187 -----------------------------------------------------------------------------
178
188
179 SIGNAL LFR_soft_rstn : STD_LOGIC;
189 SIGNAL LFR_soft_rstn : STD_LOGIC;
180 SIGNAL LFR_rstn : STD_LOGIC;
190 SIGNAL LFR_rstn : STD_LOGIC;
181
191
182
192
183 SIGNAL rstn_25 : STD_LOGIC;
193 SIGNAL rstn_25 : STD_LOGIC;
184 SIGNAL rstn_25_d1 : STD_LOGIC;
194 SIGNAL rstn_25_d1 : STD_LOGIC;
185 SIGNAL rstn_25_d2 : STD_LOGIC;
195 SIGNAL rstn_25_d2 : STD_LOGIC;
186 SIGNAL rstn_25_d3 : STD_LOGIC;
196 SIGNAL rstn_25_d3 : STD_LOGIC;
187
197
188 SIGNAL rstn_24 : STD_LOGIC;
198 SIGNAL rstn_24 : STD_LOGIC;
189 SIGNAL rstn_24_d1 : STD_LOGIC;
199 SIGNAL rstn_24_d1 : STD_LOGIC;
190 SIGNAL rstn_24_d2 : STD_LOGIC;
200 SIGNAL rstn_24_d2 : STD_LOGIC;
191 SIGNAL rstn_24_d3 : STD_LOGIC;
201 SIGNAL rstn_24_d3 : STD_LOGIC;
192
202
193 SIGNAL rstn_50 : STD_LOGIC;
203 SIGNAL rstn_50 : STD_LOGIC;
194 SIGNAL rstn_50_d1 : STD_LOGIC;
204 SIGNAL rstn_50_d1 : STD_LOGIC;
195 SIGNAL rstn_50_d2 : STD_LOGIC;
205 SIGNAL rstn_50_d2 : STD_LOGIC;
196 SIGNAL rstn_50_d3 : STD_LOGIC;
206 SIGNAL rstn_50_d3 : STD_LOGIC;
197
207
198 SIGNAL lfr_debug_vector : STD_LOGIC_VECTOR(11 DOWNTO 0);
208 SIGNAL lfr_debug_vector : STD_LOGIC_VECTOR(11 DOWNTO 0);
199 SIGNAL lfr_debug_vector_ms : STD_LOGIC_VECTOR(11 DOWNTO 0);
209 SIGNAL lfr_debug_vector_ms : STD_LOGIC_VECTOR(11 DOWNTO 0);
200
210
201 --
211 --
202 SIGNAL SRAM_CE_s : STD_LOGIC_VECTOR(1 DOWNTO 0);
212 SIGNAL SRAM_CE_s : STD_LOGIC_VECTOR(1 DOWNTO 0);
203
213
204 --
214 --
205 SIGNAL sample_hk : STD_LOGIC_VECTOR(15 DOWNTO 0);
215 SIGNAL sample_hk : STD_LOGIC_VECTOR(15 DOWNTO 0);
206 SIGNAL HK_SEL : STD_LOGIC_VECTOR(1 DOWNTO 0);
216 SIGNAL HK_SEL : STD_LOGIC_VECTOR(1 DOWNTO 0);
207
217
208 BEGIN -- beh
218 BEGIN -- beh
209
219
210 -----------------------------------------------------------------------------
220 -----------------------------------------------------------------------------
211 -- CLK
221 -- CLK
212 -----------------------------------------------------------------------------
222 -----------------------------------------------------------------------------
213
223
214 --PROCESS(clk_50)
224 --PROCESS(clk_50)
215 --BEGIN
225 --BEGIN
216 -- IF clk_50'EVENT AND clk_50 = '1' THEN
226 -- IF clk_50'EVENT AND clk_50 = '1' THEN
217 -- clk_50_s <= NOT clk_50_s;
227 -- clk_50_s <= NOT clk_50_s;
218 -- END IF;
228 -- END IF;
219 --END PROCESS;
229 --END PROCESS;
220
230
221 --PROCESS(clk_50_s)
231 --PROCESS(clk_50_s)
222 --BEGIN
232 --BEGIN
223 -- IF clk_50_s'EVENT AND clk_50_s = '1' THEN
233 -- IF clk_50_s'EVENT AND clk_50_s = '1' THEN
224 -- clk_25 <= NOT clk_25;
234 -- clk_25 <= NOT clk_25;
225 -- END IF;
235 -- END IF;
226 --END PROCESS;
236 --END PROCESS;
227
237
228 --PROCESS(clk_49)
238 --PROCESS(clk_49)
229 --BEGIN
239 --BEGIN
230 -- IF clk_49'EVENT AND clk_49 = '1' THEN
240 -- IF clk_49'EVENT AND clk_49 = '1' THEN
231 -- clk_24 <= NOT clk_24;
241 -- clk_24 <= NOT clk_24;
232 -- END IF;
242 -- END IF;
233 --END PROCESS;
243 --END PROCESS;
234
244
235 --PROCESS(clk_25)
245 --PROCESS(clk_25)
236 --BEGIN
246 --BEGIN
237 -- IF clk_25'EVENT AND clk_25 = '1' THEN
247 -- IF clk_25'EVENT AND clk_25 = '1' THEN
238 -- rstn_25 <= reset;
248 -- rstn_25 <= reset;
239 -- END IF;
249 -- END IF;
240 --END PROCESS;
250 --END PROCESS;
241
251
242 PROCESS (clk_50, reset)
252 PROCESS (clk_50, reset)
243 BEGIN -- PROCESS
253 BEGIN -- PROCESS
244 IF clk_50'EVENT AND clk_50 = '1' THEN -- rising clock edge
254 IF clk_50'EVENT AND clk_50 = '1' THEN -- rising clock edge
245 clk_50_s <= NOT clk_50_s;
255 clk_50_s <= NOT clk_50_s;
246 END IF;
256 END IF;
247 END PROCESS;
257 END PROCESS;
248
258
249 PROCESS (clk_50_s, reset)
259 PROCESS (clk_50_s, reset)
250 BEGIN -- PROCESS
260 BEGIN -- PROCESS
251 IF reset = '0' THEN -- asynchronous reset (active low)
261 IF reset = '0' THEN -- asynchronous reset (active low)
252 clk_25 <= '0';
262 clk_25 <= '0';
253 rstn_25 <= '0';
263 rstn_25 <= '0';
254 rstn_25_d1 <= '0';
264 rstn_25_d1 <= '0';
255 rstn_25_d2 <= '0';
265 rstn_25_d2 <= '0';
256 rstn_25_d3 <= '0';
266 rstn_25_d3 <= '0';
257 ELSIF clk_50_s'EVENT AND clk_50_s = '1' THEN -- rising clock edge
267 ELSIF clk_50_s'EVENT AND clk_50_s = '1' THEN -- rising clock edge
258 clk_25 <= NOT clk_25;
268 clk_25 <= NOT clk_25;
259 rstn_25_d1 <= '1';
269 rstn_25_d1 <= '1';
260 rstn_25_d2 <= rstn_25_d1;
270 rstn_25_d2 <= rstn_25_d1;
261 rstn_25_d3 <= rstn_25_d2;
271 rstn_25_d3 <= rstn_25_d2;
262 rstn_25 <= rstn_25_d3;
272 rstn_25 <= rstn_25_d3;
263 END IF;
273 END IF;
264 END PROCESS;
274 END PROCESS;
265
275
266 PROCESS (clk_49, reset)
276 PROCESS (clk_49, reset)
267 BEGIN -- PROCESS
277 BEGIN -- PROCESS
268 IF reset = '0' THEN -- asynchronous reset (active low)
278 IF reset = '0' THEN -- asynchronous reset (active low)
269 clk_24 <= '0';
279 clk_24 <= '0';
270 rstn_24_d1 <= '0';
280 rstn_24_d1 <= '0';
271 rstn_24_d2 <= '0';
281 rstn_24_d2 <= '0';
272 rstn_24_d3 <= '0';
282 rstn_24_d3 <= '0';
273 rstn_24 <= '0';
283 rstn_24 <= '0';
274 ELSIF clk_49'EVENT AND clk_49 = '1' THEN -- rising clock edge
284 ELSIF clk_49'EVENT AND clk_49 = '1' THEN -- rising clock edge
275 clk_24 <= NOT clk_24;
285 clk_24 <= NOT clk_24;
276 rstn_24_d1 <= '1';
286 rstn_24_d1 <= '1';
277 rstn_24_d2 <= rstn_24_d1;
287 rstn_24_d2 <= rstn_24_d1;
278 rstn_24_d3 <= rstn_24_d2;
288 rstn_24_d3 <= rstn_24_d2;
279 rstn_24 <= rstn_24_d3;
289 rstn_24 <= rstn_24_d3;
280 END IF;
290 END IF;
281 END PROCESS;
291 END PROCESS;
282
292
283 -----------------------------------------------------------------------------
293 -----------------------------------------------------------------------------
284
294
285 PROCESS (clk_25, rstn_25)
295 PROCESS (clk_25, rstn_25)
286 BEGIN -- PROCESS
296 BEGIN -- PROCESS
287 IF rstn_25 = '0' THEN -- asynchronous reset (active low)
297 IF rstn_25 = '0' THEN -- asynchronous reset (active low)
288 LED0 <= '0';
298 LED0 <= '0';
289 LED1 <= '0';
299 LED1 <= '0';
290 LED2 <= '0';
300 LED2 <= '0';
291 --IO1 <= '0';
301 --IO1 <= '0';
292 --IO2 <= '1';
302 --IO2 <= '1';
293 --IO3 <= '0';
303 --IO3 <= '0';
294 --IO4 <= '0';
304 --IO4 <= '0';
295 --IO5 <= '0';
305 --IO5 <= '0';
296 --IO6 <= '0';
306 --IO6 <= '0';
297 --IO7 <= '0';
307 --IO7 <= '0';
298 --IO8 <= '0';
308 --IO8 <= '0';
299 --IO9 <= '0';
309 --IO9 <= '0';
300 --IO10 <= '0';
310 --IO10 <= '0';
301 --IO11 <= '0';
311 --IO11 <= '0';
302 ELSIF clk_25'EVENT AND clk_25 = '1' THEN -- rising clock edge
312 ELSIF clk_25'EVENT AND clk_25 = '1' THEN -- rising clock edge
303 LED0 <= '0';
313 LED0 <= '0';
304 LED1 <= '1';
314 LED1 <= '1';
305 LED2 <= BP0 OR BP1 OR nDTR2 OR nRTS2 OR nRTS1;
315 LED2 <= BP0 OR BP1 OR nDTR2 OR nRTS2 OR nRTS1;
306 --IO1 <= '1';
316 --IO1 <= '1';
307 --IO2 <= SPW_NOM_DIN OR SPW_NOM_SIN OR SPW_RED_DIN OR SPW_RED_SIN;
317 --IO2 <= SPW_NOM_DIN OR SPW_NOM_SIN OR SPW_RED_DIN OR SPW_RED_SIN;
308 --IO3 <= ADC_SDO(0);
318 --IO3 <= ADC_SDO(0);
309 --IO4 <= ADC_SDO(1);
319 --IO4 <= ADC_SDO(1);
310 --IO5 <= ADC_SDO(2);
320 --IO5 <= ADC_SDO(2);
311 --IO6 <= ADC_SDO(3);
321 --IO6 <= ADC_SDO(3);
312 --IO7 <= ADC_SDO(4);
322 --IO7 <= ADC_SDO(4);
313 --IO8 <= ADC_SDO(5);
323 --IO8 <= ADC_SDO(5);
314 --IO9 <= ADC_SDO(6);
324 --IO9 <= ADC_SDO(6);
315 --IO10 <= ADC_SDO(7);
325 --IO10 <= ADC_SDO(7);
316 --IO11 <= BP1 OR nDTR2 OR nRTS2 OR nRTS1;
326 --IO11 <= BP1 OR nDTR2 OR nRTS2 OR nRTS1;
317 END IF;
327 END IF;
318 END PROCESS;
328 END PROCESS;
319
329
320 PROCESS (clk_24, rstn_24)
330 PROCESS (clk_24, rstn_24)
321 BEGIN -- PROCESS
331 BEGIN -- PROCESS
322 IF rstn_24 = '0' THEN -- asynchronous reset (active low)
332 IF rstn_24 = '0' THEN -- asynchronous reset (active low)
323 I00_s <= '0';
333 I00_s <= '0';
324 ELSIF clk_24'EVENT AND clk_24 = '1' THEN -- rising clock edge
334 ELSIF clk_24'EVENT AND clk_24 = '1' THEN -- rising clock edge
325 I00_s <= NOT I00_s;
335 I00_s <= NOT I00_s;
326 END IF;
336 END IF;
327 END PROCESS;
337 END PROCESS;
328 -- IO0 <= I00_s;
338 -- IO0 <= I00_s;
329
339
330 --UARTs
340 --UARTs
331 nCTS1 <= '1';
341 nCTS1 <= '1';
332 nCTS2 <= '1';
342 nCTS2 <= '1';
333 nDCD2 <= '1';
343 nDCD2 <= '1';
334
344
335 --
345 --
336
346
337 leon3_soc_1 : leon3_soc
347 leon3_soc_1 : leon3_soc
338 GENERIC MAP (
348 GENERIC MAP (
339 fabtech => apa3e,
349 fabtech => apa3e,
340 memtech => apa3e,
350 memtech => apa3e,
341 padtech => inferred,
351 padtech => inferred,
342 clktech => inferred,
352 clktech => inferred,
343 disas => 0,
353 disas => 0,
344 dbguart => 0,
354 dbguart => 0,
345 pclow => 2,
355 pclow => 2,
346 clk_freq => 25000,
356 clk_freq => 25000,
347 IS_RADHARD => 0,
357 IS_RADHARD => 0,
348 NB_CPU => 1,
358 NB_CPU => 1,
349 ENABLE_FPU => 1,
359 ENABLE_FPU => 1,
350 FPU_NETLIST => 0,
360 FPU_NETLIST => 0,
351 ENABLE_DSU => 1,
361 ENABLE_DSU => 1,
352 ENABLE_AHB_UART => 1,
362 ENABLE_AHB_UART => 1,
353 ENABLE_APB_UART => 1,
363 ENABLE_APB_UART => 1,
354 ENABLE_IRQMP => 1,
364 ENABLE_IRQMP => 1,
355 ENABLE_GPT => 1,
365 ENABLE_GPT => 1,
356 NB_AHB_MASTER => NB_AHB_MASTER,
366 NB_AHB_MASTER => NB_AHB_MASTER,
357 NB_AHB_SLAVE => NB_AHB_SLAVE,
367 NB_AHB_SLAVE => NB_AHB_SLAVE,
358 NB_APB_SLAVE => NB_APB_SLAVE,
368 NB_APB_SLAVE => NB_APB_SLAVE,
359 ADDRESS_SIZE => 20,
369 ADDRESS_SIZE => 20,
360 USES_IAP_MEMCTRLR => 0)
370 USES_IAP_MEMCTRLR => USE_IAP_MEMCTRL,
371 SRBANKSZ => 9)
361 PORT MAP (
372 PORT MAP (
362 clk => clk_25,
373 clk => clk_25,
363 reset => rstn_25,
374 reset => rstn_25,
364 errorn => errorn,
375 errorn => errorn,
365 ahbrxd => TXD1,
376 ahbrxd => TXD1,
366 ahbtxd => RXD1,
377 ahbtxd => RXD1,
367 urxd1 => TXD2,
378 urxd1 => TXD2,
368 utxd1 => RXD2,
379 utxd1 => RXD2,
369 address => SRAM_A,
380 address => SRAM_A,
370 data => SRAM_DQ,
381 data => SRAM_DQ,
371 nSRAM_BE0 => SRAM_nBE(0),
382 nSRAM_BE0 => SRAM_nBE(0),
372 nSRAM_BE1 => SRAM_nBE(1),
383 nSRAM_BE1 => SRAM_nBE(1),
373 nSRAM_BE2 => SRAM_nBE(2),
384 nSRAM_BE2 => SRAM_nBE(2),
374 nSRAM_BE3 => SRAM_nBE(3),
385 nSRAM_BE3 => SRAM_nBE(3),
375 nSRAM_WE => SRAM_nWE,
386 nSRAM_WE => SRAM_nWE,
376 nSRAM_CE => SRAM_CE_s,
387 nSRAM_CE => SRAM_CE_s,
377 nSRAM_OE => SRAM_nOE,
388 nSRAM_OE => SRAM_nOE,
378 nSRAM_READY => '0',
389 nSRAM_READY => '1',
379 SRAM_MBE => OPEN,
390 SRAM_MBE => OPEN,
380 apbi_ext => apbi_ext,
391 apbi_ext => apbi_ext,
381 apbo_ext => apbo_ext,
392 apbo_ext => apbo_ext,
382 ahbi_s_ext => ahbi_s_ext,
393 ahbi_s_ext => ahbi_s_ext,
383 ahbo_s_ext => ahbo_s_ext,
394 ahbo_s_ext => ahbo_s_ext,
384 ahbi_m_ext => ahbi_m_ext,
395 ahbi_m_ext => ahbi_m_ext,
385 ahbo_m_ext => ahbo_m_ext);
396 ahbo_m_ext => ahbo_m_ext);
386
397
387 SRAM_CE <= SRAM_CE_s(0);
398 IAP:if USE_IAP_MEMCTRL = 1 GENERATE
399 SRAM_CE <= not SRAM_CE_s(0);
400 END GENERATE;
401
402 NOIAP:if USE_IAP_MEMCTRL = 0 GENERATE
403 SRAM_CE <= SRAM_CE_s(0);
404 END GENERATE;
388 -------------------------------------------------------------------------------
405 -------------------------------------------------------------------------------
389 -- APB_LFR_MANAGEMENT ---------------------------------------------------------
406 -- APB_LFR_MANAGEMENT ---------------------------------------------------------
390 -------------------------------------------------------------------------------
407 -------------------------------------------------------------------------------
391 apb_lfr_management_1 : apb_lfr_management
408 apb_lfr_management_1 : apb_lfr_management
392 GENERIC MAP (
409 GENERIC MAP (
393 tech => apa3e,
410 tech => apa3e,
394 pindex => 6,
411 pindex => 6,
395 paddr => 6,
412 paddr => 6,
396 pmask => 16#fff#,
413 pmask => 16#fff#,
397 FIRST_DIVISION => 374, -- ((49.152/2) /2^16) - 1 = 375 - 1 = 374
414 FIRST_DIVISION => 374, -- ((49.152/2) /2^16) - 1 = 375 - 1 = 374
398 NB_SECOND_DESYNC => 60) -- 60 secondes of desynchronization before CoarseTime's MSB is Set
415 NB_SECOND_DESYNC => 60) -- 60 secondes of desynchronization before CoarseTime's MSB is Set
399 PORT MAP (
416 PORT MAP (
400 clk25MHz => clk_25,
417 clk25MHz => clk_25,
401 resetn_25MHz => rstn_25, -- TODO
418 resetn_25MHz => rstn_25, -- TODO
402 clk24_576MHz => clk_24, -- 49.152MHz/2
419 clk24_576MHz => clk_24, -- 49.152MHz/2
403 resetn_24_576MHz => rstn_24, -- TODO
420 resetn_24_576MHz => rstn_24, -- TODO
404 grspw_tick => swno.tickout,
421 grspw_tick => swno.tickout,
405 apbi => apbi_ext,
422 apbi => apbi_ext,
406 apbo => apbo_ext(6),
423 apbo => apbo_ext(6),
407 HK_sample => sample_hk,
424 HK_sample => sample_hk,
408 HK_val => sample_val,
425 HK_val => sample_val,
409 HK_sel => HK_SEL,
426 HK_sel => HK_SEL,
410 DAC_SDO => OPEN,
427 DAC_SDO => OPEN,
411 DAC_SCK => OPEN,
428 DAC_SCK => OPEN,
412 DAC_SYNC => OPEN,
429 DAC_SYNC => OPEN,
413 DAC_CAL_EN => OPEN,
430 DAC_CAL_EN => OPEN,
414 coarse_time => coarse_time,
431 coarse_time => coarse_time,
415 fine_time => fine_time,
432 fine_time => fine_time,
416 LFR_soft_rstn => LFR_soft_rstn
433 LFR_soft_rstn => LFR_soft_rstn
417 );
434 );
418
435
419 -----------------------------------------------------------------------
436 -----------------------------------------------------------------------
420 --- SpaceWire --------------------------------------------------------
437 --- SpaceWire --------------------------------------------------------
421 -----------------------------------------------------------------------
438 -----------------------------------------------------------------------
422
439
423 SPW_EN <= '1';
440 SPW_EN <= '1';
424
441
425 spw_clk <= clk_50_s;
442 spw_clk <= clk_50_s;
426 spw_rxtxclk <= spw_clk;
443 spw_rxtxclk <= spw_clk;
427 spw_rxclkn <= NOT spw_rxtxclk;
444 spw_rxclkn <= NOT spw_rxtxclk;
428
445
429 -- PADS for SPW1
446 -- PADS for SPW1
430 spw1_rxd_pad : inpad GENERIC MAP (tech => inferred)
447 spw1_rxd_pad : inpad GENERIC MAP (tech => inferred)
431 PORT MAP (SPW_NOM_DIN, dtmp(0));
448 PORT MAP (SPW_NOM_DIN, dtmp(0));
432 spw1_rxs_pad : inpad GENERIC MAP (tech => inferred)
449 spw1_rxs_pad : inpad GENERIC MAP (tech => inferred)
433 PORT MAP (SPW_NOM_SIN, stmp(0));
450 PORT MAP (SPW_NOM_SIN, stmp(0));
434 spw1_txd_pad : outpad GENERIC MAP (tech => inferred)
451 spw1_txd_pad : outpad GENERIC MAP (tech => inferred)
435 PORT MAP (SPW_NOM_DOUT, swno.d(0));
452 PORT MAP (SPW_NOM_DOUT, swno.d(0));
436 spw1_txs_pad : outpad GENERIC MAP (tech => inferred)
453 spw1_txs_pad : outpad GENERIC MAP (tech => inferred)
437 PORT MAP (SPW_NOM_SOUT, swno.s(0));
454 PORT MAP (SPW_NOM_SOUT, swno.s(0));
438 -- PADS FOR SPW2
455 -- PADS FOR SPW2
439 spw2_rxd_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
456 spw2_rxd_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
440 PORT MAP (SPW_RED_SIN, dtmp(1));
457 PORT MAP (SPW_RED_SIN, dtmp(1));
441 spw2_rxs_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
458 spw2_rxs_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
442 PORT MAP (SPW_RED_DIN, stmp(1));
459 PORT MAP (SPW_RED_DIN, stmp(1));
443 spw2_txd_pad : outpad GENERIC MAP (tech => inferred)
460 spw2_txd_pad : outpad GENERIC MAP (tech => inferred)
444 PORT MAP (SPW_RED_DOUT, swno.d(1));
461 PORT MAP (SPW_RED_DOUT, swno.d(1));
445 spw2_txs_pad : outpad GENERIC MAP (tech => inferred)
462 spw2_txs_pad : outpad GENERIC MAP (tech => inferred)
446 PORT MAP (SPW_RED_SOUT, swno.s(1));
463 PORT MAP (SPW_RED_SOUT, swno.s(1));
447
464
448 -- GRSPW PHY
465 -- GRSPW PHY
449 --spw1_input: if CFG_SPW_GRSPW = 1 generate
466 --spw1_input: if CFG_SPW_GRSPW = 1 generate
450 spw_inputloop : FOR j IN 0 TO 1 GENERATE
467 spw_inputloop : FOR j IN 0 TO 1 GENERATE
451 spw_phy0 : grspw_phy
468 spw_phy0 : grspw_phy
452 GENERIC MAP(
469 GENERIC MAP(
453 tech => apa3e,
470 tech => apa3e,
454 rxclkbuftype => 1,
471 rxclkbuftype => 1,
455 scantest => 0)
472 scantest => 0)
456 PORT MAP(
473 PORT MAP(
457 rxrst => swno.rxrst,
474 rxrst => swno.rxrst,
458 di => dtmp(j),
475 di => dtmp(j),
459 si => stmp(j),
476 si => stmp(j),
460 rxclko => spw_rxclk(j),
477 rxclko => spw_rxclk(j),
461 do => swni.d(j),
478 do => swni.d(j),
462 ndo => swni.nd(j*5+4 DOWNTO j*5),
479 ndo => swni.nd(j*5+4 DOWNTO j*5),
463 dconnect => swni.dconnect(j*2+1 DOWNTO j*2));
480 dconnect => swni.dconnect(j*2+1 DOWNTO j*2));
464 END GENERATE spw_inputloop;
481 END GENERATE spw_inputloop;
465
482
466 swni.rmapnodeaddr <= (OTHERS => '0');
483 swni.rmapnodeaddr <= (OTHERS => '0');
467
484
468 -- SPW core
485 -- SPW core
469 sw0 : grspwm GENERIC MAP(
486 sw0 : grspwm GENERIC MAP(
470 tech => apa3e,
487 tech => apa3e,
471 hindex => 1,
488 hindex => 1,
472 pindex => 5,
489 pindex => 5,
473 paddr => 5,
490 paddr => 5,
474 pirq => 11,
491 pirq => 11,
475 sysfreq => 25000, -- CPU_FREQ
492 sysfreq => 25000, -- CPU_FREQ
476 rmap => 1,
493 rmap => 1,
477 rmapcrc => 1,
494 rmapcrc => 1,
478 fifosize1 => 16,
495 fifosize1 => 16,
479 fifosize2 => 16,
496 fifosize2 => 16,
480 rxclkbuftype => 1,
497 rxclkbuftype => 1,
481 rxunaligned => 0,
498 rxunaligned => 0,
482 rmapbufs => 4,
499 rmapbufs => 4,
483 ft => 0,
500 ft => 0,
484 netlist => 0,
501 netlist => 0,
485 ports => 2,
502 ports => 2,
486 --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1
503 --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1
487 memtech => apa3e,
504 memtech => apa3e,
488 destkey => 2,
505 destkey => 2,
489 spwcore => 1
506 spwcore => 1
490 --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1
507 --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1
491 --output_type => CFG_SPW_OUTPUT, -- not used byt the spw core 1
508 --output_type => CFG_SPW_OUTPUT, -- not used byt the spw core 1
492 --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1
509 --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1
493 )
510 )
494 PORT MAP(rstn_25, clk_25, spw_rxclk(0),
511 PORT MAP(rstn_25, clk_25, spw_rxclk(0),
495 spw_rxclk(1), spw_rxtxclk, spw_rxtxclk,
512 spw_rxclk(1), spw_rxtxclk, spw_rxtxclk,
496 ahbi_m_ext, ahbo_m_ext(1), apbi_ext, apbo_ext(5),
513 ahbi_m_ext, ahbo_m_ext(1), apbi_ext, apbo_ext(5),
497 swni, swno);
514 swni, swno);
498
515
499 swni.tickin <= '0';
516 swni.tickin <= '0';
500 swni.rmapen <= '1';
517 swni.rmapen <= '1';
501 swni.clkdiv10 <= "00000100"; -- 10 MHz / (4 + 1) = 10 MHz
518 swni.clkdiv10 <= "00000100"; -- 10 MHz / (4 + 1) = 10 MHz
502 swni.tickinraw <= '0';
519 swni.tickinraw <= '0';
503 swni.timein <= (OTHERS => '0');
520 swni.timein <= (OTHERS => '0');
504 swni.dcrstval <= (OTHERS => '0');
521 swni.dcrstval <= (OTHERS => '0');
505 swni.timerrstval <= (OTHERS => '0');
522 swni.timerrstval <= (OTHERS => '0');
506
523
507 -------------------------------------------------------------------------------
524 -------------------------------------------------------------------------------
508 -- LFR ------------------------------------------------------------------------
525 -- LFR ------------------------------------------------------------------------
509 -------------------------------------------------------------------------------
526 -------------------------------------------------------------------------------
510
527
511
528
512 LFR_rstn <= LFR_soft_rstn AND rstn_25;
529 LFR_rstn <= LFR_soft_rstn AND rstn_25;
513 --LFR_rstn <= rstn_25;
530 --LFR_rstn <= rstn_25;
514
531
515 lpp_lfr_1 : lpp_lfr
532 lpp_lfr_1 : lpp_lfr
516 GENERIC MAP (
533 GENERIC MAP (
517 Mem_use => use_RAM,
534 Mem_use => use_RAM,
518 nb_data_by_buffer_size => 32,
535 nb_data_by_buffer_size => 32,
519 nb_snapshot_param_size => 32,
536 nb_snapshot_param_size => 32,
520 delta_vector_size => 32,
537 delta_vector_size => 32,
521 delta_vector_size_f0_2 => 7, -- log2(96)
538 delta_vector_size_f0_2 => 7, -- log2(96)
522 pindex => 15,
539 pindex => 15,
523 paddr => 15,
540 paddr => 15,
524 pmask => 16#fff#,
541 pmask => 16#fff#,
525 pirq_ms => 6,
542 pirq_ms => 6,
526 pirq_wfp => 14,
543 pirq_wfp => 14,
527 hindex => 2,
544 hindex => 2,
528 top_lfr_version => X"000144") -- aa.bb.cc version
545 top_lfr_version => X"000144") -- aa.bb.cc version
529 PORT MAP (
546 PORT MAP (
530 clk => clk_25,
547 clk => clk_25,
531 rstn => LFR_rstn,
548 rstn => LFR_rstn,
532 sample_B => sample_s(2 DOWNTO 0),
549 sample_B => sample_s(2 DOWNTO 0),
533 sample_E => sample_s(7 DOWNTO 3),
550 sample_E => sample_s(7 DOWNTO 3),
534 sample_val => sample_val,
551 sample_val => sample_val,
535 apbi => apbi_ext,
552 apbi => apbi_ext,
536 apbo => apbo_ext(15),
553 apbo => apbo_ext(15),
537 ahbi => ahbi_m_ext,
554 ahbi => ahbi_m_ext,
538 ahbo => ahbo_m_ext(2),
555 ahbo => ahbo_m_ext(2),
539 coarse_time => coarse_time,
556 coarse_time => coarse_time,
540 fine_time => fine_time,
557 fine_time => fine_time,
541 data_shaping_BW => bias_fail_sw_sig,
558 data_shaping_BW => bias_fail_sw_sig,
542 debug_vector => lfr_debug_vector,
559 debug_vector => lfr_debug_vector,
543 debug_vector_ms => lfr_debug_vector_ms
560 debug_vector_ms => lfr_debug_vector_ms
544 );
561 );
545
562
546 observation_reg(11 DOWNTO 0) <= lfr_debug_vector;
563 observation_reg(11 DOWNTO 0) <= lfr_debug_vector;
547 observation_reg(31 DOWNTO 12) <= (OTHERS => '0');
564 observation_reg(31 DOWNTO 12) <= (OTHERS => '0');
548 observation_vector_0(11 DOWNTO 0) <= lfr_debug_vector;
565 observation_vector_0(11 DOWNTO 0) <= lfr_debug_vector;
549 observation_vector_1(11 DOWNTO 0) <= lfr_debug_vector;
566 observation_vector_1(11 DOWNTO 0) <= lfr_debug_vector;
550 IO0 <= rstn_25;
567 IO0 <= rstn_25;
551 IO1 <= lfr_debug_vector_ms(0); -- LFR MS FFT data_valid
568 IO1 <= lfr_debug_vector_ms(0); -- LFR MS FFT data_valid
552 IO2 <= lfr_debug_vector_ms(0); -- LFR MS FFT ready
569 IO2 <= lfr_debug_vector_ms(0); -- LFR MS FFT ready
553 IO3 <= lfr_debug_vector(0); -- LFR APBREG error_buffer_full
570 IO3 <= lfr_debug_vector(0); -- LFR APBREG error_buffer_full
554 IO4 <= lfr_debug_vector(1); -- LFR APBREG reg_sp.status_error_buffer_full
571 IO4 <= lfr_debug_vector(1); -- LFR APBREG reg_sp.status_error_buffer_full
555 IO5 <= lfr_debug_vector(8); -- LFR APBREG ready_matrix_f2
572 IO5 <= lfr_debug_vector(8); -- LFR APBREG ready_matrix_f2
556 IO6 <= lfr_debug_vector(9); -- LFR APBREG reg0_ready_matrix_f2
573 IO6 <= lfr_debug_vector(9); -- LFR APBREG reg0_ready_matrix_f2
557 IO7 <= lfr_debug_vector(10); -- LFR APBREG reg0_ready_matrix_f2
574 IO7 <= lfr_debug_vector(10); -- LFR APBREG reg0_ready_matrix_f2
558
575
559 all_sample : FOR I IN 7 DOWNTO 0 GENERATE
576 all_sample : FOR I IN 7 DOWNTO 0 GENERATE
560 sample_s(I) <= sample(I)(11 DOWNTO 0) & '0' & '0' & '0' & '0';
577 sample_s(I) <= sample(I)(11 DOWNTO 0) & '0' & '0' & '0' & '0';
561 END GENERATE all_sample;
578 END GENERATE all_sample;
562
579
563 top_ad_conv_ADS7886_v2_1 : top_ad_conv_ADS7886_v2
580 top_ad_conv_ADS7886_v2_1 : top_ad_conv_ADS7886_v2
564 GENERIC MAP(
581 GENERIC MAP(
565 ChannelCount => 8,
582 ChannelCount => 8,
566 SampleNbBits => 14,
583 SampleNbBits => 14,
567 ncycle_cnv_high => 40, -- at least 32 cycles at 25 MHz, 32 * 49.152 / 25 /2 = 31.5
584 ncycle_cnv_high => 40, -- at least 32 cycles at 25 MHz, 32 * 49.152 / 25 /2 = 31.5
568 ncycle_cnv => 249) -- 49 152 000 / 98304 /2
585 ncycle_cnv => 249) -- 49 152 000 / 98304 /2
569 PORT MAP (
586 PORT MAP (
570 -- CONV
587 -- CONV
571 cnv_clk => clk_24,
588 cnv_clk => clk_24,
572 cnv_rstn => rstn_24,
589 cnv_rstn => rstn_24,
573 cnv => ADC_nCS_sig,
590 cnv => ADC_nCS_sig,
574 -- DATA
591 -- DATA
575 clk => clk_25,
592 clk => clk_25,
576 rstn => rstn_25,
593 rstn => rstn_25,
577 sck => ADC_CLK_sig,
594 sck => ADC_CLK_sig,
578 sdo => ADC_SDO_sig,
595 sdo => ADC_SDO_sig,
579 -- SAMPLE
596 -- SAMPLE
580 sample => sample,
597 sample => sample,
581 sample_val => sample_val);
598 sample_val => sample_val);
582
599
583 --IO10 <= ADC_SDO_sig(5);
600 --IO10 <= ADC_SDO_sig(5);
584 --IO9 <= ADC_SDO_sig(4);
601 --IO9 <= ADC_SDO_sig(4);
585 --IO8 <= ADC_SDO_sig(3);
602 --IO8 <= ADC_SDO_sig(3);
586
603
587 ADC_nCS <= ADC_nCS_sig;
604 ADC_nCS <= ADC_nCS_sig;
588 ADC_CLK <= ADC_CLK_sig;
605 ADC_CLK <= ADC_CLK_sig;
589 ADC_SDO_sig <= ADC_SDO;
606 ADC_SDO_sig <= ADC_SDO;
590
607
591 sample_hk <= "0001000100010001" WHEN HK_SEL = "00" ELSE
608 sample_hk <= "0001000100010001" WHEN HK_SEL = "00" ELSE
592 "0010001000100010" WHEN HK_SEL = "01" ELSE
609 "0010001000100010" WHEN HK_SEL = "01" ELSE
593 "0100010001000100" WHEN HK_SEL = "10" ELSE
610 "0100010001000100" WHEN HK_SEL = "10" ELSE
594 (OTHERS => '0');
611 (OTHERS => '0');
595
612
596
613
597 ----------------------------------------------------------------------
614 ----------------------------------------------------------------------
598 --- GPIO -----------------------------------------------------------
615 --- GPIO -----------------------------------------------------------
599 ----------------------------------------------------------------------
616 ----------------------------------------------------------------------
600
617
601 grgpio0 : grgpio
618 grgpio0 : grgpio
602 GENERIC MAP(pindex => 11, paddr => 11, imask => 16#0000#, nbits => 8)
619 GENERIC MAP(pindex => 11, paddr => 11, imask => 16#0000#, nbits => 8)
603 PORT MAP(rstn_25, clk_25, apbi_ext, apbo_ext(11), gpioi, gpioo);
620 PORT MAP(rstn_25, clk_25, apbi_ext, apbo_ext(11), gpioi, gpioo);
604
621
605 gpioi.sig_en <= (OTHERS => '0');
622 gpioi.sig_en <= (OTHERS => '0');
606 gpioi.sig_in <= (OTHERS => '0');
623 gpioi.sig_in <= (OTHERS => '0');
607 gpioi.din <= (OTHERS => '0');
624 gpioi.din <= (OTHERS => '0');
608 --pio_pad_0 : iopad
625 --pio_pad_0 : iopad
609 -- GENERIC MAP (tech => CFG_PADTECH)
626 -- GENERIC MAP (tech => CFG_PADTECH)
610 -- PORT MAP (IO0, gpioo.dout(0), gpioo.oen(0), gpioi.din(0));
627 -- PORT MAP (IO0, gpioo.dout(0), gpioo.oen(0), gpioi.din(0));
611 --pio_pad_1 : iopad
628 --pio_pad_1 : iopad
612 -- GENERIC MAP (tech => CFG_PADTECH)
629 -- GENERIC MAP (tech => CFG_PADTECH)
613 -- PORT MAP (IO1, gpioo.dout(1), gpioo.oen(1), gpioi.din(1));
630 -- PORT MAP (IO1, gpioo.dout(1), gpioo.oen(1), gpioi.din(1));
614 --pio_pad_2 : iopad
631 --pio_pad_2 : iopad
615 -- GENERIC MAP (tech => CFG_PADTECH)
632 -- GENERIC MAP (tech => CFG_PADTECH)
616 -- PORT MAP (IO2, gpioo.dout(2), gpioo.oen(2), gpioi.din(2));
633 -- PORT MAP (IO2, gpioo.dout(2), gpioo.oen(2), gpioi.din(2));
617 --pio_pad_3 : iopad
634 --pio_pad_3 : iopad
618 -- GENERIC MAP (tech => CFG_PADTECH)
635 -- GENERIC MAP (tech => CFG_PADTECH)
619 -- PORT MAP (IO3, gpioo.dout(3), gpioo.oen(3), gpioi.din(3));
636 -- PORT MAP (IO3, gpioo.dout(3), gpioo.oen(3), gpioi.din(3));
620 --pio_pad_4 : iopad
637 --pio_pad_4 : iopad
621 -- GENERIC MAP (tech => CFG_PADTECH)
638 -- GENERIC MAP (tech => CFG_PADTECH)
622 -- PORT MAP (IO4, gpioo.dout(4), gpioo.oen(4), gpioi.din(4));
639 -- PORT MAP (IO4, gpioo.dout(4), gpioo.oen(4), gpioi.din(4));
623 --pio_pad_5 : iopad
640 --pio_pad_5 : iopad
624 -- GENERIC MAP (tech => CFG_PADTECH)
641 -- GENERIC MAP (tech => CFG_PADTECH)
625 -- PORT MAP (IO5, gpioo.dout(5), gpioo.oen(5), gpioi.din(5));
642 -- PORT MAP (IO5, gpioo.dout(5), gpioo.oen(5), gpioi.din(5));
626 --pio_pad_6 : iopad
643 --pio_pad_6 : iopad
627 -- GENERIC MAP (tech => CFG_PADTECH)
644 -- GENERIC MAP (tech => CFG_PADTECH)
628 -- PORT MAP (IO6, gpioo.dout(6), gpioo.oen(6), gpioi.din(6));
645 -- PORT MAP (IO6, gpioo.dout(6), gpioo.oen(6), gpioi.din(6));
629 --pio_pad_7 : iopad
646 --pio_pad_7 : iopad
630 -- GENERIC MAP (tech => CFG_PADTECH)
647 -- GENERIC MAP (tech => CFG_PADTECH)
631 -- PORT MAP (IO7, gpioo.dout(7), gpioo.oen(7), gpioi.din(7));
648 -- PORT MAP (IO7, gpioo.dout(7), gpioo.oen(7), gpioi.din(7));
632
649
633 PROCESS (clk_25, rstn_25)
650 PROCESS (clk_25, rstn_25)
634 BEGIN -- PROCESS
651 BEGIN -- PROCESS
635 IF rstn_25 = '0' THEN -- asynchronous reset (active low)
652 IF rstn_25 = '0' THEN -- asynchronous reset (active low)
636 -- --IO0 <= '0';
653 -- --IO0 <= '0';
637 -- IO1 <= '0';
654 -- IO1 <= '0';
638 -- IO2 <= '0';
655 -- IO2 <= '0';
639 -- IO3 <= '0';
656 -- IO3 <= '0';
640 -- IO4 <= '0';
657 -- IO4 <= '0';
641 -- IO5 <= '0';
658 -- IO5 <= '0';
642 -- IO6 <= '0';
659 -- IO6 <= '0';
643 -- IO7 <= '0';
660 -- IO7 <= '0';
644 IO8 <= '0';
661 IO8 <= '0';
645 IO9 <= '0';
662 IO9 <= '0';
646 IO10 <= '0';
663 IO10 <= '0';
647 IO11 <= '0';
664 IO11 <= '0';
648 ELSIF clk_25'EVENT AND clk_25 = '1' THEN -- rising clock edge
665 ELSIF clk_25'EVENT AND clk_25 = '1' THEN -- rising clock edge
649 CASE gpioo.dout(2 DOWNTO 0) IS
666 CASE gpioo.dout(2 DOWNTO 0) IS
650 WHEN "011" =>
667 WHEN "011" =>
651 -- --IO0 <= observation_reg(0 );
668 -- --IO0 <= observation_reg(0 );
652 -- IO1 <= observation_reg(1 );
669 -- IO1 <= observation_reg(1 );
653 -- IO2 <= observation_reg(2 );
670 -- IO2 <= observation_reg(2 );
654 -- IO3 <= observation_reg(3 );
671 -- IO3 <= observation_reg(3 );
655 -- IO4 <= observation_reg(4 );
672 -- IO4 <= observation_reg(4 );
656 -- IO5 <= observation_reg(5 );
673 -- IO5 <= observation_reg(5 );
657 -- IO6 <= observation_reg(6 );
674 -- IO6 <= observation_reg(6 );
658 -- IO7 <= observation_reg(7 );
675 -- IO7 <= observation_reg(7 );
659 IO8 <= observation_reg(8);
676 IO8 <= observation_reg(8);
660 IO9 <= observation_reg(9);
677 IO9 <= observation_reg(9);
661 IO10 <= observation_reg(10);
678 IO10 <= observation_reg(10);
662 IO11 <= observation_reg(11);
679 IO11 <= observation_reg(11);
663 WHEN "001" =>
680 WHEN "001" =>
664 -- --IO0 <= observation_reg(0 + 12);
681 -- --IO0 <= observation_reg(0 + 12);
665 -- IO1 <= observation_reg(1 + 12);
682 -- IO1 <= observation_reg(1 + 12);
666 -- IO2 <= observation_reg(2 + 12);
683 -- IO2 <= observation_reg(2 + 12);
667 -- IO3 <= observation_reg(3 + 12);
684 -- IO3 <= observation_reg(3 + 12);
668 -- IO4 <= observation_reg(4 + 12);
685 -- IO4 <= observation_reg(4 + 12);
669 -- IO5 <= observation_reg(5 + 12);
686 -- IO5 <= observation_reg(5 + 12);
670 -- IO6 <= observation_reg(6 + 12);
687 -- IO6 <= observation_reg(6 + 12);
671 -- IO7 <= observation_reg(7 + 12);
688 -- IO7 <= observation_reg(7 + 12);
672 IO8 <= observation_reg(8 + 12);
689 IO8 <= observation_reg(8 + 12);
673 IO9 <= observation_reg(9 + 12);
690 IO9 <= observation_reg(9 + 12);
674 IO10 <= observation_reg(10 + 12);
691 IO10 <= observation_reg(10 + 12);
675 IO11 <= observation_reg(11 + 12);
692 IO11 <= observation_reg(11 + 12);
676 WHEN "010" =>
693 WHEN "010" =>
677 -- --IO0 <= observation_reg(0 + 12 + 12);
694 -- --IO0 <= observation_reg(0 + 12 + 12);
678 -- IO1 <= observation_reg(1 + 12 + 12);
695 -- IO1 <= observation_reg(1 + 12 + 12);
679 -- IO2 <= observation_reg(2 + 12 + 12);
696 -- IO2 <= observation_reg(2 + 12 + 12);
680 -- IO3 <= observation_reg(3 + 12 + 12);
697 -- IO3 <= observation_reg(3 + 12 + 12);
681 -- IO4 <= observation_reg(4 + 12 + 12);
698 -- IO4 <= observation_reg(4 + 12 + 12);
682 -- IO5 <= observation_reg(5 + 12 + 12);
699 -- IO5 <= observation_reg(5 + 12 + 12);
683 -- IO6 <= observation_reg(6 + 12 + 12);
700 -- IO6 <= observation_reg(6 + 12 + 12);
684 -- IO7 <= observation_reg(7 + 12 + 12);
701 -- IO7 <= observation_reg(7 + 12 + 12);
685 IO8 <= '0';
702 IO8 <= '0';
686 IO9 <= '0';
703 IO9 <= '0';
687 IO10 <= '0';
704 IO10 <= '0';
688 IO11 <= '0';
705 IO11 <= '0';
689 WHEN "000" =>
706 WHEN "000" =>
690 -- --IO0 <= observation_vector_0(0 );
707 -- --IO0 <= observation_vector_0(0 );
691 -- IO1 <= observation_vector_0(1 );
708 -- IO1 <= observation_vector_0(1 );
692 -- IO2 <= observation_vector_0(2 );
709 -- IO2 <= observation_vector_0(2 );
693 -- IO3 <= observation_vector_0(3 );
710 -- IO3 <= observation_vector_0(3 );
694 -- IO4 <= observation_vector_0(4 );
711 -- IO4 <= observation_vector_0(4 );
695 -- IO5 <= observation_vector_0(5 );
712 -- IO5 <= observation_vector_0(5 );
696 -- IO6 <= observation_vector_0(6 );
713 -- IO6 <= observation_vector_0(6 );
697 -- IO7 <= observation_vector_0(7 );
714 -- IO7 <= observation_vector_0(7 );
698 IO8 <= observation_vector_0(8);
715 IO8 <= observation_vector_0(8);
699 IO9 <= observation_vector_0(9);
716 IO9 <= observation_vector_0(9);
700 IO10 <= observation_vector_0(10);
717 IO10 <= observation_vector_0(10);
701 IO11 <= observation_vector_0(11);
718 IO11 <= observation_vector_0(11);
702 WHEN "100" =>
719 WHEN "100" =>
703 -- --IO0 <= observation_vector_1(0 );
720 -- --IO0 <= observation_vector_1(0 );
704 -- IO1 <= observation_vector_1(1 );
721 -- IO1 <= observation_vector_1(1 );
705 -- IO2 <= observation_vector_1(2 );
722 -- IO2 <= observation_vector_1(2 );
706 -- IO3 <= observation_vector_1(3 );
723 -- IO3 <= observation_vector_1(3 );
707 -- IO4 <= observation_vector_1(4 );
724 -- IO4 <= observation_vector_1(4 );
708 -- IO5 <= observation_vector_1(5 );
725 -- IO5 <= observation_vector_1(5 );
709 -- IO6 <= observation_vector_1(6 );
726 -- IO6 <= observation_vector_1(6 );
710 -- IO7 <= observation_vector_1(7 );
727 -- IO7 <= observation_vector_1(7 );
711 IO8 <= observation_vector_1(8);
728 IO8 <= observation_vector_1(8);
712 IO9 <= observation_vector_1(9);
729 IO9 <= observation_vector_1(9);
713 IO10 <= observation_vector_1(10);
730 IO10 <= observation_vector_1(10);
714 IO11 <= observation_vector_1(11);
731 IO11 <= observation_vector_1(11);
715 WHEN OTHERS => NULL;
732 WHEN OTHERS => NULL;
716 END CASE;
733 END CASE;
717
734
718 END IF;
735 END IF;
719 END PROCESS;
736 END PROCESS;
720 -----------------------------------------------------------------------------
737 -----------------------------------------------------------------------------
721 --
738 --
722 -----------------------------------------------------------------------------
739 -----------------------------------------------------------------------------
723 all_apbo_ext : FOR I IN NB_APB_SLAVE-1+5 DOWNTO 5 GENERATE
740 all_apbo_ext : FOR I IN NB_APB_SLAVE-1+5 DOWNTO 5 GENERATE
724 apbo_ext_not_used : IF I /= 5 AND I /= 6 AND I /= 11 AND I /= 15 GENERATE
741 apbo_ext_not_used : IF I /= 5 AND I /= 6 AND I /= 11 AND I /= 15 GENERATE
725 apbo_ext(I) <= apb_none;
742 apbo_ext(I) <= apb_none;
726 END GENERATE apbo_ext_not_used;
743 END GENERATE apbo_ext_not_used;
727 END GENERATE all_apbo_ext;
744 END GENERATE all_apbo_ext;
728
745
729
746
730 all_ahbo_ext : FOR I IN NB_AHB_SLAVE-1+3 DOWNTO 3 GENERATE
747 all_ahbo_ext : FOR I IN NB_AHB_SLAVE-1+3 DOWNTO 3 GENERATE
731 ahbo_s_ext(I) <= ahbs_none;
748 ahbo_s_ext(I) <= ahbs_none;
732 END GENERATE all_ahbo_ext;
749 END GENERATE all_ahbo_ext;
733
750
734 all_ahbo_m_ext : FOR I IN NB_AHB_MASTER-1+1 DOWNTO 1 GENERATE
751 all_ahbo_m_ext : FOR I IN NB_AHB_MASTER-1+1 DOWNTO 1 GENERATE
735 ahbo_m_ext_not_used : IF I /= 1 AND I /= 2 GENERATE
752 ahbo_m_ext_not_used : IF I /= 1 AND I /= 2 GENERATE
736 ahbo_m_ext(I) <= ahbm_none;
753 ahbo_m_ext(I) <= ahbm_none;
737 END GENERATE ahbo_m_ext_not_used;
754 END GENERATE ahbo_m_ext_not_used;
738 END GENERATE all_ahbo_m_ext;
755 END GENERATE all_ahbo_m_ext;
739
756
740 END beh;
757 END beh;
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@@ -1,517 +1,523
1 ----------------------------------------------------------------------------------
1 ----------------------------------------------------------------------------------
2 -- Company:
2 -- Company:
3 -- Engineer:
3 -- Engineer:
4 --
4 --
5 -- Create Date: 11:17:05 07/02/2012
5 -- Create Date: 11:17:05 07/02/2012
6 -- Design Name:
6 -- Design Name:
7 -- Module Name: apb_lfr_time_management - Behavioral
7 -- Module Name: apb_lfr_time_management - Behavioral
8 -- Project Name:
8 -- Project Name:
9 -- Target Devices:
9 -- Target Devices:
10 -- Tool versions:
10 -- Tool versions:
11 -- Description:
11 -- Description:
12 --
12 --
13 -- Dependencies:
13 -- Dependencies:
14 --
14 --
15 -- Revision:
15 -- Revision:
16 -- Revision 0.01 - File Created
16 -- Revision 0.01 - File Created
17 -- Additional Comments:
17 -- Additional Comments:
18 --
18 --
19 ----------------------------------------------------------------------------------
19 ----------------------------------------------------------------------------------
20 LIBRARY IEEE;
20 LIBRARY IEEE;
21 USE IEEE.STD_LOGIC_1164.ALL;
21 USE IEEE.STD_LOGIC_1164.ALL;
22 USE IEEE.NUMERIC_STD.ALL;
22 USE IEEE.NUMERIC_STD.ALL;
23 LIBRARY grlib;
23 LIBRARY grlib;
24 USE grlib.amba.ALL;
24 USE grlib.amba.ALL;
25 USE grlib.stdlib.ALL;
25 USE grlib.stdlib.ALL;
26 USE grlib.devices.ALL;
26 USE grlib.devices.ALL;
27 LIBRARY lpp;
27 LIBRARY lpp;
28 USE lpp.apb_devices_list.ALL;
28 USE lpp.apb_devices_list.ALL;
29 USE lpp.general_purpose.ALL;
29 USE lpp.general_purpose.ALL;
30 USE lpp.lpp_lfr_management.ALL;
30 USE lpp.lpp_lfr_management.ALL;
31 USE lpp.lpp_lfr_management_apbreg_pkg.ALL;
31 USE lpp.lpp_lfr_management_apbreg_pkg.ALL;
32 USE lpp.lpp_cna.ALL;
32 USE lpp.lpp_cna.ALL;
33 LIBRARY techmap;
33 LIBRARY techmap;
34 USE techmap.gencomp.ALL;
34 USE techmap.gencomp.ALL;
35
35
36
36
37 ENTITY apb_lfr_management IS
37 ENTITY apb_lfr_management IS
38
38
39 GENERIC(
39 GENERIC(
40 tech : INTEGER := 0;
40 tech : INTEGER := 0;
41 pindex : INTEGER := 0; --! APB slave index
41 pindex : INTEGER := 0; --! APB slave index
42 paddr : INTEGER := 0; --! ADDR field of the APB BAR
42 paddr : INTEGER := 0; --! ADDR field of the APB BAR
43 pmask : INTEGER := 16#fff#; --! MASK field of the APB BAR
43 pmask : INTEGER := 16#fff#; --! MASK field of the APB BAR
44 FIRST_DIVISION : INTEGER := 374;
44 -- FIRST_DIVISION : INTEGER := 374;
45 NB_SECOND_DESYNC : INTEGER := 60
45 NB_SECOND_DESYNC : INTEGER := 60
46 );
46 );
47
47
48 PORT (
48 PORT (
49 clk25MHz : IN STD_LOGIC; --! Clock
49 clk25MHz : IN STD_LOGIC; --! Clock
50 resetn_25MHz : IN STD_LOGIC; --! Reset
50 resetn_25MHz : IN STD_LOGIC; --! Reset
51 clk24_576MHz : IN STD_LOGIC; --! secondary clock
51 -- clk24_576MHz : IN STD_LOGIC; --! secondary clock
52 resetn_24_576MHz : IN STD_LOGIC; --! Reset
52 -- resetn_24_576MHz : IN STD_LOGIC; --! Reset
53
53
54 grspw_tick : IN STD_LOGIC; --! grspw signal asserted when a valid time-code is received
54 grspw_tick : IN STD_LOGIC; --! grspw signal asserted when a valid time-code is received
55
55
56 apbi : IN apb_slv_in_type; --! APB slave input signals
56 apbi : IN apb_slv_in_type; --! APB slave input signals
57 apbo : OUT apb_slv_out_type; --! APB slave output signals
57 apbo : OUT apb_slv_out_type; --! APB slave output signals
58 ---------------------------------------------------------------------------
58 ---------------------------------------------------------------------------
59 HK_sample : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
59 HK_sample : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
60 HK_val : IN STD_LOGIC;
60 HK_val : IN STD_LOGIC;
61 HK_sel : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
61 HK_sel : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
62 ---------------------------------------------------------------------------
62 ---------------------------------------------------------------------------
63 DAC_SDO : OUT STD_LOGIC;
63 DAC_SDO : OUT STD_LOGIC;
64 DAC_SCK : OUT STD_LOGIC;
64 DAC_SCK : OUT STD_LOGIC;
65 DAC_SYNC : OUT STD_LOGIC;
65 DAC_SYNC : OUT STD_LOGIC;
66 DAC_CAL_EN : OUT STD_LOGIC;
66 DAC_CAL_EN : OUT STD_LOGIC;
67 ---------------------------------------------------------------------------
67 ---------------------------------------------------------------------------
68 coarse_time : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); --! coarse time
68 coarse_time : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); --! coarse time
69 fine_time : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); --! fine TIME
69 fine_time : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); --! fine TIME
70 ---------------------------------------------------------------------------
70 ---------------------------------------------------------------------------
71 LFR_soft_rstn : OUT STD_LOGIC
71 LFR_soft_rstn : OUT STD_LOGIC
72 );
72 );
73
73
74 END apb_lfr_management;
74 END apb_lfr_management;
75
75
76 ARCHITECTURE Behavioral OF apb_lfr_management IS
76 ARCHITECTURE Behavioral OF apb_lfr_management IS
77
77
78 CONSTANT REVISION : INTEGER := 1;
78 CONSTANT REVISION : INTEGER := 1;
79 CONSTANT pconfig : apb_config_type := (
79 CONSTANT pconfig : apb_config_type := (
80 0 => ahb_device_reg (VENDOR_LPP, LPP_LFR_MANAGEMENT, 0, REVISION, 0),
80 0 => ahb_device_reg (VENDOR_LPP, LPP_LFR_MANAGEMENT, 0, REVISION, 0),
81 1 => apb_iobar(paddr, pmask)
81 1 => apb_iobar(paddr, pmask)
82 );
82 );
83
83
84 TYPE apb_lfr_time_management_Reg IS RECORD
84 TYPE apb_lfr_time_management_Reg IS RECORD
85 ctrl : STD_LOGIC;
85 ctrl : STD_LOGIC;
86 soft_reset : STD_LOGIC;
86 soft_reset : STD_LOGIC;
87 coarse_time_load : STD_LOGIC_VECTOR(30 DOWNTO 0);
87 coarse_time_load : STD_LOGIC_VECTOR(30 DOWNTO 0);
88 coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
88 coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
89 fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0);
89 fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0);
90 LFR_soft_reset : STD_LOGIC;
90 LFR_soft_reset : STD_LOGIC;
91 HK_temp_0 : STD_LOGIC_VECTOR(15 DOWNTO 0);
91 HK_temp_0 : STD_LOGIC_VECTOR(15 DOWNTO 0);
92 HK_temp_1 : STD_LOGIC_VECTOR(15 DOWNTO 0);
92 HK_temp_1 : STD_LOGIC_VECTOR(15 DOWNTO 0);
93 HK_temp_2 : STD_LOGIC_VECTOR(15 DOWNTO 0);
93 HK_temp_2 : STD_LOGIC_VECTOR(15 DOWNTO 0);
94 END RECORD;
94 END RECORD;
95 SIGNAL r : apb_lfr_time_management_Reg;
95 SIGNAL r : apb_lfr_time_management_Reg;
96
96
97 SIGNAL Rdata : STD_LOGIC_VECTOR(31 DOWNTO 0);
97 SIGNAL Rdata : STD_LOGIC_VECTOR(31 DOWNTO 0);
98 SIGNAL force_tick : STD_LOGIC;
98 SIGNAL force_tick : STD_LOGIC;
99 SIGNAL previous_force_tick : STD_LOGIC;
99 SIGNAL previous_force_tick : STD_LOGIC;
100 SIGNAL soft_tick : STD_LOGIC;
100 SIGNAL soft_tick : STD_LOGIC;
101
101
102 SIGNAL coarsetime_reg_updated : STD_LOGIC;
102 SIGNAL coarsetime_reg_updated : STD_LOGIC;
103 SIGNAL coarsetime_reg : STD_LOGIC_VECTOR(30 DOWNTO 0);
103 SIGNAL coarsetime_reg : STD_LOGIC_VECTOR(30 DOWNTO 0);
104
104
105 --SIGNAL coarse_time_new : STD_LOGIC;
105 --SIGNAL coarse_time_new : STD_LOGIC;
106 SIGNAL coarse_time_new_49 : STD_LOGIC;
106 SIGNAL coarse_time_new_49 : STD_LOGIC;
107 SIGNAL coarse_time_49 : STD_LOGIC_VECTOR(31 DOWNTO 0);
107 SIGNAL coarse_time_49 : STD_LOGIC_VECTOR(31 DOWNTO 0);
108 SIGNAL coarse_time_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
108 SIGNAL coarse_time_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
109
109
110 --SIGNAL fine_time_new : STD_LOGIC;
110 --SIGNAL fine_time_new : STD_LOGIC;
111 --SIGNAL fine_time_new_temp : STD_LOGIC;
111 --SIGNAL fine_time_new_temp : STD_LOGIC;
112 SIGNAL fine_time_new_49 : STD_LOGIC;
112 SIGNAL fine_time_new_49 : STD_LOGIC;
113 SIGNAL fine_time_49 : STD_LOGIC_VECTOR(15 DOWNTO 0);
113 SIGNAL fine_time_49 : STD_LOGIC_VECTOR(15 DOWNTO 0);
114 SIGNAL fine_time_s : STD_LOGIC_VECTOR(15 DOWNTO 0);
114 SIGNAL fine_time_s : STD_LOGIC_VECTOR(15 DOWNTO 0);
115 SIGNAL tick : STD_LOGIC;
115 SIGNAL tick : STD_LOGIC;
116 SIGNAL new_timecode : STD_LOGIC;
116 SIGNAL new_timecode : STD_LOGIC;
117 SIGNAL new_coarsetime : STD_LOGIC;
117 SIGNAL new_coarsetime : STD_LOGIC;
118
118
119 SIGNAL time_new_49 : STD_LOGIC;
119 SIGNAL time_new_49 : STD_LOGIC;
120 SIGNAL time_new : STD_LOGIC;
120 SIGNAL time_new : STD_LOGIC;
121
121
122 -----------------------------------------------------------------------------
122 -----------------------------------------------------------------------------
123 SIGNAL force_reset : STD_LOGIC;
123 SIGNAL force_reset : STD_LOGIC;
124 SIGNAL previous_force_reset : STD_LOGIC;
124 SIGNAL previous_force_reset : STD_LOGIC;
125 SIGNAL soft_reset : STD_LOGIC;
125 SIGNAL soft_reset : STD_LOGIC;
126 SIGNAL soft_reset_sync : STD_LOGIC;
126 SIGNAL soft_reset_sync : STD_LOGIC;
127 -----------------------------------------------------------------------------
127 -----------------------------------------------------------------------------
128 SIGNAL HK_sel_s : STD_LOGIC_VECTOR(1 DOWNTO 0);
128 SIGNAL HK_sel_s : STD_LOGIC_VECTOR(1 DOWNTO 0);
129
129
130 SIGNAL previous_fine_time_bit : STD_LOGIC;
130 SIGNAL previous_fine_time_bit : STD_LOGIC;
131
131
132 SIGNAL rstn_LFR_TM : STD_LOGIC;
132 SIGNAL rstn_LFR_TM : STD_LOGIC;
133
133
134 -----------------------------------------------------------------------------
134 -----------------------------------------------------------------------------
135 -- DAC
135 -- DAC
136 -----------------------------------------------------------------------------
136 -----------------------------------------------------------------------------
137 CONSTANT PRESZ : INTEGER := 8;
137 CONSTANT PRESZ : INTEGER := 8;
138 CONSTANT CPTSZ : INTEGER := 16;
138 CONSTANT CPTSZ : INTEGER := 16;
139 CONSTANT datawidth : INTEGER := 18;
139 CONSTANT datawidth : INTEGER := 18;
140 CONSTANT dacresolution : INTEGER := 12;
140 CONSTANT dacresolution : INTEGER := 12;
141 CONSTANT abits : INTEGER := 8;
141 CONSTANT abits : INTEGER := 8;
142
142
143 SIGNAL pre : STD_LOGIC_VECTOR(PRESZ-1 DOWNTO 0);
143 SIGNAL pre : STD_LOGIC_VECTOR(PRESZ-1 DOWNTO 0);
144 SIGNAL N : STD_LOGIC_VECTOR(CPTSZ-1 DOWNTO 0);
144 SIGNAL N : STD_LOGIC_VECTOR(CPTSZ-1 DOWNTO 0);
145 SIGNAL Reload : STD_LOGIC;
145 SIGNAL Reload : STD_LOGIC;
146 SIGNAL DATA_IN : STD_LOGIC_VECTOR(datawidth-1 DOWNTO 0);
146 SIGNAL DATA_IN : STD_LOGIC_VECTOR(datawidth-1 DOWNTO 0);
147 SIGNAL WEN : STD_LOGIC;
147 SIGNAL WEN : STD_LOGIC;
148 SIGNAL LOAD_ADDRESSN : STD_LOGIC;
148 SIGNAL LOAD_ADDRESSN : STD_LOGIC;
149 SIGNAL ADDRESS_IN : STD_LOGIC_VECTOR(abits-1 DOWNTO 0);
149 SIGNAL ADDRESS_IN : STD_LOGIC_VECTOR(abits-1 DOWNTO 0);
150 SIGNAL ADDRESS_OUT : STD_LOGIC_VECTOR(abits-1 DOWNTO 0);
150 SIGNAL ADDRESS_OUT : STD_LOGIC_VECTOR(abits-1 DOWNTO 0);
151 SIGNAL INTERLEAVED : STD_LOGIC;
151 SIGNAL INTERLEAVED : STD_LOGIC;
152 SIGNAL DAC_CFG : STD_LOGIC_VECTOR(3 DOWNTO 0);
152 SIGNAL DAC_CFG : STD_LOGIC_VECTOR(3 DOWNTO 0);
153 SIGNAL DAC_CAL_EN_s : STD_LOGIC;
153 SIGNAL DAC_CAL_EN_s : STD_LOGIC;
154
154
155 BEGIN
155 BEGIN
156
156
157 LFR_soft_rstn <= NOT r.LFR_soft_reset;
157 LFR_soft_rstn <= NOT r.LFR_soft_reset;
158
158
159 PROCESS(resetn_25MHz, clk25MHz)
159 PROCESS(resetn_25MHz, clk25MHz)
160 VARIABLE paddr : STD_LOGIC_VECTOR(7 DOWNTO 2);
160 VARIABLE paddr : STD_LOGIC_VECTOR(7 DOWNTO 2);
161 BEGIN
161 BEGIN
162
162
163 IF resetn_25MHz = '0' THEN
163 IF resetn_25MHz = '0' THEN
164 Rdata <= (OTHERS => '0');
164 Rdata <= (OTHERS => '0');
165 r.coarse_time_load <= (OTHERS => '0');
165 r.coarse_time_load <= (OTHERS => '0');
166 r.soft_reset <= '0';
166 r.soft_reset <= '0';
167 r.ctrl <= '0';
167 r.ctrl <= '0';
168 r.LFR_soft_reset <= '1';
168 r.LFR_soft_reset <= '1';
169
169
170 force_tick <= '0';
170 force_tick <= '0';
171 previous_force_tick <= '0';
171 previous_force_tick <= '0';
172 soft_tick <= '0';
172 soft_tick <= '0';
173
173
174 coarsetime_reg_updated <= '0';
174 coarsetime_reg_updated <= '0';
175 --DAC
175 --DAC
176 pre <= (OTHERS => '1');
176 pre <= (OTHERS => '1');
177 N <= (OTHERS => '1');
177 N <= (OTHERS => '1');
178 Reload <= '1';
178 Reload <= '1';
179 DATA_IN <= (OTHERS => '0');
179 DATA_IN <= (OTHERS => '0');
180 WEN <= '1';
180 WEN <= '1';
181 LOAD_ADDRESSN <= '1';
181 LOAD_ADDRESSN <= '1';
182 ADDRESS_IN <= (OTHERS => '1');
182 ADDRESS_IN <= (OTHERS => '1');
183 INTERLEAVED <= '0';
183 INTERLEAVED <= '0';
184 DAC_CFG <= (OTHERS => '0');
184 DAC_CFG <= (OTHERS => '0');
185 --
185 --
186 DAC_CAL_EN_s <= '0';
186 DAC_CAL_EN_s <= '0';
187 ELSIF clk25MHz'EVENT AND clk25MHz = '1' THEN
187 ELSIF clk25MHz'EVENT AND clk25MHz = '1' THEN
188 coarsetime_reg_updated <= '0';
188 coarsetime_reg_updated <= '0';
189
189
190 force_tick <= r.ctrl;
190 force_tick <= r.ctrl;
191 previous_force_tick <= force_tick;
191 previous_force_tick <= force_tick;
192 IF (previous_force_tick = '0') AND (force_tick = '1') THEN
192 IF (previous_force_tick = '0') AND (force_tick = '1') THEN
193 soft_tick <= '1';
193 soft_tick <= '1';
194 ELSE
194 ELSE
195 soft_tick <= '0';
195 soft_tick <= '0';
196 END IF;
196 END IF;
197
197
198 force_reset <= r.soft_reset;
198 force_reset <= r.soft_reset;
199 previous_force_reset <= force_reset;
199 previous_force_reset <= force_reset;
200 IF (previous_force_reset = '0') AND (force_reset = '1') THEN
200 IF (previous_force_reset = '0') AND (force_reset = '1') THEN
201 soft_reset <= '1';
201 soft_reset <= '1';
202 ELSE
202 ELSE
203 soft_reset <= '0';
203 soft_reset <= '0';
204 END IF;
204 END IF;
205
205
206 paddr := "000000";
206 paddr := "000000";
207 paddr(7 DOWNTO 2) := apbi.paddr(7 DOWNTO 2);
207 paddr(7 DOWNTO 2) := apbi.paddr(7 DOWNTO 2);
208 Rdata <= (OTHERS => '0');
208 Rdata <= (OTHERS => '0');
209
209
210 LOAD_ADDRESSN <= '1';
210 LOAD_ADDRESSN <= '1';
211 WEN <= '1';
211 WEN <= '1';
212
212
213 IF apbi.psel(pindex) = '1' THEN
213 IF apbi.psel(pindex) = '1' THEN
214 --APB READ OP
214 --APB READ OP
215 CASE paddr(7 DOWNTO 2) IS
215 CASE paddr(7 DOWNTO 2) IS
216 WHEN ADDR_LFR_MANAGMENT_CONTROL =>
216 WHEN ADDR_LFR_MANAGMENT_CONTROL =>
217 Rdata(0) <= r.ctrl;
217 Rdata(0) <= r.ctrl;
218 Rdata(1) <= r.soft_reset;
218 Rdata(1) <= r.soft_reset;
219 Rdata(2) <= r.LFR_soft_reset;
219 Rdata(2) <= r.LFR_soft_reset;
220 Rdata(31 DOWNTO 3) <= (OTHERS => '0');
220 Rdata(31 DOWNTO 3) <= (OTHERS => '0');
221 WHEN ADDR_LFR_MANAGMENT_TIME_LOAD =>
221 WHEN ADDR_LFR_MANAGMENT_TIME_LOAD =>
222 Rdata(30 DOWNTO 0) <= r.coarse_time_load(30 DOWNTO 0);
222 Rdata(30 DOWNTO 0) <= r.coarse_time_load(30 DOWNTO 0);
223 WHEN ADDR_LFR_MANAGMENT_TIME_COARSE =>
223 WHEN ADDR_LFR_MANAGMENT_TIME_COARSE =>
224 Rdata(31 DOWNTO 0) <= r.coarse_time(31 DOWNTO 0);
224 Rdata(31 DOWNTO 0) <= r.coarse_time(31 DOWNTO 0);
225 WHEN ADDR_LFR_MANAGMENT_TIME_FINE =>
225 WHEN ADDR_LFR_MANAGMENT_TIME_FINE =>
226 Rdata(31 DOWNTO 16) <= (OTHERS => '0');
226 Rdata(31 DOWNTO 16) <= (OTHERS => '0');
227 Rdata(15 DOWNTO 0) <= r.fine_time(15 DOWNTO 0);
227 Rdata(15 DOWNTO 0) <= r.fine_time(15 DOWNTO 0);
228 WHEN ADDR_LFR_MANAGMENT_HK_TEMP_0 =>
228 WHEN ADDR_LFR_MANAGMENT_HK_TEMP_0 =>
229 Rdata(31 DOWNTO 16) <= (OTHERS => '0');
229 Rdata(31 DOWNTO 16) <= (OTHERS => '0');
230 Rdata(15 DOWNTO 0) <= r.HK_temp_0;
230 Rdata(15 DOWNTO 0) <= r.HK_temp_0;
231 WHEN ADDR_LFR_MANAGMENT_HK_TEMP_1 =>
231 WHEN ADDR_LFR_MANAGMENT_HK_TEMP_1 =>
232 Rdata(31 DOWNTO 16) <= (OTHERS => '0');
232 Rdata(31 DOWNTO 16) <= (OTHERS => '0');
233 Rdata(15 DOWNTO 0) <= r.HK_temp_1;
233 Rdata(15 DOWNTO 0) <= r.HK_temp_1;
234 WHEN ADDR_LFR_MANAGMENT_HK_TEMP_2 =>
234 WHEN ADDR_LFR_MANAGMENT_HK_TEMP_2 =>
235 Rdata(31 DOWNTO 16) <= (OTHERS => '0');
235 Rdata(31 DOWNTO 16) <= (OTHERS => '0');
236 Rdata(15 DOWNTO 0) <= r.HK_temp_2;
236 Rdata(15 DOWNTO 0) <= r.HK_temp_2;
237 WHEN ADDR_LFR_MANAGMENT_DAC_CONTROL =>
237 WHEN ADDR_LFR_MANAGMENT_DAC_CONTROL =>
238 Rdata(3 DOWNTO 0) <= DAC_CFG;
238 Rdata(3 DOWNTO 0) <= DAC_CFG;
239 Rdata(4) <= Reload;
239 Rdata(4) <= Reload;
240 Rdata(5) <= INTERLEAVED;
240 Rdata(5) <= INTERLEAVED;
241 Rdata(6) <= DAC_CAL_EN_s;
241 Rdata(6) <= DAC_CAL_EN_s;
242 Rdata(31 DOWNTO 7) <= (OTHERS => '0');
242 Rdata(31 DOWNTO 7) <= (OTHERS => '0');
243 WHEN ADDR_LFR_MANAGMENT_DAC_PRE =>
243 WHEN ADDR_LFR_MANAGMENT_DAC_PRE =>
244 Rdata(PRESZ-1 DOWNTO 0) <= pre;
244 Rdata(PRESZ-1 DOWNTO 0) <= pre;
245 Rdata(31 DOWNTO PRESZ) <= (OTHERS => '0');
245 Rdata(31 DOWNTO PRESZ) <= (OTHERS => '0');
246 WHEN ADDR_LFR_MANAGMENT_DAC_N =>
246 WHEN ADDR_LFR_MANAGMENT_DAC_N =>
247 Rdata(CPTSZ-1 DOWNTO 0) <= N;
247 Rdata(CPTSZ-1 DOWNTO 0) <= N;
248 Rdata(31 DOWNTO CPTSZ) <= (OTHERS => '0');
248 Rdata(31 DOWNTO CPTSZ) <= (OTHERS => '0');
249 WHEN ADDR_LFR_MANAGMENT_DAC_ADDRESS_OUT =>
249 WHEN ADDR_LFR_MANAGMENT_DAC_ADDRESS_OUT =>
250 Rdata(abits-1 DOWNTO 0) <= ADDRESS_OUT;
250 Rdata(abits-1 DOWNTO 0) <= ADDRESS_OUT;
251 Rdata(31 DOWNTO abits) <= (OTHERS => '0');
251 Rdata(31 DOWNTO abits) <= (OTHERS => '0');
252 WHEN ADDR_LFR_MANAGMENT_DAC_DATA_IN =>
252 WHEN ADDR_LFR_MANAGMENT_DAC_DATA_IN =>
253 Rdata(datawidth-1 DOWNTO 0) <= DATA_IN;
253 Rdata(datawidth-1 DOWNTO 0) <= DATA_IN;
254 Rdata(31 DOWNTO datawidth) <= (OTHERS => '0');
254 Rdata(31 DOWNTO datawidth) <= (OTHERS => '0');
255 WHEN OTHERS =>
255 WHEN OTHERS =>
256 Rdata(31 DOWNTO 0) <= (OTHERS => '0');
256 Rdata(31 DOWNTO 0) <= (OTHERS => '0');
257 END CASE;
257 END CASE;
258
258
259 --APB Write OP
259 --APB Write OP
260 IF (apbi.pwrite AND apbi.penable) = '1' THEN
260 IF (apbi.pwrite AND apbi.penable) = '1' THEN
261 CASE paddr(7 DOWNTO 2) IS
261 CASE paddr(7 DOWNTO 2) IS
262 WHEN ADDR_LFR_MANAGMENT_CONTROL =>
262 WHEN ADDR_LFR_MANAGMENT_CONTROL =>
263 r.ctrl <= apbi.pwdata(0);
263 r.ctrl <= apbi.pwdata(0);
264 r.soft_reset <= apbi.pwdata(1);
264 r.soft_reset <= apbi.pwdata(1);
265 r.LFR_soft_reset <= apbi.pwdata(2);
265 r.LFR_soft_reset <= apbi.pwdata(2);
266 WHEN ADDR_LFR_MANAGMENT_TIME_LOAD =>
266 WHEN ADDR_LFR_MANAGMENT_TIME_LOAD =>
267 r.coarse_time_load <= apbi.pwdata(30 DOWNTO 0);
267 r.coarse_time_load <= apbi.pwdata(30 DOWNTO 0);
268 coarsetime_reg_updated <= '1';
268 coarsetime_reg_updated <= '1';
269 WHEN ADDR_LFR_MANAGMENT_DAC_CONTROL =>
269 WHEN ADDR_LFR_MANAGMENT_DAC_CONTROL =>
270 DAC_CFG <= apbi.pwdata(3 DOWNTO 0);
270 DAC_CFG <= apbi.pwdata(3 DOWNTO 0);
271 Reload <= apbi.pwdata(4);
271 Reload <= apbi.pwdata(4);
272 INTERLEAVED <= apbi.pwdata(5);
272 INTERLEAVED <= apbi.pwdata(5);
273 DAC_CAL_EN_s <= apbi.pwdata(6);
273 DAC_CAL_EN_s <= apbi.pwdata(6);
274 WHEN ADDR_LFR_MANAGMENT_DAC_PRE =>
274 WHEN ADDR_LFR_MANAGMENT_DAC_PRE =>
275 pre <= apbi.pwdata(PRESZ-1 DOWNTO 0);
275 pre <= apbi.pwdata(PRESZ-1 DOWNTO 0);
276 WHEN ADDR_LFR_MANAGMENT_DAC_N =>
276 WHEN ADDR_LFR_MANAGMENT_DAC_N =>
277 N <= apbi.pwdata(CPTSZ-1 DOWNTO 0);
277 N <= apbi.pwdata(CPTSZ-1 DOWNTO 0);
278 WHEN ADDR_LFR_MANAGMENT_DAC_ADDRESS_OUT =>
278 WHEN ADDR_LFR_MANAGMENT_DAC_ADDRESS_OUT =>
279 ADDRESS_IN <= apbi.pwdata(abits-1 DOWNTO 0);
279 ADDRESS_IN <= apbi.pwdata(abits-1 DOWNTO 0);
280 LOAD_ADDRESSN <= '0';
280 LOAD_ADDRESSN <= '0';
281 WHEN ADDR_LFR_MANAGMENT_DAC_DATA_IN =>
281 WHEN ADDR_LFR_MANAGMENT_DAC_DATA_IN =>
282 DATA_IN <= apbi.pwdata(datawidth-1 DOWNTO 0);
282 DATA_IN <= apbi.pwdata(datawidth-1 DOWNTO 0);
283 WEN <= '0';
283 WEN <= '0';
284
284
285 WHEN OTHERS =>
285 WHEN OTHERS =>
286 NULL;
286 NULL;
287 END CASE;
287 END CASE;
288 ELSE
288 ELSE
289 IF r.ctrl = '1' THEN
289 IF r.ctrl = '1' THEN
290 r.ctrl <= '0';
290 r.ctrl <= '0';
291 END IF;
291 END IF;
292 IF r.soft_reset = '1' THEN
292 IF r.soft_reset = '1' THEN
293 r.soft_reset <= '0';
293 r.soft_reset <= '0';
294 END IF;
294 END IF;
295 END IF;
295 END IF;
296
296
297 END IF;
297 END IF;
298
298
299 END IF;
299 END IF;
300 END PROCESS;
300 END PROCESS;
301
301
302 apbo.pirq <= (OTHERS => '0');
302 apbo.pirq <= (OTHERS => '0');
303 apbo.prdata <= Rdata;
303 apbo.prdata <= Rdata;
304 apbo.pconfig <= pconfig;
304 apbo.pconfig <= pconfig;
305 apbo.pindex <= pindex;
305 apbo.pindex <= pindex;
306
306
307
308
309
310
311
312
313
314
315
316
317
318
319
307 -----------------------------------------------------------------------------
320 -----------------------------------------------------------------------------
308 -- IN
321 -- IN
309 coarse_time <= r.coarse_time;
322 coarse_time <= r.coarse_time;
310 fine_time <= r.fine_time;
323 fine_time <= r.fine_time;
311 coarsetime_reg <= r.coarse_time_load;
324 coarsetime_reg <= r.coarse_time_load;
312 -----------------------------------------------------------------------------
325 -----------------------------------------------------------------------------
313
326
314 -----------------------------------------------------------------------------
327 -----------------------------------------------------------------------------
315 -- OUT
328 -- OUT
316 r.coarse_time <= coarse_time_s;
329 r.coarse_time <= coarse_time_s;
317 r.fine_time <= fine_time_s;
330 r.fine_time <= fine_time_s;
318 -----------------------------------------------------------------------------
331 -----------------------------------------------------------------------------
319
332
320 -----------------------------------------------------------------------------
333 -----------------------------------------------------------------------------
321 tick <= grspw_tick OR soft_tick;
334 tick <= grspw_tick OR soft_tick;
322
335
323 SYNC_VALID_BIT_1 : SYNC_VALID_BIT
336 --SYNC_VALID_BIT_1 : SYNC_VALID_BIT
324 GENERIC MAP (
337 -- GENERIC MAP (
325 NB_FF_OF_SYNC => 2)
338 -- NB_FF_OF_SYNC => 2)
326 PORT MAP (
339 -- PORT MAP (
327 clk_in => clk25MHz,
340 -- clk_in => clk25MHz,
328 rstn_in => resetn_25MHz,
341 -- rstn_in => resetn_25MHz,
329 clk_out => clk24_576MHz,
342 -- clk_out => clk24_576MHz,
330 rstn_out => resetn_24_576MHz,
343 -- rstn_out => resetn_24_576MHz,
331 sin => tick,
344 -- sin => tick,
332 sout => new_timecode);
345 -- sout => new_timecode);
346 new_timecode <= tick;
333
347
334 SYNC_VALID_BIT_2 : SYNC_VALID_BIT
348 --SYNC_VALID_BIT_2 : SYNC_VALID_BIT
335 GENERIC MAP (
336 NB_FF_OF_SYNC => 2)
337 PORT MAP (
338 clk_in => clk25MHz,
339 rstn_in => resetn_25MHz,
340 clk_out => clk24_576MHz,
341 rstn_out => resetn_24_576MHz,
342 sin => coarsetime_reg_updated,
343 sout => new_coarsetime);
344
345 SYNC_VALID_BIT_3 : SYNC_VALID_BIT
346 GENERIC MAP (
347 NB_FF_OF_SYNC => 2)
348 PORT MAP (
349 clk_in => clk25MHz,
350 rstn_in => resetn_25MHz,
351 clk_out => clk24_576MHz,
352 rstn_out => resetn_24_576MHz,
353 sin => soft_reset,
354 sout => soft_reset_sync);
355
356 -----------------------------------------------------------------------------
357 --SYNC_FF_1 : SYNC_FF
358 -- GENERIC MAP (
349 -- GENERIC MAP (
359 -- NB_FF_OF_SYNC => 2)
350 -- NB_FF_OF_SYNC => 2)
360 -- PORT MAP (
351 -- PORT MAP (
361 -- clk => clk25MHz,
352 -- clk_in => clk25MHz,
362 -- rstn => resetn,
353 -- rstn_in => resetn_25MHz,
363 -- A => fine_time_new_49,
354 -- clk_out => clk24_576MHz,
364 -- A_sync => fine_time_new_temp);
355 -- rstn_out => resetn_24_576MHz,
356 -- sin => coarsetime_reg_updated,
357 -- sout => new_coarsetime);
358
359 new_coarsetime <= coarsetime_reg_updated;
360
361 --SYNC_VALID_BIT_3 : SYNC_VALID_BIT
362 -- GENERIC MAP (
363 -- NB_FF_OF_SYNC => 2)
364 -- PORT MAP (
365 -- clk_in => clk25MHz,
366 -- rstn_in => resetn_25MHz,
367 -- clk_out => clk24_576MHz,
368 -- rstn_out => resetn_24_576MHz,
369 -- sin => soft_reset,
370 -- sout => soft_reset_sync);
371
365
372
366 --lpp_front_detection_1 : lpp_front_detection
373 -----------------------------------------------------------------------------
367 -- PORT MAP (
374 time_new_49 <= coarse_time_new_49 OR fine_time_new_49;
368 -- clk => clk25MHz,
369 -- rstn => resetn,
370 -- sin => fine_time_new_temp,
371 -- sout => fine_time_new);
372
375
373 --SYNC_VALID_BIT_4 : SYNC_VALID_BIT
376 --SYNC_VALID_BIT_4 : SYNC_VALID_BIT
374 -- GENERIC MAP (
377 -- GENERIC MAP (
375 -- NB_FF_OF_SYNC => 2)
378 -- NB_FF_OF_SYNC => 2)
376 -- PORT MAP (
379 -- PORT MAP (
377 -- clk_in => clk24_576MHz,
380 -- clk_in => clk24_576MHz,
381 -- rstn_in => resetn_24_576MHz,
378 -- clk_out => clk25MHz,
382 -- clk_out => clk25MHz,
379 -- rstn => resetn,
383 -- rstn_out => resetn_25MHz,
380 -- sin => coarse_time_new_49,
384 -- sin => time_new_49,
381 -- sout => coarse_time_new);
385 -- sout => time_new);
382
383 time_new_49 <= coarse_time_new_49 OR fine_time_new_49;
384
386
385 SYNC_VALID_BIT_4 : SYNC_VALID_BIT
387 time_new <= time_new_49;
386 GENERIC MAP (
387 NB_FF_OF_SYNC => 2)
388 PORT MAP (
389 clk_in => clk24_576MHz,
390 rstn_in => resetn_24_576MHz,
391 clk_out => clk25MHz,
392 rstn_out => resetn_25MHz,
393 sin => time_new_49,
394 sout => time_new);
395
396
397
388
398 PROCESS (clk25MHz, resetn_25MHz)
389 --PROCESS (clk25MHz, resetn_25MHz)
399 BEGIN -- PROCESS
390 --BEGIN -- PROCESS
400 IF resetn_25MHz = '0' THEN -- asynchronous reset (active low)
391 -- IF resetn_25MHz = '0' THEN -- asynchronous reset (active low)
401 fine_time_s <= (OTHERS => '0');
392 -- fine_time_s <= (OTHERS => '0');
402 coarse_time_s <= (OTHERS => '0');
393 -- coarse_time_s <= (OTHERS => '0');
403 ELSIF clk25MHz'EVENT AND clk25MHz = '1' THEN -- rising clock edge
394 -- ELSIF clk25MHz'EVENT AND clk25MHz = '1' THEN -- rising clock edge
404 IF time_new = '1' THEN
395 -- IF time_new = '1' THEN
405 fine_time_s <= fine_time_49;
396 -- END IF;
406 coarse_time_s <= coarse_time_49;
397 -- END IF;
407 END IF;
398 --END PROCESS;
408 END IF;
399
409 END PROCESS;
400 fine_time_s <= fine_time_49;
401 coarse_time_s <= coarse_time_49;
402
410
403
411
404 rstn_LFR_TM <= '0' WHEN resetn_25MHz = '0' ELSE
412 rstn_LFR_TM <= '0' WHEN resetn_24_576MHz = '0' ELSE
405 '0' WHEN soft_reset = '1' ELSE
413 '0' WHEN soft_reset_sync = '1' ELSE
414 '1';
406 '1';
415
407
416
417 -----------------------------------------------------------------------------
408 -----------------------------------------------------------------------------
418 -- LFR_TIME_MANAGMENT
409 -- LFR_TIME_MANAGMENT
419 -----------------------------------------------------------------------------
410 -----------------------------------------------------------------------------
420 lfr_time_management_1 : lfr_time_management
411 lfr_time_management_1 : lfr_time_management
421 GENERIC MAP (
412 GENERIC MAP (
422 FIRST_DIVISION => FIRST_DIVISION,
413 --FIRST_DIVISION => FIRST_DIVISION,
423 NB_SECOND_DESYNC => NB_SECOND_DESYNC)
414 NB_SECOND_DESYNC => NB_SECOND_DESYNC)
424 PORT MAP (
415 PORT MAP (
425 clk => clk24_576MHz,
416 clk => clk25MHz,
426 rstn => rstn_LFR_TM,
417 rstn => rstn_LFR_TM,
427
418
428 tick => new_timecode,
419 tick => new_timecode,
429 new_coarsetime => new_coarsetime,
420 new_coarsetime => new_coarsetime,
430 coarsetime_reg => coarsetime_reg(30 DOWNTO 0),
421 coarsetime_reg => coarsetime_reg(30 DOWNTO 0),
431
422
432 fine_time => fine_time_49,
423 fine_time => fine_time_49,
433 fine_time_new => fine_time_new_49,
424 fine_time_new => fine_time_new_49,
434 coarse_time => coarse_time_49,
425 coarse_time => coarse_time_49,
435 coarse_time_new => coarse_time_new_49);
426 coarse_time_new => coarse_time_new_49);
436
427
428
429
437 -----------------------------------------------------------------------------
430 -----------------------------------------------------------------------------
438 -- HK
431 -- HK
439 -----------------------------------------------------------------------------
432 -----------------------------------------------------------------------------
440
433
441 PROCESS (clk25MHz, resetn_25MHz)
434 PROCESS (clk25MHz, resetn_25MHz)
442 CONSTANT BIT_FREQUENCY_UPDATE : INTEGER := 14; -- freq = 2^(16-BIT)
435 CONSTANT BIT_FREQUENCY_UPDATE : INTEGER := 14; -- freq = 2^(16-BIT)
443 -- for each HK, the update frequency is freq/3
436 -- for each HK, the update frequency is freq/3
444 --
437 --
445 -- for 14, the update frequency is
438 -- for 14, the update frequency is
446 -- 4Hz and update for each
439 -- 4Hz and update for each
447 -- HK is 1.33Hz
440 -- HK is 1.33Hz
448 BEGIN -- PROCESS
441 BEGIN -- PROCESS
449 IF resetn_25MHz = '0' THEN -- asynchronous reset (active low)
442 IF resetn_25MHz = '0' THEN -- asynchronous reset (active low)
450
443
451 r.HK_temp_0 <= (OTHERS => '0');
444 r.HK_temp_0 <= (OTHERS => '0');
452 r.HK_temp_1 <= (OTHERS => '0');
445 r.HK_temp_1 <= (OTHERS => '0');
453 r.HK_temp_2 <= (OTHERS => '0');
446 r.HK_temp_2 <= (OTHERS => '0');
454
447
455 HK_sel_s <= "00";
448 HK_sel_s <= "00";
456
449
457 previous_fine_time_bit <= '0';
450 previous_fine_time_bit <= '0';
458
451
459 ELSIF clk25MHz'EVENT AND clk25MHz = '1' THEN -- rising clock edge
452 ELSIF clk25MHz'EVENT AND clk25MHz = '1' THEN -- rising clock edge
460
453
461 IF HK_val = '1' THEN
454 IF HK_val = '1' THEN
462 IF previous_fine_time_bit = NOT(fine_time_s(BIT_FREQUENCY_UPDATE)) THEN
455 IF previous_fine_time_bit = NOT(fine_time_s(BIT_FREQUENCY_UPDATE)) THEN
463 previous_fine_time_bit <= fine_time_s(BIT_FREQUENCY_UPDATE);
456 previous_fine_time_bit <= fine_time_s(BIT_FREQUENCY_UPDATE);
464 CASE HK_sel_s IS
457 CASE HK_sel_s IS
465 WHEN "00" =>
458 WHEN "00" =>
466 r.HK_temp_0 <= HK_sample;
459 r.HK_temp_0 <= HK_sample;
467 HK_sel_s <= "01";
460 HK_sel_s <= "01";
468 WHEN "01" =>
461 WHEN "01" =>
469 r.HK_temp_1 <= HK_sample;
462 r.HK_temp_1 <= HK_sample;
470 HK_sel_s <= "10";
463 HK_sel_s <= "10";
471 WHEN "10" =>
464 WHEN "10" =>
472 r.HK_temp_2 <= HK_sample;
465 r.HK_temp_2 <= HK_sample;
473 HK_sel_s <= "00";
466 HK_sel_s <= "00";
474 WHEN OTHERS => NULL;
467 WHEN OTHERS => NULL;
475 END CASE;
468 END CASE;
476 END IF;
469 END IF;
477 END IF;
470 END IF;
478
471
479 END IF;
472 END IF;
480 END PROCESS;
473 END PROCESS;
481
474
482 HK_sel <= HK_sel_s;
475 HK_sel <= HK_sel_s;
483
476
477
478
479
480
481
482
483
484
485
486
487
488
489
484 -----------------------------------------------------------------------------
490 -----------------------------------------------------------------------------
485 -- DAC
491 -- DAC
486 -----------------------------------------------------------------------------
492 -----------------------------------------------------------------------------
487 cal : lfr_cal_driver
493 cal : lfr_cal_driver
488 GENERIC MAP(
494 GENERIC MAP(
489 tech => tech,
495 tech => tech,
490 PRESZ => PRESZ,
496 PRESZ => PRESZ,
491 CPTSZ => CPTSZ,
497 CPTSZ => CPTSZ,
492 datawidth => datawidth,
498 datawidth => datawidth,
493 abits => abits
499 abits => abits
494 )
500 )
495 PORT MAP(
501 PORT MAP(
496 clk => clk25MHz,
502 clk => clk25MHz,
497 rstn => resetn_25MHz,
503 rstn => resetn_25MHz,
498
504
499 pre => pre,
505 pre => pre,
500 N => N,
506 N => N,
501 Reload => Reload,
507 Reload => Reload,
502 DATA_IN => DATA_IN,
508 DATA_IN => DATA_IN,
503 WEN => WEN,
509 WEN => WEN,
504 LOAD_ADDRESSN => LOAD_ADDRESSN,
510 LOAD_ADDRESSN => LOAD_ADDRESSN,
505 ADDRESS_IN => ADDRESS_IN,
511 ADDRESS_IN => ADDRESS_IN,
506 ADDRESS_OUT => ADDRESS_OUT,
512 ADDRESS_OUT => ADDRESS_OUT,
507 INTERLEAVED => INTERLEAVED,
513 INTERLEAVED => INTERLEAVED,
508 DAC_CFG => DAC_CFG,
514 DAC_CFG => DAC_CFG,
509
515
510 SYNC => DAC_SYNC,
516 SYNC => DAC_SYNC,
511 DOUT => DAC_SDO,
517 DOUT => DAC_SDO,
512 SCLK => DAC_SCK,
518 SCLK => DAC_SCK,
513 SMPCLK => OPEN --DAC_SMPCLK
519 SMPCLK => OPEN --DAC_SMPCLK
514 );
520 );
515
521
516 DAC_CAL_EN <= DAC_CAL_EN_s;
522 DAC_CAL_EN <= DAC_CAL_EN_s;
517 END Behavioral; No newline at end of file
523 END Behavioral;
Show file before | Show file after | Hide comments
@@ -1,123 +1,124
1 LIBRARY IEEE;
1 LIBRARY IEEE;
2 USE IEEE.STD_LOGIC_1164.ALL;
2 USE IEEE.STD_LOGIC_1164.ALL;
3 USE IEEE.NUMERIC_STD.ALL;
3 USE IEEE.NUMERIC_STD.ALL;
4
4
5 LIBRARY lpp;
5 LIBRARY lpp;
6 USE lpp.general_purpose.ALL;
6 USE lpp.general_purpose.ALL;
7
7
8 ENTITY coarse_time_counter IS
8 ENTITY coarse_time_counter IS
9 GENERIC (
9 GENERIC (
10 NB_SECOND_DESYNC : INTEGER := 60);
10 NB_SECOND_DESYNC : INTEGER := 60);
11
11
12 PORT (
12 PORT (
13 clk : IN STD_LOGIC;
13 clk : IN STD_LOGIC;
14 rstn : IN STD_LOGIC;
14 rstn : IN STD_LOGIC;
15
15
16 tick : IN STD_LOGIC;
16 tick : IN STD_LOGIC;
17 set_TCU : IN STD_LOGIC;
17 set_TCU : IN STD_LOGIC;
18 new_TCU : IN STD_LOGIC;
18 new_TCU : IN STD_LOGIC;
19 set_TCU_value : IN STD_LOGIC_VECTOR(30 DOWNTO 0);
19 set_TCU_value : IN STD_LOGIC_VECTOR(30 DOWNTO 0);
20 CT_add1 : IN STD_LOGIC;
20 CT_add1 : IN STD_LOGIC;
21 fsm_desync : IN STD_LOGIC;
21 fsm_desync : IN STD_LOGIC;
22 FT_max : IN STD_LOGIC;
22 FT_max : IN STD_LOGIC;
23
23
24 coarse_time : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
24 coarse_time : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
25 coarse_time_new : OUT STD_LOGIC
25 coarse_time_new : OUT STD_LOGIC
26
26
27 );
27 );
28
28
29 END coarse_time_counter;
29 END coarse_time_counter;
30
30
31 ARCHITECTURE beh OF coarse_time_counter IS
31 ARCHITECTURE beh OF coarse_time_counter IS
32
32
33 SIGNAL add1_bit31 : STD_LOGIC;
33 SIGNAL add1_bit31 : STD_LOGIC;
34 SIGNAL nb_second_counter : STD_LOGIC_VECTOR(5 DOWNTO 0);
34 SIGNAL nb_second_counter : STD_LOGIC_VECTOR(5 DOWNTO 0);
35 SIGNAL coarse_time_new_counter : STD_LOGIC;
35 SIGNAL coarse_time_new_counter : STD_LOGIC;
36 SIGNAL coarse_time_31 : STD_LOGIC;
36 SIGNAL coarse_time_31 : STD_LOGIC;
37 SIGNAL coarse_time_31_reg : STD_LOGIC;
37 SIGNAL coarse_time_31_reg : STD_LOGIC;
38
38
39 SIGNAL set_synchronized : STD_LOGIC;
39 SIGNAL set_synchronized : STD_LOGIC;
40 SIGNAL set_synchronized_value : STD_LOGIC_VECTOR(5 DOWNTO 0);
40 SIGNAL set_synchronized_value : STD_LOGIC_VECTOR(5 DOWNTO 0);
41
41
42 --CONSTANT NB_SECOND_DESYNC : INTEGER := 4; -- TODO : 60 ;
42 --CONSTANT NB_SECOND_DESYNC : INTEGER := 4; -- TODO : 60 ;
43 SIGNAL set_TCU_reg : STD_LOGIC;
43 SIGNAL set_TCU_reg : STD_LOGIC;
44
44
45 BEGIN -- beh
45 BEGIN -- beh
46
46
47 -----------------------------------------------------------------------------
47 -----------------------------------------------------------------------------
48 -- COARSE_TIME( 30 DOWNTO 0)
48 -- COARSE_TIME( 30 DOWNTO 0)
49 -----------------------------------------------------------------------------
49 -----------------------------------------------------------------------------
50 counter_1 : general_counter
50 counter_1 : general_counter
51 GENERIC MAP (
51 GENERIC MAP (
52 CYCLIC => '1',
52 CYCLIC => '1',
53 NB_BITS_COUNTER => 31,
53 NB_BITS_COUNTER => 31,
54 RST_VALUE => 0)
54 RST_VALUE => 0)
55 PORT MAP (
55 PORT MAP (
56 clk => clk,
56 clk => clk,
57 rstn => rstn,
57 rstn => rstn,
58 MAX_VALUE => "111" & X"FFFFFFF" ,
58 MAX_VALUE => "111" & X"FFFFFFF" ,
59 set => set_TCU_reg,
59 set => set_TCU_reg,
60 set_value => set_TCU_value(30 DOWNTO 0),
60 set_value => set_TCU_value(30 DOWNTO 0),
61 add1 => CT_add1,
61 add1 => CT_add1,
62 counter => coarse_time(30 DOWNTO 0));
62 counter => coarse_time(30 DOWNTO 0));
63
63
64
64
65 add1_bit31 <= '1' WHEN fsm_desync = '1' AND FT_max = '1' ELSE '0';
65 add1_bit31 <= '1' WHEN fsm_desync = '1' AND FT_max = '1' ELSE '0';
66
66
67 -----------------------------------------------------------------------------
67 -----------------------------------------------------------------------------
68 -- COARSE_TIME(31)
68 -- COARSE_TIME(31)
69 -----------------------------------------------------------------------------
69 -----------------------------------------------------------------------------
70
70
71 --set_synchronized <= (tick AND (NOT coarse_time_31)) OR (coarse_time_31 AND set_TCU);
71 --set_synchronized <= (tick AND (NOT coarse_time_31)) OR (coarse_time_31 AND set_TCU);
72 --set_synchronized_value <= STD_LOGIC_VECTOR(to_unsigned(NB_SECOND_DESYNC, 6)) WHEN (set_TCU AND set_TCU_value(31)) = '1' ELSE
72 --set_synchronized_value <= STD_LOGIC_VECTOR(to_unsigned(NB_SECOND_DESYNC, 6)) WHEN (set_TCU AND set_TCU_value(31)) = '1' ELSE
73 -- (OTHERS => '0');
73 -- (OTHERS => '0');
74 set_synchronized <= tick AND ((NOT coarse_time_31) OR (coarse_time_31 AND new_TCU));
74 set_synchronized <= tick AND ((NOT coarse_time_31) OR (coarse_time_31 AND new_TCU));
75 set_synchronized_value <= (OTHERS => '0');
75 set_synchronized_value <= (OTHERS => '0');
76
76
77 counter_2 : general_counter
77 counter_2 : general_counter
78 GENERIC MAP (
78 GENERIC MAP (
79 CYCLIC => '0',
79 CYCLIC => '0',
80 NB_BITS_COUNTER => 6,
80 NB_BITS_COUNTER => 6,
81 RST_VALUE => NB_SECOND_DESYNC
81 RST_VALUE => NB_SECOND_DESYNC
82 )
82 )
83 PORT MAP (
83 PORT MAP (
84 clk => clk,
84 clk => clk,
85 rstn => rstn,
85 rstn => rstn,
86 MAX_VALUE => STD_LOGIC_VECTOR(to_unsigned(NB_SECOND_DESYNC, 6)),
86 MAX_VALUE => STD_LOGIC_VECTOR(to_unsigned(NB_SECOND_DESYNC, 6)),
87 set => set_synchronized,
87 set => set_synchronized,
88 set_value => set_synchronized_value,
88 set_value => set_synchronized_value,
89 add1 => add1_bit31,
89 add1 => add1_bit31,
90 counter => nb_second_counter);
90 counter => nb_second_counter);
91
91
92 coarse_time_31 <= '1' WHEN nb_second_counter = STD_LOGIC_VECTOR(to_unsigned(NB_SECOND_DESYNC, 6)) ELSE '0';
92 coarse_time_31 <= '1' WHEN nb_second_counter = STD_LOGIC_VECTOR(to_unsigned(NB_SECOND_DESYNC, 6)) ELSE '0';
93 coarse_time(31) <= coarse_time_31;
93 coarse_time(31) <= coarse_time_31;
94 coarse_time_new <= coarse_time_new_counter OR (coarse_time_31 XOR coarse_time_31_reg);
94 coarse_time_new <= coarse_time_new_counter OR (coarse_time_31 XOR coarse_time_31_reg);
95
95
96 PROCESS (clk, rstn)
96 PROCESS (clk, rstn)
97 BEGIN -- PROCESS
97 BEGIN -- PROCESS
98 IF rstn = '0' THEN -- asynchronous reset (active low)
98 IF rstn = '0' THEN -- asynchronous reset (active low)
99 coarse_time_new_counter <= '0';
99 coarse_time_new_counter <= '0';
100 coarse_time_31_reg <= '0';
100 coarse_time_31_reg <= '0';
101 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
101 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
102 coarse_time_31_reg <= coarse_time_31;
102 coarse_time_31_reg <= coarse_time_31;
103 IF set_TCU_reg = '1' OR CT_add1 = '1' THEN
103 IF set_TCU_reg = '1' OR CT_add1 = '1' THEN
104 coarse_time_new_counter <= '1';
104 coarse_time_new_counter <= '1';
105 ELSE
105 ELSE
106 coarse_time_new_counter <= '0';
106 coarse_time_new_counter <= '0';
107 END IF;
107 END IF;
108 END IF;
108 END IF;
109 END PROCESS;
109 END PROCESS;
110
110
111 -----------------------------------------------------------------------------
111 -----------------------------------------------------------------------------
112 -- Just to try to limit the constraint
112 -- Just to try to limit the constraint
113 PROCESS (clk, rstn)
113 --PROCESS (clk, rstn)
114 BEGIN -- PROCESS
114 --BEGIN -- PROCESS
115 IF rstn = '0' THEN -- asynchronous reset (active low)
115 -- IF rstn = '0' THEN -- asynchronous reset (active low)
116 set_TCU_reg <= '0';
116 -- set_TCU_reg <= '0';
117 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
117 -- ELSIF clk'event AND clk = '1' THEN -- rising clock edge
118 set_TCU_reg <= set_TCU;
118 -- set_TCU_reg <= set_TCU;
119 END IF;
119 -- END IF;
120 END PROCESS;
120 --END PROCESS;
121 -----------------------------------------------------------------------------
121 -----------------------------------------------------------------------------
122
122 set_TCU_reg <= set_TCU;
123 END beh; No newline at end of file
123
124 END beh;
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@@ -1,94 +1,106
1 LIBRARY IEEE;
1 LIBRARY IEEE;
2 USE IEEE.STD_LOGIC_1164.ALL;
2 USE IEEE.STD_LOGIC_1164.ALL;
3 USE IEEE.NUMERIC_STD.ALL;
3 USE IEEE.NUMERIC_STD.ALL;
4
4
5 LIBRARY lpp;
5 LIBRARY lpp;
6 USE lpp.general_purpose.ALL;
6 USE lpp.general_purpose.ALL;
7 USE lpp.lpp_lfr_management.ALL;
7
8
8 ENTITY fine_time_counter IS
9 ENTITY fine_time_counter IS
9
10
10 GENERIC (
11 GENERIC (
11 WAITING_TIME : STD_LOGIC_VECTOR(15 DOWNTO 0) := X"0040";
12 WAITING_TIME : STD_LOGIC_VECTOR(15 DOWNTO 0) := X"0040"
12 FIRST_DIVISION : INTEGER := 374
13 );
13 );
14
14
15 PORT (
15 PORT (
16 clk : IN STD_LOGIC;
16 clk : IN STD_LOGIC;
17 rstn : IN STD_LOGIC;
17 rstn : IN STD_LOGIC;
18 --
18 --
19 tick : IN STD_LOGIC;
19 tick : IN STD_LOGIC;
20 fsm_transition : IN STD_LOGIC;
20 fsm_transition : IN STD_LOGIC;
21
21
22 FT_max : OUT STD_LOGIC;
22 FT_max : OUT STD_LOGIC;
23 FT_half : OUT STD_LOGIC;
23 FT_half : OUT STD_LOGIC;
24 FT_wait : OUT STD_LOGIC;
24 FT_wait : OUT STD_LOGIC;
25 fine_time : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
25 fine_time : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
26 fine_time_new : OUT STD_LOGIC
26 fine_time_new : OUT STD_LOGIC
27 );
27 );
28
28
29 END fine_time_counter;
29 END fine_time_counter;
30
30
31 ARCHITECTURE beh OF fine_time_counter IS
31 ARCHITECTURE beh OF fine_time_counter IS
32
32
33 SIGNAL new_ft_counter : STD_LOGIC_VECTOR(8 DOWNTO 0);
33 SIGNAL new_ft_counter : STD_LOGIC_VECTOR(8 DOWNTO 0);
34 SIGNAL new_ft : STD_LOGIC;
34 SIGNAL new_ft : STD_LOGIC;
35 SIGNAL fine_time_counter : STD_LOGIC_VECTOR(15 DOWNTO 0);
35 SIGNAL fine_time_counter : STD_LOGIC_VECTOR(15 DOWNTO 0);
36
37 SIGNAL fine_time_max_value : STD_LOGIC_VECTOR(8 DOWNTO 0);
38 SIGNAL tick_value_gen : STD_LOGIC;
39 SIGNAL FT_max_s : STD_LOGIC;
36
40
37 -- CONSTANT FIRST_DIVISION : INTEGER := 20; -- TODO : 374
38
39 BEGIN -- beh
41 BEGIN -- beh
40
42
43 tick_value_gen <= tick OR FT_max_s;
41
44
45 fine_time_max_value_gen_1: fine_time_max_value_gen
46 PORT MAP (
47 clk => clk,
48 rstn => rstn,
49 tick => tick_value_gen,
50 fine_time_add => new_ft,
51 fine_time_max_value => fine_time_max_value);
42
52
43 counter_1 : general_counter
53 counter_1 : general_counter
44 GENERIC MAP (
54 GENERIC MAP (
45 CYCLIC => '1',
55 CYCLIC => '1',
46 NB_BITS_COUNTER => 9,
56 NB_BITS_COUNTER => 9,
47 RST_VALUE => 0
57 RST_VALUE => 0
48 )
58 )
49 PORT MAP (
59 PORT MAP (
50 clk => clk,
60 clk => clk,
51 rstn => rstn,
61 rstn => rstn,
52 MAX_VALUE => STD_LOGIC_VECTOR(to_unsigned(FIRST_DIVISION, 9)),
62 MAX_VALUE => fine_time_max_value,
53 set => tick,
63 set => tick,
54 set_value => (OTHERS => '0'),
64 set_value => (OTHERS => '0'),
55 add1 => '1',
65 add1 => '1',
56 counter => new_ft_counter);
66 counter => new_ft_counter);
57
67
58 new_ft <= '1' WHEN new_ft_counter = STD_LOGIC_VECTOR(to_unsigned(FIRST_DIVISION, 9)) ELSE '0';
68 new_ft <= '1' WHEN new_ft_counter = fine_time_max_value ELSE '0';
59
69
60 counter_2 : general_counter
70 counter_2 : general_counter
61 GENERIC MAP (
71 GENERIC MAP (
62 CYCLIC => '1',
72 CYCLIC => '1',
63 NB_BITS_COUNTER => 16,
73 NB_BITS_COUNTER => 16,
64 RST_VALUE => 0
74 RST_VALUE => 0
65 )
75 )
66 PORT MAP (
76 PORT MAP (
67 clk => clk,
77 clk => clk,
68 rstn => rstn,
78 rstn => rstn,
69 MAX_VALUE => X"FFFF",
79 MAX_VALUE => X"FFFF",
70 set => tick,
80 set => tick,
71 set_value => (OTHERS => '0'),
81 set_value => (OTHERS => '0'),
72 add1 => new_ft,
82 add1 => new_ft,
73 counter => fine_time_counter);
83 counter => fine_time_counter);
74
84
75 FT_max <= '1' WHEN new_ft = '1' AND fine_time_counter = X"FFFF" ELSE '0';
85 FT_max_s <= '1' WHEN new_ft = '1' AND fine_time_counter = X"FFFF" ELSE '0';
86
87 FT_max <= FT_max_s;
76 FT_half <= '1' WHEN fine_time_counter > X"7FFF" ELSE '0';
88 FT_half <= '1' WHEN fine_time_counter > X"7FFF" ELSE '0';
77 FT_wait <= '1' WHEN fine_time_counter > WAITING_TIME ELSE '0';
89 FT_wait <= '1' WHEN fine_time_counter > WAITING_TIME ELSE '0';
78
90
79 fine_time <= X"FFFF" WHEN fsm_transition = '1' ELSE fine_time_counter;
91 fine_time <= X"FFFF" WHEN fsm_transition = '1' ELSE fine_time_counter;
80
92
81 PROCESS (clk, rstn)
93 PROCESS (clk, rstn)
82 BEGIN -- PROCESS
94 BEGIN -- PROCESS
83 IF rstn = '0' THEN -- asynchronous reset (active low)
95 IF rstn = '0' THEN -- asynchronous reset (active low)
84 fine_time_new <= '0';
96 fine_time_new <= '0';
85 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
97 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
86 IF (new_ft = '1' AND fsm_transition = '0') OR tick = '1' THEN
98 IF (new_ft = '1' AND fsm_transition = '0') OR tick = '1' THEN
87 fine_time_new <= '1';
99 fine_time_new <= '1';
88 ELSE
100 ELSE
89 fine_time_new <= '0';
101 fine_time_new <= '0';
90 END IF;
102 END IF;
91 END IF;
103 END IF;
92 END PROCESS;
104 END PROCESS;
93
105
94 END beh;
106 END beh;
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@@ -1,174 +1,172
1 ----------------------------------------------------------------------------------
1 ----------------------------------------------------------------------------------
2 -- Company:
2 -- Company:
3 -- Engineer:
3 -- Engineer:
4 --
4 --
5 -- Create Date: 11:14:05 07/02/2012
5 -- Create Date: 11:14:05 07/02/2012
6 -- Design Name:
6 -- Design Name:
7 -- Module Name: lfr_time_management - Behavioral
7 -- Module Name: lfr_time_management - Behavioral
8 -- Project Name:
8 -- Project Name:
9 -- Target Devices:
9 -- Target Devices:
10 -- Tool versions:
10 -- Tool versions:
11 -- Description:
11 -- Description:
12 --
12 --
13 -- Dependencies:
13 -- Dependencies:
14 --
14 --
15 -- Revision:
15 -- Revision:
16 -- Revision 0.01 - File Created
16 -- Revision 0.01 - File Created
17 -- Additional Comments:
17 -- Additional Comments:
18 --
18 --
19 ----------------------------------------------------------------------------------
19 ----------------------------------------------------------------------------------
20 LIBRARY IEEE;
20 LIBRARY IEEE;
21 USE IEEE.STD_LOGIC_1164.ALL;
21 USE IEEE.STD_LOGIC_1164.ALL;
22 USE IEEE.NUMERIC_STD.ALL;
22 USE IEEE.NUMERIC_STD.ALL;
23 LIBRARY lpp;
23 LIBRARY lpp;
24 USE lpp.lpp_lfr_management.ALL;
24 USE lpp.lpp_lfr_management.ALL;
25
25
26 ENTITY lfr_time_management IS
26 ENTITY lfr_time_management IS
27 GENERIC (
27 GENERIC (
28 FIRST_DIVISION : INTEGER := 374;
29 NB_SECOND_DESYNC : INTEGER := 60);
28 NB_SECOND_DESYNC : INTEGER := 60);
30 PORT (
29 PORT (
31 clk : IN STD_LOGIC;
30 clk : IN STD_LOGIC;
32 rstn : IN STD_LOGIC;
31 rstn : IN STD_LOGIC;
33
32
34 tick : IN STD_LOGIC; -- transition signal information
33 tick : IN STD_LOGIC; -- transition signal information
35
34
36 new_coarsetime : IN STD_LOGIC; -- transition signal information
35 new_coarsetime : IN STD_LOGIC; -- transition signal information
37 coarsetime_reg : IN STD_LOGIC_VECTOR(30 DOWNTO 0);
36 coarsetime_reg : IN STD_LOGIC_VECTOR(30 DOWNTO 0);
38
37
39 fine_time : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
38 fine_time : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
40 fine_time_new : OUT STD_LOGIC;
39 fine_time_new : OUT STD_LOGIC;
41 coarse_time : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
40 coarse_time : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
42 coarse_time_new : OUT STD_LOGIC
41 coarse_time_new : OUT STD_LOGIC
43 );
42 );
44 END lfr_time_management;
43 END lfr_time_management;
45
44
46 ARCHITECTURE Behavioral OF lfr_time_management IS
45 ARCHITECTURE Behavioral OF lfr_time_management IS
47
46
48 SIGNAL FT_max : STD_LOGIC;
47 SIGNAL FT_max : STD_LOGIC;
49 SIGNAL FT_half : STD_LOGIC;
48 SIGNAL FT_half : STD_LOGIC;
50 SIGNAL FT_wait : STD_LOGIC;
49 SIGNAL FT_wait : STD_LOGIC;
51
50
52 TYPE state_fsm_time_management IS (DESYNC, TRANSITION, SYNC);
51 TYPE state_fsm_time_management IS (DESYNC, TRANSITION, SYNC);
53 SIGNAL state : state_fsm_time_management;
52 SIGNAL state : state_fsm_time_management;
54
53
55 SIGNAL fsm_desync : STD_LOGIC;
54 SIGNAL fsm_desync : STD_LOGIC;
56 SIGNAL fsm_transition : STD_LOGIC;
55 SIGNAL fsm_transition : STD_LOGIC;
57
56
58 SIGNAL set_TCU : STD_LOGIC;
57 SIGNAL set_TCU : STD_LOGIC;
59 SIGNAL CT_add1 : STD_LOGIC;
58 SIGNAL CT_add1 : STD_LOGIC;
60
59
61 SIGNAL new_coarsetime_reg : STD_LOGIC;
60 SIGNAL new_coarsetime_reg : STD_LOGIC;
62
61
63 BEGIN
62 BEGIN
64
63
65 -----------------------------------------------------------------------------
64 -----------------------------------------------------------------------------
66 --
65 --
67 -----------------------------------------------------------------------------
66 -----------------------------------------------------------------------------
68 PROCESS (clk, rstn)
67 PROCESS (clk, rstn)
69 BEGIN -- PROCESS
68 BEGIN -- PROCESS
70 IF rstn = '0' THEN -- asynchronous reset (active low)
69 IF rstn = '0' THEN -- asynchronous reset (active low)
71 new_coarsetime_reg <= '0';
70 new_coarsetime_reg <= '0';
72 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
71 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
73 IF new_coarsetime = '1' THEN
72 IF new_coarsetime = '1' THEN
74 new_coarsetime_reg <= '1';
73 new_coarsetime_reg <= '1';
75 ELSIF tick = '1' THEN
74 ELSIF tick = '1' THEN
76 new_coarsetime_reg <= '0';
75 new_coarsetime_reg <= '0';
77 END IF;
76 END IF;
78 END IF;
77 END IF;
79 END PROCESS;
78 END PROCESS;
80
79
81 -----------------------------------------------------------------------------
80 -----------------------------------------------------------------------------
82 -- FINE_TIME
81 -- FINE_TIME
83 -----------------------------------------------------------------------------
82 -----------------------------------------------------------------------------
84 fine_time_counter_1: fine_time_counter
83 fine_time_counter_1: fine_time_counter
85 GENERIC MAP (
84 GENERIC MAP (
86 WAITING_TIME => X"0040",
85 WAITING_TIME => X"0040")
87 FIRST_DIVISION => FIRST_DIVISION)
88 PORT MAP (
86 PORT MAP (
89 clk => clk,
87 clk => clk,
90 rstn => rstn,
88 rstn => rstn,
91 tick => tick,
89 tick => tick,
92 fsm_transition => fsm_transition, -- todo
90 fsm_transition => fsm_transition, -- todo
93 FT_max => FT_max,
91 FT_max => FT_max,
94 FT_half => FT_half,
92 FT_half => FT_half,
95 FT_wait => FT_wait,
93 FT_wait => FT_wait,
96 fine_time => fine_time,
94 fine_time => fine_time,
97 fine_time_new => fine_time_new);
95 fine_time_new => fine_time_new);
98
96
99 -----------------------------------------------------------------------------
97 -----------------------------------------------------------------------------
100 -- COARSE_TIME
98 -- COARSE_TIME
101 -----------------------------------------------------------------------------
99 -----------------------------------------------------------------------------
102 coarse_time_counter_1: coarse_time_counter
100 coarse_time_counter_1: coarse_time_counter
103 GENERIC MAP(
101 GENERIC MAP(
104 NB_SECOND_DESYNC => NB_SECOND_DESYNC )
102 NB_SECOND_DESYNC => NB_SECOND_DESYNC )
105 PORT MAP (
103 PORT MAP (
106 clk => clk,
104 clk => clk,
107 rstn => rstn,
105 rstn => rstn,
108 tick => tick,
106 tick => tick,
109 set_TCU => set_TCU, -- todo
107 set_TCU => set_TCU, -- todo
110 new_TCU => new_coarsetime_reg,
108 new_TCU => new_coarsetime_reg,
111 set_TCU_value => coarsetime_reg, -- todo
109 set_TCU_value => coarsetime_reg, -- todo
112 CT_add1 => CT_add1, -- todo
110 CT_add1 => CT_add1, -- todo
113 fsm_desync => fsm_desync, -- todo
111 fsm_desync => fsm_desync, -- todo
114 FT_max => FT_max,
112 FT_max => FT_max,
115 coarse_time => coarse_time,
113 coarse_time => coarse_time,
116 coarse_time_new => coarse_time_new);
114 coarse_time_new => coarse_time_new);
117
115
118 -----------------------------------------------------------------------------
116 -----------------------------------------------------------------------------
119 -- FSM
117 -- FSM
120 -----------------------------------------------------------------------------
118 -----------------------------------------------------------------------------
121 fsm_desync <= '1' WHEN state = DESYNC ELSE '0';
119 fsm_desync <= '1' WHEN state = DESYNC ELSE '0';
122 fsm_transition <= '1' WHEN state = TRANSITION ELSE '0';
120 fsm_transition <= '1' WHEN state = TRANSITION ELSE '0';
123
121
124 PROCESS (clk, rstn)
122 PROCESS (clk, rstn)
125 BEGIN -- PROCESS
123 BEGIN -- PROCESS
126 IF rstn = '0' THEN -- asynchronous reset (active low)
124 IF rstn = '0' THEN -- asynchronous reset (active low)
127 state <= DESYNC;
125 state <= DESYNC;
128 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
126 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
129 --CT_add1 <= '0';
127 --CT_add1 <= '0';
130 set_TCU <= '0';
128 set_TCU <= '0';
131 CASE state IS
129 CASE state IS
132 WHEN DESYNC =>
130 WHEN DESYNC =>
133 IF tick = '1' THEN
131 IF tick = '1' THEN
134 state <= SYNC;
132 state <= SYNC;
135 set_TCU <= new_coarsetime_reg;
133 set_TCU <= new_coarsetime_reg;
136 --IF new_coarsetime = '0' AND FT_half = '1' THEN
134 --IF new_coarsetime = '0' AND FT_half = '1' THEN
137 -- CT_add1 <= '1';
135 -- CT_add1 <= '1';
138 --END IF;
136 --END IF;
139 --ELSIF FT_max = '1' THEN
137 --ELSIF FT_max = '1' THEN
140 -- CT_add1 <= '1';
138 -- CT_add1 <= '1';
141 END IF;
139 END IF;
142 WHEN TRANSITION =>
140 WHEN TRANSITION =>
143 IF tick = '1' THEN
141 IF tick = '1' THEN
144 state <= SYNC;
142 state <= SYNC;
145 set_TCU <= new_coarsetime_reg;
143 set_TCU <= new_coarsetime_reg;
146 --IF new_coarsetime = '0' THEN
144 --IF new_coarsetime = '0' THEN
147 -- CT_add1 <= '1';
145 -- CT_add1 <= '1';
148 --END IF;
146 --END IF;
149 ELSIF FT_wait = '1' THEN
147 ELSIF FT_wait = '1' THEN
150 --CT_add1 <= '1';
148 --CT_add1 <= '1';
151 state <= DESYNC;
149 state <= DESYNC;
152 END IF;
150 END IF;
153 WHEN SYNC =>
151 WHEN SYNC =>
154 IF tick = '1' THEN
152 IF tick = '1' THEN
155 set_TCU <= new_coarsetime_reg;
153 set_TCU <= new_coarsetime_reg;
156 --IF new_coarsetime = '0' THEN
154 --IF new_coarsetime = '0' THEN
157 -- CT_add1 <= '1';
155 -- CT_add1 <= '1';
158 --END IF;
156 --END IF;
159 ELSIF FT_max = '1' THEN
157 ELSIF FT_max = '1' THEN
160 state <= TRANSITION;
158 state <= TRANSITION;
161 END IF;
159 END IF;
162 WHEN OTHERS => NULL;
160 WHEN OTHERS => NULL;
163 END CASE;
161 END CASE;
164 END IF;
162 END IF;
165 END PROCESS;
163 END PROCESS;
166
164
167
165
168 CT_add1 <= '1' WHEN state = SYNC AND tick = '1' AND new_coarsetime_reg = '0' ELSE
166 CT_add1 <= '1' WHEN state = SYNC AND tick = '1' AND new_coarsetime_reg = '0' ELSE
169 '1' WHEN state = DESYNC AND tick = '1' AND new_coarsetime_reg = '0' AND FT_half = '1' ELSE
167 '1' WHEN state = DESYNC AND tick = '1' AND new_coarsetime_reg = '0' AND FT_half = '1' ELSE
170 '1' WHEN state = DESYNC AND tick = '0' AND FT_max = '1' ELSE
168 '1' WHEN state = DESYNC AND tick = '0' AND FT_max = '1' ELSE
171 '1' WHEN state = TRANSITION AND tick = '1' AND new_coarsetime_reg = '0' ELSE
169 '1' WHEN state = TRANSITION AND tick = '1' AND new_coarsetime_reg = '0' ELSE
172 '1' WHEN state = TRANSITION AND tick = '0' AND FT_wait = '1' ELSE
170 '1' WHEN state = TRANSITION AND tick = '0' AND FT_wait = '1' ELSE
173 '0';
171 '0';
174 END Behavioral;
172 END Behavioral;
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@@ -1,111 +1,119
1 ----------------------------------------------------------------------------------
1 ----------------------------------------------------------------------------------
2 -- Company:
2 -- Company:
3 -- Engineer:
3 -- Engineer:
4 --
4 --
5 -- Create Date: 13:04:01 07/02/2012
5 -- Create Date: 13:04:01 07/02/2012
6 -- Design Name:
6 -- Design Name:
7 -- Module Name: lpp_lfr_time_management - Behavioral
7 -- Module Name: lpp_lfr_time_management - Behavioral
8 -- Project Name:
8 -- Project Name:
9 -- Target Devices:
9 -- Target Devices:
10 -- Tool versions:
10 -- Tool versions:
11 -- Description:
11 -- Description:
12 --
12 --
13 -- Dependencies:
13 -- Dependencies:
14 --
14 --
15 -- Revision:
15 -- Revision:
16 -- Revision 0.01 - File Created
16 -- Revision 0.01 - File Created
17 -- Additional Comments:
17 -- Additional Comments:
18 --
18 --
19 ----------------------------------------------------------------------------------
19 ----------------------------------------------------------------------------------
20 LIBRARY IEEE;
20 LIBRARY IEEE;
21 USE IEEE.STD_LOGIC_1164.ALL;
21 USE IEEE.STD_LOGIC_1164.ALL;
22 LIBRARY grlib;
22 LIBRARY grlib;
23 USE grlib.amba.ALL;
23 USE grlib.amba.ALL;
24 USE grlib.stdlib.ALL;
24 USE grlib.stdlib.ALL;
25 USE grlib.devices.ALL;
25 USE grlib.devices.ALL;
26
26
27 PACKAGE lpp_lfr_management IS
27 PACKAGE lpp_lfr_management IS
28
28
29 --***************************
29 --***************************
30 -- APB_LFR_MANAGEMENT
30 -- APB_LFR_MANAGEMENT
31
31
32 COMPONENT apb_lfr_management
32 COMPONENT apb_lfr_management
33 GENERIC (
33 GENERIC (
34 tech : INTEGER;
34 tech : INTEGER;
35 pindex : INTEGER;
35 pindex : INTEGER;
36 paddr : INTEGER;
36 paddr : INTEGER;
37 pmask : INTEGER;
37 pmask : INTEGER;
38 FIRST_DIVISION : INTEGER;
38 -- FIRST_DIVISION : INTEGER;
39 NB_SECOND_DESYNC : INTEGER);
39 NB_SECOND_DESYNC : INTEGER);
40 PORT (
40 PORT (
41 clk25MHz : IN STD_LOGIC;
41 clk25MHz : IN STD_LOGIC;
42 resetn_25MHz : IN STD_LOGIC;
42 resetn_25MHz : IN STD_LOGIC;
43 clk24_576MHz : IN STD_LOGIC;
43 -- clk24_576MHz : IN STD_LOGIC;
44 resetn_24_576MHz : IN STD_LOGIC;
44 -- resetn_24_576MHz : IN STD_LOGIC;
45 grspw_tick : IN STD_LOGIC;
45 grspw_tick : IN STD_LOGIC;
46 apbi : IN apb_slv_in_type;
46 apbi : IN apb_slv_in_type;
47 apbo : OUT apb_slv_out_type;
47 apbo : OUT apb_slv_out_type;
48 HK_sample : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
48 HK_sample : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
49 HK_val : IN STD_LOGIC;
49 HK_val : IN STD_LOGIC;
50 HK_sel : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
50 HK_sel : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
51 DAC_SDO : OUT STD_LOGIC;
51 DAC_SDO : OUT STD_LOGIC;
52 DAC_SCK : OUT STD_LOGIC;
52 DAC_SCK : OUT STD_LOGIC;
53 DAC_SYNC : OUT STD_LOGIC;
53 DAC_SYNC : OUT STD_LOGIC;
54 DAC_CAL_EN : OUT STD_LOGIC;
54 DAC_CAL_EN : OUT STD_LOGIC;
55 coarse_time : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
55 coarse_time : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
56 fine_time : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
56 fine_time : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
57 LFR_soft_rstn : OUT STD_LOGIC);
57 LFR_soft_rstn : OUT STD_LOGIC);
58 END COMPONENT;
58 END COMPONENT;
59
59
60 COMPONENT lfr_time_management
60 COMPONENT lfr_time_management
61 GENERIC (
61 GENERIC (
62 FIRST_DIVISION : INTEGER;
62 --FIRST_DIVISION : INTEGER;
63 NB_SECOND_DESYNC : INTEGER);
63 NB_SECOND_DESYNC : INTEGER);
64 PORT (
64 PORT (
65 clk : IN STD_LOGIC;
65 clk : IN STD_LOGIC;
66 rstn : IN STD_LOGIC;
66 rstn : IN STD_LOGIC;
67 tick : IN STD_LOGIC;
67 tick : IN STD_LOGIC;
68 new_coarsetime : IN STD_LOGIC;
68 new_coarsetime : IN STD_LOGIC;
69 coarsetime_reg : IN STD_LOGIC_VECTOR(30 DOWNTO 0);
69 coarsetime_reg : IN STD_LOGIC_VECTOR(30 DOWNTO 0);
70 fine_time : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
70 fine_time : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
71 fine_time_new : OUT STD_LOGIC;
71 fine_time_new : OUT STD_LOGIC;
72 coarse_time : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
72 coarse_time : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
73 coarse_time_new : OUT STD_LOGIC);
73 coarse_time_new : OUT STD_LOGIC);
74 END COMPONENT;
74 END COMPONENT;
75
75
76 COMPONENT coarse_time_counter
76 COMPONENT coarse_time_counter
77 GENERIC (
77 GENERIC (
78 NB_SECOND_DESYNC : INTEGER);
78 NB_SECOND_DESYNC : INTEGER);
79 PORT (
79 PORT (
80 clk : IN STD_LOGIC;
80 clk : IN STD_LOGIC;
81 rstn : IN STD_LOGIC;
81 rstn : IN STD_LOGIC;
82 tick : IN STD_LOGIC;
82 tick : IN STD_LOGIC;
83 set_TCU : IN STD_LOGIC;
83 set_TCU : IN STD_LOGIC;
84 new_TCU : IN STD_LOGIC;
84 new_TCU : IN STD_LOGIC;
85 set_TCU_value : IN STD_LOGIC_VECTOR(30 DOWNTO 0);
85 set_TCU_value : IN STD_LOGIC_VECTOR(30 DOWNTO 0);
86 CT_add1 : IN STD_LOGIC;
86 CT_add1 : IN STD_LOGIC;
87 fsm_desync : IN STD_LOGIC;
87 fsm_desync : IN STD_LOGIC;
88 FT_max : IN STD_LOGIC;
88 FT_max : IN STD_LOGIC;
89 coarse_time : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
89 coarse_time : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
90 coarse_time_new : OUT STD_LOGIC);
90 coarse_time_new : OUT STD_LOGIC);
91 END COMPONENT;
91 END COMPONENT;
92
92
93 COMPONENT fine_time_counter
93 COMPONENT fine_time_counter
94 GENERIC (
94 GENERIC (
95 WAITING_TIME : STD_LOGIC_VECTOR(15 DOWNTO 0);
95 WAITING_TIME : STD_LOGIC_VECTOR(15 DOWNTO 0));--;
96 FIRST_DIVISION : INTEGER);
96 -- FIRST_DIVISION : INTEGER);
97 PORT (
97 PORT (
98 clk : IN STD_LOGIC;
98 clk : IN STD_LOGIC;
99 rstn : IN STD_LOGIC;
99 rstn : IN STD_LOGIC;
100 tick : IN STD_LOGIC;
100 tick : IN STD_LOGIC;
101 fsm_transition : IN STD_LOGIC;
101 fsm_transition : IN STD_LOGIC;
102 FT_max : OUT STD_LOGIC;
102 FT_max : OUT STD_LOGIC;
103 FT_half : OUT STD_LOGIC;
103 FT_half : OUT STD_LOGIC;
104 FT_wait : OUT STD_LOGIC;
104 FT_wait : OUT STD_LOGIC;
105 fine_time : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
105 fine_time : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
106 fine_time_new : OUT STD_LOGIC);
106 fine_time_new : OUT STD_LOGIC);
107 END COMPONENT;
107 END COMPONENT;
108
108
109
109 COMPONENT fine_time_max_value_gen
110 END lpp_lfr_management;
110 PORT (
111
111 clk : IN STD_LOGIC;
112 rstn : IN STD_LOGIC;
113 tick : IN STD_LOGIC;
114 fine_time_add : IN STD_LOGIC;
115 fine_time_max_value : OUT STD_LOGIC_VECTOR(8 DOWNTO 0));
116 END COMPONENT;
117
118 END lpp_lfr_management;
119
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@@ -1,6 +1,7
1 lpp_lfr_management.vhd
1 lpp_lfr_management.vhd
2 lpp_lfr_management_apbreg_pkg.vhd
2 lpp_lfr_management_apbreg_pkg.vhd
3 apb_lfr_management.vhd
3 apb_lfr_management.vhd
4 lfr_time_management.vhd
4 lfr_time_management.vhd
5 fine_time_counter.vhd
5 fine_time_counter.vhd
6 coarse_time_counter.vhd
6 coarse_time_counter.vhd
7 fine_time_max_value_gen.vhd
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@@ -1,195 +1,196
1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
18 -------------------------------------------------------------------------------
19 -- Author : Jean-christophe Pellion
19 -- Author : Jean-christophe Pellion
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 -- jean-christophe.pellion@easii-ic.com
21 -- jean-christophe.pellion@easii-ic.com
22 ----------------------------------------------------------------------------
22 ----------------------------------------------------------------------------
23
23
24 LIBRARY ieee;
24 LIBRARY ieee;
25 USE ieee.std_logic_1164.ALL;
25 USE ieee.std_logic_1164.ALL;
26 USE ieee.numeric_std.ALL;
26 USE ieee.numeric_std.ALL;
27 LIBRARY grlib;
27 LIBRARY grlib;
28 USE grlib.amba.ALL;
28 USE grlib.amba.ALL;
29 USE grlib.stdlib.ALL;
29 USE grlib.stdlib.ALL;
30 USE grlib.devices.ALL;
30 USE grlib.devices.ALL;
31 USE GRLIB.DMA2AHB_Package.ALL;
31 USE GRLIB.DMA2AHB_Package.ALL;
32 LIBRARY lpp;
32 LIBRARY lpp;
33 USE lpp.lpp_amba.ALL;
33 USE lpp.lpp_amba.ALL;
34 USE lpp.apb_devices_list.ALL;
34 USE lpp.apb_devices_list.ALL;
35 USE lpp.lpp_memory.ALL;
35 USE lpp.lpp_memory.ALL;
36 LIBRARY techmap;
36 LIBRARY techmap;
37 USE techmap.gencomp.ALL;
37 USE techmap.gencomp.ALL;
38
38
39 ENTITY lpp_dma_send_16word IS
39 ENTITY lpp_dma_send_16word IS
40 PORT (
40 PORT (
41 -- AMBA AHB system signals
41 -- AMBA AHB system signals
42 HCLK : IN STD_ULOGIC;
42 HCLK : IN STD_ULOGIC;
43 HRESETn : IN STD_ULOGIC;
43 HRESETn : IN STD_ULOGIC;
44
44
45 -- DMA
45 -- DMA
46 DMAIn : OUT DMA_In_Type;
46 DMAIn : OUT DMA_In_Type;
47 DMAOut : IN DMA_OUt_Type;
47 DMAOut : IN DMA_OUt_Type;
48
48
49 --
49 --
50 send : IN STD_LOGIC;
50 send : IN STD_LOGIC;
51 address : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
51 address : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
52 data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
52 data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
53 ren : OUT STD_LOGIC;
53 ren : OUT STD_LOGIC;
54 --
54 --
55 send_ok : OUT STD_LOGIC;
55 send_ok : OUT STD_LOGIC;
56 send_ko : OUT STD_LOGIC
56 send_ko : OUT STD_LOGIC
57
57
58 );
58 );
59 END lpp_dma_send_16word;
59 END lpp_dma_send_16word;
60
60
61 ARCHITECTURE beh OF lpp_dma_send_16word IS
61 ARCHITECTURE beh OF lpp_dma_send_16word IS
62
62
63 TYPE state_fsm_send_16word IS (IDLE, REQUEST_BUS, SEND_DATA, ERROR0, ERROR1, WAIT_LAST_READY);
63 TYPE state_fsm_send_16word IS (IDLE, REQUEST_BUS, SEND_DATA, ERROR0, ERROR1, WAIT_LAST_READY);
64 SIGNAL state : state_fsm_send_16word;
64 SIGNAL state : state_fsm_send_16word;
65
65
66 SIGNAL data_counter : INTEGER;
66 SIGNAL data_counter : INTEGER;
67 SIGNAL grant_counter : INTEGER;
67 SIGNAL grant_counter : INTEGER;
68
68
69 BEGIN -- beh
69 BEGIN -- beh
70
70
71 DMAIn.Beat <= HINCR16;
71 DMAIn.Beat <= HINCR16;
72 DMAIn.Size <= HSIZE32;
72 DMAIn.Size <= HSIZE32;
73
73
74 PROCESS (HCLK, HRESETn)
74 PROCESS (HCLK, HRESETn)
75 BEGIN -- PROCESS
75 BEGIN -- PROCESS
76 IF HRESETn = '0' THEN -- asynchronous reset (active low)
76 IF HRESETn = '0' THEN -- asynchronous reset (active low)
77 state <= IDLE;
77 state <= IDLE;
78 send_ok <= '0';
78 send_ok <= '0';
79 send_ko <= '0';
79 send_ko <= '0';
80
80
81 DMAIn.Reset <= '1';
81 DMAIn.Reset <= '1';
82 DMAIn.Address <= (OTHERS => '0');
82 DMAIn.Address <= (OTHERS => '0');
83 DMAIn.Request <= '0';
83 DMAIn.Request <= '0';
84 DMAIn.Store <= '0';
84 DMAIn.Store <= '0';
85 DMAIn.Burst <= '1';
85 DMAIn.Burst <= '1';
86 DMAIn.Lock <= '0';
86 DMAIn.Lock <= '0';
87 data_counter <= 0;
87 data_counter <= 0;
88 grant_counter <= 0;
88 grant_counter <= 0;
89 ELSIF HCLK'EVENT AND HCLK = '1' THEN -- rising clock edge
89 ELSIF HCLK'EVENT AND HCLK = '1' THEN -- rising clock edge
90
90
91 DMAIn.Reset <= '0';
91 DMAIn.Reset <= '0';
92
92
93 CASE state IS
93 CASE state IS
94 WHEN IDLE =>
94 WHEN IDLE =>
95 DMAIn.Store <= '1';
95 DMAIn.Store <= '1';
96 DMAIn.Request <= '0';
96 DMAIn.Request <= '0';
97 send_ok <= '0';
97 send_ok <= '0';
98 send_ko <= '0';
98 send_ko <= '0';
99 DMAIn.Address <= address;
99 DMAIn.Address <= address;
100 data_counter <= 0;
100 data_counter <= 0;
101 DMAIn.Lock <= '0'; -- FIX test
101 DMAIn.Lock <= '0';
102 IF send = '1' THEN
102 IF send = '1' THEN
103 state <= REQUEST_BUS;
103 state <= REQUEST_BUS;
104 DMAIn.Request <= '1';
104 DMAIn.Request <= '1';
105 DMAIn.Lock <= '1'; -- FIX test
105 DMAIn.Lock <= '1';
106 DMAIn.Store <= '1';
106 DMAIn.Store <= '1';
107 END IF;
107 END IF;
108 WHEN REQUEST_BUS =>
108 WHEN REQUEST_BUS =>
109 IF DMAOut.Grant = '1' THEN
109 IF DMAOut.Grant = '1' THEN
110 data_counter <= 1;
110 data_counter <= 1;
111 grant_counter <= 1;
111 grant_counter <= 1;
112 state <= SEND_DATA;
112 state <= SEND_DATA;
113 END IF;
113 END IF;
114 WHEN SEND_DATA =>
114 WHEN SEND_DATA =>
115
115
116 IF DMAOut.Fault = '1' THEN
116 IF DMAOut.Fault = '1' THEN
117 DMAIn.Reset <= '0';
117 DMAIn.Reset <= '0';
118 DMAIn.Address <= (OTHERS => '0');
118 DMAIn.Address <= (OTHERS => '0');
119 DMAIn.Request <= '0';
119 DMAIn.Request <= '0';
120 DMAIn.Store <= '0';
120 DMAIn.Store <= '0';
121 DMAIn.Burst <= '0';
121 DMAIn.Burst <= '0';
122 state <= ERROR0;
122 state <= ERROR0;
123 ELSE
123 ELSE
124
124
125 IF DMAOut.Grant = '1' THEN
125 IF DMAOut.Grant = '1' THEN
126 IF grant_counter = 15 THEN
126 IF grant_counter = 15 THEN
127 DMAIn.Reset <= '0';
127 DMAIn.Reset <= '0';
128 DMAIn.Request <= '0';
128 DMAIn.Request <= '0';
129 DMAIn.Store <= '0';
129 DMAIn.Store <= '0';
130 DMAIn.Burst <= '0';
130 DMAIn.Burst <= '0';
131 ELSE
131 ELSE
132 grant_counter <= grant_counter+1;
132 grant_counter <= grant_counter+1;
133 END IF;
133 END IF;
134 END IF;
134 END IF;
135
135
136 IF DMAOut.OKAY = '1' THEN
136 IF DMAOut.OKAY = '1' THEN
137 IF data_counter = 15 THEN
137 IF data_counter = 15 THEN
138 --DMAIn.Request <= '0'; -- FIX Test 31/03/2014 to handle burst interruption
138 DMAIn.Address <= (OTHERS => '0');
139 DMAIn.Address <= (OTHERS => '0');
139 state <= WAIT_LAST_READY;
140 state <= WAIT_LAST_READY;
140 ELSE
141 ELSE
141 data_counter <= data_counter + 1;
142 data_counter <= data_counter + 1;
142 END IF;
143 END IF;
143 END IF;
144 END IF;
144 END IF;
145 END IF;
145
146
146
147
147 WHEN WAIT_LAST_READY =>
148 WHEN WAIT_LAST_READY =>
148 IF DMAOut.Ready = '1' THEN
149 IF DMAOut.Ready = '1' THEN
149 IF grant_counter = 15 THEN
150 IF grant_counter = 15 THEN
150 state <= IDLE;
151 state <= IDLE;
151 send_ok <= '1';
152 send_ok <= '1';
152 send_ko <= '0';
153 send_ko <= '0';
153 ELSE
154 ELSE
154 state <= ERROR0;
155 state <= ERROR0;
155 END IF;
156 END IF;
156 END IF;
157 END IF;
157
158
158 WHEN ERROR0 =>
159 WHEN ERROR0 =>
159 state <= ERROR1;
160 state <= ERROR1;
160 WHEN ERROR1 =>
161 WHEN ERROR1 =>
161 send_ok <= '0';
162 send_ok <= '0';
162 send_ko <= '1';
163 send_ko <= '1';
163 state <= IDLE;
164 state <= IDLE;
164 WHEN OTHERS => NULL;
165 WHEN OTHERS => NULL;
165 END CASE;
166 END CASE;
166 END IF;
167 END IF;
167 END PROCESS;
168 END PROCESS;
168
169
169 DMAIn.Data <= data;
170 DMAIn.Data <= data;
170
171
171 ren <= NOT (DMAOut.OKAY OR DMAOut.GRANT) WHEN state = SEND_DATA ELSE
172 ren <= NOT (DMAOut.OKAY OR DMAOut.GRANT) WHEN state = SEND_DATA ELSE
172 '1';
173 '1';
173
174
174 -- \/ JC - 20/01/2014 \/
175 -- \/ JC - 20/01/2014 \/
175 --ren <= '0' WHEN DMAOut.OKAY = '1' ELSE --AND (state = SEND_DATA OR state = WAIT_LAST_READY) ELSE
176 --ren <= '0' WHEN DMAOut.OKAY = '1' ELSE --AND (state = SEND_DATA OR state = WAIT_LAST_READY) ELSE
176 -- '1';
177 -- '1';
177 -- /\ JC - 20/01/2014 /\
178 -- /\ JC - 20/01/2014 /\
178
179
179 -- \/ JC - 11/12/2013 \/
180 -- \/ JC - 11/12/2013 \/
180 --ren <= '0' WHEN DMAOut.OKAY = '1' AND state = SEND_DATA ELSE
181 --ren <= '0' WHEN DMAOut.OKAY = '1' AND state = SEND_DATA ELSE
181 -- '1';
182 -- '1';
182 -- /\ JC - 11/12/2013 /\
183 -- /\ JC - 11/12/2013 /\
183
184
184 -- \/ JC - 10/12/2013 \/
185 -- \/ JC - 10/12/2013 \/
185 --ren <= '0' WHEN DMAOut.OKAY = '1' AND state = SEND_DATA ELSE
186 --ren <= '0' WHEN DMAOut.OKAY = '1' AND state = SEND_DATA ELSE
186 -- '0' WHEN state = REQUEST_BUS AND DMAOut.Grant = '1' ELSE
187 -- '0' WHEN state = REQUEST_BUS AND DMAOut.Grant = '1' ELSE
187 -- '1';
188 -- '1';
188 -- /\ JC - 10/12/2013 /\
189 -- /\ JC - 10/12/2013 /\
189
190
190 -- \/ JC - 09/12/2013 \/
191 -- \/ JC - 09/12/2013 \/
191 --ren <= '0' WHEN state = SEND_DATA ELSE
192 --ren <= '0' WHEN state = SEND_DATA ELSE
192 -- '1';
193 -- '1';
193 -- /\ JC - 09/12/2013 /\
194 -- /\ JC - 09/12/2013 /\
194
195
195 END beh;
196 END beh;
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@@ -1,566 +1,569
1 -----------------------------------------------------------------------------
1 -----------------------------------------------------------------------------
2 -- LEON3 Demonstration design
2 -- LEON3 Demonstration design
3 -- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
3 -- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 2 of the License, or
7 -- the Free Software Foundation; either version 2 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 ------------------------------------------------------------------------------
18 ------------------------------------------------------------------------------
19
19
20
20
21 LIBRARY ieee;
21 LIBRARY ieee;
22 USE ieee.std_logic_1164.ALL;
22 USE ieee.std_logic_1164.ALL;
23 LIBRARY grlib;
23 LIBRARY grlib;
24 USE grlib.amba.ALL;
24 USE grlib.amba.ALL;
25 USE grlib.stdlib.ALL;
25 USE grlib.stdlib.ALL;
26 LIBRARY techmap;
26 LIBRARY techmap;
27 USE techmap.gencomp.ALL;
27 USE techmap.gencomp.ALL;
28 LIBRARY gaisler;
28 LIBRARY gaisler;
29 USE gaisler.memctrl.ALL;
29 USE gaisler.memctrl.ALL;
30 USE gaisler.leon3.ALL;
30 USE gaisler.leon3.ALL;
31 USE gaisler.uart.ALL;
31 USE gaisler.uart.ALL;
32 USE gaisler.misc.ALL;
32 USE gaisler.misc.ALL;
33 USE gaisler.spacewire.ALL; -- PLE
33 USE gaisler.spacewire.ALL; -- PLE
34 LIBRARY esa;
34 LIBRARY esa;
35 USE esa.memoryctrl.ALL;
35 USE esa.memoryctrl.ALL;
36 LIBRARY lpp;
36 LIBRARY lpp;
37 USE lpp.lpp_memory.ALL;
37 USE lpp.lpp_memory.ALL;
38 USE lpp.lpp_ad_conv.ALL;
38 USE lpp.lpp_ad_conv.ALL;
39 USE lpp.lpp_lfr_pkg.ALL;
39 USE lpp.lpp_lfr_pkg.ALL;
40 USE lpp.iir_filter.ALL;
40 USE lpp.iir_filter.ALL;
41 USE lpp.general_purpose.ALL;
41 USE lpp.general_purpose.ALL;
42 USE lpp.lpp_leon3_soc_pkg.ALL;
42 USE lpp.lpp_leon3_soc_pkg.ALL;
43 LIBRARY iap;
43 LIBRARY iap;
44 USE iap.memctrl.ALL;
44 USE iap.memctrl.ALL;
45
45
46
46
47 ENTITY leon3_soc IS
47 ENTITY leon3_soc IS
48 GENERIC (
48 GENERIC (
49 fabtech : INTEGER := apa3e;
49 fabtech : INTEGER := apa3e;
50 memtech : INTEGER := apa3e;
50 memtech : INTEGER := apa3e;
51 padtech : INTEGER := inferred;
51 padtech : INTEGER := inferred;
52 clktech : INTEGER := inferred;
52 clktech : INTEGER := inferred;
53 disas : INTEGER := 0; -- Enable disassembly to console
53 disas : INTEGER := 0; -- Enable disassembly to console
54 dbguart : INTEGER := 0; -- Print UART on console
54 dbguart : INTEGER := 0; -- Print UART on console
55 pclow : INTEGER := 2;
55 pclow : INTEGER := 2;
56 --
56 --
57 clk_freq : INTEGER := 25000; --kHz
57 clk_freq : INTEGER := 25000; --kHz
58 --
58 --
59 IS_RADHARD : INTEGER := 0;
59 IS_RADHARD : INTEGER := 0;
60 --
60 --
61 NB_CPU : INTEGER := 1;
61 NB_CPU : INTEGER := 1;
62 ENABLE_FPU : INTEGER := 1;
62 ENABLE_FPU : INTEGER := 1;
63 FPU_NETLIST : INTEGER := 1;
63 FPU_NETLIST : INTEGER := 1;
64 ENABLE_DSU : INTEGER := 1;
64 ENABLE_DSU : INTEGER := 1;
65 ENABLE_AHB_UART : INTEGER := 1;
65 ENABLE_AHB_UART : INTEGER := 1;
66 ENABLE_APB_UART : INTEGER := 1;
66 ENABLE_APB_UART : INTEGER := 1;
67 ENABLE_IRQMP : INTEGER := 1;
67 ENABLE_IRQMP : INTEGER := 1;
68 ENABLE_GPT : INTEGER := 1;
68 ENABLE_GPT : INTEGER := 1;
69 --
69 --
70 NB_AHB_MASTER : INTEGER := 1;
70 NB_AHB_MASTER : INTEGER := 1;
71 NB_AHB_SLAVE : INTEGER := 1;
71 NB_AHB_SLAVE : INTEGER := 1;
72 NB_APB_SLAVE : INTEGER := 1;
72 NB_APB_SLAVE : INTEGER := 1;
73 --
73 --
74 ADDRESS_SIZE : INTEGER := 20;
74 ADDRESS_SIZE : INTEGER := 20;
75 USES_IAP_MEMCTRLR : INTEGER := 0
75 USES_IAP_MEMCTRLR : INTEGER := 0;
76 BYPASS_EDAC_MEMCTRLR : STD_LOGIC := '0';
77 SRBANKSZ : INTEGER := 8
76
78
77 );
79 );
78 PORT (
80 PORT (
79 clk : IN STD_ULOGIC;
81 clk : IN STD_ULOGIC;
80 reset : IN STD_ULOGIC;
82 reset : IN STD_ULOGIC;
81
83
82 errorn : OUT STD_ULOGIC;
84 errorn : OUT STD_ULOGIC;
83
85
84 -- UART AHB ---------------------------------------------------------------
86 -- UART AHB ---------------------------------------------------------------
85 ahbrxd : IN STD_ULOGIC; -- DSU rx data
87 ahbrxd : IN STD_ULOGIC; -- DSU rx data
86 ahbtxd : OUT STD_ULOGIC; -- DSU tx data
88 ahbtxd : OUT STD_ULOGIC; -- DSU tx data
87
89
88 -- UART APB ---------------------------------------------------------------
90 -- UART APB ---------------------------------------------------------------
89 urxd1 : IN STD_ULOGIC; -- UART1 rx data
91 urxd1 : IN STD_ULOGIC; -- UART1 rx data
90 utxd1 : OUT STD_ULOGIC; -- UART1 tx data
92 utxd1 : OUT STD_ULOGIC; -- UART1 tx data
91
93
92 -- RAM --------------------------------------------------------------------
94 -- RAM --------------------------------------------------------------------
93 address : OUT STD_LOGIC_VECTOR(ADDRESS_SIZE-1 DOWNTO 0);
95 address : OUT STD_LOGIC_VECTOR(ADDRESS_SIZE-1 DOWNTO 0);
94 data : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0);
96 data : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0);
95 nSRAM_BE0 : OUT STD_LOGIC;
97 nSRAM_BE0 : OUT STD_LOGIC;
96 nSRAM_BE1 : OUT STD_LOGIC;
98 nSRAM_BE1 : OUT STD_LOGIC;
97 nSRAM_BE2 : OUT STD_LOGIC;
99 nSRAM_BE2 : OUT STD_LOGIC;
98 nSRAM_BE3 : OUT STD_LOGIC;
100 nSRAM_BE3 : OUT STD_LOGIC;
99 nSRAM_WE : OUT STD_LOGIC;
101 nSRAM_WE : OUT STD_LOGIC;
100 nSRAM_CE : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
102 nSRAM_CE : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
101 nSRAM_OE : OUT STD_LOGIC;
103 nSRAM_OE : OUT STD_LOGIC;
102 nSRAM_READY : IN STD_LOGIC;
104 nSRAM_READY : IN STD_LOGIC;
103 SRAM_MBE : INOUT STD_LOGIC;
105 SRAM_MBE : INOUT STD_LOGIC;
104 -- APB --------------------------------------------------------------------
106 -- APB --------------------------------------------------------------------
105 apbi_ext : OUT apb_slv_in_type;
107 apbi_ext : OUT apb_slv_in_type;
106 apbo_ext : IN soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5);
108 apbo_ext : IN soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5);
107 -- AHB_Slave --------------------------------------------------------------
109 -- AHB_Slave --------------------------------------------------------------
108 ahbi_s_ext : OUT ahb_slv_in_type;
110 ahbi_s_ext : OUT ahb_slv_in_type;
109 ahbo_s_ext : IN soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3);
111 ahbo_s_ext : IN soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3);
110 -- AHB_Master -------------------------------------------------------------
112 -- AHB_Master -------------------------------------------------------------
111 ahbi_m_ext : OUT AHB_Mst_In_Type;
113 ahbi_m_ext : OUT AHB_Mst_In_Type;
112 ahbo_m_ext : IN soc_ahb_mst_out_vector(NB_AHB_MASTER-1+NB_CPU DOWNTO NB_CPU)
114 ahbo_m_ext : IN soc_ahb_mst_out_vector(NB_AHB_MASTER-1+NB_CPU DOWNTO NB_CPU)
113
115
114 );
116 );
115 END;
117 END;
116
118
117 ARCHITECTURE Behavioral OF leon3_soc IS
119 ARCHITECTURE Behavioral OF leon3_soc IS
118
120
119 -----------------------------------------------------------------------------
121 -----------------------------------------------------------------------------
120 -- CONFIG -------------------------------------------------------------------
122 -- CONFIG -------------------------------------------------------------------
121 -----------------------------------------------------------------------------
123 -----------------------------------------------------------------------------
122
124
123 -- Clock generator
125 -- Clock generator
124 CONSTANT CFG_CLKMUL : INTEGER := (1);
126 CONSTANT CFG_CLKMUL : INTEGER := (1);
125 CONSTANT CFG_CLKDIV : INTEGER := (1); -- divide 50MHz by 2 to get 25MHz
127 CONSTANT CFG_CLKDIV : INTEGER := (1); -- divide 50MHz by 2 to get 25MHz
126 CONSTANT CFG_OCLKDIV : INTEGER := (1);
128 CONSTANT CFG_OCLKDIV : INTEGER := (1);
127 CONSTANT CFG_CLK_NOFB : INTEGER := 0;
129 CONSTANT CFG_CLK_NOFB : INTEGER := 0;
128 -- LEON3 processor core
130 -- LEON3 processor core
129 CONSTANT CFG_LEON3 : INTEGER := 1;
131 CONSTANT CFG_LEON3 : INTEGER := 1;
130 CONSTANT CFG_NCPU : INTEGER := NB_CPU;
132 CONSTANT CFG_NCPU : INTEGER := NB_CPU;
131 CONSTANT CFG_NWIN : INTEGER := (8); -- to be compatible with BCC and RCC
133 CONSTANT CFG_NWIN : INTEGER := (8); -- to be compatible with BCC and RCC
132 CONSTANT CFG_V8 : INTEGER := 0;
134 CONSTANT CFG_V8 : INTEGER := 0;
133 CONSTANT CFG_MAC : INTEGER := 0;
135 CONSTANT CFG_MAC : INTEGER := 0;
134 CONSTANT CFG_SVT : INTEGER := 0;
136 CONSTANT CFG_SVT : INTEGER := 0;
135 CONSTANT CFG_RSTADDR : INTEGER := 16#00000#;
137 CONSTANT CFG_RSTADDR : INTEGER := 16#00000#;
136 CONSTANT CFG_LDDEL : INTEGER := (1);
138 CONSTANT CFG_LDDEL : INTEGER := (1);
137 CONSTANT CFG_NWP : INTEGER := (0);
139 CONSTANT CFG_NWP : INTEGER := (0);
138 CONSTANT CFG_PWD : INTEGER := 1*2;
140 CONSTANT CFG_PWD : INTEGER := 1*2;
139 CONSTANT CFG_FPU : INTEGER := ENABLE_FPU *(8 + 16 * FPU_NETLIST);
141 CONSTANT CFG_FPU : INTEGER := ENABLE_FPU *(8 + 16 * FPU_NETLIST);
140 -- 1*(8 + 16 * 0) => grfpu-light
142 -- 1*(8 + 16 * 0) => grfpu-light
141 -- 1*(8 + 16 * 1) => netlist
143 -- 1*(8 + 16 * 1) => netlist
142 -- 0*(8 + 16 * 0) => No FPU
144 -- 0*(8 + 16 * 0) => No FPU
143 -- 0*(8 + 16 * 1) => No FPU;
145 -- 0*(8 + 16 * 1) => No FPU;
144 CONSTANT CFG_ICEN : INTEGER := 1;
146 CONSTANT CFG_ICEN : INTEGER := 1;
145 CONSTANT CFG_ISETS : INTEGER := 1;
147 CONSTANT CFG_ISETS : INTEGER := 1;
146 CONSTANT CFG_ISETSZ : INTEGER := 4;
148 CONSTANT CFG_ISETSZ : INTEGER := 4;
147 CONSTANT CFG_ILINE : INTEGER := 4;
149 CONSTANT CFG_ILINE : INTEGER := 4;
148 CONSTANT CFG_IREPL : INTEGER := 0;
150 CONSTANT CFG_IREPL : INTEGER := 0;
149 CONSTANT CFG_ILOCK : INTEGER := 0;
151 CONSTANT CFG_ILOCK : INTEGER := 0;
150 CONSTANT CFG_ILRAMEN : INTEGER := 0;
152 CONSTANT CFG_ILRAMEN : INTEGER := 0;
151 CONSTANT CFG_ILRAMADDR : INTEGER := 16#8E#;
153 CONSTANT CFG_ILRAMADDR : INTEGER := 16#8E#;
152 CONSTANT CFG_ILRAMSZ : INTEGER := 1;
154 CONSTANT CFG_ILRAMSZ : INTEGER := 1;
153 CONSTANT CFG_DCEN : INTEGER := 1;
155 CONSTANT CFG_DCEN : INTEGER := 1;
154 CONSTANT CFG_DSETS : INTEGER := 1;
156 CONSTANT CFG_DSETS : INTEGER := 1;
155 CONSTANT CFG_DSETSZ : INTEGER := 4;
157 CONSTANT CFG_DSETSZ : INTEGER := 4;
156 CONSTANT CFG_DLINE : INTEGER := 4;
158 CONSTANT CFG_DLINE : INTEGER := 4;
157 CONSTANT CFG_DREPL : INTEGER := 0;
159 CONSTANT CFG_DREPL : INTEGER := 0;
158 CONSTANT CFG_DLOCK : INTEGER := 0;
160 CONSTANT CFG_DLOCK : INTEGER := 0;
159 CONSTANT CFG_DSNOOP : INTEGER := 0 + 0 + 4*0;
161 CONSTANT CFG_DSNOOP : INTEGER := 0 + 0 + 4*0;
160 CONSTANT CFG_DLRAMEN : INTEGER := 0;
162 CONSTANT CFG_DLRAMEN : INTEGER := 0;
161 CONSTANT CFG_DLRAMADDR : INTEGER := 16#8F#;
163 CONSTANT CFG_DLRAMADDR : INTEGER := 16#8F#;
162 CONSTANT CFG_DLRAMSZ : INTEGER := 1;
164 CONSTANT CFG_DLRAMSZ : INTEGER := 1;
163 CONSTANT CFG_MMUEN : INTEGER := 0;
165 CONSTANT CFG_MMUEN : INTEGER := 0;
164 CONSTANT CFG_ITLBNUM : INTEGER := 2;
166 CONSTANT CFG_ITLBNUM : INTEGER := 2;
165 CONSTANT CFG_DTLBNUM : INTEGER := 2;
167 CONSTANT CFG_DTLBNUM : INTEGER := 2;
166 CONSTANT CFG_TLB_TYPE : INTEGER := 1 + 0*2;
168 CONSTANT CFG_TLB_TYPE : INTEGER := 1 + 0*2;
167 CONSTANT CFG_TLB_REP : INTEGER := 1;
169 CONSTANT CFG_TLB_REP : INTEGER := 1;
168
170
169 CONSTANT CFG_DSU : INTEGER := ENABLE_DSU;
171 CONSTANT CFG_DSU : INTEGER := ENABLE_DSU;
170 CONSTANT CFG_ITBSZ : INTEGER := 0;
172 CONSTANT CFG_ITBSZ : INTEGER := 0;
171 CONSTANT CFG_ATBSZ : INTEGER := 0;
173 CONSTANT CFG_ATBSZ : INTEGER := 0;
172
174
173 -- AMBA settings
175 -- AMBA settings
174 CONSTANT CFG_DEFMST : INTEGER := (0);
176 CONSTANT CFG_DEFMST : INTEGER := (0);
175 CONSTANT CFG_RROBIN : INTEGER := 1;
177 CONSTANT CFG_RROBIN : INTEGER := 1;
176 CONSTANT CFG_SPLIT : INTEGER := 0;
178 CONSTANT CFG_SPLIT : INTEGER := 0;
177 CONSTANT CFG_AHBIO : INTEGER := 16#FFF#;
179 CONSTANT CFG_AHBIO : INTEGER := 16#FFF#;
178 CONSTANT CFG_APBADDR : INTEGER := 16#800#;
180 CONSTANT CFG_APBADDR : INTEGER := 16#800#;
179
181
180 -- DSU UART
182 -- DSU UART
181 CONSTANT CFG_AHB_UART : INTEGER := ENABLE_AHB_UART;
183 CONSTANT CFG_AHB_UART : INTEGER := ENABLE_AHB_UART;
182
184
183 -- LEON2 memory controller
185 -- LEON2 memory controller
184 CONSTANT CFG_MCTRL_SDEN : INTEGER := 0;
186 CONSTANT CFG_MCTRL_SDEN : INTEGER := 0;
185
187
186 -- UART 1
188 -- UART 1
187 CONSTANT CFG_UART1_ENABLE : INTEGER := ENABLE_APB_UART;
189 CONSTANT CFG_UART1_ENABLE : INTEGER := ENABLE_APB_UART;
188 CONSTANT CFG_UART1_FIFO : INTEGER := 1;
190 CONSTANT CFG_UART1_FIFO : INTEGER := 1;
189
191
190 -- LEON3 interrupt controller
192 -- LEON3 interrupt controller
191 CONSTANT CFG_IRQ3_ENABLE : INTEGER := ENABLE_IRQMP;
193 CONSTANT CFG_IRQ3_ENABLE : INTEGER := ENABLE_IRQMP;
192
194
193 -- Modular timer
195 -- Modular timer
194 CONSTANT CFG_GPT_ENABLE : INTEGER := ENABLE_GPT;
196 CONSTANT CFG_GPT_ENABLE : INTEGER := ENABLE_GPT;
195 CONSTANT CFG_GPT_NTIM : INTEGER := (2);
197 CONSTANT CFG_GPT_NTIM : INTEGER := (2);
196 CONSTANT CFG_GPT_SW : INTEGER := (8);
198 CONSTANT CFG_GPT_SW : INTEGER := (8);
197 CONSTANT CFG_GPT_TW : INTEGER := (32);
199 CONSTANT CFG_GPT_TW : INTEGER := (32);
198 CONSTANT CFG_GPT_IRQ : INTEGER := (8);
200 CONSTANT CFG_GPT_IRQ : INTEGER := (8);
199 CONSTANT CFG_GPT_SEPIRQ : INTEGER := 1;
201 CONSTANT CFG_GPT_SEPIRQ : INTEGER := 1;
200 CONSTANT CFG_GPT_WDOGEN : INTEGER := 0;
202 CONSTANT CFG_GPT_WDOGEN : INTEGER := 0;
201 CONSTANT CFG_GPT_WDOG : INTEGER := 16#0#;
203 CONSTANT CFG_GPT_WDOG : INTEGER := 16#0#;
202 -----------------------------------------------------------------------------
204 -----------------------------------------------------------------------------
203
205
204 -----------------------------------------------------------------------------
206 -----------------------------------------------------------------------------
205 -- SIGNALs
207 -- SIGNALs
206 -----------------------------------------------------------------------------
208 -----------------------------------------------------------------------------
207 CONSTANT maxahbmsp : INTEGER := CFG_NCPU + CFG_AHB_UART + NB_AHB_MASTER;
209 CONSTANT maxahbmsp : INTEGER := CFG_NCPU + CFG_AHB_UART + NB_AHB_MASTER;
208 -- CLK & RST --
210 -- CLK & RST --
209 SIGNAL clk2x : STD_ULOGIC;
211 SIGNAL clk2x : STD_ULOGIC;
210 SIGNAL clkmn : STD_ULOGIC;
212 SIGNAL clkmn : STD_ULOGIC;
211 SIGNAL clkm : STD_ULOGIC;
213 SIGNAL clkm : STD_ULOGIC;
212 SIGNAL rstn : STD_ULOGIC;
214 SIGNAL rstn : STD_ULOGIC;
213 SIGNAL rstraw : STD_ULOGIC;
215 SIGNAL rstraw : STD_ULOGIC;
214 SIGNAL pciclk : STD_ULOGIC;
216 SIGNAL pciclk : STD_ULOGIC;
215 SIGNAL sdclkl : STD_ULOGIC;
217 SIGNAL sdclkl : STD_ULOGIC;
216 SIGNAL cgi : clkgen_in_type;
218 SIGNAL cgi : clkgen_in_type;
217 SIGNAL cgo : clkgen_out_type;
219 SIGNAL cgo : clkgen_out_type;
218 --- AHB / APB
220 --- AHB / APB
219 SIGNAL apbi : apb_slv_in_type;
221 SIGNAL apbi : apb_slv_in_type;
220 SIGNAL apbo : apb_slv_out_vector := (OTHERS => apb_none);
222 SIGNAL apbo : apb_slv_out_vector := (OTHERS => apb_none);
221 SIGNAL ahbsi : ahb_slv_in_type;
223 SIGNAL ahbsi : ahb_slv_in_type;
222 SIGNAL ahbso : ahb_slv_out_vector := (OTHERS => ahbs_none);
224 SIGNAL ahbso : ahb_slv_out_vector := (OTHERS => ahbs_none);
223 SIGNAL ahbmi : ahb_mst_in_type;
225 SIGNAL ahbmi : ahb_mst_in_type;
224 SIGNAL ahbmo : ahb_mst_out_vector := (OTHERS => ahbm_none);
226 SIGNAL ahbmo : ahb_mst_out_vector := (OTHERS => ahbm_none);
225 --UART
227 --UART
226 SIGNAL ahbuarti : uart_in_type;
228 SIGNAL ahbuarti : uart_in_type;
227 SIGNAL ahbuarto : uart_out_type;
229 SIGNAL ahbuarto : uart_out_type;
228 SIGNAL apbuarti : uart_in_type;
230 SIGNAL apbuarti : uart_in_type;
229 SIGNAL apbuarto : uart_out_type;
231 SIGNAL apbuarto : uart_out_type;
230 --MEM CTRLR
232 --MEM CTRLR
231 SIGNAL memi : memory_in_type;
233 SIGNAL memi : memory_in_type;
232 SIGNAL memo : memory_out_type;
234 SIGNAL memo : memory_out_type;
233 SIGNAL wpo : wprot_out_type;
235 SIGNAL wpo : wprot_out_type;
234 SIGNAL sdo : sdram_out_type;
236 SIGNAL sdo : sdram_out_type;
235 SIGNAL mbe : STD_LOGIC; -- enable memory programming
237 SIGNAL mbe : STD_LOGIC; -- enable memory programming
236 SIGNAL mbe_drive : STD_LOGIC; -- drive the MBE memory signal
238 SIGNAL mbe_drive : STD_LOGIC; -- drive the MBE memory signal
237 SIGNAL nSRAM_CE_s : STD_LOGIC_VECTOR(1 DOWNTO 0);
239 SIGNAL nSRAM_CE_s : STD_LOGIC_VECTOR(1 DOWNTO 0);
238 SIGNAL nSRAM_OE_s : STD_LOGIC;
240 SIGNAL nSRAM_OE_s : STD_LOGIC;
239 --IRQ
241 --IRQ
240 SIGNAL irqi : irq_in_vector(0 TO CFG_NCPU-1);
242 SIGNAL irqi : irq_in_vector(0 TO CFG_NCPU-1);
241 SIGNAL irqo : irq_out_vector(0 TO CFG_NCPU-1);
243 SIGNAL irqo : irq_out_vector(0 TO CFG_NCPU-1);
242 --Timer
244 --Timer
243 SIGNAL gpti : gptimer_in_type;
245 SIGNAL gpti : gptimer_in_type;
244 SIGNAL gpto : gptimer_out_type;
246 SIGNAL gpto : gptimer_out_type;
245 --DSU
247 --DSU
246 SIGNAL dbgi : l3_debug_in_vector(0 TO CFG_NCPU-1);
248 SIGNAL dbgi : l3_debug_in_vector(0 TO CFG_NCPU-1);
247 SIGNAL dbgo : l3_debug_out_vector(0 TO CFG_NCPU-1);
249 SIGNAL dbgo : l3_debug_out_vector(0 TO CFG_NCPU-1);
248 SIGNAL dsui : dsu_in_type;
250 SIGNAL dsui : dsu_in_type;
249 SIGNAL dsuo : dsu_out_type;
251 SIGNAL dsuo : dsu_out_type;
250 -----------------------------------------------------------------------------
252 -----------------------------------------------------------------------------
251
253
252
254
253 BEGIN
255 BEGIN
254
256
255
257
256 ----------------------------------------------------------------------
258 ----------------------------------------------------------------------
257 --- Reset and Clock generation -------------------------------------
259 --- Reset and Clock generation -------------------------------------
258 ----------------------------------------------------------------------
260 ----------------------------------------------------------------------
259
261
260 cgi.pllctrl <= "00";
262 cgi.pllctrl <= "00";
261 cgi.pllrst <= rstraw;
263 cgi.pllrst <= rstraw;
262
264
263 rst0 : rstgen PORT MAP (reset, clkm, cgo.clklock, rstn, rstraw);
265 rst0 : rstgen PORT MAP (reset, clkm, cgo.clklock, rstn, rstraw);
264
266
265 clkgen0 : clkgen -- clock generator
267 clkgen0 : clkgen -- clock generator
266 GENERIC MAP (clktech, CFG_CLKMUL, CFG_CLKDIV, CFG_MCTRL_SDEN,
268 GENERIC MAP (clktech, CFG_CLKMUL, CFG_CLKDIV, CFG_MCTRL_SDEN,
267 CFG_CLK_NOFB, 0, 0, 0, clk_freq, 0, 0, CFG_OCLKDIV)
269 CFG_CLK_NOFB, 0, 0, 0, clk_freq, 0, 0, CFG_OCLKDIV)
268 PORT MAP (clk, clk, clkm, clkmn, clk2x, sdclkl, pciclk, cgi, cgo);
270 PORT MAP (clk, clk, clkm, clkmn, clk2x, sdclkl, pciclk, cgi, cgo);
269
271
270 ----------------------------------------------------------------------
272 ----------------------------------------------------------------------
271 --- LEON3 processor / DSU / IRQ ------------------------------------
273 --- LEON3 processor / DSU / IRQ ------------------------------------
272 ----------------------------------------------------------------------
274 ----------------------------------------------------------------------
273
275
274 l3 : IF CFG_LEON3 = 1 GENERATE
276 l3 : IF CFG_LEON3 = 1 GENERATE
275 cpu : FOR i IN 0 TO CFG_NCPU-1 GENERATE
277 cpu : FOR i IN 0 TO CFG_NCPU-1 GENERATE
276 leon3_non_radhard : IF IS_RADHARD = 0 GENERATE
278 leon3_non_radhard : IF IS_RADHARD = 0 GENERATE
277 u0 : ENTITY gaisler.leon3s -- LEON3 processor
279 u0 : ENTITY gaisler.leon3s -- LEON3 processor
278 GENERIC MAP (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
280 GENERIC MAP (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
279 0, CFG_MAC, pclow, 0, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
281 0, CFG_MAC, pclow, 0, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
280 CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
282 CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
281 CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
283 CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
282 CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
284 CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
283 CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1)
285 CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1)
284 PORT MAP (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
286 PORT MAP (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
285 irqi(i), irqo(i), dbgi(i), dbgo(i));
287 irqi(i), irqo(i), dbgi(i), dbgo(i));
286 END GENERATE leon3_non_radhard;
288 END GENERATE leon3_non_radhard;
287
289
288 leon3_radhard_i : IF IS_RADHARD = 1 GENERATE
290 leon3_radhard_i : IF IS_RADHARD = 1 GENERATE
289 cpu : ENTITY gaisler.leon3ft
291 cpu : ENTITY gaisler.leon3ft
290 GENERIC MAP (
292 GENERIC MAP (
291 HINDEX => i, --: integer; --CPU_HINDEX,
293 HINDEX => i, --: integer; --CPU_HINDEX,
292 FABTECH => fabtech, --CFG_TECH,
294 FABTECH => fabtech, --CFG_TECH,
293 MEMTECH => memtech, --CFG_TECH,
295 MEMTECH => memtech, --CFG_TECH,
294 NWINDOWS => CFG_NWIN, --CFG_NWIN,
296 NWINDOWS => CFG_NWIN, --CFG_NWIN,
295 DSU => CFG_DSU, --condSel (HAS_DEBUG, 1, 0),
297 DSU => CFG_DSU, --condSel (HAS_DEBUG, 1, 0),
296 FPU => CFG_FPU, --CFG_FPU,
298 FPU => CFG_FPU, --CFG_FPU,
297 V8 => CFG_V8, --CFG_V8,
299 V8 => CFG_V8, --CFG_V8,
298 CP => 0, --CFG_CP,
300 CP => 0, --CFG_CP,
299 MAC => CFG_MAC, --CFG_MAC,
301 MAC => CFG_MAC, --CFG_MAC,
300 PCLOW => pclow, --CFG_PCLOW,
302 PCLOW => pclow, --CFG_PCLOW,
301 NOTAG => 0, --CFG_NOTAG,
303 NOTAG => 0, --CFG_NOTAG,
302 NWP => CFG_NWP, --CFG_NWP,
304 NWP => CFG_NWP, --CFG_NWP,
303 ICEN => CFG_ICEN, --CFG_ICEN,
305 ICEN => CFG_ICEN, --CFG_ICEN,
304 IREPL => CFG_IREPL, --CFG_IREPL,
306 IREPL => CFG_IREPL, --CFG_IREPL,
305 ISETS => CFG_ISETS, --CFG_ISETS,
307 ISETS => CFG_ISETS, --CFG_ISETS,
306 ILINESIZE => CFG_ILINE, --CFG_ILINE,
308 ILINESIZE => CFG_ILINE, --CFG_ILINE,
307 ISETSIZE => CFG_ISETSZ, --CFG_ISETSZ,
309 ISETSIZE => CFG_ISETSZ, --CFG_ISETSZ,
308 ISETLOCK => CFG_ILOCK, --CFG_ILOCK,
310 ISETLOCK => CFG_ILOCK, --CFG_ILOCK,
309 DCEN => CFG_DCEN, --CFG_DCEN,
311 DCEN => CFG_DCEN, --CFG_DCEN,
310 DREPL => CFG_DREPL, --CFG_DREPL,
312 DREPL => CFG_DREPL, --CFG_DREPL,
311 DSETS => CFG_DSETS, --CFG_DSETS,
313 DSETS => CFG_DSETS, --CFG_DSETS,
312 DLINESIZE => CFG_DLINE, --CFG_DLINE,
314 DLINESIZE => CFG_DLINE, --CFG_DLINE,
313 DSETSIZE => CFG_DSETSZ, --CFG_DSETSZ,
315 DSETSIZE => CFG_DSETSZ, --CFG_DSETSZ,
314 DSETLOCK => CFG_DLOCK, --CFG_DLOCK,
316 DSETLOCK => CFG_DLOCK, --CFG_DLOCK,
315 DSNOOP => CFG_DSNOOP, --CFG_DSNOOP,
317 DSNOOP => CFG_DSNOOP, --CFG_DSNOOP,
316 ILRAM => CFG_ILRAMEN, --CFG_ILRAMEN,
318 ILRAM => CFG_ILRAMEN, --CFG_ILRAMEN,
317 ILRAMSIZE => CFG_ILRAMSZ, --CFG_ILRAMSZ,
319 ILRAMSIZE => CFG_ILRAMSZ, --CFG_ILRAMSZ,
318 ILRAMSTART => CFG_ILRAMADDR, --CFG_ILRAMADDR,
320 ILRAMSTART => CFG_ILRAMADDR, --CFG_ILRAMADDR,
319 DLRAM => CFG_DLRAMEN, --CFG_DLRAMEN,
321 DLRAM => CFG_DLRAMEN, --CFG_DLRAMEN,
320 DLRAMSIZE => CFG_DLRAMSZ, --CFG_DLRAMSZ,
322 DLRAMSIZE => CFG_DLRAMSZ, --CFG_DLRAMSZ,
321 DLRAMSTART => CFG_DLRAMADDR, --CFG_DLRAMADDR,
323 DLRAMSTART => CFG_DLRAMADDR, --CFG_DLRAMADDR,
322 MMUEN => CFG_MMUEN, --CFG_MMUEN,
324 MMUEN => CFG_MMUEN, --CFG_MMUEN,
323 ITLBNUM => CFG_ITLBNUM, --CFG_ITLBNUM,
325 ITLBNUM => CFG_ITLBNUM, --CFG_ITLBNUM,
324 DTLBNUM => CFG_DTLBNUM, --CFG_DTLBNUM,
326 DTLBNUM => CFG_DTLBNUM, --CFG_DTLBNUM,
325 TLB_TYPE => CFG_TLB_TYPE, --CFG_TLB_TYPE,
327 TLB_TYPE => CFG_TLB_TYPE, --CFG_TLB_TYPE,
326 TLB_REP => CFG_TLB_REP, --CFG_TLB_REP,
328 TLB_REP => CFG_TLB_REP, --CFG_TLB_REP,
327 LDDEL => CFG_LDDEL, --CFG_LDDEL,
329 LDDEL => CFG_LDDEL, --CFG_LDDEL,
328 DISAS => disas, --condSel (SIM_ENABLED, 1, 0),
330 DISAS => disas, --condSel (SIM_ENABLED, 1, 0),
329 TBUF => CFG_ITBSZ, --CFG_ITBSZ,
331 TBUF => CFG_ITBSZ, --CFG_ITBSZ,
330 PWD => CFG_PWD, --CFG_PWD,
332 PWD => CFG_PWD, --CFG_PWD,
331 SVT => CFG_SVT, --CFG_SVT,
333 SVT => CFG_SVT, --CFG_SVT,
332 RSTADDR => CFG_RSTADDR, --CFG_RSTADDR,
334 RSTADDR => CFG_RSTADDR, --CFG_RSTADDR,
333 SMP => CFG_NCPU-1, --CFG_NCPU-1,
335 SMP => CFG_NCPU-1, --CFG_NCPU-1,
334 IUFT => 2, --: integer range 0 to 4;--CFG_IUFT_EN,
336 IUFT => 2, --: integer range 0 to 4;--CFG_IUFT_EN,
335 FPFT => 1, --: integer range 0 to 4;--CFG_FPUFT_EN,
337 FPFT => 1, --: integer range 0 to 4;--CFG_FPUFT_EN,
336 CMFT => 1, --: integer range 0 to 1;--CFG_CACHE_FT_EN,
338 CMFT => 1, --: integer range 0 to 1;--CFG_CACHE_FT_EN,
337 IUINJ => 0, --: integer; --CFG_RF_ERRINJ,
339 IUINJ => 0, --: integer; --CFG_RF_ERRINJ,
338 CEINJ => 0, --: integer range 0 to 3;--CFG_CACHE_ERRINJ,
340 CEINJ => 0, --: integer range 0 to 3;--CFG_CACHE_ERRINJ,
339 CACHED => 0, --: integer; --CFG_DFIXED,
341 CACHED => 0, --: integer; --CFG_DFIXED,
340 NETLIST => 0, --: integer; --CFG_LEON3_NETLIST,
342 NETLIST => 0, --: integer; --CFG_LEON3_NETLIST,
341 SCANTEST => 0, --: integer; --CFG_SCANTEST,
343 SCANTEST => 0, --: integer; --CFG_SCANTEST,
342 MMUPGSZ => 0, --: integer range 0 to 5;--CFG_MMU_PAGE,
344 MMUPGSZ => 0, --: integer range 0 to 5;--CFG_MMU_PAGE,
343 BP => 1) --CFG_BP
345 BP => 1) --CFG_BP
344 PORT MAP ( --
346 PORT MAP ( --
345 rstn => rstn, --rst_n,
347 rstn => rstn, --rst_n,
346 clk => clkm, --clk,
348 clk => clkm, --clk,
347 ahbi => ahbmi, --ahbmi,
349 ahbi => ahbmi, --ahbmi,
348 ahbo => ahbmo(i), --ahbmo(CPU_HINDEX),
350 ahbo => ahbmo(i), --ahbmo(CPU_HINDEX),
349 ahbsi => ahbsi, --ahbsi,
351 ahbsi => ahbsi, --ahbsi,
350 ahbso => ahbso, --ahbso,
352 ahbso => ahbso, --ahbso,
351 irqi => irqi(i), --irqi(CPU_HINDEX),
353 irqi => irqi(i), --irqi(CPU_HINDEX),
352 irqo => irqo(i), --irqo(CPU_HINDEX),
354 irqo => irqo(i), --irqo(CPU_HINDEX),
353 dbgi => dbgi(i), --dbgi(CPU_HINDEX),
355 dbgi => dbgi(i), --dbgi(CPU_HINDEX),
354 dbgo => dbgo(i), --dbgo(CPU_HINDEX),
356 dbgo => dbgo(i), --dbgo(CPU_HINDEX),
355 gclk => clkm --clk
357 gclk => clkm --clk
356 );
358 );
357 END GENERATE leon3_radhard_i;
359 END GENERATE leon3_radhard_i;
358
360
359 END GENERATE;
361 END GENERATE;
360 errorn_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (errorn, dbgo(0).error);
362 errorn_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (errorn, dbgo(0).error);
361
363
362 dsugen : IF CFG_DSU = 1 GENERATE
364 dsugen : IF CFG_DSU = 1 GENERATE
363 dsu0 : dsu3 -- LEON3 Debug Support Unit
365 dsu0 : dsu3 -- LEON3 Debug Support Unit
364 GENERIC MAP (hindex => 2, haddr => 16#900#, hmask => 16#F00#,
366 GENERIC MAP (hindex => 2, haddr => 16#900#, hmask => 16#F00#,
365 ncpu => CFG_NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ)
367 ncpu => CFG_NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ)
366 PORT MAP (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo);
368 PORT MAP (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo);
367 dsui.enable <= '1';
369 dsui.enable <= '1';
368 dsui.break <= '0';
370 dsui.break <= '0';
369 END GENERATE;
371 END GENERATE;
370 END GENERATE;
372 END GENERATE;
371
373
372 nodsu : IF CFG_DSU = 0 GENERATE
374 nodsu : IF CFG_DSU = 0 GENERATE
373 ahbso(2) <= ahbs_none;
375 ahbso(2) <= ahbs_none;
374 dsuo.tstop <= '0';
376 dsuo.tstop <= '0';
375 dsuo.active <= '0';
377 dsuo.active <= '0';
376 END GENERATE;
378 END GENERATE;
377
379
378 irqctrl : IF CFG_IRQ3_ENABLE /= 0 GENERATE
380 irqctrl : IF CFG_IRQ3_ENABLE /= 0 GENERATE
379 irqctrl0 : irqmp -- interrupt controller
381 irqctrl0 : irqmp -- interrupt controller
380 GENERIC MAP (pindex => 2, paddr => 2, ncpu => CFG_NCPU)
382 GENERIC MAP (pindex => 2, paddr => 2, ncpu => CFG_NCPU)
381 PORT MAP (rstn, clkm, apbi, apbo(2), irqo, irqi);
383 PORT MAP (rstn, clkm, apbi, apbo(2), irqo, irqi);
382 END GENERATE;
384 END GENERATE;
383 irq3 : IF CFG_IRQ3_ENABLE = 0 GENERATE
385 irq3 : IF CFG_IRQ3_ENABLE = 0 GENERATE
384 x : FOR i IN 0 TO CFG_NCPU-1 GENERATE
386 x : FOR i IN 0 TO CFG_NCPU-1 GENERATE
385 irqi(i).irl <= "0000";
387 irqi(i).irl <= "0000";
386 END GENERATE;
388 END GENERATE;
387 apbo(2) <= apb_none;
389 apbo(2) <= apb_none;
388 END GENERATE;
390 END GENERATE;
389
391
390 ----------------------------------------------------------------------
392 ----------------------------------------------------------------------
391 --- Memory controllers ---------------------------------------------
393 --- Memory controllers ---------------------------------------------
392 ----------------------------------------------------------------------
394 ----------------------------------------------------------------------
393 ESAMEMCT : IF USES_IAP_MEMCTRLR = 0 GENERATE
395 ESAMEMCT : IF USES_IAP_MEMCTRLR = 0 GENERATE
394 memctrlr : mctrl GENERIC MAP (
396 memctrlr : mctrl GENERIC MAP (
395 hindex => 0,
397 hindex => 0,
396 pindex => 0,
398 pindex => 0,
397 paddr => 0,
399 paddr => 0,
398 srbanks => 1
400 srbanks => 1
399 )
401 )
400 PORT MAP (rstn, clkm, memi, memo, ahbsi, ahbso(0), apbi, apbo(0), wpo, sdo);
402 PORT MAP (rstn, clkm, memi, memo, ahbsi, ahbso(0), apbi, apbo(0), wpo, sdo);
401 memi.bexcn <= '1';
403 memi.bexcn <= '1';
402 memi.brdyn <= '1';
404 memi.brdyn <= '1';
403
405
404 nSRAM_CE_s <= NOT (memo.ramsn(1 DOWNTO 0));
406 nSRAM_CE_s <= NOT (memo.ramsn(1 DOWNTO 0));
405 nSRAM_OE_s <= memo.ramoen(0);
407 nSRAM_OE_s <= memo.ramoen(0);
406 END GENERATE;
408 END GENERATE;
407
409
408 IAPMEMCT : IF USES_IAP_MEMCTRLR = 1 GENERATE
410 IAPMEMCT : IF USES_IAP_MEMCTRLR = 1 GENERATE
409 memctrlr : srctrle_0ws
411 memctrlr : srctrle_0ws
410 GENERIC MAP(
412 GENERIC MAP(
411 hindex => 0,
413 hindex => 0,
412 pindex => 0,
414 pindex => 0,
413 paddr => 0,
415 paddr => 0,
414 srbanks => 2,
416 srbanks => 2,
415 banksz => 8, --512k * 32
417 banksz => SRBANKSZ, --512k * 32
416 rmw => 1,
418 rmw => 1,
417 --Aeroflex memory generics:
419 --Aeroflex memory generics:
420 mbpbusy => BYPASS_EDAC_MEMCTRLR,
418 mprog => 1, -- program memory by default values after reset
421 mprog => 1, -- program memory by default values after reset
419 mpsrate => 15, -- default scrub rate period
422 mpsrate => 15, -- default scrub rate period
420 mpb2s => 14, -- default busy to scrub delay
423 mpb2s => 14, -- default busy to scrub delay
421 mpapb => 1, -- instantiate apb register
424 mpapb => 1, -- instantiate apb register
422 mchipcnt => 2,
425 mchipcnt => 2,
423 mpenall => 1 -- when 0 program only E1 chip, else program all dies
426 mpenall => 1 -- when 0 program only E1 chip, else program all dies
424 )
427 )
425 PORT MAP (
428 PORT MAP (
426 rst => rstn,
429 rst => rstn,
427 clk => clkm,
430 clk => clkm,
428 ahbsi => ahbsi,
431 ahbsi => ahbsi,
429 ahbso => ahbso(0),
432 ahbso => ahbso(0),
430 apbi => apbi,
433 apbi => apbi,
431 apbo => apbo(0),
434 apbo => apbo(0),
432 sri => memi,
435 sri => memi,
433 sro => memo,
436 sro => memo,
434 --Aeroflex memory signals:
437 --Aeroflex memory signals:
435 ucerr => OPEN, -- uncorrectable error signal
438 ucerr => OPEN, -- uncorrectable error signal
436 mbe => mbe, -- enable memory programming
439 mbe => mbe, -- enable memory programming
437 mbe_drive => mbe_drive -- drive the MBE memory signal
440 mbe_drive => mbe_drive -- drive the MBE memory signal
438 );
441 );
439
442
440 memi.brdyn <= nSRAM_READY;
443 memi.brdyn <= nSRAM_READY;
441
444
442 mbe_pad : iopad
445 mbe_pad : iopad
443 GENERIC MAP(tech => padtech)
446 GENERIC MAP(tech => padtech, oepol => USES_IAP_MEMCTRLR)
444 PORT MAP(pad => SRAM_MBE,
447 PORT MAP(pad => SRAM_MBE,
445 i => mbe,
448 i => mbe,
446 en => mbe_drive,
449 en => mbe_drive,
447 o => memi.bexcn);
450 o => memi.bexcn);
448
451
449 nSRAM_CE_s <= (memo.ramsn(1 DOWNTO 0));
452 nSRAM_CE_s <= (memo.ramsn(1 DOWNTO 0));
450 nSRAM_OE_s <= memo.oen;
453 nSRAM_OE_s <= memo.oen;
451
454
452 END GENERATE;
455 END GENERATE;
453
456
454
457
455 memi.writen <= '1';
458 memi.writen <= '1';
456 memi.wrn <= "1111";
459 memi.wrn <= "1111";
457 memi.bwidth <= "10";
460 memi.bwidth <= "10";
458
461
459 bdr : FOR i IN 0 TO 3 GENERATE
462 bdr : FOR i IN 0 TO 3 GENERATE
460 data_pad : iopadv GENERIC MAP (tech => padtech, width => 8, oepol => USES_IAP_MEMCTRLR)
463 data_pad : iopadv GENERIC MAP (tech => padtech, width => 8, oepol => USES_IAP_MEMCTRLR)
461 PORT MAP (
464 PORT MAP (
462 data(31-i*8 DOWNTO 24-i*8),
465 data(31-i*8 DOWNTO 24-i*8),
463 memo.data(31-i*8 DOWNTO 24-i*8),
466 memo.data(31-i*8 DOWNTO 24-i*8),
464 memo.bdrive(i),
467 memo.bdrive(i),
465 memi.data(31-i*8 DOWNTO 24-i*8));
468 memi.data(31-i*8 DOWNTO 24-i*8));
466 END GENERATE;
469 END GENERATE;
467
470
468 addr_pad : outpadv GENERIC MAP (width => ADDRESS_SIZE, tech => padtech)
471 addr_pad : outpadv GENERIC MAP (width => ADDRESS_SIZE, tech => padtech)
469 PORT MAP (address, memo.address(ADDRESS_SIZE+1 DOWNTO 2));
472 PORT MAP (address, memo.address(ADDRESS_SIZE+1 DOWNTO 2));
470 rams_pad : outpadv GENERIC MAP (tech => padtech, width => 2) PORT MAP (nSRAM_CE, nSRAM_CE_s);
473 rams_pad : outpadv GENERIC MAP (tech => padtech, width => 2) PORT MAP (nSRAM_CE, nSRAM_CE_s);
471 oen_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_OE, nSRAM_OE_s);
474 oen_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_OE, nSRAM_OE_s);
472 nBWE_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_WE, memo.writen);
475 nBWE_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_WE, memo.writen);
473 nBWa_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE0, memo.mben(3));
476 nBWa_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE0, memo.mben(3));
474 nBWb_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE1, memo.mben(2));
477 nBWb_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE1, memo.mben(2));
475 nBWc_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE2, memo.mben(1));
478 nBWc_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE2, memo.mben(1));
476 nBWd_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE3, memo.mben(0));
479 nBWd_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE3, memo.mben(0));
477
480
478
481
479
482
480 ----------------------------------------------------------------------
483 ----------------------------------------------------------------------
481 --- AHB CONTROLLER -------------------------------------------------
484 --- AHB CONTROLLER -------------------------------------------------
482 ----------------------------------------------------------------------
485 ----------------------------------------------------------------------
483 ahb0 : ahbctrl -- AHB arbiter/multiplexer
486 ahb0 : ahbctrl -- AHB arbiter/multiplexer
484 GENERIC MAP (defmast => CFG_DEFMST, split => CFG_SPLIT,
487 GENERIC MAP (defmast => CFG_DEFMST, split => CFG_SPLIT,
485 rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO,
488 rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO,
486 ioen => 0, nahbm => maxahbmsp, nahbs => 8)
489 ioen => 0, nahbm => maxahbmsp, nahbs => 8)
487 PORT MAP (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
490 PORT MAP (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
488
491
489 ----------------------------------------------------------------------
492 ----------------------------------------------------------------------
490 --- AHB UART -------------------------------------------------------
493 --- AHB UART -------------------------------------------------------
491 ----------------------------------------------------------------------
494 ----------------------------------------------------------------------
492 dcomgen : IF CFG_AHB_UART = 1 GENERATE
495 dcomgen : IF CFG_AHB_UART = 1 GENERATE
493 dcom0 : ahbuart
496 dcom0 : ahbuart
494 GENERIC MAP (hindex => maxahbmsp-1, pindex => 4, paddr => 4)
497 GENERIC MAP (hindex => maxahbmsp-1, pindex => 4, paddr => 4)
495 PORT MAP (rstn, clkm, ahbuarti, ahbuarto, apbi, apbo(4), ahbmi, ahbmo(maxahbmsp-1));
498 PORT MAP (rstn, clkm, ahbuarti, ahbuarto, apbi, apbo(4), ahbmi, ahbmo(maxahbmsp-1));
496 dsurx_pad : inpad GENERIC MAP (tech => padtech) PORT MAP (ahbrxd, ahbuarti.rxd);
499 dsurx_pad : inpad GENERIC MAP (tech => padtech) PORT MAP (ahbrxd, ahbuarti.rxd);
497 dsutx_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (ahbtxd, ahbuarto.txd);
500 dsutx_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (ahbtxd, ahbuarto.txd);
498 END GENERATE;
501 END GENERATE;
499 nouah : IF CFG_AHB_UART = 0 GENERATE apbo(4) <= apb_none; END GENERATE;
502 nouah : IF CFG_AHB_UART = 0 GENERATE apbo(4) <= apb_none; END GENERATE;
500
503
501 ----------------------------------------------------------------------
504 ----------------------------------------------------------------------
502 --- APB Bridge -----------------------------------------------------
505 --- APB Bridge -----------------------------------------------------
503 ----------------------------------------------------------------------
506 ----------------------------------------------------------------------
504 apb0 : apbctrl -- AHB/APB bridge
507 apb0 : apbctrl -- AHB/APB bridge
505 GENERIC MAP (hindex => 1, haddr => CFG_APBADDR)
508 GENERIC MAP (hindex => 1, haddr => CFG_APBADDR)
506 PORT MAP (rstn, clkm, ahbsi, ahbso(1), apbi, apbo);
509 PORT MAP (rstn, clkm, ahbsi, ahbso(1), apbi, apbo);
507
510
508 ----------------------------------------------------------------------
511 ----------------------------------------------------------------------
509 --- GPT Timer ------------------------------------------------------
512 --- GPT Timer ------------------------------------------------------
510 ----------------------------------------------------------------------
513 ----------------------------------------------------------------------
511 gpt : IF CFG_GPT_ENABLE /= 0 GENERATE
514 gpt : IF CFG_GPT_ENABLE /= 0 GENERATE
512 timer0 : gptimer -- timer unit
515 timer0 : gptimer -- timer unit
513 GENERIC MAP (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ,
516 GENERIC MAP (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ,
514 sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM,
517 sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM,
515 nbits => CFG_GPT_TW)
518 nbits => CFG_GPT_TW)
516 PORT MAP (rstn, clkm, apbi, apbo(3), gpti, gpto);
519 PORT MAP (rstn, clkm, apbi, apbo(3), gpti, gpto);
517 gpti.dhalt <= dsuo.tstop;
520 gpti.dhalt <= dsuo.tstop;
518 gpti.extclk <= '0';
521 gpti.extclk <= '0';
519 END GENERATE;
522 END GENERATE;
520 notim : IF CFG_GPT_ENABLE = 0 GENERATE apbo(3) <= apb_none; END GENERATE;
523 notim : IF CFG_GPT_ENABLE = 0 GENERATE apbo(3) <= apb_none; END GENERATE;
521
524
522
525
523 ----------------------------------------------------------------------
526 ----------------------------------------------------------------------
524 --- APB UART -------------------------------------------------------
527 --- APB UART -------------------------------------------------------
525 ----------------------------------------------------------------------
528 ----------------------------------------------------------------------
526 ua1 : IF CFG_UART1_ENABLE /= 0 GENERATE
529 ua1 : IF CFG_UART1_ENABLE /= 0 GENERATE
527 uart1 : apbuart -- UART 1
530 uart1 : apbuart -- UART 1
528 GENERIC MAP (pindex => 1, paddr => 1, pirq => 2, console => dbguart,
531 GENERIC MAP (pindex => 1, paddr => 1, pirq => 2, console => dbguart,
529 fifosize => CFG_UART1_FIFO)
532 fifosize => CFG_UART1_FIFO)
530 PORT MAP (rstn, clkm, apbi, apbo(1), apbuarti, apbuarto);
533 PORT MAP (rstn, clkm, apbi, apbo(1), apbuarti, apbuarto);
531 apbuarti.rxd <= urxd1;
534 apbuarti.rxd <= urxd1;
532 apbuarti.extclk <= '0';
535 apbuarti.extclk <= '0';
533 utxd1 <= apbuarto.txd;
536 utxd1 <= apbuarto.txd;
534 apbuarti.ctsn <= '0';
537 apbuarti.ctsn <= '0';
535 END GENERATE;
538 END GENERATE;
536 noua0 : IF CFG_UART1_ENABLE = 0 GENERATE apbo(1) <= apb_none; END GENERATE;
539 noua0 : IF CFG_UART1_ENABLE = 0 GENERATE apbo(1) <= apb_none; END GENERATE;
537
540
538 -------------------------------------------------------------------------------
541 -------------------------------------------------------------------------------
539 -- AMBA BUS -------------------------------------------------------------------
542 -- AMBA BUS -------------------------------------------------------------------
540 -------------------------------------------------------------------------------
543 -------------------------------------------------------------------------------
541
544
542 -- APB --------------------------------------------------------------------
545 -- APB --------------------------------------------------------------------
543 apbi_ext <= apbi;
546 apbi_ext <= apbi;
544 all_apb : FOR I IN 0 TO NB_APB_SLAVE-1 GENERATE
547 all_apb : FOR I IN 0 TO NB_APB_SLAVE-1 GENERATE
545 max_16_apb : IF I + 5 < 16 GENERATE
548 max_16_apb : IF I + 5 < 16 GENERATE
546 apbo(I+5) <= apbo_ext(I+5);
549 apbo(I+5) <= apbo_ext(I+5);
547 END GENERATE max_16_apb;
550 END GENERATE max_16_apb;
548 END GENERATE all_apb;
551 END GENERATE all_apb;
549 -- AHB_Slave --------------------------------------------------------------
552 -- AHB_Slave --------------------------------------------------------------
550 ahbi_s_ext <= ahbsi;
553 ahbi_s_ext <= ahbsi;
551 all_ahbs : FOR I IN 0 TO NB_AHB_SLAVE-1 GENERATE
554 all_ahbs : FOR I IN 0 TO NB_AHB_SLAVE-1 GENERATE
552 max_16_ahbs : IF I + 3 < 16 GENERATE
555 max_16_ahbs : IF I + 3 < 16 GENERATE
553 ahbso(I+3) <= ahbo_s_ext(I+3);
556 ahbso(I+3) <= ahbo_s_ext(I+3);
554 END GENERATE max_16_ahbs;
557 END GENERATE max_16_ahbs;
555 END GENERATE all_ahbs;
558 END GENERATE all_ahbs;
556 -- AHB_Master -------------------------------------------------------------
559 -- AHB_Master -------------------------------------------------------------
557 ahbi_m_ext <= ahbmi;
560 ahbi_m_ext <= ahbmi;
558 all_ahbm : FOR I IN 0 TO NB_AHB_MASTER-1 GENERATE
561 all_ahbm : FOR I IN 0 TO NB_AHB_MASTER-1 GENERATE
559 max_16_ahbm : IF I + CFG_NCPU + CFG_AHB_UART < 16 GENERATE
562 max_16_ahbm : IF I + CFG_NCPU + CFG_AHB_UART < 16 GENERATE
560 ahbmo(I + CFG_NCPU) <= ahbo_m_ext(I+CFG_NCPU);
563 ahbmo(I + CFG_NCPU) <= ahbo_m_ext(I+CFG_NCPU);
561 END GENERATE max_16_ahbm;
564 END GENERATE max_16_ahbm;
562 END GENERATE all_ahbm;
565 END GENERATE all_ahbm;
563
566
564
567
565
568
566 END Behavioral;
569 END Behavioral;
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@@ -1,143 +1,145
1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
18 -------------------------------------------------------------------------------
19 -- Author : Jean-christophe Pellion
19 -- Author : Jean-christophe Pellion
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 -- jean-christophe.pellion@easii-ic.com
21 -- jean-christophe.pellion@easii-ic.com
22 ----------------------------------------------------------------------------
22 ----------------------------------------------------------------------------
23 LIBRARY ieee;
23 LIBRARY ieee;
24 USE ieee.std_logic_1164.ALL;
24 USE ieee.std_logic_1164.ALL;
25 LIBRARY grlib;
25 LIBRARY grlib;
26 USE grlib.amba.ALL;
26 USE grlib.amba.ALL;
27
27
28 PACKAGE lpp_leon3_soc_pkg IS
28 PACKAGE lpp_leon3_soc_pkg IS
29
29
30 type soc_ahb_mst_out_vector is array (natural range <>) of ahb_mst_out_type;
30 type soc_ahb_mst_out_vector is array (natural range <>) of ahb_mst_out_type;
31 type soc_ahb_slv_out_vector is array (natural range <>) of ahb_slv_out_type;
31 type soc_ahb_slv_out_vector is array (natural range <>) of ahb_slv_out_type;
32 type soc_apb_slv_out_vector is array (natural range <>) of apb_slv_out_type;
32 type soc_apb_slv_out_vector is array (natural range <>) of apb_slv_out_type;
33
33
34 COMPONENT leon3_soc
34 COMPONENT leon3_soc
35 GENERIC (
35 GENERIC (
36 fabtech : INTEGER;
36 fabtech : INTEGER;
37 memtech : INTEGER;
37 memtech : INTEGER;
38 padtech : INTEGER;
38 padtech : INTEGER;
39 clktech : INTEGER;
39 clktech : INTEGER;
40 disas : INTEGER;
40 disas : INTEGER;
41 dbguart : INTEGER;
41 dbguart : INTEGER;
42 pclow : INTEGER;
42 pclow : INTEGER;
43 clk_freq : INTEGER;
43 clk_freq : INTEGER;
44 IS_RADHARD : INTEGER;
44 IS_RADHARD : INTEGER;
45 NB_CPU : INTEGER;
45 NB_CPU : INTEGER;
46 ENABLE_FPU : INTEGER;
46 ENABLE_FPU : INTEGER;
47 FPU_NETLIST : INTEGER;
47 FPU_NETLIST : INTEGER;
48 ENABLE_DSU : INTEGER;
48 ENABLE_DSU : INTEGER;
49 ENABLE_AHB_UART : INTEGER;
49 ENABLE_AHB_UART : INTEGER;
50 ENABLE_APB_UART : INTEGER;
50 ENABLE_APB_UART : INTEGER;
51 ENABLE_IRQMP : INTEGER;
51 ENABLE_IRQMP : INTEGER;
52 ENABLE_GPT : INTEGER;
52 ENABLE_GPT : INTEGER;
53 NB_AHB_MASTER : INTEGER;
53 NB_AHB_MASTER : INTEGER;
54 NB_AHB_SLAVE : INTEGER;
54 NB_AHB_SLAVE : INTEGER;
55 NB_APB_SLAVE : INTEGER;
55 NB_APB_SLAVE : INTEGER;
56 ADDRESS_SIZE : INTEGER;
56 ADDRESS_SIZE : INTEGER;
57 USES_IAP_MEMCTRLR : INTEGER
57 USES_IAP_MEMCTRLR : INTEGER;
58 BYPASS_EDAC_MEMCTRLR : STD_LOGIC;
59 SRBANKSZ : INTEGER := 8
58 );
60 );
59 PORT (
61 PORT (
60 clk : IN STD_ULOGIC;
62 clk : IN STD_ULOGIC;
61 reset : IN STD_ULOGIC;
63 reset : IN STD_ULOGIC;
62
64
63 errorn : OUT STD_ULOGIC;
65 errorn : OUT STD_ULOGIC;
64
66
65 -- UART AHB ---------------------------------------------------------------
67 -- UART AHB ---------------------------------------------------------------
66 ahbrxd : IN STD_ULOGIC; -- DSU rx data
68 ahbrxd : IN STD_ULOGIC; -- DSU rx data
67 ahbtxd : OUT STD_ULOGIC; -- DSU tx data
69 ahbtxd : OUT STD_ULOGIC; -- DSU tx data
68
70
69 -- UART APB ---------------------------------------------------------------
71 -- UART APB ---------------------------------------------------------------
70 urxd1 : IN STD_ULOGIC; -- UART1 rx data
72 urxd1 : IN STD_ULOGIC; -- UART1 rx data
71 utxd1 : OUT STD_ULOGIC; -- UART1 tx data
73 utxd1 : OUT STD_ULOGIC; -- UART1 tx data
72
74
73 -- RAM --------------------------------------------------------------------
75 -- RAM --------------------------------------------------------------------
74 address : OUT STD_LOGIC_VECTOR(ADDRESS_SIZE-1 DOWNTO 0);
76 address : OUT STD_LOGIC_VECTOR(ADDRESS_SIZE-1 DOWNTO 0);
75 data : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0);
77 data : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0);
76 nSRAM_BE0 : OUT STD_LOGIC;
78 nSRAM_BE0 : OUT STD_LOGIC;
77 nSRAM_BE1 : OUT STD_LOGIC;
79 nSRAM_BE1 : OUT STD_LOGIC;
78 nSRAM_BE2 : OUT STD_LOGIC;
80 nSRAM_BE2 : OUT STD_LOGIC;
79 nSRAM_BE3 : OUT STD_LOGIC;
81 nSRAM_BE3 : OUT STD_LOGIC;
80 nSRAM_WE : OUT STD_LOGIC;
82 nSRAM_WE : OUT STD_LOGIC;
81 nSRAM_CE : OUT STD_LOGIC_VECTOR(1 downto 0);
83 nSRAM_CE : OUT STD_LOGIC_VECTOR(1 downto 0);
82 nSRAM_OE : OUT STD_LOGIC;
84 nSRAM_OE : OUT STD_LOGIC;
83 nSRAM_READY : IN STD_LOGIC;
85 nSRAM_READY : IN STD_LOGIC;
84 SRAM_MBE : INOUT STD_LOGIC;
86 SRAM_MBE : INOUT STD_LOGIC;
85 -- APB --------------------------------------------------------------------
87 -- APB --------------------------------------------------------------------
86 apbi_ext : OUT apb_slv_in_type;
88 apbi_ext : OUT apb_slv_in_type;
87 apbo_ext : IN soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5);
89 apbo_ext : IN soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5);
88 -- AHB_Slave --------------------------------------------------------------
90 -- AHB_Slave --------------------------------------------------------------
89 ahbi_s_ext : OUT ahb_slv_in_type;
91 ahbi_s_ext : OUT ahb_slv_in_type;
90 ahbo_s_ext : IN soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3);
92 ahbo_s_ext : IN soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3);
91 -- AHB_Master -------------------------------------------------------------
93 -- AHB_Master -------------------------------------------------------------
92 ahbi_m_ext : OUT AHB_Mst_In_Type;
94 ahbi_m_ext : OUT AHB_Mst_In_Type;
93 ahbo_m_ext : IN soc_ahb_mst_out_vector(NB_AHB_MASTER-1+NB_CPU DOWNTO NB_CPU));
95 ahbo_m_ext : IN soc_ahb_mst_out_vector(NB_AHB_MASTER-1+NB_CPU DOWNTO NB_CPU));
94 END COMPONENT;
96 END COMPONENT;
95
97
96
98
97 --COMPONENT leon3ft_soc
99 --COMPONENT leon3ft_soc
98 -- GENERIC (
100 -- GENERIC (
99 -- fabtech : INTEGER;
101 -- fabtech : INTEGER;
100 -- memtech : INTEGER;
102 -- memtech : INTEGER;
101 -- padtech : INTEGER;
103 -- padtech : INTEGER;
102 -- clktech : INTEGER;
104 -- clktech : INTEGER;
103 -- disas : INTEGER;
105 -- disas : INTEGER;
104 -- dbguart : INTEGER;
106 -- dbguart : INTEGER;
105 -- pclow : INTEGER;
107 -- pclow : INTEGER;
106 -- clk_freq : INTEGER;
108 -- clk_freq : INTEGER;
107 -- NB_CPU : INTEGER;
109 -- NB_CPU : INTEGER;
108 -- ENABLE_FPU : INTEGER;
110 -- ENABLE_FPU : INTEGER;
109 -- FPU_NETLIST : INTEGER;
111 -- FPU_NETLIST : INTEGER;
110 -- ENABLE_DSU : INTEGER;
112 -- ENABLE_DSU : INTEGER;
111 -- ENABLE_AHB_UART : INTEGER;
113 -- ENABLE_AHB_UART : INTEGER;
112 -- ENABLE_APB_UART : INTEGER;
114 -- ENABLE_APB_UART : INTEGER;
113 -- ENABLE_IRQMP : INTEGER;
115 -- ENABLE_IRQMP : INTEGER;
114 -- ENABLE_GPT : INTEGER;
116 -- ENABLE_GPT : INTEGER;
115 -- NB_AHB_MASTER : INTEGER;
117 -- NB_AHB_MASTER : INTEGER;
116 -- NB_AHB_SLAVE : INTEGER;
118 -- NB_AHB_SLAVE : INTEGER;
117 -- NB_APB_SLAVE : INTEGER);
119 -- NB_APB_SLAVE : INTEGER);
118 -- PORT (
120 -- PORT (
119 -- clk : IN STD_ULOGIC;
121 -- clk : IN STD_ULOGIC;
120 -- reset : IN STD_ULOGIC;
122 -- reset : IN STD_ULOGIC;
121 -- errorn : OUT STD_ULOGIC;
123 -- errorn : OUT STD_ULOGIC;
122 -- ahbrxd : IN STD_ULOGIC;
124 -- ahbrxd : IN STD_ULOGIC;
123 -- ahbtxd : OUT STD_ULOGIC;
125 -- ahbtxd : OUT STD_ULOGIC;
124 -- urxd1 : IN STD_ULOGIC;
126 -- urxd1 : IN STD_ULOGIC;
125 -- utxd1 : OUT STD_ULOGIC;
127 -- utxd1 : OUT STD_ULOGIC;
126 -- address : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
128 -- address : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
127 -- data : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0);
129 -- data : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0);
128 -- nSRAM_BE0 : OUT STD_LOGIC;
130 -- nSRAM_BE0 : OUT STD_LOGIC;
129 -- nSRAM_BE1 : OUT STD_LOGIC;
131 -- nSRAM_BE1 : OUT STD_LOGIC;
130 -- nSRAM_BE2 : OUT STD_LOGIC;
132 -- nSRAM_BE2 : OUT STD_LOGIC;
131 -- nSRAM_BE3 : OUT STD_LOGIC;
133 -- nSRAM_BE3 : OUT STD_LOGIC;
132 -- nSRAM_WE : OUT STD_LOGIC;
134 -- nSRAM_WE : OUT STD_LOGIC;
133 -- nSRAM_CE : OUT STD_LOGIC;
135 -- nSRAM_CE : OUT STD_LOGIC;
134 -- nSRAM_OE : OUT STD_LOGIC;
136 -- nSRAM_OE : OUT STD_LOGIC;
135 -- apbi_ext : OUT apb_slv_in_type;
137 -- apbi_ext : OUT apb_slv_in_type;
136 -- apbo_ext : IN soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5);
138 -- apbo_ext : IN soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5);
137 -- ahbi_s_ext : OUT ahb_slv_in_type;
139 -- ahbi_s_ext : OUT ahb_slv_in_type;
138 -- ahbo_s_ext : IN soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3);
140 -- ahbo_s_ext : IN soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3);
139 -- ahbi_m_ext : OUT AHB_Mst_In_Type;
141 -- ahbi_m_ext : OUT AHB_Mst_In_Type;
140 -- ahbo_m_ext : IN soc_ahb_mst_out_vector(NB_AHB_MASTER-1+NB_CPU DOWNTO NB_CPU));
142 -- ahbo_m_ext : IN soc_ahb_mst_out_vector(NB_AHB_MASTER-1+NB_CPU DOWNTO NB_CPU));
141 --END COMPONENT;
143 --END COMPONENT;
142
144
143 END;
145 END;
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