# HG changeset patch # User pellion # Date 2015-04-01 08:53:52 # Node ID 0b1aedcd41967280fbab5b0361dbe57b18a779be # Parent 64f72d322da8b58469d2b83147540afb187395c3 debug EQM => memory controller and DMA lock W.I.P. diff --git a/.hgignore b/.hgignore --- a/.hgignore +++ b/.hgignore @@ -35,4 +35,7 @@ fftDp.vhd fft_components.vhd CoreFFT.vhd actram.vhd -actar.vhd \ No newline at end of file +actar.vhd +*.bak +*.pdc.ce +*.zip diff --git a/boards/LFR-EQM/LFR_EQM_A3PE3000_debug.pdc b/boards/LFR-EQM/LFR_EQM_A3PE3000_debug.pdc --- a/boards/LFR-EQM/LFR_EQM_A3PE3000_debug.pdc +++ b/boards/LFR-EQM/LFR_EQM_A3PE3000_debug.pdc @@ -80,8 +80,8 @@ set_io TAG2 -pinname K12 -fixed yes -D set_io TAG3 -pinname K13 -fixed yes -DIRECTION Inout set_io TAG4 -pinname L16 -fixed yes -DIRECTION Inout #set_io TAG5 -pinname L15 -fixed yes -DIRECTION Inout -#set_io TAG6 -pinname M16 -fixed yes -DIRECTION Inout -#set_io TAG7 -pinname J14 -fixed yes -DIRECTION Inout +set_io TAG6 -pinname M16 -fixed yes -DIRECTION Inout +set_io TAG7 -pinname J14 -fixed yes -DIRECTION Inout set_io TAG8 -pinname K15 -fixed yes -DIRECTION Inout #set_io TAG9 -pinname J17 -fixed yes -DIRECTION Inout diff --git a/boards/LFR-EQM/LFR_EQM_place_and_route-debug.sdc b/boards/LFR-EQM/LFR_EQM_place_and_route-debug.sdc --- a/boards/LFR-EQM/LFR_EQM_place_and_route-debug.sdc +++ b/boards/LFR-EQM/LFR_EQM_place_and_route-debug.sdc @@ -3,11 +3,12 @@ # Clocks create_clock -period 20.000000 -waveform {0.000000 10.000000} clk50MHz -create_clock -period 40.000000 -waveform {0.000000 20.000000} clk_25 +create_clock -period 20.344999 -waveform {0.000000 10.172500} clk49_152MHz + + +#create_clock -period 40.000000 -waveform {0.000000 20.000000} clk_25 #create_generated_clock -name{clk_domain_25} -divide_by 2 -source{clk_25_int:CLK}{clk_25_int:Q} - -#create_clock -period 20.344999 -waveform {0.000000 10.172500} clk49_152MHz #create_clock -period 40.690000 -waveform {0.000000 20.345100} clk_24:Q #create_clock -name SPW_CLOCK -period 100.000000 -waveform {0.000000 50.000000} {spw1_din spw1_sin spw2_din spw2_sin} diff --git a/designs/LFR-EQM-WFP_MS/LFR-EQM.vhd b/designs/LFR-EQM-WFP_MS/LFR-EQM.vhd --- a/designs/LFR-EQM-WFP_MS/LFR-EQM.vhd +++ b/designs/LFR-EQM-WFP_MS/LFR-EQM.vhd @@ -49,6 +49,8 @@ library proasic3l; use proasic3l.all; ENTITY LFR_EQM IS + GENERIC ( + Mem_use : INTEGER := use_RAM); PORT ( clk50MHz : IN STD_ULOGIC; @@ -216,7 +218,8 @@ BEGIN -- beh NB_AHB_SLAVE => NB_AHB_SLAVE, NB_APB_SLAVE => NB_APB_SLAVE, ADDRESS_SIZE => 19, - USES_IAP_MEMCTRLR => 1) + USES_IAP_MEMCTRLR => 1, + BYPASS_EDAC_MEMCTRLR => '1') PORT MAP ( clk => clk_25, reset => rstn_25, @@ -259,13 +262,13 @@ BEGIN -- beh pindex => 6, paddr => 6, pmask => 16#fff#, - FIRST_DIVISION => 374, -- ((49.152/2) /2^16) - 1 = 375 - 1 = 374 + --FIRST_DIVISION => 374, -- ((49.152/2) /2^16) - 1 = 375 - 1 = 374 NB_SECOND_DESYNC => 60) -- 60 secondes of desynchronization before CoarseTime's MSB is Set PORT MAP ( clk25MHz => clk_25, resetn_25MHz => rstn_25, -- TODO - clk24_576MHz => clk_24, -- 49.152MHz/2 - resetn_24_576MHz => rstn_24, -- TODO + --clk24_576MHz => clk_24, -- 49.152MHz/2 + --resetn_24_576MHz => rstn_24, -- TODO grspw_tick => swno.tickout, apbi => apbi_ext, @@ -388,7 +391,7 @@ BEGIN -- beh lpp_lfr_1 : lpp_lfr GENERIC MAP ( - Mem_use => use_RAM, + Mem_use => Mem_use, nb_data_by_buffer_size => 32, --nb_word_by_buffer_size => 30, nb_snapshot_param_size => 32, diff --git a/designs/LFR-EQM-WFP_MS/Makefile b/designs/LFR-EQM-WFP_MS/Makefile --- a/designs/LFR-EQM-WFP_MS/Makefile +++ b/designs/LFR-EQM-WFP_MS/Makefile @@ -23,7 +23,7 @@ SDC=$(VHDLIB)/boards/$(BOARD)/LFR_EQM_pl BITGEN=$(VHDLIB)/boards/$(BOARD)/default.ut CLEAN=soft-clean -TECHLIBS = proasic3e +TECHLIBS = proasic3l LIBSKIP = core1553bbc core1553brm core1553brt gr1553 corePCIF \ tmtc openchip hynix ihp gleichmann micron usbhc diff --git a/designs/MINI-LFR_WFP_MS/MINI_LFR_top.vhd b/designs/MINI-LFR_WFP_MS/MINI_LFR_top.vhd --- a/designs/MINI-LFR_WFP_MS/MINI_LFR_top.vhd +++ b/designs/MINI-LFR_WFP_MS/MINI_LFR_top.vhd @@ -113,6 +113,16 @@ END MINI_LFR_top; ARCHITECTURE beh OF MINI_LFR_top IS + +--========================================================================== +-- USE_IAP_MEMCTRL allow to use the srctrle-0ws on MINILFR board +-- when enabled, chip enable polarity should be reversed and bank size also +-- MINILFR -> 1 bank of 4MBytes -> SRBANKSZ=9 +-- LFR EQM & FM -> 2 banks of 2MBytes -> SRBANKSZ=8 +--========================================================================== + CONSTANT USE_IAP_MEMCTRL : integer := 1; +--========================================================================== + SIGNAL clk_50_s : STD_LOGIC := '0'; SIGNAL clk_25 : STD_LOGIC := '0'; SIGNAL clk_24 : STD_LOGIC := '0'; @@ -357,7 +367,8 @@ BEGIN -- beh NB_AHB_SLAVE => NB_AHB_SLAVE, NB_APB_SLAVE => NB_APB_SLAVE, ADDRESS_SIZE => 20, - USES_IAP_MEMCTRLR => 0) + USES_IAP_MEMCTRLR => USE_IAP_MEMCTRL, + SRBANKSZ => 9) PORT MAP ( clk => clk_25, reset => rstn_25, @@ -375,7 +386,7 @@ BEGIN -- beh nSRAM_WE => SRAM_nWE, nSRAM_CE => SRAM_CE_s, nSRAM_OE => SRAM_nOE, - nSRAM_READY => '0', + nSRAM_READY => '1', SRAM_MBE => OPEN, apbi_ext => apbi_ext, apbo_ext => apbo_ext, @@ -384,7 +395,13 @@ BEGIN -- beh ahbi_m_ext => ahbi_m_ext, ahbo_m_ext => ahbo_m_ext); - SRAM_CE <= SRAM_CE_s(0); +IAP:if USE_IAP_MEMCTRL = 1 GENERATE + SRAM_CE <= not SRAM_CE_s(0); +END GENERATE; + +NOIAP:if USE_IAP_MEMCTRL = 0 GENERATE + SRAM_CE <= SRAM_CE_s(0); +END GENERATE; ------------------------------------------------------------------------------- -- APB_LFR_MANAGEMENT --------------------------------------------------------- ------------------------------------------------------------------------------- diff --git a/lib/lpp/lfr_management/apb_lfr_management.vhd b/lib/lpp/lfr_management/apb_lfr_management.vhd --- a/lib/lpp/lfr_management/apb_lfr_management.vhd +++ b/lib/lpp/lfr_management/apb_lfr_management.vhd @@ -41,15 +41,15 @@ ENTITY apb_lfr_management IS pindex : INTEGER := 0; --! APB slave index paddr : INTEGER := 0; --! ADDR field of the APB BAR pmask : INTEGER := 16#fff#; --! MASK field of the APB BAR - FIRST_DIVISION : INTEGER := 374; +-- FIRST_DIVISION : INTEGER := 374; NB_SECOND_DESYNC : INTEGER := 60 ); PORT ( clk25MHz : IN STD_LOGIC; --! Clock resetn_25MHz : IN STD_LOGIC; --! Reset - clk24_576MHz : IN STD_LOGIC; --! secondary clock - resetn_24_576MHz : IN STD_LOGIC; --! Reset +-- clk24_576MHz : IN STD_LOGIC; --! secondary clock +-- resetn_24_576MHz : IN STD_LOGIC; --! Reset grspw_tick : IN STD_LOGIC; --! grspw signal asserted when a valid time-code is received @@ -304,6 +304,19 @@ BEGIN apbo.pconfig <= pconfig; apbo.pindex <= pindex; + + + + + + + + + + + + + ----------------------------------------------------------------------------- -- IN coarse_time <= r.coarse_time; @@ -320,109 +333,87 @@ BEGIN ----------------------------------------------------------------------------- tick <= grspw_tick OR soft_tick; - SYNC_VALID_BIT_1 : SYNC_VALID_BIT - GENERIC MAP ( - NB_FF_OF_SYNC => 2) - PORT MAP ( - clk_in => clk25MHz, - rstn_in => resetn_25MHz, - clk_out => clk24_576MHz, - rstn_out => resetn_24_576MHz, - sin => tick, - sout => new_timecode); + --SYNC_VALID_BIT_1 : SYNC_VALID_BIT + -- GENERIC MAP ( + -- NB_FF_OF_SYNC => 2) + -- PORT MAP ( + -- clk_in => clk25MHz, + -- rstn_in => resetn_25MHz, + -- clk_out => clk24_576MHz, + -- rstn_out => resetn_24_576MHz, + -- sin => tick, + -- sout => new_timecode); + new_timecode <= tick; - SYNC_VALID_BIT_2 : SYNC_VALID_BIT - GENERIC MAP ( - NB_FF_OF_SYNC => 2) - PORT MAP ( - clk_in => clk25MHz, - rstn_in => resetn_25MHz, - clk_out => clk24_576MHz, - rstn_out => resetn_24_576MHz, - sin => coarsetime_reg_updated, - sout => new_coarsetime); - - SYNC_VALID_BIT_3 : SYNC_VALID_BIT - GENERIC MAP ( - NB_FF_OF_SYNC => 2) - PORT MAP ( - clk_in => clk25MHz, - rstn_in => resetn_25MHz, - clk_out => clk24_576MHz, - rstn_out => resetn_24_576MHz, - sin => soft_reset, - sout => soft_reset_sync); - - ----------------------------------------------------------------------------- - --SYNC_FF_1 : SYNC_FF + --SYNC_VALID_BIT_2 : SYNC_VALID_BIT -- GENERIC MAP ( -- NB_FF_OF_SYNC => 2) -- PORT MAP ( - -- clk => clk25MHz, - -- rstn => resetn, - -- A => fine_time_new_49, - -- A_sync => fine_time_new_temp); + -- clk_in => clk25MHz, + -- rstn_in => resetn_25MHz, + -- clk_out => clk24_576MHz, + -- rstn_out => resetn_24_576MHz, + -- sin => coarsetime_reg_updated, + -- sout => new_coarsetime); + + new_coarsetime <= coarsetime_reg_updated; + + --SYNC_VALID_BIT_3 : SYNC_VALID_BIT + -- GENERIC MAP ( + -- NB_FF_OF_SYNC => 2) + -- PORT MAP ( + -- clk_in => clk25MHz, + -- rstn_in => resetn_25MHz, + -- clk_out => clk24_576MHz, + -- rstn_out => resetn_24_576MHz, + -- sin => soft_reset, + -- sout => soft_reset_sync); + - --lpp_front_detection_1 : lpp_front_detection - -- PORT MAP ( - -- clk => clk25MHz, - -- rstn => resetn, - -- sin => fine_time_new_temp, - -- sout => fine_time_new); + ----------------------------------------------------------------------------- + time_new_49 <= coarse_time_new_49 OR fine_time_new_49; --SYNC_VALID_BIT_4 : SYNC_VALID_BIT -- GENERIC MAP ( -- NB_FF_OF_SYNC => 2) -- PORT MAP ( -- clk_in => clk24_576MHz, + -- rstn_in => resetn_24_576MHz, -- clk_out => clk25MHz, - -- rstn => resetn, - -- sin => coarse_time_new_49, - -- sout => coarse_time_new); - - time_new_49 <= coarse_time_new_49 OR fine_time_new_49; + -- rstn_out => resetn_25MHz, + -- sin => time_new_49, + -- sout => time_new); - SYNC_VALID_BIT_4 : SYNC_VALID_BIT - GENERIC MAP ( - NB_FF_OF_SYNC => 2) - PORT MAP ( - clk_in => clk24_576MHz, - rstn_in => resetn_24_576MHz, - clk_out => clk25MHz, - rstn_out => resetn_25MHz, - sin => time_new_49, - sout => time_new); - - + time_new <= time_new_49; - PROCESS (clk25MHz, resetn_25MHz) - BEGIN -- PROCESS - IF resetn_25MHz = '0' THEN -- asynchronous reset (active low) - fine_time_s <= (OTHERS => '0'); - coarse_time_s <= (OTHERS => '0'); - ELSIF clk25MHz'EVENT AND clk25MHz = '1' THEN -- rising clock edge - IF time_new = '1' THEN - fine_time_s <= fine_time_49; - coarse_time_s <= coarse_time_49; - END IF; - END IF; - END PROCESS; + --PROCESS (clk25MHz, resetn_25MHz) + --BEGIN -- PROCESS + -- IF resetn_25MHz = '0' THEN -- asynchronous reset (active low) + -- fine_time_s <= (OTHERS => '0'); + -- coarse_time_s <= (OTHERS => '0'); + -- ELSIF clk25MHz'EVENT AND clk25MHz = '1' THEN -- rising clock edge + -- IF time_new = '1' THEN + -- END IF; + -- END IF; + --END PROCESS; + + fine_time_s <= fine_time_49; + coarse_time_s <= coarse_time_49; + - - rstn_LFR_TM <= '0' WHEN resetn_24_576MHz = '0' ELSE - '0' WHEN soft_reset_sync = '1' ELSE + rstn_LFR_TM <= '0' WHEN resetn_25MHz = '0' ELSE + '0' WHEN soft_reset = '1' ELSE '1'; - - + ----------------------------------------------------------------------------- -- LFR_TIME_MANAGMENT ----------------------------------------------------------------------------- lfr_time_management_1 : lfr_time_management GENERIC MAP ( - FIRST_DIVISION => FIRST_DIVISION, + --FIRST_DIVISION => FIRST_DIVISION, NB_SECOND_DESYNC => NB_SECOND_DESYNC) PORT MAP ( - clk => clk24_576MHz, + clk => clk25MHz, rstn => rstn_LFR_TM, tick => new_timecode, @@ -434,6 +425,8 @@ BEGIN coarse_time => coarse_time_49, coarse_time_new => coarse_time_new_49); + + ----------------------------------------------------------------------------- -- HK ----------------------------------------------------------------------------- @@ -481,6 +474,19 @@ BEGIN HK_sel <= HK_sel_s; + + + + + + + + + + + + + ----------------------------------------------------------------------------- -- DAC ----------------------------------------------------------------------------- @@ -514,4 +520,4 @@ BEGIN ); DAC_CAL_EN <= DAC_CAL_EN_s; -END Behavioral; \ No newline at end of file +END Behavioral; diff --git a/lib/lpp/lfr_management/coarse_time_counter.vhd b/lib/lpp/lfr_management/coarse_time_counter.vhd --- a/lib/lpp/lfr_management/coarse_time_counter.vhd +++ b/lib/lpp/lfr_management/coarse_time_counter.vhd @@ -110,14 +110,15 @@ BEGIN -- beh ----------------------------------------------------------------------------- -- Just to try to limit the constraint - PROCESS (clk, rstn) - BEGIN -- PROCESS - IF rstn = '0' THEN -- asynchronous reset (active low) - set_TCU_reg <= '0'; - ELSIF clk'event AND clk = '1' THEN -- rising clock edge - set_TCU_reg <= set_TCU; - END IF; - END PROCESS; + --PROCESS (clk, rstn) + --BEGIN -- PROCESS + -- IF rstn = '0' THEN -- asynchronous reset (active low) + -- set_TCU_reg <= '0'; + -- ELSIF clk'event AND clk = '1' THEN -- rising clock edge + -- set_TCU_reg <= set_TCU; + -- END IF; + --END PROCESS; ----------------------------------------------------------------------------- - -END beh; \ No newline at end of file + set_TCU_reg <= set_TCU; + +END beh; diff --git a/lib/lpp/lfr_management/fine_time_counter.vhd b/lib/lpp/lfr_management/fine_time_counter.vhd --- a/lib/lpp/lfr_management/fine_time_counter.vhd +++ b/lib/lpp/lfr_management/fine_time_counter.vhd @@ -4,12 +4,12 @@ USE IEEE.NUMERIC_STD.ALL; LIBRARY lpp; USE lpp.general_purpose.ALL; +USE lpp.lpp_lfr_management.ALL; ENTITY fine_time_counter IS GENERIC ( - WAITING_TIME : STD_LOGIC_VECTOR(15 DOWNTO 0) := X"0040"; - FIRST_DIVISION : INTEGER := 374 + WAITING_TIME : STD_LOGIC_VECTOR(15 DOWNTO 0) := X"0040" ); PORT ( @@ -33,12 +33,22 @@ ARCHITECTURE beh OF fine_time_counter IS SIGNAL new_ft_counter : STD_LOGIC_VECTOR(8 DOWNTO 0); SIGNAL new_ft : STD_LOGIC; SIGNAL fine_time_counter : STD_LOGIC_VECTOR(15 DOWNTO 0); + + SIGNAL fine_time_max_value : STD_LOGIC_VECTOR(8 DOWNTO 0); + SIGNAL tick_value_gen : STD_LOGIC; + SIGNAL FT_max_s : STD_LOGIC; --- CONSTANT FIRST_DIVISION : INTEGER := 20; -- TODO : 374 - BEGIN -- beh + tick_value_gen <= tick OR FT_max_s; + fine_time_max_value_gen_1: fine_time_max_value_gen + PORT MAP ( + clk => clk, + rstn => rstn, + tick => tick_value_gen, + fine_time_add => new_ft, + fine_time_max_value => fine_time_max_value); counter_1 : general_counter GENERIC MAP ( @@ -49,13 +59,13 @@ BEGIN -- beh PORT MAP ( clk => clk, rstn => rstn, - MAX_VALUE => STD_LOGIC_VECTOR(to_unsigned(FIRST_DIVISION, 9)), + MAX_VALUE => fine_time_max_value, set => tick, set_value => (OTHERS => '0'), add1 => '1', counter => new_ft_counter); - new_ft <= '1' WHEN new_ft_counter = STD_LOGIC_VECTOR(to_unsigned(FIRST_DIVISION, 9)) ELSE '0'; + new_ft <= '1' WHEN new_ft_counter = fine_time_max_value ELSE '0'; counter_2 : general_counter GENERIC MAP ( @@ -72,7 +82,9 @@ BEGIN -- beh add1 => new_ft, counter => fine_time_counter); - FT_max <= '1' WHEN new_ft = '1' AND fine_time_counter = X"FFFF" ELSE '0'; + FT_max_s <= '1' WHEN new_ft = '1' AND fine_time_counter = X"FFFF" ELSE '0'; + + FT_max <= FT_max_s; FT_half <= '1' WHEN fine_time_counter > X"7FFF" ELSE '0'; FT_wait <= '1' WHEN fine_time_counter > WAITING_TIME ELSE '0'; diff --git a/lib/lpp/lfr_management/fine_time_max_value_gen.vhd b/lib/lpp/lfr_management/fine_time_max_value_gen.vhd new file mode 100644 --- /dev/null +++ b/lib/lpp/lfr_management/fine_time_max_value_gen.vhd @@ -0,0 +1,73 @@ +LIBRARY IEEE; +USE IEEE.STD_LOGIC_1164.ALL; +USE IEEE.NUMERIC_STD.ALL; + +ENTITY fine_time_max_value_gen IS + + PORT ( + clk : IN STD_LOGIC; + rstn : IN STD_LOGIC; + tick : IN STD_LOGIC; + fine_time_add : IN STD_LOGIC; + fine_time_max_value : OUT STD_LOGIC_VECTOR(8 DOWNTO 0) + ); + +END fine_time_max_value_gen; + +ARCHITECTURE beh OF fine_time_max_value_gen IS + + SIGNAL count_even : STD_LOGIC; + SIGNAL count_first : STD_LOGIC; + SIGNAL count_modulo_33 : STD_LOGIC; + + + SIGNAL count_33 : INTEGER range 0 TO 32; + +BEGIN -- beh + + fine_time_max_value <= STD_LOGIC_VECTOR(to_unsigned(381,9)) WHEN count_first = '1' ELSE + STD_LOGIC_VECTOR(to_unsigned(380,9)) WHEN count_even = count_modulo_33 ELSE + STD_LOGIC_VECTOR(to_unsigned(381,9)) WHEN count_even = '1' ELSE + STD_LOGIC_VECTOR(to_unsigned(379,9)) WHEN count_modulo_33 = '1' ELSE + STD_LOGIC_VECTOR(to_unsigned(380,9)); + + + + PROCESS (clk, rstn) + BEGIN -- PROCESS + IF rstn = '0' THEN -- asynchronous reset (active low) + count_first <= '1'; + count_even <= '0'; + count_modulo_33 <= '0'; + count_33 <= 0; + ELSIF clk'event AND clk = '1' THEN -- rising clock edge + IF tick = '1' THEN + count_even <= '0'; + count_first <= '1'; + count_modulo_33 <= '0'; + count_33 <= 0; + ELSE + IF fine_time_add = '1' THEN + count_first <= '0'; + IF count_even = '1' THEN + count_even <= '0'; + ELSE + count_even <= '1'; + END IF; + IF count_33 = 31 THEN + count_modulo_33 <= '1'; + ELSE + count_modulo_33 <= '0'; + END IF; + + IF count_33 = 32 THEN + count_33 <= 0; + ELSE + count_33 <= count_33 + 1; + END IF; + END IF; + END IF; + END IF; + END PROCESS; + +END beh; diff --git a/lib/lpp/lfr_management/lfr_time_management.vhd b/lib/lpp/lfr_management/lfr_time_management.vhd --- a/lib/lpp/lfr_management/lfr_time_management.vhd +++ b/lib/lpp/lfr_management/lfr_time_management.vhd @@ -25,7 +25,6 @@ USE lpp.lpp_lfr_management.ALL; ENTITY lfr_time_management IS GENERIC ( - FIRST_DIVISION : INTEGER := 374; NB_SECOND_DESYNC : INTEGER := 60); PORT ( clk : IN STD_LOGIC; @@ -83,8 +82,7 @@ BEGIN ----------------------------------------------------------------------------- fine_time_counter_1: fine_time_counter GENERIC MAP ( - WAITING_TIME => X"0040", - FIRST_DIVISION => FIRST_DIVISION) + WAITING_TIME => X"0040") PORT MAP ( clk => clk, rstn => rstn, diff --git a/lib/lpp/lfr_management/lpp_lfr_management.vhd b/lib/lpp/lfr_management/lpp_lfr_management.vhd --- a/lib/lpp/lfr_management/lpp_lfr_management.vhd +++ b/lib/lpp/lfr_management/lpp_lfr_management.vhd @@ -1,111 +1,119 @@ ----------------------------------------------------------------------------------- --- Company: --- Engineer: --- --- Create Date: 13:04:01 07/02/2012 --- Design Name: --- Module Name: lpp_lfr_time_management - Behavioral --- Project Name: --- Target Devices: --- Tool versions: --- Description: --- --- Dependencies: --- --- Revision: --- Revision 0.01 - File Created --- Additional Comments: --- ----------------------------------------------------------------------------------- -LIBRARY IEEE; -USE IEEE.STD_LOGIC_1164.ALL; -LIBRARY grlib; -USE grlib.amba.ALL; -USE grlib.stdlib.ALL; -USE grlib.devices.ALL; - -PACKAGE lpp_lfr_management IS - ---*************************** --- APB_LFR_MANAGEMENT - - COMPONENT apb_lfr_management - GENERIC ( - tech : INTEGER; - pindex : INTEGER; - paddr : INTEGER; - pmask : INTEGER; - FIRST_DIVISION : INTEGER; - NB_SECOND_DESYNC : INTEGER); - PORT ( - clk25MHz : IN STD_LOGIC; - resetn_25MHz : IN STD_LOGIC; - clk24_576MHz : IN STD_LOGIC; - resetn_24_576MHz : IN STD_LOGIC; - grspw_tick : IN STD_LOGIC; - apbi : IN apb_slv_in_type; - apbo : OUT apb_slv_out_type; - HK_sample : IN STD_LOGIC_VECTOR(15 DOWNTO 0); - HK_val : IN STD_LOGIC; - HK_sel : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); - DAC_SDO : OUT STD_LOGIC; - DAC_SCK : OUT STD_LOGIC; - DAC_SYNC : OUT STD_LOGIC; - DAC_CAL_EN : OUT STD_LOGIC; - coarse_time : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); - fine_time : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); - LFR_soft_rstn : OUT STD_LOGIC); - END COMPONENT; - - COMPONENT lfr_time_management - GENERIC ( - FIRST_DIVISION : INTEGER; - NB_SECOND_DESYNC : INTEGER); - PORT ( - clk : IN STD_LOGIC; - rstn : IN STD_LOGIC; - tick : IN STD_LOGIC; - new_coarsetime : IN STD_LOGIC; - coarsetime_reg : IN STD_LOGIC_VECTOR(30 DOWNTO 0); - fine_time : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); - fine_time_new : OUT STD_LOGIC; - coarse_time : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); - coarse_time_new : OUT STD_LOGIC); - END COMPONENT; - - COMPONENT coarse_time_counter - GENERIC ( - NB_SECOND_DESYNC : INTEGER); - PORT ( - clk : IN STD_LOGIC; - rstn : IN STD_LOGIC; - tick : IN STD_LOGIC; - set_TCU : IN STD_LOGIC; - new_TCU : IN STD_LOGIC; - set_TCU_value : IN STD_LOGIC_VECTOR(30 DOWNTO 0); - CT_add1 : IN STD_LOGIC; - fsm_desync : IN STD_LOGIC; - FT_max : IN STD_LOGIC; - coarse_time : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); - coarse_time_new : OUT STD_LOGIC); - END COMPONENT; - - COMPONENT fine_time_counter - GENERIC ( - WAITING_TIME : STD_LOGIC_VECTOR(15 DOWNTO 0); - FIRST_DIVISION : INTEGER); - PORT ( - clk : IN STD_LOGIC; - rstn : IN STD_LOGIC; - tick : IN STD_LOGIC; - fsm_transition : IN STD_LOGIC; - FT_max : OUT STD_LOGIC; - FT_half : OUT STD_LOGIC; - FT_wait : OUT STD_LOGIC; - fine_time : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); - fine_time_new : OUT STD_LOGIC); - END COMPONENT; - - -END lpp_lfr_management; - +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 13:04:01 07/02/2012 +-- Design Name: +-- Module Name: lpp_lfr_time_management - Behavioral +-- Project Name: +-- Target Devices: +-- Tool versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- +LIBRARY IEEE; +USE IEEE.STD_LOGIC_1164.ALL; +LIBRARY grlib; +USE grlib.amba.ALL; +USE grlib.stdlib.ALL; +USE grlib.devices.ALL; + +PACKAGE lpp_lfr_management IS + +--*************************** +-- APB_LFR_MANAGEMENT + + COMPONENT apb_lfr_management + GENERIC ( + tech : INTEGER; + pindex : INTEGER; + paddr : INTEGER; + pmask : INTEGER; +-- FIRST_DIVISION : INTEGER; + NB_SECOND_DESYNC : INTEGER); + PORT ( + clk25MHz : IN STD_LOGIC; + resetn_25MHz : IN STD_LOGIC; +-- clk24_576MHz : IN STD_LOGIC; +-- resetn_24_576MHz : IN STD_LOGIC; + grspw_tick : IN STD_LOGIC; + apbi : IN apb_slv_in_type; + apbo : OUT apb_slv_out_type; + HK_sample : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + HK_val : IN STD_LOGIC; + HK_sel : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); + DAC_SDO : OUT STD_LOGIC; + DAC_SCK : OUT STD_LOGIC; + DAC_SYNC : OUT STD_LOGIC; + DAC_CAL_EN : OUT STD_LOGIC; + coarse_time : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + fine_time : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + LFR_soft_rstn : OUT STD_LOGIC); + END COMPONENT; + + COMPONENT lfr_time_management + GENERIC ( + --FIRST_DIVISION : INTEGER; + NB_SECOND_DESYNC : INTEGER); + PORT ( + clk : IN STD_LOGIC; + rstn : IN STD_LOGIC; + tick : IN STD_LOGIC; + new_coarsetime : IN STD_LOGIC; + coarsetime_reg : IN STD_LOGIC_VECTOR(30 DOWNTO 0); + fine_time : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + fine_time_new : OUT STD_LOGIC; + coarse_time : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + coarse_time_new : OUT STD_LOGIC); + END COMPONENT; + + COMPONENT coarse_time_counter + GENERIC ( + NB_SECOND_DESYNC : INTEGER); + PORT ( + clk : IN STD_LOGIC; + rstn : IN STD_LOGIC; + tick : IN STD_LOGIC; + set_TCU : IN STD_LOGIC; + new_TCU : IN STD_LOGIC; + set_TCU_value : IN STD_LOGIC_VECTOR(30 DOWNTO 0); + CT_add1 : IN STD_LOGIC; + fsm_desync : IN STD_LOGIC; + FT_max : IN STD_LOGIC; + coarse_time : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + coarse_time_new : OUT STD_LOGIC); + END COMPONENT; + + COMPONENT fine_time_counter + GENERIC ( + WAITING_TIME : STD_LOGIC_VECTOR(15 DOWNTO 0));--; +-- FIRST_DIVISION : INTEGER); + PORT ( + clk : IN STD_LOGIC; + rstn : IN STD_LOGIC; + tick : IN STD_LOGIC; + fsm_transition : IN STD_LOGIC; + FT_max : OUT STD_LOGIC; + FT_half : OUT STD_LOGIC; + FT_wait : OUT STD_LOGIC; + fine_time : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + fine_time_new : OUT STD_LOGIC); + END COMPONENT; + + COMPONENT fine_time_max_value_gen + PORT ( + clk : IN STD_LOGIC; + rstn : IN STD_LOGIC; + tick : IN STD_LOGIC; + fine_time_add : IN STD_LOGIC; + fine_time_max_value : OUT STD_LOGIC_VECTOR(8 DOWNTO 0)); + END COMPONENT; + +END lpp_lfr_management; + diff --git a/lib/lpp/lfr_management/vhdlsyn.txt b/lib/lpp/lfr_management/vhdlsyn.txt --- a/lib/lpp/lfr_management/vhdlsyn.txt +++ b/lib/lpp/lfr_management/vhdlsyn.txt @@ -4,3 +4,4 @@ apb_lfr_management.vhd lfr_time_management.vhd fine_time_counter.vhd coarse_time_counter.vhd +fine_time_max_value_gen.vhd diff --git a/lib/lpp/lpp_dma/lpp_dma_send_16word.vhd b/lib/lpp/lpp_dma/lpp_dma_send_16word.vhd --- a/lib/lpp/lpp_dma/lpp_dma_send_16word.vhd +++ b/lib/lpp/lpp_dma/lpp_dma_send_16word.vhd @@ -54,7 +54,7 @@ ENTITY lpp_dma_send_16word IS -- send_ok : OUT STD_LOGIC; send_ko : OUT STD_LOGIC - + ); END lpp_dma_send_16word; @@ -88,8 +88,8 @@ BEGIN -- beh grant_counter <= 0; ELSIF HCLK'EVENT AND HCLK = '1' THEN -- rising clock edge - DMAIn.Reset <= '0'; - + DMAIn.Reset <= '0'; + CASE state IS WHEN IDLE => DMAIn.Store <= '1'; @@ -98,11 +98,11 @@ BEGIN -- beh send_ko <= '0'; DMAIn.Address <= address; data_counter <= 0; - DMAIn.Lock <= '0'; -- FIX test + DMAIn.Lock <= '0'; IF send = '1' THEN state <= REQUEST_BUS; DMAIn.Request <= '1'; - DMAIn.Lock <= '1'; -- FIX test + DMAIn.Lock <= '1'; DMAIn.Store <= '1'; END IF; WHEN REQUEST_BUS => @@ -124,10 +124,10 @@ BEGIN -- beh IF DMAOut.Grant = '1' THEN IF grant_counter = 15 THEN - DMAIn.Reset <= '0'; + DMAIn.Reset <= '0'; DMAIn.Request <= '0'; - DMAIn.Store <= '0'; - DMAIn.Burst <= '0'; + DMAIn.Store <= '0'; + DMAIn.Burst <= '0'; ELSE grant_counter <= grant_counter+1; END IF; @@ -135,6 +135,7 @@ BEGIN -- beh IF DMAOut.OKAY = '1' THEN IF data_counter = 15 THEN + --DMAIn.Request <= '0'; -- FIX Test 31/03/2014 to handle burst interruption DMAIn.Address <= (OTHERS => '0'); state <= WAIT_LAST_READY; ELSE @@ -167,7 +168,7 @@ BEGIN -- beh END PROCESS; DMAIn.Data <= data; - + ren <= NOT (DMAOut.OKAY OR DMAOut.GRANT) WHEN state = SEND_DATA ELSE '1'; @@ -175,7 +176,7 @@ BEGIN -- beh --ren <= '0' WHEN DMAOut.OKAY = '1' ELSE --AND (state = SEND_DATA OR state = WAIT_LAST_READY) ELSE -- '1'; -- /\ JC - 20/01/2014 /\ - + -- \/ JC - 11/12/2013 \/ --ren <= '0' WHEN DMAOut.OKAY = '1' AND state = SEND_DATA ELSE -- '1'; @@ -191,5 +192,5 @@ BEGIN -- beh --ren <= '0' WHEN state = SEND_DATA ELSE -- '1'; -- /\ JC - 09/12/2013 /\ - + END beh; diff --git a/lib/lpp/lpp_leon3_soc/leon3_soc.vhd b/lib/lpp/lpp_leon3_soc/leon3_soc.vhd --- a/lib/lpp/lpp_leon3_soc/leon3_soc.vhd +++ b/lib/lpp/lpp_leon3_soc/leon3_soc.vhd @@ -72,7 +72,9 @@ ENTITY leon3_soc IS NB_APB_SLAVE : INTEGER := 1; -- ADDRESS_SIZE : INTEGER := 20; - USES_IAP_MEMCTRLR : INTEGER := 0 + USES_IAP_MEMCTRLR : INTEGER := 0; + BYPASS_EDAC_MEMCTRLR : STD_LOGIC := '0'; + SRBANKSZ : INTEGER := 8 ); PORT ( @@ -412,9 +414,10 @@ BEGIN pindex => 0, paddr => 0, srbanks => 2, - banksz => 8, --512k * 32 + banksz => SRBANKSZ, --512k * 32 rmw => 1, --Aeroflex memory generics: + mbpbusy => BYPASS_EDAC_MEMCTRLR, mprog => 1, -- program memory by default values after reset mpsrate => 15, -- default scrub rate period mpb2s => 14, -- default busy to scrub delay @@ -440,7 +443,7 @@ BEGIN memi.brdyn <= nSRAM_READY; mbe_pad : iopad - GENERIC MAP(tech => padtech) + GENERIC MAP(tech => padtech, oepol => USES_IAP_MEMCTRLR) PORT MAP(pad => SRAM_MBE, i => mbe, en => mbe_drive, diff --git a/lib/lpp/lpp_leon3_soc/lpp_leon3_soc_pkg.vhd b/lib/lpp/lpp_leon3_soc/lpp_leon3_soc_pkg.vhd --- a/lib/lpp/lpp_leon3_soc/lpp_leon3_soc_pkg.vhd +++ b/lib/lpp/lpp_leon3_soc/lpp_leon3_soc_pkg.vhd @@ -54,7 +54,9 @@ PACKAGE lpp_leon3_soc_pkg IS NB_AHB_SLAVE : INTEGER; NB_APB_SLAVE : INTEGER; ADDRESS_SIZE : INTEGER; - USES_IAP_MEMCTRLR : INTEGER + USES_IAP_MEMCTRLR : INTEGER; + BYPASS_EDAC_MEMCTRLR : STD_LOGIC; + SRBANKSZ : INTEGER := 8 ); PORT ( clk : IN STD_ULOGIC;