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LIBRARY IEEE;
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USE IEEE.STD_LOGIC_1164.ALL;
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USE IEEE.NUMERIC_STD.ALL;
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LIBRARY lpp;
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USE lpp.general_purpose.ALL;
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ENTITY fine_time_counter IS
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GENERIC (
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WAITING_TIME : STD_LOGIC_VECTOR(15 DOWNTO 0) := X"0040";
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FIRST_DIVISION : INTEGER := 374
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);
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PORT (
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clk : IN STD_LOGIC;
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rstn : IN STD_LOGIC;
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--
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tick : IN STD_LOGIC;
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fsm_transition : IN STD_LOGIC;
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FT_max : OUT STD_LOGIC;
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FT_half : OUT STD_LOGIC;
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FT_wait : OUT STD_LOGIC;
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fine_time : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
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fine_time_new : OUT STD_LOGIC
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);
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END fine_time_counter;
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ARCHITECTURE beh OF fine_time_counter IS
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SIGNAL new_ft_counter : STD_LOGIC_VECTOR(8 DOWNTO 0);
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SIGNAL new_ft : STD_LOGIC;
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SIGNAL fine_time_counter : STD_LOGIC_VECTOR(15 DOWNTO 0);
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-- CONSTANT FIRST_DIVISION : INTEGER := 20; -- TODO : 374
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BEGIN -- beh
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counter_1 : general_counter
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GENERIC MAP (
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CYCLIC => '1',
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NB_BITS_COUNTER => 9,
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RST_VALUE => 0
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)
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PORT MAP (
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clk => clk,
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rstn => rstn,
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MAX_VALUE => STD_LOGIC_VECTOR(to_unsigned(FIRST_DIVISION, 9)),
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set => tick,
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set_value => (OTHERS => '0'),
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add1 => '1',
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counter => new_ft_counter);
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new_ft <= '1' WHEN new_ft_counter = STD_LOGIC_VECTOR(to_unsigned(FIRST_DIVISION, 9)) ELSE '0';
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counter_2 : general_counter
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GENERIC MAP (
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CYCLIC => '1',
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NB_BITS_COUNTER => 16,
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RST_VALUE => 0
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)
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PORT MAP (
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clk => clk,
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rstn => rstn,
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MAX_VALUE => X"FFFF",
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set => tick,
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set_value => (OTHERS => '0'),
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add1 => new_ft,
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counter => fine_time_counter);
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FT_max <= '1' WHEN new_ft = '1' AND fine_time_counter = X"FFFF" ELSE '0';
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FT_half <= '1' WHEN fine_time_counter > X"7FFF" ELSE '0';
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FT_wait <= '1' WHEN fine_time_counter > WAITING_TIME ELSE '0';
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fine_time <= X"FFFF" WHEN fsm_transition = '1' ELSE fine_time_counter;
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PROCESS (clk, rstn)
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BEGIN -- PROCESS
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IF rstn = '0' THEN -- asynchronous reset (active low)
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fine_time_new <= '0';
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ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
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IF (new_ft = '1' AND fsm_transition = '0') OR tick = '1' THEN
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fine_time_new <= '1';
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ELSE
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fine_time_new <= '0';
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END IF;
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END IF;
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END PROCESS;
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END beh;
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