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debug EQM...
pellion -
r570:0b1aedcd4196 JC
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@@ -0,0 +1,73
1 LIBRARY IEEE;
2 USE IEEE.STD_LOGIC_1164.ALL;
3 USE IEEE.NUMERIC_STD.ALL;
4
5 ENTITY fine_time_max_value_gen IS
6
7 PORT (
8 clk : IN STD_LOGIC;
9 rstn : IN STD_LOGIC;
10 tick : IN STD_LOGIC;
11 fine_time_add : IN STD_LOGIC;
12 fine_time_max_value : OUT STD_LOGIC_VECTOR(8 DOWNTO 0)
13 );
14
15 END fine_time_max_value_gen;
16
17 ARCHITECTURE beh OF fine_time_max_value_gen IS
18
19 SIGNAL count_even : STD_LOGIC;
20 SIGNAL count_first : STD_LOGIC;
21 SIGNAL count_modulo_33 : STD_LOGIC;
22
23
24 SIGNAL count_33 : INTEGER range 0 TO 32;
25
26 BEGIN -- beh
27
28 fine_time_max_value <= STD_LOGIC_VECTOR(to_unsigned(381,9)) WHEN count_first = '1' ELSE
29 STD_LOGIC_VECTOR(to_unsigned(380,9)) WHEN count_even = count_modulo_33 ELSE
30 STD_LOGIC_VECTOR(to_unsigned(381,9)) WHEN count_even = '1' ELSE
31 STD_LOGIC_VECTOR(to_unsigned(379,9)) WHEN count_modulo_33 = '1' ELSE
32 STD_LOGIC_VECTOR(to_unsigned(380,9));
33
34
35
36 PROCESS (clk, rstn)
37 BEGIN -- PROCESS
38 IF rstn = '0' THEN -- asynchronous reset (active low)
39 count_first <= '1';
40 count_even <= '0';
41 count_modulo_33 <= '0';
42 count_33 <= 0;
43 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
44 IF tick = '1' THEN
45 count_even <= '0';
46 count_first <= '1';
47 count_modulo_33 <= '0';
48 count_33 <= 0;
49 ELSE
50 IF fine_time_add = '1' THEN
51 count_first <= '0';
52 IF count_even = '1' THEN
53 count_even <= '0';
54 ELSE
55 count_even <= '1';
56 END IF;
57 IF count_33 = 31 THEN
58 count_modulo_33 <= '1';
59 ELSE
60 count_modulo_33 <= '0';
61 END IF;
62
63 IF count_33 = 32 THEN
64 count_33 <= 0;
65 ELSE
66 count_33 <= count_33 + 1;
67 END IF;
68 END IF;
69 END IF;
70 END IF;
71 END PROCESS;
72
73 END beh;
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@@ -35,4 +35,7 fftDp.vhd
35 35 fft_components.vhd
36 36 CoreFFT.vhd
37 37 actram.vhd
38 actar.vhd No newline at end of file
38 actar.vhd
39 *.bak
40 *.pdc.ce
41 *.zip
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@@ -80,8 +80,8 set_io TAG2 -pinname K12 -fixed yes -D
80 80 set_io TAG3 -pinname K13 -fixed yes -DIRECTION Inout
81 81 set_io TAG4 -pinname L16 -fixed yes -DIRECTION Inout
82 82 #set_io TAG5 -pinname L15 -fixed yes -DIRECTION Inout
83 #set_io TAG6 -pinname M16 -fixed yes -DIRECTION Inout
84 #set_io TAG7 -pinname J14 -fixed yes -DIRECTION Inout
83 set_io TAG6 -pinname M16 -fixed yes -DIRECTION Inout
84 set_io TAG7 -pinname J14 -fixed yes -DIRECTION Inout
85 85 set_io TAG8 -pinname K15 -fixed yes -DIRECTION Inout
86 86 #set_io TAG9 -pinname J17 -fixed yes -DIRECTION Inout
87 87
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@@ -3,11 +3,12
3 3 # Clocks
4 4
5 5 create_clock -period 20.000000 -waveform {0.000000 10.000000} clk50MHz
6 create_clock -period 40.000000 -waveform {0.000000 20.000000} clk_25
6 create_clock -period 20.344999 -waveform {0.000000 10.172500} clk49_152MHz
7
7 8
9
10 #create_clock -period 40.000000 -waveform {0.000000 20.000000} clk_25
8 11 #create_generated_clock -name{clk_domain_25} -divide_by 2 -source{clk_25_int:CLK}{clk_25_int:Q}
9
10 #create_clock -period 20.344999 -waveform {0.000000 10.172500} clk49_152MHz
11 12 #create_clock -period 40.690000 -waveform {0.000000 20.345100} clk_24:Q
12 13 #create_clock -name SPW_CLOCK -period 100.000000 -waveform {0.000000 50.000000} {spw1_din spw1_sin spw2_din spw2_sin}
13 14
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@@ -49,6 +49,8 library proasic3l;
49 49 use proasic3l.all;
50 50
51 51 ENTITY LFR_EQM IS
52 GENERIC (
53 Mem_use : INTEGER := use_RAM);
52 54
53 55 PORT (
54 56 clk50MHz : IN STD_ULOGIC;
@@ -216,7 +218,8 BEGIN -- beh
216 218 NB_AHB_SLAVE => NB_AHB_SLAVE,
217 219 NB_APB_SLAVE => NB_APB_SLAVE,
218 220 ADDRESS_SIZE => 19,
219 USES_IAP_MEMCTRLR => 1)
221 USES_IAP_MEMCTRLR => 1,
222 BYPASS_EDAC_MEMCTRLR => '1')
220 223 PORT MAP (
221 224 clk => clk_25,
222 225 reset => rstn_25,
@@ -259,13 +262,13 BEGIN -- beh
259 262 pindex => 6,
260 263 paddr => 6,
261 264 pmask => 16#fff#,
262 FIRST_DIVISION => 374, -- ((49.152/2) /2^16) - 1 = 375 - 1 = 374
265 --FIRST_DIVISION => 374, -- ((49.152/2) /2^16) - 1 = 375 - 1 = 374
263 266 NB_SECOND_DESYNC => 60) -- 60 secondes of desynchronization before CoarseTime's MSB is Set
264 267 PORT MAP (
265 268 clk25MHz => clk_25,
266 269 resetn_25MHz => rstn_25, -- TODO
267 clk24_576MHz => clk_24, -- 49.152MHz/2
268 resetn_24_576MHz => rstn_24, -- TODO
270 --clk24_576MHz => clk_24, -- 49.152MHz/2
271 --resetn_24_576MHz => rstn_24, -- TODO
269 272
270 273 grspw_tick => swno.tickout,
271 274 apbi => apbi_ext,
@@ -388,7 +391,7 BEGIN -- beh
388 391
389 392 lpp_lfr_1 : lpp_lfr
390 393 GENERIC MAP (
391 Mem_use => use_RAM,
394 Mem_use => Mem_use,
392 395 nb_data_by_buffer_size => 32,
393 396 --nb_word_by_buffer_size => 30,
394 397 nb_snapshot_param_size => 32,
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@@ -23,7 +23,7 SDC=$(VHDLIB)/boards/$(BOARD)/LFR_EQM_pl
23 23 BITGEN=$(VHDLIB)/boards/$(BOARD)/default.ut
24 24 CLEAN=soft-clean
25 25
26 TECHLIBS = proasic3e
26 TECHLIBS = proasic3l
27 27
28 28 LIBSKIP = core1553bbc core1553brm core1553brt gr1553 corePCIF \
29 29 tmtc openchip hynix ihp gleichmann micron usbhc
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@@ -113,6 +113,16 END MINI_LFR_top;
113 113
114 114
115 115 ARCHITECTURE beh OF MINI_LFR_top IS
116
117 --==========================================================================
118 -- USE_IAP_MEMCTRL allow to use the srctrle-0ws on MINILFR board
119 -- when enabled, chip enable polarity should be reversed and bank size also
120 -- MINILFR -> 1 bank of 4MBytes -> SRBANKSZ=9
121 -- LFR EQM & FM -> 2 banks of 2MBytes -> SRBANKSZ=8
122 --==========================================================================
123 CONSTANT USE_IAP_MEMCTRL : integer := 1;
124 --==========================================================================
125
116 126 SIGNAL clk_50_s : STD_LOGIC := '0';
117 127 SIGNAL clk_25 : STD_LOGIC := '0';
118 128 SIGNAL clk_24 : STD_LOGIC := '0';
@@ -357,7 +367,8 BEGIN -- beh
357 367 NB_AHB_SLAVE => NB_AHB_SLAVE,
358 368 NB_APB_SLAVE => NB_APB_SLAVE,
359 369 ADDRESS_SIZE => 20,
360 USES_IAP_MEMCTRLR => 0)
370 USES_IAP_MEMCTRLR => USE_IAP_MEMCTRL,
371 SRBANKSZ => 9)
361 372 PORT MAP (
362 373 clk => clk_25,
363 374 reset => rstn_25,
@@ -375,7 +386,7 BEGIN -- beh
375 386 nSRAM_WE => SRAM_nWE,
376 387 nSRAM_CE => SRAM_CE_s,
377 388 nSRAM_OE => SRAM_nOE,
378 nSRAM_READY => '0',
389 nSRAM_READY => '1',
379 390 SRAM_MBE => OPEN,
380 391 apbi_ext => apbi_ext,
381 392 apbo_ext => apbo_ext,
@@ -384,7 +395,13 BEGIN -- beh
384 395 ahbi_m_ext => ahbi_m_ext,
385 396 ahbo_m_ext => ahbo_m_ext);
386 397
387 SRAM_CE <= SRAM_CE_s(0);
398 IAP:if USE_IAP_MEMCTRL = 1 GENERATE
399 SRAM_CE <= not SRAM_CE_s(0);
400 END GENERATE;
401
402 NOIAP:if USE_IAP_MEMCTRL = 0 GENERATE
403 SRAM_CE <= SRAM_CE_s(0);
404 END GENERATE;
388 405 -------------------------------------------------------------------------------
389 406 -- APB_LFR_MANAGEMENT ---------------------------------------------------------
390 407 -------------------------------------------------------------------------------
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@@ -41,15 +41,15 ENTITY apb_lfr_management IS
41 41 pindex : INTEGER := 0; --! APB slave index
42 42 paddr : INTEGER := 0; --! ADDR field of the APB BAR
43 43 pmask : INTEGER := 16#fff#; --! MASK field of the APB BAR
44 FIRST_DIVISION : INTEGER := 374;
44 -- FIRST_DIVISION : INTEGER := 374;
45 45 NB_SECOND_DESYNC : INTEGER := 60
46 46 );
47 47
48 48 PORT (
49 49 clk25MHz : IN STD_LOGIC; --! Clock
50 50 resetn_25MHz : IN STD_LOGIC; --! Reset
51 clk24_576MHz : IN STD_LOGIC; --! secondary clock
52 resetn_24_576MHz : IN STD_LOGIC; --! Reset
51 -- clk24_576MHz : IN STD_LOGIC; --! secondary clock
52 -- resetn_24_576MHz : IN STD_LOGIC; --! Reset
53 53
54 54 grspw_tick : IN STD_LOGIC; --! grspw signal asserted when a valid time-code is received
55 55
@@ -304,6 +304,19 BEGIN
304 304 apbo.pconfig <= pconfig;
305 305 apbo.pindex <= pindex;
306 306
307
308
309
310
311
312
313
314
315
316
317
318
319
307 320 -----------------------------------------------------------------------------
308 321 -- IN
309 322 coarse_time <= r.coarse_time;
@@ -320,109 +333,87 BEGIN
320 333 -----------------------------------------------------------------------------
321 334 tick <= grspw_tick OR soft_tick;
322 335
323 SYNC_VALID_BIT_1 : SYNC_VALID_BIT
324 GENERIC MAP (
325 NB_FF_OF_SYNC => 2)
326 PORT MAP (
327 clk_in => clk25MHz,
328 rstn_in => resetn_25MHz,
329 clk_out => clk24_576MHz,
330 rstn_out => resetn_24_576MHz,
331 sin => tick,
332 sout => new_timecode);
336 --SYNC_VALID_BIT_1 : SYNC_VALID_BIT
337 -- GENERIC MAP (
338 -- NB_FF_OF_SYNC => 2)
339 -- PORT MAP (
340 -- clk_in => clk25MHz,
341 -- rstn_in => resetn_25MHz,
342 -- clk_out => clk24_576MHz,
343 -- rstn_out => resetn_24_576MHz,
344 -- sin => tick,
345 -- sout => new_timecode);
346 new_timecode <= tick;
333 347
334 SYNC_VALID_BIT_2 : SYNC_VALID_BIT
335 GENERIC MAP (
336 NB_FF_OF_SYNC => 2)
337 PORT MAP (
338 clk_in => clk25MHz,
339 rstn_in => resetn_25MHz,
340 clk_out => clk24_576MHz,
341 rstn_out => resetn_24_576MHz,
342 sin => coarsetime_reg_updated,
343 sout => new_coarsetime);
344
345 SYNC_VALID_BIT_3 : SYNC_VALID_BIT
346 GENERIC MAP (
347 NB_FF_OF_SYNC => 2)
348 PORT MAP (
349 clk_in => clk25MHz,
350 rstn_in => resetn_25MHz,
351 clk_out => clk24_576MHz,
352 rstn_out => resetn_24_576MHz,
353 sin => soft_reset,
354 sout => soft_reset_sync);
355
356 -----------------------------------------------------------------------------
357 --SYNC_FF_1 : SYNC_FF
348 --SYNC_VALID_BIT_2 : SYNC_VALID_BIT
358 349 -- GENERIC MAP (
359 350 -- NB_FF_OF_SYNC => 2)
360 351 -- PORT MAP (
361 -- clk => clk25MHz,
362 -- rstn => resetn,
363 -- A => fine_time_new_49,
364 -- A_sync => fine_time_new_temp);
352 -- clk_in => clk25MHz,
353 -- rstn_in => resetn_25MHz,
354 -- clk_out => clk24_576MHz,
355 -- rstn_out => resetn_24_576MHz,
356 -- sin => coarsetime_reg_updated,
357 -- sout => new_coarsetime);
358
359 new_coarsetime <= coarsetime_reg_updated;
360
361 --SYNC_VALID_BIT_3 : SYNC_VALID_BIT
362 -- GENERIC MAP (
363 -- NB_FF_OF_SYNC => 2)
364 -- PORT MAP (
365 -- clk_in => clk25MHz,
366 -- rstn_in => resetn_25MHz,
367 -- clk_out => clk24_576MHz,
368 -- rstn_out => resetn_24_576MHz,
369 -- sin => soft_reset,
370 -- sout => soft_reset_sync);
371
365 372
366 --lpp_front_detection_1 : lpp_front_detection
367 -- PORT MAP (
368 -- clk => clk25MHz,
369 -- rstn => resetn,
370 -- sin => fine_time_new_temp,
371 -- sout => fine_time_new);
373 -----------------------------------------------------------------------------
374 time_new_49 <= coarse_time_new_49 OR fine_time_new_49;
372 375
373 376 --SYNC_VALID_BIT_4 : SYNC_VALID_BIT
374 377 -- GENERIC MAP (
375 378 -- NB_FF_OF_SYNC => 2)
376 379 -- PORT MAP (
377 380 -- clk_in => clk24_576MHz,
381 -- rstn_in => resetn_24_576MHz,
378 382 -- clk_out => clk25MHz,
379 -- rstn => resetn,
380 -- sin => coarse_time_new_49,
381 -- sout => coarse_time_new);
382
383 time_new_49 <= coarse_time_new_49 OR fine_time_new_49;
383 -- rstn_out => resetn_25MHz,
384 -- sin => time_new_49,
385 -- sout => time_new);
384 386
385 SYNC_VALID_BIT_4 : SYNC_VALID_BIT
386 GENERIC MAP (
387 NB_FF_OF_SYNC => 2)
388 PORT MAP (
389 clk_in => clk24_576MHz,
390 rstn_in => resetn_24_576MHz,
391 clk_out => clk25MHz,
392 rstn_out => resetn_25MHz,
393 sin => time_new_49,
394 sout => time_new);
395
396
387 time_new <= time_new_49;
397 388
398 PROCESS (clk25MHz, resetn_25MHz)
399 BEGIN -- PROCESS
400 IF resetn_25MHz = '0' THEN -- asynchronous reset (active low)
401 fine_time_s <= (OTHERS => '0');
402 coarse_time_s <= (OTHERS => '0');
403 ELSIF clk25MHz'EVENT AND clk25MHz = '1' THEN -- rising clock edge
404 IF time_new = '1' THEN
405 fine_time_s <= fine_time_49;
406 coarse_time_s <= coarse_time_49;
407 END IF;
408 END IF;
409 END PROCESS;
389 --PROCESS (clk25MHz, resetn_25MHz)
390 --BEGIN -- PROCESS
391 -- IF resetn_25MHz = '0' THEN -- asynchronous reset (active low)
392 -- fine_time_s <= (OTHERS => '0');
393 -- coarse_time_s <= (OTHERS => '0');
394 -- ELSIF clk25MHz'EVENT AND clk25MHz = '1' THEN -- rising clock edge
395 -- IF time_new = '1' THEN
396 -- END IF;
397 -- END IF;
398 --END PROCESS;
399
400 fine_time_s <= fine_time_49;
401 coarse_time_s <= coarse_time_49;
402
410 403
411
412 rstn_LFR_TM <= '0' WHEN resetn_24_576MHz = '0' ELSE
413 '0' WHEN soft_reset_sync = '1' ELSE
404 rstn_LFR_TM <= '0' WHEN resetn_25MHz = '0' ELSE
405 '0' WHEN soft_reset = '1' ELSE
414 406 '1';
415
416
407
417 408 -----------------------------------------------------------------------------
418 409 -- LFR_TIME_MANAGMENT
419 410 -----------------------------------------------------------------------------
420 411 lfr_time_management_1 : lfr_time_management
421 412 GENERIC MAP (
422 FIRST_DIVISION => FIRST_DIVISION,
413 --FIRST_DIVISION => FIRST_DIVISION,
423 414 NB_SECOND_DESYNC => NB_SECOND_DESYNC)
424 415 PORT MAP (
425 clk => clk24_576MHz,
416 clk => clk25MHz,
426 417 rstn => rstn_LFR_TM,
427 418
428 419 tick => new_timecode,
@@ -434,6 +425,8 BEGIN
434 425 coarse_time => coarse_time_49,
435 426 coarse_time_new => coarse_time_new_49);
436 427
428
429
437 430 -----------------------------------------------------------------------------
438 431 -- HK
439 432 -----------------------------------------------------------------------------
@@ -481,6 +474,19 BEGIN
481 474
482 475 HK_sel <= HK_sel_s;
483 476
477
478
479
480
481
482
483
484
485
486
487
488
489
484 490 -----------------------------------------------------------------------------
485 491 -- DAC
486 492 -----------------------------------------------------------------------------
@@ -514,4 +520,4 BEGIN
514 520 );
515 521
516 522 DAC_CAL_EN <= DAC_CAL_EN_s;
517 END Behavioral; No newline at end of file
523 END Behavioral;
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@@ -110,14 +110,15 BEGIN -- beh
110 110
111 111 -----------------------------------------------------------------------------
112 112 -- Just to try to limit the constraint
113 PROCESS (clk, rstn)
114 BEGIN -- PROCESS
115 IF rstn = '0' THEN -- asynchronous reset (active low)
116 set_TCU_reg <= '0';
117 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
118 set_TCU_reg <= set_TCU;
119 END IF;
120 END PROCESS;
113 --PROCESS (clk, rstn)
114 --BEGIN -- PROCESS
115 -- IF rstn = '0' THEN -- asynchronous reset (active low)
116 -- set_TCU_reg <= '0';
117 -- ELSIF clk'event AND clk = '1' THEN -- rising clock edge
118 -- set_TCU_reg <= set_TCU;
119 -- END IF;
120 --END PROCESS;
121 121 -----------------------------------------------------------------------------
122
123 END beh; No newline at end of file
122 set_TCU_reg <= set_TCU;
123
124 END beh;
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@@ -4,12 +4,12 USE IEEE.NUMERIC_STD.ALL;
4 4
5 5 LIBRARY lpp;
6 6 USE lpp.general_purpose.ALL;
7 USE lpp.lpp_lfr_management.ALL;
7 8
8 9 ENTITY fine_time_counter IS
9 10
10 11 GENERIC (
11 WAITING_TIME : STD_LOGIC_VECTOR(15 DOWNTO 0) := X"0040";
12 FIRST_DIVISION : INTEGER := 374
12 WAITING_TIME : STD_LOGIC_VECTOR(15 DOWNTO 0) := X"0040"
13 13 );
14 14
15 15 PORT (
@@ -33,12 +33,22 ARCHITECTURE beh OF fine_time_counter IS
33 33 SIGNAL new_ft_counter : STD_LOGIC_VECTOR(8 DOWNTO 0);
34 34 SIGNAL new_ft : STD_LOGIC;
35 35 SIGNAL fine_time_counter : STD_LOGIC_VECTOR(15 DOWNTO 0);
36
37 SIGNAL fine_time_max_value : STD_LOGIC_VECTOR(8 DOWNTO 0);
38 SIGNAL tick_value_gen : STD_LOGIC;
39 SIGNAL FT_max_s : STD_LOGIC;
36 40
37 -- CONSTANT FIRST_DIVISION : INTEGER := 20; -- TODO : 374
38
39 41 BEGIN -- beh
40 42
43 tick_value_gen <= tick OR FT_max_s;
41 44
45 fine_time_max_value_gen_1: fine_time_max_value_gen
46 PORT MAP (
47 clk => clk,
48 rstn => rstn,
49 tick => tick_value_gen,
50 fine_time_add => new_ft,
51 fine_time_max_value => fine_time_max_value);
42 52
43 53 counter_1 : general_counter
44 54 GENERIC MAP (
@@ -49,13 +59,13 BEGIN -- beh
49 59 PORT MAP (
50 60 clk => clk,
51 61 rstn => rstn,
52 MAX_VALUE => STD_LOGIC_VECTOR(to_unsigned(FIRST_DIVISION, 9)),
62 MAX_VALUE => fine_time_max_value,
53 63 set => tick,
54 64 set_value => (OTHERS => '0'),
55 65 add1 => '1',
56 66 counter => new_ft_counter);
57 67
58 new_ft <= '1' WHEN new_ft_counter = STD_LOGIC_VECTOR(to_unsigned(FIRST_DIVISION, 9)) ELSE '0';
68 new_ft <= '1' WHEN new_ft_counter = fine_time_max_value ELSE '0';
59 69
60 70 counter_2 : general_counter
61 71 GENERIC MAP (
@@ -72,7 +82,9 BEGIN -- beh
72 82 add1 => new_ft,
73 83 counter => fine_time_counter);
74 84
75 FT_max <= '1' WHEN new_ft = '1' AND fine_time_counter = X"FFFF" ELSE '0';
85 FT_max_s <= '1' WHEN new_ft = '1' AND fine_time_counter = X"FFFF" ELSE '0';
86
87 FT_max <= FT_max_s;
76 88 FT_half <= '1' WHEN fine_time_counter > X"7FFF" ELSE '0';
77 89 FT_wait <= '1' WHEN fine_time_counter > WAITING_TIME ELSE '0';
78 90
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@@ -25,7 +25,6 USE lpp.lpp_lfr_management.ALL;
25 25
26 26 ENTITY lfr_time_management IS
27 27 GENERIC (
28 FIRST_DIVISION : INTEGER := 374;
29 28 NB_SECOND_DESYNC : INTEGER := 60);
30 29 PORT (
31 30 clk : IN STD_LOGIC;
@@ -83,8 +82,7 BEGIN
83 82 -----------------------------------------------------------------------------
84 83 fine_time_counter_1: fine_time_counter
85 84 GENERIC MAP (
86 WAITING_TIME => X"0040",
87 FIRST_DIVISION => FIRST_DIVISION)
85 WAITING_TIME => X"0040")
88 86 PORT MAP (
89 87 clk => clk,
90 88 rstn => rstn,
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@@ -1,111 +1,119
1 ----------------------------------------------------------------------------------
2 -- Company:
3 -- Engineer:
4 --
5 -- Create Date: 13:04:01 07/02/2012
6 -- Design Name:
7 -- Module Name: lpp_lfr_time_management - Behavioral
8 -- Project Name:
9 -- Target Devices:
10 -- Tool versions:
11 -- Description:
12 --
13 -- Dependencies:
14 --
15 -- Revision:
16 -- Revision 0.01 - File Created
17 -- Additional Comments:
18 --
19 ----------------------------------------------------------------------------------
20 LIBRARY IEEE;
21 USE IEEE.STD_LOGIC_1164.ALL;
22 LIBRARY grlib;
23 USE grlib.amba.ALL;
24 USE grlib.stdlib.ALL;
25 USE grlib.devices.ALL;
26
27 PACKAGE lpp_lfr_management IS
28
29 --***************************
30 -- APB_LFR_MANAGEMENT
31
32 COMPONENT apb_lfr_management
33 GENERIC (
34 tech : INTEGER;
35 pindex : INTEGER;
36 paddr : INTEGER;
37 pmask : INTEGER;
38 FIRST_DIVISION : INTEGER;
39 NB_SECOND_DESYNC : INTEGER);
40 PORT (
41 clk25MHz : IN STD_LOGIC;
42 resetn_25MHz : IN STD_LOGIC;
43 clk24_576MHz : IN STD_LOGIC;
44 resetn_24_576MHz : IN STD_LOGIC;
45 grspw_tick : IN STD_LOGIC;
46 apbi : IN apb_slv_in_type;
47 apbo : OUT apb_slv_out_type;
48 HK_sample : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
49 HK_val : IN STD_LOGIC;
50 HK_sel : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
51 DAC_SDO : OUT STD_LOGIC;
52 DAC_SCK : OUT STD_LOGIC;
53 DAC_SYNC : OUT STD_LOGIC;
54 DAC_CAL_EN : OUT STD_LOGIC;
55 coarse_time : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
56 fine_time : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
57 LFR_soft_rstn : OUT STD_LOGIC);
58 END COMPONENT;
59
60 COMPONENT lfr_time_management
61 GENERIC (
62 FIRST_DIVISION : INTEGER;
63 NB_SECOND_DESYNC : INTEGER);
64 PORT (
65 clk : IN STD_LOGIC;
66 rstn : IN STD_LOGIC;
67 tick : IN STD_LOGIC;
68 new_coarsetime : IN STD_LOGIC;
69 coarsetime_reg : IN STD_LOGIC_VECTOR(30 DOWNTO 0);
70 fine_time : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
71 fine_time_new : OUT STD_LOGIC;
72 coarse_time : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
73 coarse_time_new : OUT STD_LOGIC);
74 END COMPONENT;
75
76 COMPONENT coarse_time_counter
77 GENERIC (
78 NB_SECOND_DESYNC : INTEGER);
79 PORT (
80 clk : IN STD_LOGIC;
81 rstn : IN STD_LOGIC;
82 tick : IN STD_LOGIC;
83 set_TCU : IN STD_LOGIC;
84 new_TCU : IN STD_LOGIC;
85 set_TCU_value : IN STD_LOGIC_VECTOR(30 DOWNTO 0);
86 CT_add1 : IN STD_LOGIC;
87 fsm_desync : IN STD_LOGIC;
88 FT_max : IN STD_LOGIC;
89 coarse_time : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
90 coarse_time_new : OUT STD_LOGIC);
91 END COMPONENT;
92
93 COMPONENT fine_time_counter
94 GENERIC (
95 WAITING_TIME : STD_LOGIC_VECTOR(15 DOWNTO 0);
96 FIRST_DIVISION : INTEGER);
97 PORT (
98 clk : IN STD_LOGIC;
99 rstn : IN STD_LOGIC;
100 tick : IN STD_LOGIC;
101 fsm_transition : IN STD_LOGIC;
102 FT_max : OUT STD_LOGIC;
103 FT_half : OUT STD_LOGIC;
104 FT_wait : OUT STD_LOGIC;
105 fine_time : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
106 fine_time_new : OUT STD_LOGIC);
107 END COMPONENT;
108
109
110 END lpp_lfr_management;
111
1 ----------------------------------------------------------------------------------
2 -- Company:
3 -- Engineer:
4 --
5 -- Create Date: 13:04:01 07/02/2012
6 -- Design Name:
7 -- Module Name: lpp_lfr_time_management - Behavioral
8 -- Project Name:
9 -- Target Devices:
10 -- Tool versions:
11 -- Description:
12 --
13 -- Dependencies:
14 --
15 -- Revision:
16 -- Revision 0.01 - File Created
17 -- Additional Comments:
18 --
19 ----------------------------------------------------------------------------------
20 LIBRARY IEEE;
21 USE IEEE.STD_LOGIC_1164.ALL;
22 LIBRARY grlib;
23 USE grlib.amba.ALL;
24 USE grlib.stdlib.ALL;
25 USE grlib.devices.ALL;
26
27 PACKAGE lpp_lfr_management IS
28
29 --***************************
30 -- APB_LFR_MANAGEMENT
31
32 COMPONENT apb_lfr_management
33 GENERIC (
34 tech : INTEGER;
35 pindex : INTEGER;
36 paddr : INTEGER;
37 pmask : INTEGER;
38 -- FIRST_DIVISION : INTEGER;
39 NB_SECOND_DESYNC : INTEGER);
40 PORT (
41 clk25MHz : IN STD_LOGIC;
42 resetn_25MHz : IN STD_LOGIC;
43 -- clk24_576MHz : IN STD_LOGIC;
44 -- resetn_24_576MHz : IN STD_LOGIC;
45 grspw_tick : IN STD_LOGIC;
46 apbi : IN apb_slv_in_type;
47 apbo : OUT apb_slv_out_type;
48 HK_sample : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
49 HK_val : IN STD_LOGIC;
50 HK_sel : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
51 DAC_SDO : OUT STD_LOGIC;
52 DAC_SCK : OUT STD_LOGIC;
53 DAC_SYNC : OUT STD_LOGIC;
54 DAC_CAL_EN : OUT STD_LOGIC;
55 coarse_time : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
56 fine_time : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
57 LFR_soft_rstn : OUT STD_LOGIC);
58 END COMPONENT;
59
60 COMPONENT lfr_time_management
61 GENERIC (
62 --FIRST_DIVISION : INTEGER;
63 NB_SECOND_DESYNC : INTEGER);
64 PORT (
65 clk : IN STD_LOGIC;
66 rstn : IN STD_LOGIC;
67 tick : IN STD_LOGIC;
68 new_coarsetime : IN STD_LOGIC;
69 coarsetime_reg : IN STD_LOGIC_VECTOR(30 DOWNTO 0);
70 fine_time : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
71 fine_time_new : OUT STD_LOGIC;
72 coarse_time : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
73 coarse_time_new : OUT STD_LOGIC);
74 END COMPONENT;
75
76 COMPONENT coarse_time_counter
77 GENERIC (
78 NB_SECOND_DESYNC : INTEGER);
79 PORT (
80 clk : IN STD_LOGIC;
81 rstn : IN STD_LOGIC;
82 tick : IN STD_LOGIC;
83 set_TCU : IN STD_LOGIC;
84 new_TCU : IN STD_LOGIC;
85 set_TCU_value : IN STD_LOGIC_VECTOR(30 DOWNTO 0);
86 CT_add1 : IN STD_LOGIC;
87 fsm_desync : IN STD_LOGIC;
88 FT_max : IN STD_LOGIC;
89 coarse_time : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
90 coarse_time_new : OUT STD_LOGIC);
91 END COMPONENT;
92
93 COMPONENT fine_time_counter
94 GENERIC (
95 WAITING_TIME : STD_LOGIC_VECTOR(15 DOWNTO 0));--;
96 -- FIRST_DIVISION : INTEGER);
97 PORT (
98 clk : IN STD_LOGIC;
99 rstn : IN STD_LOGIC;
100 tick : IN STD_LOGIC;
101 fsm_transition : IN STD_LOGIC;
102 FT_max : OUT STD_LOGIC;
103 FT_half : OUT STD_LOGIC;
104 FT_wait : OUT STD_LOGIC;
105 fine_time : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
106 fine_time_new : OUT STD_LOGIC);
107 END COMPONENT;
108
109 COMPONENT fine_time_max_value_gen
110 PORT (
111 clk : IN STD_LOGIC;
112 rstn : IN STD_LOGIC;
113 tick : IN STD_LOGIC;
114 fine_time_add : IN STD_LOGIC;
115 fine_time_max_value : OUT STD_LOGIC_VECTOR(8 DOWNTO 0));
116 END COMPONENT;
117
118 END lpp_lfr_management;
119
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@@ -4,3 +4,4 apb_lfr_management.vhd
4 4 lfr_time_management.vhd
5 5 fine_time_counter.vhd
6 6 coarse_time_counter.vhd
7 fine_time_max_value_gen.vhd
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@@ -54,7 +54,7 ENTITY lpp_dma_send_16word IS
54 54 --
55 55 send_ok : OUT STD_LOGIC;
56 56 send_ko : OUT STD_LOGIC
57
57
58 58 );
59 59 END lpp_dma_send_16word;
60 60
@@ -88,8 +88,8 BEGIN -- beh
88 88 grant_counter <= 0;
89 89 ELSIF HCLK'EVENT AND HCLK = '1' THEN -- rising clock edge
90 90
91 DMAIn.Reset <= '0';
92
91 DMAIn.Reset <= '0';
92
93 93 CASE state IS
94 94 WHEN IDLE =>
95 95 DMAIn.Store <= '1';
@@ -98,11 +98,11 BEGIN -- beh
98 98 send_ko <= '0';
99 99 DMAIn.Address <= address;
100 100 data_counter <= 0;
101 DMAIn.Lock <= '0'; -- FIX test
101 DMAIn.Lock <= '0';
102 102 IF send = '1' THEN
103 103 state <= REQUEST_BUS;
104 104 DMAIn.Request <= '1';
105 DMAIn.Lock <= '1'; -- FIX test
105 DMAIn.Lock <= '1';
106 106 DMAIn.Store <= '1';
107 107 END IF;
108 108 WHEN REQUEST_BUS =>
@@ -124,10 +124,10 BEGIN -- beh
124 124
125 125 IF DMAOut.Grant = '1' THEN
126 126 IF grant_counter = 15 THEN
127 DMAIn.Reset <= '0';
127 DMAIn.Reset <= '0';
128 128 DMAIn.Request <= '0';
129 DMAIn.Store <= '0';
130 DMAIn.Burst <= '0';
129 DMAIn.Store <= '0';
130 DMAIn.Burst <= '0';
131 131 ELSE
132 132 grant_counter <= grant_counter+1;
133 133 END IF;
@@ -135,6 +135,7 BEGIN -- beh
135 135
136 136 IF DMAOut.OKAY = '1' THEN
137 137 IF data_counter = 15 THEN
138 --DMAIn.Request <= '0'; -- FIX Test 31/03/2014 to handle burst interruption
138 139 DMAIn.Address <= (OTHERS => '0');
139 140 state <= WAIT_LAST_READY;
140 141 ELSE
@@ -167,7 +168,7 BEGIN -- beh
167 168 END PROCESS;
168 169
169 170 DMAIn.Data <= data;
170
171
171 172 ren <= NOT (DMAOut.OKAY OR DMAOut.GRANT) WHEN state = SEND_DATA ELSE
172 173 '1';
173 174
@@ -175,7 +176,7 BEGIN -- beh
175 176 --ren <= '0' WHEN DMAOut.OKAY = '1' ELSE --AND (state = SEND_DATA OR state = WAIT_LAST_READY) ELSE
176 177 -- '1';
177 178 -- /\ JC - 20/01/2014 /\
178
179
179 180 -- \/ JC - 11/12/2013 \/
180 181 --ren <= '0' WHEN DMAOut.OKAY = '1' AND state = SEND_DATA ELSE
181 182 -- '1';
@@ -191,5 +192,5 BEGIN -- beh
191 192 --ren <= '0' WHEN state = SEND_DATA ELSE
192 193 -- '1';
193 194 -- /\ JC - 09/12/2013 /\
194
195
195 196 END beh;
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@@ -72,7 +72,9 ENTITY leon3_soc IS
72 72 NB_APB_SLAVE : INTEGER := 1;
73 73 --
74 74 ADDRESS_SIZE : INTEGER := 20;
75 USES_IAP_MEMCTRLR : INTEGER := 0
75 USES_IAP_MEMCTRLR : INTEGER := 0;
76 BYPASS_EDAC_MEMCTRLR : STD_LOGIC := '0';
77 SRBANKSZ : INTEGER := 8
76 78
77 79 );
78 80 PORT (
@@ -412,9 +414,10 BEGIN
412 414 pindex => 0,
413 415 paddr => 0,
414 416 srbanks => 2,
415 banksz => 8, --512k * 32
417 banksz => SRBANKSZ, --512k * 32
416 418 rmw => 1,
417 419 --Aeroflex memory generics:
420 mbpbusy => BYPASS_EDAC_MEMCTRLR,
418 421 mprog => 1, -- program memory by default values after reset
419 422 mpsrate => 15, -- default scrub rate period
420 423 mpb2s => 14, -- default busy to scrub delay
@@ -440,7 +443,7 BEGIN
440 443 memi.brdyn <= nSRAM_READY;
441 444
442 445 mbe_pad : iopad
443 GENERIC MAP(tech => padtech)
446 GENERIC MAP(tech => padtech, oepol => USES_IAP_MEMCTRLR)
444 447 PORT MAP(pad => SRAM_MBE,
445 448 i => mbe,
446 449 en => mbe_drive,
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@@ -54,7 +54,9 PACKAGE lpp_leon3_soc_pkg IS
54 54 NB_AHB_SLAVE : INTEGER;
55 55 NB_APB_SLAVE : INTEGER;
56 56 ADDRESS_SIZE : INTEGER;
57 USES_IAP_MEMCTRLR : INTEGER
57 USES_IAP_MEMCTRLR : INTEGER;
58 BYPASS_EDAC_MEMCTRLR : STD_LOGIC;
59 SRBANKSZ : INTEGER := 8
58 60 );
59 61 PORT (
60 62 clk : IN STD_ULOGIC;
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