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update delay function
martin -
r87:097bccb7dd53 martin
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@@ -0,0 +1,108
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 ------------------------------------------------------------------------------
19 -- Author : Martin Morlot
20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 ------------------------------------------------------------------------------
22 library IEEE;
23 use IEEE.std_logic_1164.all;
24 use IEEE.numeric_std.all;
25
26 --! Programme qui va permettre de "pipeliner" la FIFO, donn�e disponible en sortie d� son �criture en entr�e de la FIFO
27
28 entity Pipeline is
29 generic(Data_sz : integer := 16);
30 port(
31 clk,raz : in std_logic; --! Horloge et reset general du composant
32 Data_one : in std_logic_vector(Data_sz-1 downto 0); --! Donn�e en entr�e de la FIFO, cot� �criture
33 Data_two : in std_logic_vector(Data_sz-1 downto 0); --! Donn�e en sortie de la FIFO, cot� lecture
34 -- ReUse : in std_logic; --! Flag, Permet de relire la m�moire du d�but
35 flag_RE : in std_logic; --! Flag, Demande la lecture de la m�moire
36 flag_WR : in std_logic; --! Flag, Demande l'�criture dans la m�moire
37 empty : in std_logic; --! Flag, M�moire vide
38 Data_out : out std_logic_vector(Data_sz-1 downto 0) --! Donn�e en sortie, pipelin�e
39 );
40 end Pipeline;
41
42 architecture ar_Pipeline of Pipeline is
43
44 type etat is (e0,e1,e2,eX);
45 signal ect : etat;
46
47 begin
48 process (clk,raz)
49 begin
50 if(raz='0')then
51 Data_out <= (others => 'X');
52 ect <= e0;
53
54 elsif(clk' event and clk='1')then
55 case ect is
56 when e0 =>
57 if(flag_WR='1')then
58 Data_out <= Data_one;
59 ect <= e1;
60 -- elsif(ReUse='1')then
61 -- ect <= e1;
62 end if;
63
64 when e1 =>
65 if(flag_RE='1')then
66 --Data_out <= Data_two;
67 ect <= eX;
68 end if;
69
70 when eX =>
71 --Data_out <= Data_two;
72 ect <= e2;
73
74 when e2 =>
75 Data_out <= Data_two;
76 if(empty='1')then
77 ect <= e0;
78 else
79 --Data_out <= Data_two;
80 ect <= e2;
81 end if;
82
83
84
85 end case;
86 end if;
87 end process;
88
89 end ar_Pipeline;
90
91
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108
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@@ -26,5 +26,4 all:
26 make all -C BenchUART
26 make all -C BenchUART
27 make all -C BenchFFT
27 make all -C BenchFFT
28 make all -C BenchGPIO
28 make all -C BenchGPIO
29 make all -C BenchMatrix
29 make all -C BenchMatrix No newline at end of file
30
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@@ -51,7 +51,7 entity APB_Matrix is
51 ReadFIFO : out std_logic_vector(1 downto 0);
51 ReadFIFO : out std_logic_vector(1 downto 0);
52 WriteFIFO : out std_logic;
52 WriteFIFO : out std_logic;
53 Result : out std_logic_vector(Result_SZ-1 downto 0);
53 Result : out std_logic_vector(Result_SZ-1 downto 0);
54 -- Start : out std_logic;
54 Start : out std_logic;
55 -- Read : out std_logic;
55 -- Read : out std_logic;
56 -- Take : out std_logic;
56 -- Take : out std_logic;
57 -- Valid : out std_logic;
57 -- Valid : out std_logic;
@@ -84,7 +84,7 begin
84
84
85 Mspec0 : SpectralMatrix
85 Mspec0 : SpectralMatrix
86 generic map (Input_SZ,Result_SZ)
86 generic map (Input_SZ,Result_SZ)
87 port map(clk,rst,FIFO1,FIFO2,Full,Empty,Rec.MATRIX_Statu,ReadFIFO,WriteFIFO,Result); --Start,Read,Take,Valid,Received,Conjugate,OP1,OP2
87 port map(clk,rst,FIFO1,FIFO2,Full,Empty,Rec.MATRIX_Statu,ReadFIFO,WriteFIFO,Start,Result); --Start,Read,Take,Valid,Received,Conjugate,OP1,OP2
88
88
89 process(rst,clk)
89 process(rst,clk)
90 begin
90 begin
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@@ -38,7 +38,7 port(
38 Statu : in std_logic_vector(3 downto 0);
38 Statu : in std_logic_vector(3 downto 0);
39 ReadFIFO : out std_logic_vector(1 downto 0);
39 ReadFIFO : out std_logic_vector(1 downto 0);
40 WriteFIFO : out std_logic;
40 WriteFIFO : out std_logic;
41 -- Start : out std_logic;
41 Start : out std_logic;
42 -- Read : out std_logic;
42 -- Read : out std_logic;
43 -- Take : out std_logic;
43 -- Take : out std_logic;
44 -- Valid : out std_logic;
44 -- Valid : out std_logic;
@@ -97,7 +97,7 With Statu select
97 '1' when "1111",
97 '1' when "1111",
98 '0' when others;
98 '0' when others;
99
99
100 --Start <= Start_int;
100 Start <= Start_int;
101 --Read <= Read_int;
101 --Read <= Read_int;
102 --Take <= Take_int;
102 --Take <= Take_int;
103 --Received <= Received_int;
103 --Received <= Received_int;
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@@ -50,6 +50,7 component APB_Matrix is
50 ReadFIFO : out std_logic_vector(1 downto 0);
50 ReadFIFO : out std_logic_vector(1 downto 0);
51 WriteFIFO : out std_logic;
51 WriteFIFO : out std_logic;
52 Result : out std_logic_vector(Result_SZ-1 downto 0);
52 Result : out std_logic_vector(Result_SZ-1 downto 0);
53 Start : out std_logic;
53 apbi : in apb_slv_in_type; --! Registre de gestion des entr�es du bus
54 apbi : in apb_slv_in_type; --! Registre de gestion des entr�es du bus
54 apbo : out apb_slv_out_type --! Registre de gestion des sorties du bus
55 apbo : out apb_slv_out_type --! Registre de gestion des sorties du bus
55 );
56 );
@@ -70,6 +71,7 port(
70 Statu : in std_logic_vector(3 downto 0);
71 Statu : in std_logic_vector(3 downto 0);
71 ReadFIFO : out std_logic_vector(1 downto 0);
72 ReadFIFO : out std_logic_vector(1 downto 0);
72 WriteFIFO : out std_logic;
73 WriteFIFO : out std_logic;
74 Start : out std_logic;
73 Result : out std_logic_vector(Result_SZ-1 downto 0)
75 Result : out std_logic_vector(Result_SZ-1 downto 0)
74 );
76 );
75 end component;
77 end component;
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@@ -61,8 +61,9 signal ReadEnable : std_logic;
61 signal WriteEnable : std_logic;
61 signal WriteEnable : std_logic;
62 signal FlagEmpty : std_logic;
62 signal FlagEmpty : std_logic;
63 signal FlagFull : std_logic;
63 signal FlagFull : std_logic;
64 signal ReUse : std_logic;
64 --signal ReUse : std_logic;
65 signal Lock : std_logic;
65 --signal Lock : std_logic;
66 --signal RstMem : std_logic;
66 signal DataIn : std_logic_vector(Data_sz-1 downto 0);
67 signal DataIn : std_logic_vector(Data_sz-1 downto 0);
67 signal DataOut : std_logic_vector(Data_sz-1 downto 0);
68 signal DataOut : std_logic_vector(Data_sz-1 downto 0);
68 signal AddrIn : std_logic_vector(Addr_sz-1 downto 0);
69 signal AddrIn : std_logic_vector(Addr_sz-1 downto 0);
@@ -72,12 +73,12 begin
72
73
73 APB : ApbDriver
74 APB : ApbDriver
74 generic map(pindex,paddr,pmask,pirq,abits,LPP_FIFO,Data_sz,Addr_sz,addr_max_int)
75 generic map(pindex,paddr,pmask,pirq,abits,LPP_FIFO,Data_sz,Addr_sz,addr_max_int)
75 port map(clk,rst,ReadEnable,WriteEnable,FlagEmpty,FlagFull,ReUse,Lock,DataIn,DataOut,AddrIn,AddrOut,apbi,apbo);
76 port map(clk,rst,ReadEnable,WriteEnable,FlagEmpty,FlagFull,DataIn,DataOut,AddrIn,AddrOut,apbi,apbo);
76
77
77
78
78 DEVICE : Top_FIFO
79 DEVICE : Top_FIFO
79 generic map(Data_sz,Addr_sz,addr_max_int)
80 generic map(Data_sz,Addr_sz,addr_max_int)
80 port map(clk,rst,ReadEnable,WriteEnable,ReUse,Lock,DataIn,AddrOut,AddrIn,FlagFull,FlagEmpty,DataOut);
81 port map(clk,rst,ReadEnable,WriteEnable,DataIn,AddrOut,AddrIn,FlagFull,FlagEmpty,DataOut);
81
82
82 Empty <= FlagEmpty;
83 Empty <= FlagEmpty;
83 Full <= FlagFull;
84 Full <= FlagFull;
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@@ -62,8 +62,9 signal Low : std_logic:='0';
62 signal ReadEnable : std_logic;
62 signal ReadEnable : std_logic;
63 signal FlagEmpty : std_logic;
63 signal FlagEmpty : std_logic;
64 signal FlagFull : std_logic;
64 signal FlagFull : std_logic;
65 signal ReUse : std_logic;
65 --signal ReUse : std_logic;
66 signal Lock : std_logic;
66 --signal Lock : std_logic;
67 --signal RstMem : std_logic;
67 signal DataIn : std_logic_vector(Data_sz-1 downto 0);
68 signal DataIn : std_logic_vector(Data_sz-1 downto 0);
68 signal DataOut : std_logic_vector(Data_sz-1 downto 0);
69 signal DataOut : std_logic_vector(Data_sz-1 downto 0);
69 signal AddrIn : std_logic_vector(Addr_sz-1 downto 0);
70 signal AddrIn : std_logic_vector(Addr_sz-1 downto 0);
@@ -73,12 +74,12 begin
73
74
74 APB : ApbDriver
75 APB : ApbDriver
75 generic map(pindex,paddr,pmask,pirq,abits,LPP_FIFO,Data_sz,Addr_sz,addr_max_int)
76 generic map(pindex,paddr,pmask,pirq,abits,LPP_FIFO,Data_sz,Addr_sz,addr_max_int)
76 port map(clk,rst,ReadEnable,Low,FlagEmpty,FlagFull,ReUse,Lock,DataIn,DataOut,AddrIn,AddrOut,apbi,apbo);
77 port map(clk,rst,ReadEnable,Low,FlagEmpty,FlagFull,DataIn,DataOut,AddrIn,AddrOut,apbi,apbo);
77
78
78
79
79 FIFO : Top_FIFO
80 FIFO : Top_FIFO
80 generic map(Data_sz,Addr_sz,addr_max_int)
81 generic map(Data_sz,Addr_sz,addr_max_int)
81 port map(clk,rst,ReadEnable,WriteEnable,ReUse,Lock,DATA,AddrOut,AddrIn,FlagFull,FlagEmpty,DataOut);
82 port map(clk,rst,ReadEnable,WriteEnable,DATA,AddrOut,AddrIn,FlagFull,FlagEmpty,DataOut);
82
83
83 Empty <= FlagEmpty;
84 Empty <= FlagEmpty;
84 Full <= FlagFull;
85 Full <= FlagFull;
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@@ -62,8 +62,9 signal Low : std_logic:='0';
62 signal WriteEnable : std_logic;
62 signal WriteEnable : std_logic;
63 signal FlagEmpty : std_logic;
63 signal FlagEmpty : std_logic;
64 signal FlagFull : std_logic;
64 signal FlagFull : std_logic;
65 signal ReUse : std_logic;
65 --signal ReUse : std_logic;
66 signal Lock : std_logic;
66 --signal Lock : std_logic;
67 --signal RstMem : std_logic;
67 signal DataIn : std_logic_vector(Data_sz-1 downto 0);
68 signal DataIn : std_logic_vector(Data_sz-1 downto 0);
68 signal DataOut : std_logic_vector(Data_sz-1 downto 0);
69 signal DataOut : std_logic_vector(Data_sz-1 downto 0);
69 signal AddrIn : std_logic_vector(Addr_sz-1 downto 0);
70 signal AddrIn : std_logic_vector(Addr_sz-1 downto 0);
@@ -73,12 +74,12 begin
73
74
74 APB : ApbDriver
75 APB : ApbDriver
75 generic map(pindex,paddr,pmask,pirq,abits,LPP_FIFO,Data_sz,Addr_sz,addr_max_int)
76 generic map(pindex,paddr,pmask,pirq,abits,LPP_FIFO,Data_sz,Addr_sz,addr_max_int)
76 port map(clk,rst,Low,WriteEnable,FlagEmpty,FlagFull,ReUse,Lock,DataIn,DataOut,AddrIn,AddrOut,apbi,apbo);
77 port map(clk,rst,Low,WriteEnable,FlagEmpty,FlagFull,DataIn,DataOut,AddrIn,AddrOut,apbi,apbo);
77
78
78
79
79 FIFO : Top_FIFO
80 FIFO : Top_FIFO
80 generic map(Data_sz,Addr_sz,addr_max_int)
81 generic map(Data_sz,Addr_sz,addr_max_int)
81 port map(clk,rst,ReadEnable,WriteEnable,ReUse,Lock,DataIn,AddrOut,AddrIn,FlagFull,FlagEmpty,DataOut);
82 port map(clk,rst,ReadEnable,WriteEnable,DataIn,AddrOut,AddrIn,FlagFull,FlagEmpty,DataOut);
82
83
83 DATA <= DataOut;
84 DATA <= DataOut;
84 Empty <= FlagEmpty;
85 Empty <= FlagEmpty;
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@@ -49,8 +49,9 entity ApbDriver is
49 WriteEnable : out std_logic; --! Instruction d'�criture en m�moire
49 WriteEnable : out std_logic; --! Instruction d'�criture en m�moire
50 FlagEmpty : in std_logic; --! Flag, M�moire vide
50 FlagEmpty : in std_logic; --! Flag, M�moire vide
51 FlagFull : in std_logic; --! Flag, M�moire pleine
51 FlagFull : in std_logic; --! Flag, M�moire pleine
52 ReUse : out std_logic; --! Flag, Permet de relire la m�moire du d�but
52 -- ReUse : out std_logic; --! Flag, Permet de relire la m�moire en boucle sans nouvelle donn�es
53 Lock : out std_logic; --! Flag, Permet de bloquer l'�criture dans la m�moire
53 -- Lock : out std_logic; --! Flag, Permet de bloquer l'�criture dans la m�moire
54 -- RstMem : out std_logic; --! Flag, Reset "manuel" sp�cifique au composant
54 DataIn : out std_logic_vector(Data_sz-1 downto 0); --! Registre de donn�es en entr�e
55 DataIn : out std_logic_vector(Data_sz-1 downto 0); --! Registre de donn�es en entr�e
55 DataOut : in std_logic_vector(Data_sz-1 downto 0); --! Registre de donn�es en sortie
56 DataOut : in std_logic_vector(Data_sz-1 downto 0); --! Registre de donn�es en sortie
56 AddrIn : in std_logic_vector(Addr_sz-1 downto 0); --! Registre d'addresse (�criture)
57 AddrIn : in std_logic_vector(Addr_sz-1 downto 0); --! Registre d'addresse (�criture)
@@ -71,7 +72,7 constant pconfig : apb_config_type := (
71 1 => apb_iobar(paddr, pmask));
72 1 => apb_iobar(paddr, pmask));
72
73
73 type DEVICE_ctrlr_Reg is record
74 type DEVICE_ctrlr_Reg is record
74 DEVICE_Cfg : std_logic_vector(5 downto 0);
75 DEVICE_Cfg : std_logic_vector(3 downto 0);
75 DEVICE_DataW : std_logic_vector(Data_sz-1 downto 0);
76 DEVICE_DataW : std_logic_vector(Data_sz-1 downto 0);
76 DEVICE_DataR : std_logic_vector(Data_sz-1 downto 0);
77 DEVICE_DataR : std_logic_vector(Data_sz-1 downto 0);
77 DEVICE_AddrW : std_logic_vector(Addr_sz-1 downto 0);
78 DEVICE_AddrW : std_logic_vector(Addr_sz-1 downto 0);
@@ -90,8 +91,9 Rec.DEVICE_Cfg(0) <= FlagRE;
90 Rec.DEVICE_Cfg(1) <= FlagWR;
91 Rec.DEVICE_Cfg(1) <= FlagWR;
91 Rec.DEVICE_Cfg(2) <= FlagEmpty;
92 Rec.DEVICE_Cfg(2) <= FlagEmpty;
92 Rec.DEVICE_Cfg(3) <= FlagFull;
93 Rec.DEVICE_Cfg(3) <= FlagFull;
93 ReUse <= Rec.DEVICE_Cfg(4);
94 --ReUse <= Rec.DEVICE_Cfg(4);
94 Lock <= Rec.DEVICE_Cfg(5);
95 --Lock <= Rec.DEVICE_Cfg(5);
96 --RstMem <= Rec.DEVICE_Cfg(7);
95
97
96 DataIn <= Rec.DEVICE_DataW;
98 DataIn <= Rec.DEVICE_DataW;
97 Rec.DEVICE_DataR <= DataOut;
99 Rec.DEVICE_DataR <= DataOut;
@@ -106,8 +108,9 Rec.DEVICE_AddrR <= AddrOut;
106 Rec.DEVICE_DataW <= (others => '0');
108 Rec.DEVICE_DataW <= (others => '0');
107 FlagWR <= '0';
109 FlagWR <= '0';
108 FlagRE <= '0';
110 FlagRE <= '0';
109 Rec.DEVICE_Cfg(4) <= '0';
111 -- Rec.DEVICE_Cfg(4) <= '0';
110 Rec.DEVICE_Cfg(5) <= '0';
112 -- Rec.DEVICE_Cfg(5) <= '0';
113 -- Rec.DEVICE_Cfg(7) <= '0';
111
114
112 elsif(clk'event and clk='1')then
115 elsif(clk'event and clk='1')then
113
116
@@ -117,9 +120,10 Rec.DEVICE_AddrR <= AddrOut;
117 when "000000" =>
120 when "000000" =>
118 FlagWR <= '1';
121 FlagWR <= '1';
119 Rec.DEVICE_DataW <= apbi.pwdata(Data_sz-1 downto 0);
122 Rec.DEVICE_DataW <= apbi.pwdata(Data_sz-1 downto 0);
120 when "000010" =>
123 -- when "000010" =>
121 Rec.DEVICE_Cfg(4) <= apbi.pwdata(16);
124 -- Rec.DEVICE_Cfg(7) <= apbi.pwdata(28);
122 Rec.DEVICE_Cfg(5) <= apbi.pwdata(20);
125 -- Rec.DEVICE_Cfg(5) <= apbi.pwdata(20);
126 -- Rec.DEVICE_Cfg(6) <= apbi.pwdata(24);
123 when others =>
127 when others =>
124 null;
128 null;
125 end case;
129 end case;
@@ -134,19 +138,21 Rec.DEVICE_AddrR <= AddrOut;
134 FlagRE <= '1';
138 FlagRE <= '1';
135 Rdata(Data_sz-1 downto 0) <= Rec.DEVICE_DataR;
139 Rdata(Data_sz-1 downto 0) <= Rec.DEVICE_DataR;
136 when "000001" =>
140 when "000001" =>
137 Rdata(31 downto 8) <= X"AAAAAA";
141 -- Rdata(31 downto 8) <= X"AAAAAA";
138 Rdata(7 downto 0) <= Rec.DEVICE_AddrR;
142 Rdata(Addr_sz-1 downto 0) <= Rec.DEVICE_AddrR;
139 when "000101" =>
143 when "000101" =>
140 Rdata(31 downto 8) <= X"AAAAAA";
144 -- Rdata(31 downto 8) <= X"AAAAAA";
141 Rdata(7 downto 0) <= Rec.DEVICE_AddrW;
145 Rdata(Addr_sz-1 downto 0) <= Rec.DEVICE_AddrW;
142 when "000010" =>
146 when "000010" =>
143 Rdata(3 downto 0) <= "000" & Rec.DEVICE_Cfg(0);
147 Rdata(3 downto 0) <= "000" & Rec.DEVICE_Cfg(0);
144 Rdata(7 downto 4) <= "000" & Rec.DEVICE_Cfg(1);
148 Rdata(7 downto 4) <= "000" & Rec.DEVICE_Cfg(1);
145 Rdata(11 downto 8) <= "000" & Rec.DEVICE_Cfg(2);
149 Rdata(11 downto 8) <= "000" & Rec.DEVICE_Cfg(2);
146 Rdata(15 downto 12) <= "000" & Rec.DEVICE_Cfg(3);
150 Rdata(15 downto 12) <= "000" & Rec.DEVICE_Cfg(3);
147 Rdata(19 downto 16) <= "000" & Rec.DEVICE_Cfg(4);
151 -- Rdata(27 downto 16) <= X"000";
148 Rdata(23 downto 20) <= "000" & Rec.DEVICE_Cfg(5);
152 -- Rdata(31 downto 28) <= "000" & Rec.DEVICE_Cfg(7);
149 Rdata(31 downto 24) <= X"CC";
153 -- Rdata(23 downto 20) <= "000" & Rec.DEVICE_Cfg(5);
154 -- Rdata(27 downto 24) <= "000" & Rec.DEVICE_Cfg(6);
155 Rdata(31 downto 16) <= X"CCCC";
150 when others =>
156 when others =>
151 Rdata <= (others => '0');
157 Rdata <= (others => '0');
152 end case;
158 end case;
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@@ -32,7 +32,7 generic(
32 port(
32 port(
33 clk,raz : in std_logic; --! Horloge et reset general du composant
33 clk,raz : in std_logic; --! Horloge et reset general du composant
34 flag_RE : in std_logic; --! Flag, Demande la lecture de la m�moire
34 flag_RE : in std_logic; --! Flag, Demande la lecture de la m�moire
35 ReUse : in std_logic; --! Flag, Permet de relire la m�moire du d�but
35 -- ReUse : in std_logic; --! Flag, Permet de relire la m�moire du d�but
36 Waddr : in std_logic_vector(addr_sz-1 downto 0); --! Adresse du registre d'�criture dans la m�moire
36 Waddr : in std_logic_vector(addr_sz-1 downto 0); --! Adresse du registre d'�criture dans la m�moire
37 empty : out std_logic; --! Flag, M�moire vide
37 empty : out std_logic; --! Flag, M�moire vide
38 Raddr : out std_logic_vector(addr_sz-1 downto 0) --! Adresse du registre de lecture de la m�moire
38 Raddr : out std_logic_vector(addr_sz-1 downto 0) --! Adresse du registre de lecture de la m�moire
@@ -55,6 +55,7 begin
55 if(raz='0')then
55 if(raz='0')then
56 Rad_int <= 0;
56 Rad_int <= 0;
57 empty <= '1';
57 empty <= '1';
58 flag_reg <= '0';
58
59
59 elsif(clk' event and clk='1')then
60 elsif(clk' event and clk='1')then
60 Wad_int_reg <= Wad_int;
61 Wad_int_reg <= Wad_int;
@@ -70,9 +71,9 begin
70 end if;
71 end if;
71 end if;
72 end if;
72
73
73 if(ReUse='1')then
74 -- if(ReUse='1')then
74 empty <= '0';
75 -- empty <= '0';
75 else
76 -- else
76 if(Rad_int_reg /= Rad_int)then
77 if(Rad_int_reg /= Rad_int)then
77 if(Rad_int=Wad_int)then
78 if(Rad_int=Wad_int)then
78 empty <= '1';
79 empty <= '1';
@@ -84,7 +85,7 begin
84 end if;
85 end if;
85 end if;
86 end if;
86
87
87 end if;
88 -- end if;
88 end process;
89 end process;
89
90
90 Wad_int <= to_integer(unsigned(Waddr));
91 Wad_int <= to_integer(unsigned(Waddr));
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@@ -46,6 +46,7 signal Wad_int : integer range 0 to
46 signal Wad_int_reg : integer range 0 to addr_max_int;
46 signal Wad_int_reg : integer range 0 to addr_max_int;
47 signal Rad_int : integer range 0 to addr_max_int;
47 signal Rad_int : integer range 0 to addr_max_int;
48 signal Rad_int_reg : integer range 0 to addr_max_int;
48 signal Rad_int_reg : integer range 0 to addr_max_int;
49 signal flag_reg : std_logic;
49
50
50 begin
51 begin
51 process (clk,raz)
52 process (clk,raz)
@@ -53,13 +54,15 begin
53 if(raz='0')then
54 if(raz='0')then
54 Wad_int <= 0;
55 Wad_int <= 0;
55 full <= '0';
56 full <= '0';
57 flag_reg <= '0';
56
58
57 elsif(clk' event and clk='1')then
59 elsif(clk' event and clk='1')then
58 Wad_int_reg <= Wad_int;
60 Wad_int_reg <= Wad_int;
59 Rad_int_reg <= Rad_int;
61 Rad_int_reg <= Rad_int;
62 flag_reg <= flag_WR;
60
63
61
64
62 if(flag_WR='1')then
65 if(flag_reg ='0' and flag_WR='1')then
63 if(Wad_int=addr_max_int-1)then
66 if(Wad_int=addr_max_int-1)then
64 Wad_int <= 0;
67 Wad_int <= 0;
65 else
68 else
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@@ -39,8 +39,9 entity Top_FIFO is
39 clk,raz : in std_logic; --! Horloge et reset general du composant
39 clk,raz : in std_logic; --! Horloge et reset general du composant
40 flag_RE : in std_logic; --! Flag, Demande la lecture de la m�moire
40 flag_RE : in std_logic; --! Flag, Demande la lecture de la m�moire
41 flag_WR : in std_logic; --! Flag, Demande l'�criture dans la m�moire
41 flag_WR : in std_logic; --! Flag, Demande l'�criture dans la m�moire
42 ReUse : in std_logic; --! Flag, Permet de relire la m�moire du d�but
42 -- ReUse : in std_logic; --! Flag, Permet de relire la m�moire en boucle sans nouvelle donn�es
43 Lock : in std_logic; --! Permet de bloquer l'�criture dans la m�moire
43 -- Lock : in std_logic; --! Permet de bloquer l'�criture dans la m�moire
44 -- RstMem : in std_logic; --! Flag, Reset "manuel" sp�cifique au composant
44 Data_in : in std_logic_vector(Data_sz-1 downto 0); --! Data en entr�e du composant
45 Data_in : in std_logic_vector(Data_sz-1 downto 0); --! Data en entr�e du composant
45 Addr_RE : out std_logic_vector(addr_sz-1 downto 0); --! Adresse d'�criture
46 Addr_RE : out std_logic_vector(addr_sz-1 downto 0); --! Adresse d'�criture
46 Addr_WR : out std_logic_vector(addr_sz-1 downto 0); --! Adresse de lecture
47 Addr_WR : out std_logic_vector(addr_sz-1 downto 0); --! Adresse de lecture
@@ -73,12 +74,18 signal Waddr : std_logic_vector(addr
73 --signal Data_int : std_logic_vector(Data_sz-1 downto 0);
74 --signal Data_int : std_logic_vector(Data_sz-1 downto 0);
74 signal s_empty : std_logic;
75 signal s_empty : std_logic;
75 signal s_full : std_logic;
76 signal s_full : std_logic;
76 signal s_full2 : std_logic;
77 --signal s_full2 : std_logic;
77 signal s_flag_RE : std_logic;
78 signal s_flag_RE : std_logic;
78 signal s_flag_WR : std_logic;
79 signal s_flag_WR : std_logic;
80 signal Flag_WR_reg : std_logic;
81 --signal rst : std_logic;
82 --signal RstMem_inv : std_logic;
79
83
80 begin
84 begin
81
85
86 --RstMem_inv <= not RstMem;
87 --rst <= raz and RstMem_inv;
88
82 WR : Fifo_Write
89 WR : Fifo_Write
83 generic map(Addr_sz,addr_max_int)
90 generic map(Addr_sz,addr_max_int)
84 port map(clk,raz,s_flag_WR,Raddr,s_full,Waddr);
91 port map(clk,raz,s_flag_WR,Raddr,s_full,Waddr);
@@ -89,25 +96,32 begin
89 port map(clk,s_flag_RE,Raddr,Data_out,clk,s_flag_WR,Waddr,Data_in);
96 port map(clk,s_flag_RE,Raddr,Data_out,clk,s_flag_WR,Waddr,Data_in);
90
97
91
98
92 -- link : Link_Reg
99 -- Pipe : Pipeline
93 -- generic map(Data_sz)
100 -- generic map(Data_sz)
94 -- port map(clk,raz,Data_in,Data_int,ReUse,s_flag_RE,s_flag_WR,s_empty,Data_out);
101 -- port map(clk,raz,Data_in,Data_int,s_flag_RE,s_flag_WR,s_empty,Data_out);
95
102
96
103
97 RE : Fifo_Read
104 RE : Fifo_Read
98 generic map(Addr_sz,addr_max_int)
105 generic map(Addr_sz,addr_max_int)
99 port map(clk,raz,s_flag_RE,ReUse,Waddr,s_empty,Raddr);
106 port map(clk,raz,s_flag_RE,Waddr,s_empty,Raddr);
100
107
101 process(clk,raz)
108 process(clk,raz)
102 begin
109 begin
103 if(raz='0')then
110 if(raz='0')then
104 s_flag_RE <= '0';
111 s_flag_RE <= '0';
105 s_flag_WR <= '0';
112 s_flag_WR <= '0';
106 s_full2 <= s_full;
113 -- s_full2 <= s_full;
114 Flag_WR_reg <= '0';
107
115
108 elsif(clk'event and clk='1')then
116 elsif(clk'event and clk='1')then
109 if(s_full2='0')then
117 Flag_WR_reg <= Flag_WR;
118
119 if(s_full='0')then --2
120 if(s_empty='1')then
121 s_flag_WR <= Flag_WR_reg;
122 else
110 s_flag_WR <= Flag_WR;
123 s_flag_WR <= Flag_WR;
124 end if;
111 else
125 else
112 s_flag_WR <= '0';
126 s_flag_WR <= '0';
113 end if;
127 end if;
@@ -118,16 +132,16 begin
118 s_flag_RE <= '0';
132 s_flag_RE <= '0';
119 end if;
133 end if;
120
134
121 if(Lock='1')then
135 -- if(Lock='1')then
122 s_full2 <= '1';
136 -- s_full2 <= '1';
123 else
137 -- else
124 s_full2 <= s_full;
138 -- s_full2 <= s_full;
125 end if;
139 -- end if;
126
140
127 end if;
141 end if;
128 end process;
142 end process;
129
143
130 full <= s_full2;
144 full <= s_full; --2
131 empty <= s_empty;
145 empty <= s_empty;
132 Addr_RE <= Raddr;
146 Addr_RE <= Raddr;
133 Addr_WR <= Waddr;
147 Addr_WR <= Waddr;
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@@ -76,8 +76,9 component ApbDriver is
76 WriteEnable : out std_logic;
76 WriteEnable : out std_logic;
77 FlagEmpty : in std_logic;
77 FlagEmpty : in std_logic;
78 FlagFull : in std_logic;
78 FlagFull : in std_logic;
79 ReUse : out std_logic;
79 -- ReUse : out std_logic;
80 Lock : out std_logic;
80 -- Lock : out std_logic;
81 -- RstMem : out std_logic;
81 DataIn : out std_logic_vector(Data_sz-1 downto 0);
82 DataIn : out std_logic_vector(Data_sz-1 downto 0);
82 DataOut : in std_logic_vector(Data_sz-1 downto 0);
83 DataOut : in std_logic_vector(Data_sz-1 downto 0);
83 AddrIn : in std_logic_vector(Addr_sz-1 downto 0);
84 AddrIn : in std_logic_vector(Addr_sz-1 downto 0);
@@ -98,8 +99,9 component Top_FIFO is
98 clk,raz : in std_logic;
99 clk,raz : in std_logic;
99 flag_RE : in std_logic;
100 flag_RE : in std_logic;
100 flag_WR : in std_logic;
101 flag_WR : in std_logic;
101 ReUse : in std_logic;
102 -- ReUse : in std_logic;
102 Lock : in std_logic;
103 -- Lock : in std_logic;
104 -- RstMem : in std_logic;
103 Data_in : in std_logic_vector(Data_sz-1 downto 0);
105 Data_in : in std_logic_vector(Data_sz-1 downto 0);
104 Addr_RE : out std_logic_vector(addr_sz-1 downto 0);
106 Addr_RE : out std_logic_vector(addr_sz-1 downto 0);
105 Addr_WR : out std_logic_vector(addr_sz-1 downto 0);
107 Addr_WR : out std_logic_vector(addr_sz-1 downto 0);
@@ -118,7 +120,7 component Fifo_Read is
118 clk : in std_logic;
120 clk : in std_logic;
119 raz : in std_logic;
121 raz : in std_logic;
120 flag_RE : in std_logic;
122 flag_RE : in std_logic;
121 ReUse : in std_logic;
123 -- ReUse : in std_logic;
122 Waddr : in std_logic_vector(addr_sz-1 downto 0);
124 Waddr : in std_logic_vector(addr_sz-1 downto 0);
123 empty : out std_logic;
125 empty : out std_logic;
124 Raddr : out std_logic_vector(addr_sz-1 downto 0)
126 Raddr : out std_logic_vector(addr_sz-1 downto 0)
@@ -141,13 +143,13 component Fifo_Write is
141 end component;
143 end component;
142
144
143
145
144 component Link_Reg is
146 component Pipeline is
145 generic(Data_sz : integer := 16);
147 generic(Data_sz : integer := 16);
146 port(
148 port(
147 clk,raz : in std_logic;
149 clk,raz : in std_logic;
148 Data_one : in std_logic_vector(Data_sz-1 downto 0);
150 Data_one : in std_logic_vector(Data_sz-1 downto 0);
149 Data_two : in std_logic_vector(Data_sz-1 downto 0);
151 Data_two : in std_logic_vector(Data_sz-1 downto 0);
150 ReUse : in std_logic;
152 -- ReUse : in std_logic;
151 flag_RE : in std_logic;
153 flag_RE : in std_logic;
152 flag_WR : in std_logic;
154 flag_WR : in std_logic;
153 empty : in std_logic;
155 empty : in std_logic;
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