diff --git a/LPP_drivers/exemples/Makefile b/LPP_drivers/exemples/Makefile --- a/LPP_drivers/exemples/Makefile +++ b/LPP_drivers/exemples/Makefile @@ -26,5 +26,4 @@ all: make all -C BenchUART make all -C BenchFFT make all -C BenchGPIO - make all -C BenchMatrix - + make all -C BenchMatrix \ No newline at end of file diff --git a/lib/lpp/lpp_matrix/APB_Matrix.vhd b/lib/lpp/lpp_matrix/APB_Matrix.vhd --- a/lib/lpp/lpp_matrix/APB_Matrix.vhd +++ b/lib/lpp/lpp_matrix/APB_Matrix.vhd @@ -51,7 +51,7 @@ entity APB_Matrix is ReadFIFO : out std_logic_vector(1 downto 0); WriteFIFO : out std_logic; Result : out std_logic_vector(Result_SZ-1 downto 0); --- Start : out std_logic; + Start : out std_logic; -- Read : out std_logic; -- Take : out std_logic; -- Valid : out std_logic; @@ -84,7 +84,7 @@ begin Mspec0 : SpectralMatrix generic map (Input_SZ,Result_SZ) - port map(clk,rst,FIFO1,FIFO2,Full,Empty,Rec.MATRIX_Statu,ReadFIFO,WriteFIFO,Result); --Start,Read,Take,Valid,Received,Conjugate,OP1,OP2 + port map(clk,rst,FIFO1,FIFO2,Full,Empty,Rec.MATRIX_Statu,ReadFIFO,WriteFIFO,Start,Result); --Start,Read,Take,Valid,Received,Conjugate,OP1,OP2 process(rst,clk) begin diff --git a/lib/lpp/lpp_matrix/SpectralMatrix.vhd b/lib/lpp/lpp_matrix/SpectralMatrix.vhd --- a/lib/lpp/lpp_matrix/SpectralMatrix.vhd +++ b/lib/lpp/lpp_matrix/SpectralMatrix.vhd @@ -38,7 +38,7 @@ port( Statu : in std_logic_vector(3 downto 0); ReadFIFO : out std_logic_vector(1 downto 0); WriteFIFO : out std_logic; --- Start : out std_logic; + Start : out std_logic; -- Read : out std_logic; -- Take : out std_logic; -- Valid : out std_logic; @@ -97,7 +97,7 @@ With Statu select '1' when "1111", '0' when others; ---Start <= Start_int; +Start <= Start_int; --Read <= Read_int; --Take <= Take_int; --Received <= Received_int; diff --git a/lib/lpp/lpp_matrix/lpp_matrix.vhd b/lib/lpp/lpp_matrix/lpp_matrix.vhd --- a/lib/lpp/lpp_matrix/lpp_matrix.vhd +++ b/lib/lpp/lpp_matrix/lpp_matrix.vhd @@ -50,6 +50,7 @@ component APB_Matrix is ReadFIFO : out std_logic_vector(1 downto 0); WriteFIFO : out std_logic; Result : out std_logic_vector(Result_SZ-1 downto 0); + Start : out std_logic; apbi : in apb_slv_in_type; --! Registre de gestion des entrées du bus apbo : out apb_slv_out_type --! Registre de gestion des sorties du bus ); @@ -70,6 +71,7 @@ port( Statu : in std_logic_vector(3 downto 0); ReadFIFO : out std_logic_vector(1 downto 0); WriteFIFO : out std_logic; + Start : out std_logic; Result : out std_logic_vector(Result_SZ-1 downto 0) ); end component; diff --git a/lib/lpp/lpp_memory/APB_FIFO.vhd b/lib/lpp/lpp_memory/APB_FIFO.vhd --- a/lib/lpp/lpp_memory/APB_FIFO.vhd +++ b/lib/lpp/lpp_memory/APB_FIFO.vhd @@ -61,8 +61,9 @@ signal ReadEnable : std_logic; signal WriteEnable : std_logic; signal FlagEmpty : std_logic; signal FlagFull : std_logic; -signal ReUse : std_logic; -signal Lock : std_logic; +--signal ReUse : std_logic; +--signal Lock : std_logic; +--signal RstMem : std_logic; signal DataIn : std_logic_vector(Data_sz-1 downto 0); signal DataOut : std_logic_vector(Data_sz-1 downto 0); signal AddrIn : std_logic_vector(Addr_sz-1 downto 0); @@ -72,12 +73,12 @@ begin APB : ApbDriver generic map(pindex,paddr,pmask,pirq,abits,LPP_FIFO,Data_sz,Addr_sz,addr_max_int) - port map(clk,rst,ReadEnable,WriteEnable,FlagEmpty,FlagFull,ReUse,Lock,DataIn,DataOut,AddrIn,AddrOut,apbi,apbo); + port map(clk,rst,ReadEnable,WriteEnable,FlagEmpty,FlagFull,DataIn,DataOut,AddrIn,AddrOut,apbi,apbo); DEVICE : Top_FIFO generic map(Data_sz,Addr_sz,addr_max_int) - port map(clk,rst,ReadEnable,WriteEnable,ReUse,Lock,DataIn,AddrOut,AddrIn,FlagFull,FlagEmpty,DataOut); + port map(clk,rst,ReadEnable,WriteEnable,DataIn,AddrOut,AddrIn,FlagFull,FlagEmpty,DataOut); Empty <= FlagEmpty; Full <= FlagFull; diff --git a/lib/lpp/lpp_memory/APB_FifoRead.vhd b/lib/lpp/lpp_memory/APB_FifoRead.vhd --- a/lib/lpp/lpp_memory/APB_FifoRead.vhd +++ b/lib/lpp/lpp_memory/APB_FifoRead.vhd @@ -62,8 +62,9 @@ signal Low : std_logic:='0'; signal ReadEnable : std_logic; signal FlagEmpty : std_logic; signal FlagFull : std_logic; -signal ReUse : std_logic; -signal Lock : std_logic; +--signal ReUse : std_logic; +--signal Lock : std_logic; +--signal RstMem : std_logic; signal DataIn : std_logic_vector(Data_sz-1 downto 0); signal DataOut : std_logic_vector(Data_sz-1 downto 0); signal AddrIn : std_logic_vector(Addr_sz-1 downto 0); @@ -73,12 +74,12 @@ begin APB : ApbDriver generic map(pindex,paddr,pmask,pirq,abits,LPP_FIFO,Data_sz,Addr_sz,addr_max_int) - port map(clk,rst,ReadEnable,Low,FlagEmpty,FlagFull,ReUse,Lock,DataIn,DataOut,AddrIn,AddrOut,apbi,apbo); + port map(clk,rst,ReadEnable,Low,FlagEmpty,FlagFull,DataIn,DataOut,AddrIn,AddrOut,apbi,apbo); FIFO : Top_FIFO generic map(Data_sz,Addr_sz,addr_max_int) - port map(clk,rst,ReadEnable,WriteEnable,ReUse,Lock,DATA,AddrOut,AddrIn,FlagFull,FlagEmpty,DataOut); + port map(clk,rst,ReadEnable,WriteEnable,DATA,AddrOut,AddrIn,FlagFull,FlagEmpty,DataOut); Empty <= FlagEmpty; Full <= FlagFull; diff --git a/lib/lpp/lpp_memory/APB_FifoWrite.vhd b/lib/lpp/lpp_memory/APB_FifoWrite.vhd --- a/lib/lpp/lpp_memory/APB_FifoWrite.vhd +++ b/lib/lpp/lpp_memory/APB_FifoWrite.vhd @@ -47,7 +47,7 @@ entity APB_FifoWrite is rst : in std_logic; --! Reset general du composant apbi : in apb_slv_in_type; --! Registre de gestion des entrées du bus ReadEnable : in std_logic; --! Demande de lecture de la mémoire, géré hors de l'IP - Empty : out std_logic; --! Flag, Memoire vide + Empty : out std_logic; --! Flag, Memoire vide Full : out std_logic; --! Flag, Memoire pleine DATA : out std_logic_vector(Data_sz-1 downto 0); --! Données en sortie de la mémoire apbo : out apb_slv_out_type --! Registre de gestion des sorties du bus @@ -62,8 +62,9 @@ signal Low : std_logic:='0'; signal WriteEnable : std_logic; signal FlagEmpty : std_logic; signal FlagFull : std_logic; -signal ReUse : std_logic; -signal Lock : std_logic; +--signal ReUse : std_logic; +--signal Lock : std_logic; +--signal RstMem : std_logic; signal DataIn : std_logic_vector(Data_sz-1 downto 0); signal DataOut : std_logic_vector(Data_sz-1 downto 0); signal AddrIn : std_logic_vector(Addr_sz-1 downto 0); @@ -73,12 +74,12 @@ begin APB : ApbDriver generic map(pindex,paddr,pmask,pirq,abits,LPP_FIFO,Data_sz,Addr_sz,addr_max_int) - port map(clk,rst,Low,WriteEnable,FlagEmpty,FlagFull,ReUse,Lock,DataIn,DataOut,AddrIn,AddrOut,apbi,apbo); + port map(clk,rst,Low,WriteEnable,FlagEmpty,FlagFull,DataIn,DataOut,AddrIn,AddrOut,apbi,apbo); FIFO : Top_FIFO generic map(Data_sz,Addr_sz,addr_max_int) - port map(clk,rst,ReadEnable,WriteEnable,ReUse,Lock,DataIn,AddrOut,AddrIn,FlagFull,FlagEmpty,DataOut); + port map(clk,rst,ReadEnable,WriteEnable,DataIn,AddrOut,AddrIn,FlagFull,FlagEmpty,DataOut); DATA <= DataOut; Empty <= FlagEmpty; diff --git a/lib/lpp/lpp_memory/ApbDriver.vhd b/lib/lpp/lpp_memory/ApbDriver.vhd --- a/lib/lpp/lpp_memory/ApbDriver.vhd +++ b/lib/lpp/lpp_memory/ApbDriver.vhd @@ -49,8 +49,9 @@ entity ApbDriver is WriteEnable : out std_logic; --! Instruction d'écriture en mémoire FlagEmpty : in std_logic; --! Flag, Mémoire vide FlagFull : in std_logic; --! Flag, Mémoire pleine - ReUse : out std_logic; --! Flag, Permet de relire la mémoire du début - Lock : out std_logic; --! Flag, Permet de bloquer l'écriture dans la mémoire +-- ReUse : out std_logic; --! Flag, Permet de relire la mémoire en boucle sans nouvelle données +-- Lock : out std_logic; --! Flag, Permet de bloquer l'écriture dans la mémoire +-- RstMem : out std_logic; --! Flag, Reset "manuel" spécifique au composant DataIn : out std_logic_vector(Data_sz-1 downto 0); --! Registre de données en entrée DataOut : in std_logic_vector(Data_sz-1 downto 0); --! Registre de données en sortie AddrIn : in std_logic_vector(Addr_sz-1 downto 0); --! Registre d'addresse (écriture) @@ -71,7 +72,7 @@ constant pconfig : apb_config_type := ( 1 => apb_iobar(paddr, pmask)); type DEVICE_ctrlr_Reg is record - DEVICE_Cfg : std_logic_vector(5 downto 0); + DEVICE_Cfg : std_logic_vector(3 downto 0); DEVICE_DataW : std_logic_vector(Data_sz-1 downto 0); DEVICE_DataR : std_logic_vector(Data_sz-1 downto 0); DEVICE_AddrW : std_logic_vector(Addr_sz-1 downto 0); @@ -90,8 +91,9 @@ Rec.DEVICE_Cfg(0) <= FlagRE; Rec.DEVICE_Cfg(1) <= FlagWR; Rec.DEVICE_Cfg(2) <= FlagEmpty; Rec.DEVICE_Cfg(3) <= FlagFull; -ReUse <= Rec.DEVICE_Cfg(4); -Lock <= Rec.DEVICE_Cfg(5); +--ReUse <= Rec.DEVICE_Cfg(4); +--Lock <= Rec.DEVICE_Cfg(5); +--RstMem <= Rec.DEVICE_Cfg(7); DataIn <= Rec.DEVICE_DataW; Rec.DEVICE_DataR <= DataOut; @@ -106,8 +108,9 @@ Rec.DEVICE_AddrR <= AddrOut; Rec.DEVICE_DataW <= (others => '0'); FlagWR <= '0'; FlagRE <= '0'; - Rec.DEVICE_Cfg(4) <= '0'; - Rec.DEVICE_Cfg(5) <= '0'; +-- Rec.DEVICE_Cfg(4) <= '0'; +-- Rec.DEVICE_Cfg(5) <= '0'; +-- Rec.DEVICE_Cfg(7) <= '0'; elsif(clk'event and clk='1')then @@ -117,9 +120,10 @@ Rec.DEVICE_AddrR <= AddrOut; when "000000" => FlagWR <= '1'; Rec.DEVICE_DataW <= apbi.pwdata(Data_sz-1 downto 0); - when "000010" => - Rec.DEVICE_Cfg(4) <= apbi.pwdata(16); - Rec.DEVICE_Cfg(5) <= apbi.pwdata(20); +-- when "000010" => +-- Rec.DEVICE_Cfg(7) <= apbi.pwdata(28); +-- Rec.DEVICE_Cfg(5) <= apbi.pwdata(20); +-- Rec.DEVICE_Cfg(6) <= apbi.pwdata(24); when others => null; end case; @@ -134,19 +138,21 @@ Rec.DEVICE_AddrR <= AddrOut; FlagRE <= '1'; Rdata(Data_sz-1 downto 0) <= Rec.DEVICE_DataR; when "000001" => - Rdata(31 downto 8) <= X"AAAAAA"; - Rdata(7 downto 0) <= Rec.DEVICE_AddrR; +-- Rdata(31 downto 8) <= X"AAAAAA"; + Rdata(Addr_sz-1 downto 0) <= Rec.DEVICE_AddrR; when "000101" => - Rdata(31 downto 8) <= X"AAAAAA"; - Rdata(7 downto 0) <= Rec.DEVICE_AddrW; +-- Rdata(31 downto 8) <= X"AAAAAA"; + Rdata(Addr_sz-1 downto 0) <= Rec.DEVICE_AddrW; when "000010" => Rdata(3 downto 0) <= "000" & Rec.DEVICE_Cfg(0); Rdata(7 downto 4) <= "000" & Rec.DEVICE_Cfg(1); Rdata(11 downto 8) <= "000" & Rec.DEVICE_Cfg(2); Rdata(15 downto 12) <= "000" & Rec.DEVICE_Cfg(3); - Rdata(19 downto 16) <= "000" & Rec.DEVICE_Cfg(4); - Rdata(23 downto 20) <= "000" & Rec.DEVICE_Cfg(5); - Rdata(31 downto 24) <= X"CC"; +-- Rdata(27 downto 16) <= X"000"; +-- Rdata(31 downto 28) <= "000" & Rec.DEVICE_Cfg(7); +-- Rdata(23 downto 20) <= "000" & Rec.DEVICE_Cfg(5); +-- Rdata(27 downto 24) <= "000" & Rec.DEVICE_Cfg(6); + Rdata(31 downto 16) <= X"CCCC"; when others => Rdata <= (others => '0'); end case; diff --git a/lib/lpp/lpp_memory/Fifo_Read.vhd b/lib/lpp/lpp_memory/Fifo_Read.vhd --- a/lib/lpp/lpp_memory/Fifo_Read.vhd +++ b/lib/lpp/lpp_memory/Fifo_Read.vhd @@ -32,7 +32,7 @@ generic( port( clk,raz : in std_logic; --! Horloge et reset general du composant flag_RE : in std_logic; --! Flag, Demande la lecture de la mémoire - ReUse : in std_logic; --! Flag, Permet de relire la mémoire du début +-- ReUse : in std_logic; --! Flag, Permet de relire la mémoire du début Waddr : in std_logic_vector(addr_sz-1 downto 0); --! Adresse du registre d'écriture dans la mémoire empty : out std_logic; --! Flag, Mémoire vide Raddr : out std_logic_vector(addr_sz-1 downto 0) --! Adresse du registre de lecture de la mémoire @@ -53,13 +53,14 @@ begin process (clk,raz) begin if(raz='0')then - Rad_int <= 0; - empty <= '1'; + Rad_int <= 0; + empty <= '1'; + flag_reg <= '0'; elsif(clk' event and clk='1')then Wad_int_reg <= Wad_int; Rad_int_reg <= Rad_int; - flag_reg <= flag_RE; + flag_reg <= flag_RE; if(flag_reg ='0' and flag_RE='1')then @@ -70,9 +71,9 @@ begin end if; end if; - if(ReUse='1')then - empty <= '0'; - else +-- if(ReUse='1')then +-- empty <= '0'; +-- else if(Rad_int_reg /= Rad_int)then if(Rad_int=Wad_int)then empty <= '1'; @@ -84,7 +85,7 @@ begin end if; end if; - end if; +-- end if; end process; Wad_int <= to_integer(unsigned(Waddr)); diff --git a/lib/lpp/lpp_memory/Fifo_Write.vhd b/lib/lpp/lpp_memory/Fifo_Write.vhd --- a/lib/lpp/lpp_memory/Fifo_Write.vhd +++ b/lib/lpp/lpp_memory/Fifo_Write.vhd @@ -46,6 +46,7 @@ signal Wad_int : integer range 0 to signal Wad_int_reg : integer range 0 to addr_max_int; signal Rad_int : integer range 0 to addr_max_int; signal Rad_int_reg : integer range 0 to addr_max_int; +signal flag_reg : std_logic; begin process (clk,raz) @@ -53,13 +54,15 @@ begin if(raz='0')then Wad_int <= 0; full <= '0'; + flag_reg <= '0'; elsif(clk' event and clk='1')then Wad_int_reg <= Wad_int; Rad_int_reg <= Rad_int; + flag_reg <= flag_WR; - if(flag_WR='1')then + if(flag_reg ='0' and flag_WR='1')then if(Wad_int=addr_max_int-1)then Wad_int <= 0; else diff --git a/lib/lpp/lpp_memory/Link_Reg.vhd b/lib/lpp/lpp_memory/Link_Reg.vhd deleted file mode 100644 --- a/lib/lpp/lpp_memory/Link_Reg.vhd +++ /dev/null @@ -1,106 +0,0 @@ ------------------------------------------------------------------------------- --- This file is a part of the LPP VHDL IP LIBRARY --- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS --- --- This program is free software; you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation; either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program; if not, write to the Free Software --- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ------------------------------------------------------------------------------- --- Author : Martin Morlot --- Mail : martin.morlot@lpp.polytechnique.fr ------------------------------------------------------------------------------- -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.numeric_std.all; -use work.FIFO_Config.all; - ---! Programme qui va permettre de "pipeliner" la FIFO, donnée disponible en sortie dé son écriture en entrée de la FIFO - -entity Link_Reg is -generic(Data_sz : integer := 16); -port( - clk,raz : in std_logic; --! Horloge et reset general du composant - Data_one : in std_logic_vector(Data_sz-1 downto 0); --! Donnée en entrée de la FIFO, coté écriture - Data_two : in std_logic_vector(Data_sz-1 downto 0); --! Donnée en sortie de la FIFO, coté lecture - ReUse : in std_logic; --! Flag, Permet de relire la mémoire du début - flag_RE : in std_logic; --! Flag, Demande la lecture de la mémoire - flag_WR : in std_logic; --! Flag, Demande l'écriture dans la mémoire - empty : in std_logic; --! Flag, Mémoire vide - Data_out : out std_logic_vector(Data_sz-1 downto 0) --! Donnée en sortie, pipelinée - ); -end Link_Reg; - -architecture ar_Link_Reg of Link_Reg is - -type etat is (e0,e1,e2,e3); -signal ect : etat; - -begin - process (clk,raz) - begin - if(raz='0')then - Data_out <= (others => 'X'); - ect <= e0; - - elsif(clk' event and clk='1')then - case ect is - when e0 => - if(flag_WR='1')then - Data_out <= Data_one; - ect <= e1; - elsif(ReUse='1')then - ect <= e1; - end if; - - when e1 => - if(flag_RE='1')then - Data_out <= Data_two; - ect <= e2; - end if; - - when e2 => - if(empty='1')then - ect <= e3; - else - Data_out <= Data_two; - ect <= e2; - end if; - - when e3 => - Data_out <= Data_two; - ect <= e0; - - end case; - end if; - end process; - -end ar_Link_Reg; - - - - - - - - - - - - - - - - - - - diff --git a/lib/lpp/lpp_memory/Pipeline.vhd b/lib/lpp/lpp_memory/Pipeline.vhd new file mode 100644 --- /dev/null +++ b/lib/lpp/lpp_memory/Pipeline.vhd @@ -0,0 +1,108 @@ +------------------------------------------------------------------------------ +-- This file is a part of the LPP VHDL IP LIBRARY +-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 3 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +------------------------------------------------------------------------------ +-- Author : Martin Morlot +-- Mail : martin.morlot@lpp.polytechnique.fr +------------------------------------------------------------------------------ +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +--! Programme qui va permettre de "pipeliner" la FIFO, donnée disponible en sortie dé son écriture en entrée de la FIFO + +entity Pipeline is +generic(Data_sz : integer := 16); +port( + clk,raz : in std_logic; --! Horloge et reset general du composant + Data_one : in std_logic_vector(Data_sz-1 downto 0); --! Donnée en entrée de la FIFO, coté écriture + Data_two : in std_logic_vector(Data_sz-1 downto 0); --! Donnée en sortie de la FIFO, coté lecture +-- ReUse : in std_logic; --! Flag, Permet de relire la mémoire du début + flag_RE : in std_logic; --! Flag, Demande la lecture de la mémoire + flag_WR : in std_logic; --! Flag, Demande l'écriture dans la mémoire + empty : in std_logic; --! Flag, Mémoire vide + Data_out : out std_logic_vector(Data_sz-1 downto 0) --! Donnée en sortie, pipelinée + ); +end Pipeline; + +architecture ar_Pipeline of Pipeline is + +type etat is (e0,e1,e2,eX); +signal ect : etat; + +begin + process (clk,raz) + begin + if(raz='0')then + Data_out <= (others => 'X'); + ect <= e0; + + elsif(clk' event and clk='1')then + case ect is + when e0 => + if(flag_WR='1')then + Data_out <= Data_one; + ect <= e1; + -- elsif(ReUse='1')then + -- ect <= e1; + end if; + + when e1 => + if(flag_RE='1')then + --Data_out <= Data_two; + ect <= eX; + end if; + + when eX => + --Data_out <= Data_two; + ect <= e2; + + when e2 => + Data_out <= Data_two; + if(empty='1')then + ect <= e0; + else + --Data_out <= Data_two; + ect <= e2; + end if; + + + + end case; + end if; + end process; + +end ar_Pipeline; + + + + + + + + + + + + + + + + + + + diff --git a/lib/lpp/lpp_memory/Top_FIFO.vhd b/lib/lpp/lpp_memory/Top_FIFO.vhd --- a/lib/lpp/lpp_memory/Top_FIFO.vhd +++ b/lib/lpp/lpp_memory/Top_FIFO.vhd @@ -39,8 +39,9 @@ entity Top_FIFO is clk,raz : in std_logic; --! Horloge et reset general du composant flag_RE : in std_logic; --! Flag, Demande la lecture de la mémoire flag_WR : in std_logic; --! Flag, Demande l'écriture dans la mémoire - ReUse : in std_logic; --! Flag, Permet de relire la mémoire du début - Lock : in std_logic; --! Permet de bloquer l'écriture dans la mémoire +-- ReUse : in std_logic; --! Flag, Permet de relire la mémoire en boucle sans nouvelle données +-- Lock : in std_logic; --! Permet de bloquer l'écriture dans la mémoire +-- RstMem : in std_logic; --! Flag, Reset "manuel" spécifique au composant Data_in : in std_logic_vector(Data_sz-1 downto 0); --! Data en entrée du composant Addr_RE : out std_logic_vector(addr_sz-1 downto 0); --! Adresse d'écriture Addr_WR : out std_logic_vector(addr_sz-1 downto 0); --! Adresse de lecture @@ -73,12 +74,18 @@ signal Waddr : std_logic_vector(addr --signal Data_int : std_logic_vector(Data_sz-1 downto 0); signal s_empty : std_logic; signal s_full : std_logic; -signal s_full2 : std_logic; +--signal s_full2 : std_logic; signal s_flag_RE : std_logic; signal s_flag_WR : std_logic; +signal Flag_WR_reg : std_logic; +--signal rst : std_logic; +--signal RstMem_inv : std_logic; begin - + +--RstMem_inv <= not RstMem; +--rst <= raz and RstMem_inv; + WR : Fifo_Write generic map(Addr_sz,addr_max_int) port map(clk,raz,s_flag_WR,Raddr,s_full,Waddr); @@ -89,25 +96,32 @@ begin port map(clk,s_flag_RE,Raddr,Data_out,clk,s_flag_WR,Waddr,Data_in); --- link : Link_Reg +-- Pipe : Pipeline -- generic map(Data_sz) --- port map(clk,raz,Data_in,Data_int,ReUse,s_flag_RE,s_flag_WR,s_empty,Data_out); +-- port map(clk,raz,Data_in,Data_int,s_flag_RE,s_flag_WR,s_empty,Data_out); RE : Fifo_Read generic map(Addr_sz,addr_max_int) - port map(clk,raz,s_flag_RE,ReUse,Waddr,s_empty,Raddr); + port map(clk,raz,s_flag_RE,Waddr,s_empty,Raddr); process(clk,raz) begin if(raz='0')then s_flag_RE <= '0'; s_flag_WR <= '0'; - s_full2 <= s_full; +-- s_full2 <= s_full; + Flag_WR_reg <= '0'; elsif(clk'event and clk='1')then - if(s_full2='0')then - s_flag_WR <= Flag_WR; + Flag_WR_reg <= Flag_WR; + + if(s_full='0')then --2 + if(s_empty='1')then + s_flag_WR <= Flag_WR_reg; + else + s_flag_WR <= Flag_WR; + end if; else s_flag_WR <= '0'; end if; @@ -118,16 +132,16 @@ begin s_flag_RE <= '0'; end if; - if(Lock='1')then - s_full2 <= '1'; - else - s_full2 <= s_full; - end if; +-- if(Lock='1')then +-- s_full2 <= '1'; +-- else +-- s_full2 <= s_full; +-- end if; end if; end process; -full <= s_full2; +full <= s_full; --2 empty <= s_empty; Addr_RE <= Raddr; Addr_WR <= Waddr; diff --git a/lib/lpp/lpp_memory/lpp_memory.vhd b/lib/lpp/lpp_memory/lpp_memory.vhd --- a/lib/lpp/lpp_memory/lpp_memory.vhd +++ b/lib/lpp/lpp_memory/lpp_memory.vhd @@ -76,8 +76,9 @@ component ApbDriver is WriteEnable : out std_logic; FlagEmpty : in std_logic; FlagFull : in std_logic; - ReUse : out std_logic; - Lock : out std_logic; +-- ReUse : out std_logic; +-- Lock : out std_logic; +-- RstMem : out std_logic; DataIn : out std_logic_vector(Data_sz-1 downto 0); DataOut : in std_logic_vector(Data_sz-1 downto 0); AddrIn : in std_logic_vector(Addr_sz-1 downto 0); @@ -98,8 +99,9 @@ component Top_FIFO is clk,raz : in std_logic; flag_RE : in std_logic; flag_WR : in std_logic; - ReUse : in std_logic; - Lock : in std_logic; +-- ReUse : in std_logic; +-- Lock : in std_logic; +-- RstMem : in std_logic; Data_in : in std_logic_vector(Data_sz-1 downto 0); Addr_RE : out std_logic_vector(addr_sz-1 downto 0); Addr_WR : out std_logic_vector(addr_sz-1 downto 0); @@ -118,7 +120,7 @@ component Fifo_Read is clk : in std_logic; raz : in std_logic; flag_RE : in std_logic; - ReUse : in std_logic; +-- ReUse : in std_logic; Waddr : in std_logic_vector(addr_sz-1 downto 0); empty : out std_logic; Raddr : out std_logic_vector(addr_sz-1 downto 0) @@ -141,13 +143,13 @@ component Fifo_Write is end component; -component Link_Reg is +component Pipeline is generic(Data_sz : integer := 16); port( clk,raz : in std_logic; Data_one : in std_logic_vector(Data_sz-1 downto 0); Data_two : in std_logic_vector(Data_sz-1 downto 0); - ReUse : in std_logic; +-- ReUse : in std_logic; flag_RE : in std_logic; flag_WR : in std_logic; empty : in std_logic;