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------------------------------------------------------------------------------
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-- This file is a part of the LPP VHDL IP LIBRARY
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-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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------------------------------------------------------------------------------
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-- Author : Martin Morlot
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-- Mail : martin.morlot@lpp.polytechnique.fr
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------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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library grlib;
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use grlib.amba.all;
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use std.textio.all;
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library lpp;
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use lpp.lpp_amba.all;
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--! Package contenant tous les programmes qui forment le composant int�gr� dans le l�on
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package lpp_memory is
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--===========================================================|
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--=================== FIFO Compl�te =========================|
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--===========================================================|
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component APB_FIFO is
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generic (
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pindex : integer := 0;
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paddr : integer := 0;
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pmask : integer := 16#fff#;
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pirq : integer := 0;
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abits : integer := 8;
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Data_sz : integer := 16;
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Addr_sz : integer := 8;
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addr_max_int : integer := 256);
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port (
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clk : in std_logic;
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rst : in std_logic;
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apbi : in apb_slv_in_type;
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Full : out std_logic;
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Empty : out std_logic;
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WR : out std_logic;
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RE : out std_logic;
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apbo : out apb_slv_out_type
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);
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end component;
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component ApbDriver is
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generic (
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pindex : integer := 0;
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paddr : integer := 0;
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pmask : integer := 16#fff#;
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pirq : integer := 0;
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abits : integer := 8;
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LPP_DEVICE : integer;
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Data_sz : integer := 16;
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Addr_sz : integer := 8;
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addr_max_int : integer := 256);
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port (
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clk : in std_logic;
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rst : in std_logic;
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ReadEnable : out std_logic;
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WriteEnable : out std_logic;
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FlagEmpty : in std_logic;
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FlagFull : in std_logic;
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ReUse : out std_logic;
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Lock : out std_logic;
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DataIn : out std_logic_vector(Data_sz-1 downto 0);
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DataOut : in std_logic_vector(Data_sz-1 downto 0);
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AddrIn : in std_logic_vector(Addr_sz-1 downto 0);
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AddrOut : in std_logic_vector(Addr_sz-1 downto 0);
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apbi : in apb_slv_in_type;
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apbo : out apb_slv_out_type
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);
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end component;
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component Top_FIFO is
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generic(
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Data_sz : integer := 16;
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Addr_sz : integer := 8;
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addr_max_int : integer := 256
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);
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port(
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clk,raz : in std_logic;
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flag_RE : in std_logic;
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flag_WR : in std_logic;
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ReUse : in std_logic;
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Lock : in std_logic;
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Data_in : in std_logic_vector(Data_sz-1 downto 0);
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Addr_RE : out std_logic_vector(addr_sz-1 downto 0);
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Addr_WR : out std_logic_vector(addr_sz-1 downto 0);
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full : out std_logic;
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empty : out std_logic;
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Data_out : out std_logic_vector(Data_sz-1 downto 0)
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);
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end component;
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component Fifo_Read is
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generic(
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Addr_sz : integer := 8;
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addr_max_int : integer := 256);
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port(
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clk : in std_logic;
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raz : in std_logic;
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flag_RE : in std_logic;
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ReUse : in std_logic;
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Waddr : in std_logic_vector(addr_sz-1 downto 0);
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empty : out std_logic;
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Raddr : out std_logic_vector(addr_sz-1 downto 0)
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);
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end component;
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component Fifo_Write is
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generic(
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Addr_sz : integer := 8;
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addr_max_int : integer := 256);
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port(
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clk : in std_logic;
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raz : in std_logic;
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flag_WR : in std_logic;
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Raddr : in std_logic_vector(addr_sz-1 downto 0);
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full : out std_logic;
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Waddr : out std_logic_vector(addr_sz-1 downto 0)
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);
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end component;
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component Link_Reg is
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generic(Data_sz : integer := 16);
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port(
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clk,raz : in std_logic;
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Data_one : in std_logic_vector(Data_sz-1 downto 0);
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Data_two : in std_logic_vector(Data_sz-1 downto 0);
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ReUse : in std_logic;
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flag_RE : in std_logic;
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flag_WR : in std_logic;
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empty : in std_logic;
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Data_out : out std_logic_vector(Data_sz-1 downto 0)
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);
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end component;
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--===========================================================|
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--================= Demi FIFO Ecriture ======================|
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--===========================================================|
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component APB_FifoWrite is
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generic (
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pindex : integer := 0;
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paddr : integer := 0;
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pmask : integer := 16#fff#;
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pirq : integer := 0;
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abits : integer := 8;
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Data_sz : integer := 16;
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Addr_sz : integer := 8;
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addr_max_int : integer := 256);
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port (
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clk : in std_logic;
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rst : in std_logic;
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apbi : in apb_slv_in_type;
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ReadEnable : in std_logic;
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Empty : out std_logic;
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Full : out std_logic;
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DATA : out std_logic_vector(Data_sz-1 downto 0);
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apbo : out apb_slv_out_type
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);
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end component;
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--component Top_FifoWrite is
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-- generic(
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-- Data_sz : integer := 16;
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-- Addr_sz : integer := 8;
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-- addr_max_int : integer := 256);
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-- port(
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-- clk : in std_logic;
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-- raz : in std_logic;
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-- flag_RE : in std_logic;
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-- flag_WR : in std_logic;
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-- Data_in : in std_logic_vector(Data_sz-1 downto 0);
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-- Raddr : in std_logic_vector(addr_sz-1 downto 0);
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-- full : out std_logic;
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-- empty : out std_logic;
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-- Waddr : out std_logic_vector(addr_sz-1 downto 0);
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-- Data_out : out std_logic_vector(Data_sz-1 downto 0)
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-- );
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--end component;
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--===========================================================|
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--================== Demi FIFO Lecture ======================|
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--===========================================================|
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component APB_FifoRead is
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generic (
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pindex : integer := 0;
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paddr : integer := 0;
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pmask : integer := 16#fff#;
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pirq : integer := 0;
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abits : integer := 8;
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Data_sz : integer := 16;
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Addr_sz : integer := 8;
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addr_max_int : integer := 256);
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port (
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clk : in std_logic;
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rst : in std_logic;
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apbi : in apb_slv_in_type;
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WriteEnable : in std_logic;
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Full : out std_logic;
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Empty : out std_logic;
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DATA : in std_logic_vector(Data_sz-1 downto 0);
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apbo : out apb_slv_out_type
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);
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end component;
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--component Top_FifoRead is
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-- generic(
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-- Data_sz : integer := 16;
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-- Addr_sz : integer := 8;
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-- addr_max_int : integer := 256);
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-- port(
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-- clk : in std_logic;
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-- raz : in std_logic;
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-- flag_RE : in std_logic;
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-- flag_WR : in std_logic;
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-- Data_in : in std_logic_vector(Data_sz-1 downto 0);
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-- Waddr : in std_logic_vector(addr_sz-1 downto 0);
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-- full : out std_logic;
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-- empty : out std_logic;
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-- Raddr : out std_logic_vector(addr_sz-1 downto 0);
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-- Data_out : out std_logic_vector(Data_sz-1 downto 0)
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-- );
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--end component;
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end;
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