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1 | 1 | ------------------------------------------------------------------------------ |
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2 | 2 | -- This file is a part of the LPP VHDL IP LIBRARY |
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3 | 3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS |
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4 | 4 | -- |
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5 | 5 | -- This program is free software; you can redistribute it and/or modify |
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6 | 6 | -- it under the terms of the GNU General Public License as published by |
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7 | 7 | -- the Free Software Foundation; either version 3 of the License, or |
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8 | 8 | -- (at your option) any later version. |
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9 | 9 | -- |
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10 | 10 | -- This program is distributed in the hope that it will be useful, |
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11 | 11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of |
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12 | 12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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13 | 13 | -- GNU General Public License for more details. |
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14 | 14 | -- |
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15 | 15 | -- You should have received a copy of the GNU General Public License |
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16 | 16 | -- along with this program; if not, write to the Free Software |
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17 | 17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
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18 | 18 | ------------------------------------------------------------------------------- |
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19 | 19 | -- Author : Jean-christophe Pellion |
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20 | 20 | -- Mail : jean-christophe.pellion@lpp.polytechnique.fr |
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21 | 21 | ------------------------------------------------------------------------------- |
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22 | 22 | LIBRARY IEEE; |
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23 | 23 | USE IEEE.numeric_std.ALL; |
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24 | 24 | USE IEEE.std_logic_1164.ALL; |
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25 | 25 | LIBRARY grlib; |
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26 | 26 | USE grlib.amba.ALL; |
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27 | 27 | USE grlib.stdlib.ALL; |
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28 | 28 | LIBRARY techmap; |
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29 | 29 | USE techmap.gencomp.ALL; |
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30 | 30 | LIBRARY gaisler; |
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31 | 31 | USE gaisler.memctrl.ALL; |
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32 | 32 | USE gaisler.leon3.ALL; |
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33 | 33 | USE gaisler.uart.ALL; |
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34 | 34 | USE gaisler.misc.ALL; |
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35 | 35 | USE gaisler.spacewire.ALL; |
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36 | 36 | LIBRARY esa; |
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37 | 37 | USE esa.memoryctrl.ALL; |
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38 | 38 | LIBRARY lpp; |
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39 | 39 | USE lpp.lpp_memory.ALL; |
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40 | 40 | USE lpp.lpp_ad_conv.ALL; |
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41 | 41 | USE lpp.lpp_lfr_pkg.ALL; -- contains lpp_lfr, not in the 206 rev of the VHD_Lib |
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42 | 42 | USE lpp.lpp_top_lfr_pkg.ALL; -- contains top_wf_picker |
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43 | 43 | USE lpp.iir_filter.ALL; |
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44 | 44 | USE lpp.general_purpose.ALL; |
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45 | 45 | USE lpp.lpp_lfr_time_management.ALL; |
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46 | 46 | USE lpp.lpp_leon3_soc_pkg.ALL; |
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47 | 47 | |
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48 | 48 | ENTITY MINI_LFR_top IS |
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49 | 49 | |
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50 | 50 | PORT ( |
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51 | 51 | clk_50 : IN STD_LOGIC; |
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52 | 52 | clk_49 : IN STD_LOGIC; |
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53 | 53 | reset : IN STD_LOGIC; |
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54 | 54 | --BPs |
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55 | 55 | BP0 : IN STD_LOGIC; |
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56 | 56 | BP1 : IN STD_LOGIC; |
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57 | 57 | --LEDs |
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58 | 58 | LED0 : OUT STD_LOGIC; |
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59 | 59 | LED1 : OUT STD_LOGIC; |
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60 | 60 | LED2 : OUT STD_LOGIC; |
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61 | 61 | --UARTs |
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62 | 62 | TXD1 : IN STD_LOGIC; |
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63 | 63 | RXD1 : OUT STD_LOGIC; |
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64 | 64 | nCTS1 : OUT STD_LOGIC; |
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65 | 65 | nRTS1 : IN STD_LOGIC; |
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66 | 66 | |
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67 | 67 | TXD2 : IN STD_LOGIC; |
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68 | 68 | RXD2 : OUT STD_LOGIC; |
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69 | 69 | nCTS2 : OUT STD_LOGIC; |
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70 | 70 | nDTR2 : IN STD_LOGIC; |
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71 | 71 | nRTS2 : IN STD_LOGIC; |
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72 | 72 | nDCD2 : OUT STD_LOGIC; |
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73 | 73 | |
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74 | 74 | --EXT CONNECTOR |
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75 | 75 | IO0 : INOUT STD_LOGIC; |
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76 | 76 | IO1 : INOUT STD_LOGIC; |
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77 | 77 | IO2 : INOUT STD_LOGIC; |
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78 | 78 | IO3 : INOUT STD_LOGIC; |
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79 | 79 | IO4 : INOUT STD_LOGIC; |
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80 | 80 | IO5 : INOUT STD_LOGIC; |
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81 | 81 | IO6 : INOUT STD_LOGIC; |
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82 | 82 | IO7 : INOUT STD_LOGIC; |
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83 | 83 | IO8 : INOUT STD_LOGIC; |
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84 | 84 | IO9 : INOUT STD_LOGIC; |
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85 | 85 | IO10 : INOUT STD_LOGIC; |
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86 | 86 | IO11 : INOUT STD_LOGIC; |
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87 | 87 | |
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88 | 88 | --SPACE WIRE |
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89 | 89 | SPW_EN : OUT STD_LOGIC; -- 0 => off |
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90 | 90 | SPW_NOM_DIN : IN STD_LOGIC; -- NOMINAL LINK |
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91 | 91 | SPW_NOM_SIN : IN STD_LOGIC; |
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92 | 92 | SPW_NOM_DOUT : OUT STD_LOGIC; |
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93 | 93 | SPW_NOM_SOUT : OUT STD_LOGIC; |
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94 | 94 | SPW_RED_DIN : IN STD_LOGIC; -- REDUNDANT LINK |
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95 | 95 | SPW_RED_SIN : IN STD_LOGIC; |
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96 | 96 | SPW_RED_DOUT : OUT STD_LOGIC; |
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97 | 97 | SPW_RED_SOUT : OUT STD_LOGIC; |
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98 | 98 | -- MINI LFR ADC INPUTS |
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99 | 99 | ADC_nCS : OUT STD_LOGIC; |
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100 | 100 | ADC_CLK : OUT STD_LOGIC; |
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101 | 101 | ADC_SDO : IN STD_LOGIC_VECTOR(7 DOWNTO 0); |
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102 | 102 | |
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103 | 103 | -- SRAM |
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104 | 104 | SRAM_nWE : OUT STD_LOGIC; |
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105 | 105 | SRAM_CE : OUT STD_LOGIC; |
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106 | 106 | SRAM_nOE : OUT STD_LOGIC; |
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107 | 107 | SRAM_nBE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); |
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108 | 108 | SRAM_A : OUT STD_LOGIC_VECTOR(19 DOWNTO 0); |
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109 | 109 | SRAM_DQ : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0) |
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110 | 110 | ); |
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111 | 111 | |
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112 | 112 | END MINI_LFR_top; |
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113 | 113 | |
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114 | 114 | |
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115 | 115 | ARCHITECTURE beh OF MINI_LFR_top IS |
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116 | 116 | SIGNAL clk_50_s : STD_LOGIC := '0'; |
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117 | 117 | SIGNAL clk_25 : STD_LOGIC := '0'; |
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118 | 118 | SIGNAL clk_24 : STD_LOGIC := '0'; |
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119 | 119 | ----------------------------------------------------------------------------- |
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120 | 120 | SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0); |
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121 | 121 | SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0); |
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122 | 122 | -- |
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123 | 123 | SIGNAL errorn : STD_LOGIC; |
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124 | 124 | -- UART AHB --------------------------------------------------------------- |
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125 | 125 | SIGNAL ahbrxd : STD_ULOGIC; -- DSU rx data |
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126 | 126 | SIGNAL ahbtxd : STD_ULOGIC; -- DSU tx data |
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127 | 127 | |
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128 | 128 | -- UART APB --------------------------------------------------------------- |
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129 | 129 | SIGNAL urxd1 : STD_ULOGIC; -- UART1 rx data |
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130 | 130 | SIGNAL utxd1 : STD_ULOGIC; -- UART1 tx data |
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131 | 131 | -- |
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132 | 132 | SIGNAL I00_s : STD_LOGIC; |
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133 | 133 | |
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134 | 134 | -- CONSTANTS |
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135 | 135 | CONSTANT CFG_PADTECH : INTEGER := inferred; |
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136 | 136 | -- |
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137 | 137 | CONSTANT NB_APB_SLAVE : INTEGER := 11; -- 3 = grspw + waveform picker + time manager, 11 allows pindex = f |
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138 | 138 | CONSTANT NB_AHB_SLAVE : INTEGER := 1; |
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139 | 139 | CONSTANT NB_AHB_MASTER : INTEGER := 2; -- 2 = grspw + waveform picker |
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140 | 140 | |
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141 | 141 | SIGNAL apbi_ext : apb_slv_in_type; |
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142 | 142 | SIGNAL apbo_ext : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5) := (OTHERS => apb_none); |
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143 | 143 | SIGNAL ahbi_s_ext : ahb_slv_in_type; |
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144 | 144 | SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3) := (OTHERS => ahbs_none); |
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145 | 145 | SIGNAL ahbi_m_ext : AHB_Mst_In_Type; |
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146 | 146 | SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1) := (OTHERS => ahbm_none); |
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147 | 147 | |
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148 | 148 | -- Spacewire signals |
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149 | 149 | SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0); |
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150 | 150 | SIGNAL stmp : STD_LOGIC_VECTOR(1 DOWNTO 0); |
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151 | 151 | SIGNAL spw_rxclk : STD_LOGIC_VECTOR(1 DOWNTO 0); |
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152 | 152 | SIGNAL spw_rxtxclk : STD_ULOGIC; |
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153 | 153 | SIGNAL spw_rxclkn : STD_ULOGIC; |
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154 | 154 | SIGNAL spw_clk : STD_LOGIC; |
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155 | 155 | SIGNAL swni : grspw_in_type; |
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156 | 156 | SIGNAL swno : grspw_out_type; |
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157 | 157 | -- SIGNAL clkmn : STD_ULOGIC; |
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158 | 158 | -- SIGNAL txclk : STD_ULOGIC; |
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159 | 159 | |
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160 | 160 | --GPIO |
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161 | 161 | SIGNAL gpioi : gpio_in_type; |
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162 | 162 | SIGNAL gpioo : gpio_out_type; |
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163 | 163 | |
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164 | 164 | -- AD Converter ADS7886 |
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165 | 165 | SIGNAL sample : Samples14v(7 DOWNTO 0); |
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166 | 166 | SIGNAL sample_val : STD_LOGIC; |
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167 | 167 | SIGNAL ADC_nCS_sig : STD_LOGIC; |
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168 | 168 | SIGNAL ADC_CLK_sig : STD_LOGIC; |
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169 | 169 | SIGNAL ADC_SDO_sig : STD_LOGIC_VECTOR(7 DOWNTO 0); |
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170 | 170 | |
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171 | 171 | SIGNAL bias_fail_sw_sig : STD_LOGIC; |
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172 | 172 | |
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173 | 173 | SIGNAL observation_reg : STD_LOGIC_VECTOR(31 DOWNTO 0); |
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174 | 174 | ----------------------------------------------------------------------------- |
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175 | 175 | |
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176 | 176 | BEGIN -- beh |
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177 | 177 | |
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178 | 178 | ----------------------------------------------------------------------------- |
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179 | 179 | -- CLK |
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180 | 180 | ----------------------------------------------------------------------------- |
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181 | 181 | |
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182 | 182 | PROCESS(clk_50) |
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183 | 183 | BEGIN |
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184 | 184 | IF clk_50'EVENT AND clk_50 = '1' THEN |
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185 | 185 | clk_50_s <= NOT clk_50_s; |
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186 | 186 | END IF; |
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187 | 187 | END PROCESS; |
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188 | 188 | |
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189 | 189 | PROCESS(clk_50_s) |
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190 | 190 | BEGIN |
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191 | 191 | IF clk_50_s'EVENT AND clk_50_s = '1' THEN |
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192 | 192 | clk_25 <= NOT clk_25; |
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193 | 193 | END IF; |
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194 | 194 | END PROCESS; |
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195 | 195 | |
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196 | 196 | PROCESS(clk_49) |
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197 | 197 | BEGIN |
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198 | 198 | IF clk_49'EVENT AND clk_49 = '1' THEN |
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199 | 199 | clk_24 <= NOT clk_24; |
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200 | 200 | END IF; |
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201 | 201 | END PROCESS; |
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202 | 202 | |
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203 | 203 | ----------------------------------------------------------------------------- |
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204 | 204 | |
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205 | 205 | PROCESS (clk_25, reset) |
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206 | 206 | BEGIN -- PROCESS |
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207 | 207 | IF reset = '0' THEN -- asynchronous reset (active low) |
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208 | 208 | LED0 <= '0'; |
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209 | 209 | LED1 <= '0'; |
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210 | 210 | LED2 <= '0'; |
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211 | 211 | --IO1 <= '0'; |
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212 | 212 | --IO2 <= '1'; |
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213 | 213 | --IO3 <= '0'; |
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214 | 214 | --IO4 <= '0'; |
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215 | 215 | --IO5 <= '0'; |
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216 | 216 | --IO6 <= '0'; |
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217 | 217 | --IO7 <= '0'; |
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218 | 218 | --IO8 <= '0'; |
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219 | 219 | --IO9 <= '0'; |
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220 | 220 | --IO10 <= '0'; |
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221 | 221 | --IO11 <= '0'; |
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222 | 222 | ELSIF clk_25'EVENT AND clk_25 = '1' THEN -- rising clock edge |
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223 | 223 | LED0 <= '0'; |
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224 | 224 | LED1 <= '1'; |
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225 | 225 | LED2 <= BP0 OR BP1 OR nDTR2 OR nRTS2 OR nRTS1; |
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226 | 226 | --IO1 <= '1'; |
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227 | 227 | --IO2 <= SPW_NOM_DIN OR SPW_NOM_SIN OR SPW_RED_DIN OR SPW_RED_SIN; |
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228 | 228 | --IO3 <= ADC_SDO(0); |
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229 | 229 | --IO4 <= ADC_SDO(1); |
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230 | 230 | --IO5 <= ADC_SDO(2); |
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231 | 231 | --IO6 <= ADC_SDO(3); |
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232 | 232 | --IO7 <= ADC_SDO(4); |
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233 | 233 | --IO8 <= ADC_SDO(5); |
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234 | 234 | --IO9 <= ADC_SDO(6); |
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235 | 235 | --IO10 <= ADC_SDO(7); |
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236 | 236 | --IO11 <= BP1 OR nDTR2 OR nRTS2 OR nRTS1; |
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237 | 237 | END IF; |
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238 | 238 | END PROCESS; |
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239 | 239 | |
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240 | 240 | PROCESS (clk_24, reset) |
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241 | 241 | BEGIN -- PROCESS |
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242 | 242 | IF reset = '0' THEN -- asynchronous reset (active low) |
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243 | 243 | I00_s <= '0'; |
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244 | 244 | ELSIF clk_24'EVENT AND clk_24 = '1' THEN -- rising clock edge |
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245 | 245 | I00_s <= NOT I00_s ; |
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246 | 246 | END IF; |
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247 | 247 | END PROCESS; |
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248 | 248 | -- IO0 <= I00_s; |
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249 | 249 | |
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250 | 250 | --UARTs |
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251 | 251 | nCTS1 <= '1'; |
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252 | 252 | nCTS2 <= '1'; |
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253 | 253 | nDCD2 <= '1'; |
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254 | 254 | |
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255 | 255 | --EXT CONNECTOR |
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256 | 256 | |
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257 | 257 | --SPACE WIRE |
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258 | 258 | |
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259 | 259 | leon3_soc_1 : leon3_soc |
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260 | 260 | GENERIC MAP ( |
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261 | 261 | fabtech => apa3e, |
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262 | 262 | memtech => apa3e, |
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263 | 263 | padtech => inferred, |
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264 | 264 | clktech => inferred, |
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265 | 265 | disas => 0, |
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266 | 266 | dbguart => 0, |
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267 | 267 | pclow => 2, |
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268 | 268 | clk_freq => 25000, |
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269 | 269 | NB_CPU => 1, |
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270 | 270 | ENABLE_FPU => 1, |
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271 | 271 | FPU_NETLIST => 0, |
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272 | 272 | ENABLE_DSU => 1, |
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273 | 273 | ENABLE_AHB_UART => 1, |
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274 | 274 | ENABLE_APB_UART => 1, |
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275 | 275 | ENABLE_IRQMP => 1, |
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276 | 276 | ENABLE_GPT => 1, |
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277 | 277 | NB_AHB_MASTER => NB_AHB_MASTER, |
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278 | 278 | NB_AHB_SLAVE => NB_AHB_SLAVE, |
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279 | 279 | NB_APB_SLAVE => NB_APB_SLAVE) |
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280 | 280 | PORT MAP ( |
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281 | 281 | clk => clk_25, |
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282 | 282 | reset => reset, |
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283 | 283 | errorn => errorn, |
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284 | 284 | ahbrxd => TXD1, |
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285 | 285 | ahbtxd => RXD1, |
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286 | 286 | urxd1 => TXD2, |
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287 | 287 | utxd1 => RXD2, |
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288 | 288 | address => SRAM_A, |
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289 | 289 | data => SRAM_DQ, |
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290 | 290 | nSRAM_BE0 => SRAM_nBE(0), |
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291 | 291 | nSRAM_BE1 => SRAM_nBE(1), |
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292 | 292 | nSRAM_BE2 => SRAM_nBE(2), |
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293 | 293 | nSRAM_BE3 => SRAM_nBE(3), |
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294 | 294 | nSRAM_WE => SRAM_nWE, |
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295 | 295 | nSRAM_CE => SRAM_CE, |
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296 | 296 | nSRAM_OE => SRAM_nOE, |
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297 | 297 | |
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298 | 298 | apbi_ext => apbi_ext, |
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299 | 299 | apbo_ext => apbo_ext, |
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300 | 300 | ahbi_s_ext => ahbi_s_ext, |
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301 | 301 | ahbo_s_ext => ahbo_s_ext, |
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302 | 302 | ahbi_m_ext => ahbi_m_ext, |
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303 | 303 | ahbo_m_ext => ahbo_m_ext); |
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304 | 304 | |
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305 | 305 | ------------------------------------------------------------------------------- |
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306 | 306 | -- APB_LFR_TIME_MANAGEMENT ---------------------------------------------------- |
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307 | 307 | ------------------------------------------------------------------------------- |
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308 | 308 | apb_lfr_time_management_1 : apb_lfr_time_management |
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309 | 309 | GENERIC MAP ( |
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310 | 310 | pindex => 6, |
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311 | 311 | paddr => 6, |
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312 | 312 | pmask => 16#fff#, |
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313 | 313 | pirq => 12, |
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314 | 314 | nb_wait_pediod => 375) -- (49.152/2) /2^16 = 375 |
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315 | 315 | PORT MAP ( |
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316 | 316 | clk25MHz => clk_25, |
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317 | 317 | clk49_152MHz => clk_24, -- 49.152MHz/2 |
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318 | 318 | resetn => reset, |
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319 | 319 | grspw_tick => swno.tickout, |
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320 | 320 | apbi => apbi_ext, |
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321 | 321 | apbo => apbo_ext(6), |
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322 | 322 | coarse_time => coarse_time, |
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323 | 323 | fine_time => fine_time); |
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324 | 324 | |
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325 | 325 | ----------------------------------------------------------------------- |
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326 | 326 | --- SpaceWire -------------------------------------------------------- |
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327 | 327 | ----------------------------------------------------------------------- |
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328 | 328 | |
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329 | 329 | SPW_EN <= '1'; |
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330 | 330 | |
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331 | 331 | spw_clk <= clk_50_s; |
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332 | 332 | spw_rxtxclk <= spw_clk; |
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333 | 333 | spw_rxclkn <= NOT spw_rxtxclk; |
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334 | 334 | |
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335 | 335 | -- PADS for SPW1 |
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336 | 336 | spw1_rxd_pad : inpad GENERIC MAP (tech => inferred) |
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337 | 337 | PORT MAP (SPW_NOM_DIN, dtmp(0)); |
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338 | 338 | spw1_rxs_pad : inpad GENERIC MAP (tech => inferred) |
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339 | 339 | PORT MAP (SPW_NOM_SIN, stmp(0)); |
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340 | 340 | spw1_txd_pad : outpad GENERIC MAP (tech => inferred) |
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341 | 341 | PORT MAP (SPW_NOM_DOUT, swno.d(0)); |
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342 | 342 | spw1_txs_pad : outpad GENERIC MAP (tech => inferred) |
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343 | 343 | PORT MAP (SPW_NOM_SOUT, swno.s(0)); |
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344 | 344 | -- PADS FOR SPW2 |
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345 | 345 | spw2_rxd_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\ |
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346 | 346 | PORT MAP (SPW_RED_SIN, dtmp(1)); |
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347 | 347 | spw2_rxs_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\ |
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348 | 348 | PORT MAP (SPW_RED_DIN, stmp(1)); |
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349 | 349 | spw2_txd_pad : outpad GENERIC MAP (tech => inferred) |
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350 | 350 | PORT MAP (SPW_RED_DOUT, swno.d(1)); |
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351 | 351 | spw2_txs_pad : outpad GENERIC MAP (tech => inferred) |
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352 | 352 | PORT MAP (SPW_RED_SOUT, swno.s(1)); |
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353 | 353 | |
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354 | 354 | -- GRSPW PHY |
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355 | 355 | --spw1_input: if CFG_SPW_GRSPW = 1 generate |
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356 | 356 | spw_inputloop : FOR j IN 0 TO 1 GENERATE |
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357 | 357 | spw_phy0 : grspw_phy |
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358 | 358 | GENERIC MAP( |
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359 | 359 | tech => apa3e, |
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360 | 360 | rxclkbuftype => 1, |
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361 | 361 | scantest => 0) |
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362 | 362 | PORT MAP( |
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363 | 363 | rxrst => swno.rxrst, |
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364 | 364 | di => dtmp(j), |
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365 | 365 | si => stmp(j), |
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366 | 366 | rxclko => spw_rxclk(j), |
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367 | 367 | do => swni.d(j), |
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368 | 368 | ndo => swni.nd(j*5+4 DOWNTO j*5), |
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369 | 369 | dconnect => swni.dconnect(j*2+1 DOWNTO j*2)); |
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370 | 370 | END GENERATE spw_inputloop; |
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371 | 371 | |
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372 | 372 | -- SPW core |
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373 | 373 | sw0 : grspwm GENERIC MAP( |
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374 | 374 | tech => apa3e, |
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375 | 375 | hindex => 1, |
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376 | 376 | pindex => 5, |
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377 | 377 | paddr => 5, |
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378 | 378 | pirq => 11, |
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379 | 379 | sysfreq => 25000, -- CPU_FREQ |
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380 | 380 | rmap => 1, |
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381 | 381 | rmapcrc => 1, |
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382 | 382 | fifosize1 => 16, |
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383 | 383 | fifosize2 => 16, |
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384 | 384 | rxclkbuftype => 1, |
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385 | 385 | rxunaligned => 0, |
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386 | 386 | rmapbufs => 4, |
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387 | 387 | ft => 0, |
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388 | 388 | netlist => 0, |
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389 | 389 | ports => 2, |
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390 | 390 | --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1 |
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391 | 391 | memtech => apa3e, |
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392 | 392 | destkey => 2, |
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393 | 393 | spwcore => 1 |
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394 | 394 | --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1 |
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395 | 395 | --output_type => CFG_SPW_OUTPUT, -- not used byt the spw core 1 |
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396 | 396 | --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1 |
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397 | 397 | ) |
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398 | 398 | PORT MAP(reset, clk_25, spw_rxclk(0), |
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399 | 399 | spw_rxclk(1), spw_rxtxclk, spw_rxtxclk, |
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400 | 400 | ahbi_m_ext, ahbo_m_ext(1), apbi_ext, apbo_ext(5), |
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401 | 401 | swni, swno); |
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402 | 402 | |
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403 | 403 | swni.tickin <= '0'; |
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404 | 404 | swni.rmapen <= '1'; |
|
405 | 405 | swni.clkdiv10 <= "00000100"; -- 10 MHz / (4 + 1) = 10 MHz |
|
406 | 406 | swni.tickinraw <= '0'; |
|
407 | 407 | swni.timein <= (OTHERS => '0'); |
|
408 | 408 | swni.dcrstval <= (OTHERS => '0'); |
|
409 | 409 | swni.timerrstval <= (OTHERS => '0'); |
|
410 | 410 | |
|
411 | 411 | ------------------------------------------------------------------------------- |
|
412 | 412 | -- LFR ------------------------------------------------------------------------ |
|
413 | 413 | ------------------------------------------------------------------------------- |
|
414 | 414 | lpp_lfr_1 : lpp_lfr |
|
415 | 415 | GENERIC MAP ( |
|
416 | 416 | Mem_use => use_RAM, |
|
417 | 417 | nb_data_by_buffer_size => 32, |
|
418 | 418 | nb_word_by_buffer_size => 30, |
|
419 | 419 | nb_snapshot_param_size => 32, |
|
420 | 420 | delta_vector_size => 32, |
|
421 | 421 | delta_vector_size_f0_2 => 7, -- log2(96) |
|
422 | 422 | pindex => 15, |
|
423 | 423 | paddr => 15, |
|
424 | 424 | pmask => 16#fff#, |
|
425 | 425 | pirq_ms => 6, |
|
426 | 426 | pirq_wfp => 14, |
|
427 | 427 | hindex => 2, |
|
428 |
top_lfr_version => X"00010 |
|
|
428 | top_lfr_version => X"000105") -- aa.bb.cc version | |
|
429 | 429 | PORT MAP ( |
|
430 | 430 | clk => clk_25, |
|
431 | 431 | rstn => reset, |
|
432 | 432 | sample_B => sample(2 DOWNTO 0), |
|
433 | 433 | sample_E => sample(7 DOWNTO 3), |
|
434 | 434 | sample_val => sample_val, |
|
435 | 435 | apbi => apbi_ext, |
|
436 | 436 | apbo => apbo_ext(15), |
|
437 | 437 | ahbi => ahbi_m_ext, |
|
438 | 438 | ahbo => ahbo_m_ext(2), |
|
439 | 439 | coarse_time => coarse_time, |
|
440 | 440 | fine_time => fine_time, |
|
441 | 441 | data_shaping_BW => bias_fail_sw_sig, |
|
442 | 442 | observation_reg => observation_reg); |
|
443 | 443 | |
|
444 | 444 | top_ad_conv_ADS7886_v2_1 : top_ad_conv_ADS7886_v2 |
|
445 | 445 | GENERIC MAP( |
|
446 | 446 | ChannelCount => 8, |
|
447 | 447 | SampleNbBits => 14, |
|
448 | 448 | ncycle_cnv_high => 40, -- at least 32 cycles at 25 MHz, 32 * 49.152 / 25 /2 = 31.5 |
|
449 | 449 | ncycle_cnv => 249) -- 49 152 000 / 98304 /2 |
|
450 | 450 | PORT MAP ( |
|
451 | 451 | -- CONV |
|
452 | 452 | cnv_clk => clk_24, |
|
453 | 453 | cnv_rstn => reset, |
|
454 | 454 | cnv => ADC_nCS_sig, |
|
455 | 455 | -- DATA |
|
456 | 456 | clk => clk_25, |
|
457 | 457 | rstn => reset, |
|
458 | 458 | sck => ADC_CLK_sig, |
|
459 | 459 | sdo => ADC_SDO_sig, |
|
460 | 460 | -- SAMPLE |
|
461 | 461 | sample => sample, |
|
462 | 462 | sample_val => sample_val); |
|
463 | 463 | |
|
464 | 464 | --IO10 <= ADC_SDO_sig(5); |
|
465 | 465 | --IO9 <= ADC_SDO_sig(4); |
|
466 | 466 | --IO8 <= ADC_SDO_sig(3); |
|
467 | 467 | |
|
468 | 468 | ADC_nCS <= ADC_nCS_sig; |
|
469 | 469 | ADC_CLK <= ADC_CLK_sig; |
|
470 | 470 | ADC_SDO_sig <= ADC_SDO; |
|
471 | 471 | |
|
472 | 472 | ---------------------------------------------------------------------- |
|
473 | 473 | --- GPIO ----------------------------------------------------------- |
|
474 | 474 | ---------------------------------------------------------------------- |
|
475 | 475 | |
|
476 | 476 | grgpio0 : grgpio |
|
477 | 477 | GENERIC MAP(pindex => 11, paddr => 11, imask => 16#0000#, nbits => 8) |
|
478 | 478 | PORT MAP(reset, clk_25, apbi_ext, apbo_ext(11), gpioi, gpioo); |
|
479 | 479 | |
|
480 | 480 | --pio_pad_0 : iopad |
|
481 | 481 | -- GENERIC MAP (tech => CFG_PADTECH) |
|
482 | 482 | -- PORT MAP (IO0, gpioo.dout(0), gpioo.oen(0), gpioi.din(0)); |
|
483 | 483 | --pio_pad_1 : iopad |
|
484 | 484 | -- GENERIC MAP (tech => CFG_PADTECH) |
|
485 | 485 | -- PORT MAP (IO1, gpioo.dout(1), gpioo.oen(1), gpioi.din(1)); |
|
486 | 486 | --pio_pad_2 : iopad |
|
487 | 487 | -- GENERIC MAP (tech => CFG_PADTECH) |
|
488 | 488 | -- PORT MAP (IO2, gpioo.dout(2), gpioo.oen(2), gpioi.din(2)); |
|
489 | 489 | --pio_pad_3 : iopad |
|
490 | 490 | -- GENERIC MAP (tech => CFG_PADTECH) |
|
491 | 491 | -- PORT MAP (IO3, gpioo.dout(3), gpioo.oen(3), gpioi.din(3)); |
|
492 | 492 | --pio_pad_4 : iopad |
|
493 | 493 | -- GENERIC MAP (tech => CFG_PADTECH) |
|
494 | 494 | -- PORT MAP (IO4, gpioo.dout(4), gpioo.oen(4), gpioi.din(4)); |
|
495 | 495 | --pio_pad_5 : iopad |
|
496 | 496 | -- GENERIC MAP (tech => CFG_PADTECH) |
|
497 | 497 | -- PORT MAP (IO5, gpioo.dout(5), gpioo.oen(5), gpioi.din(5)); |
|
498 | 498 | --pio_pad_6 : iopad |
|
499 | 499 | -- GENERIC MAP (tech => CFG_PADTECH) |
|
500 | 500 | -- PORT MAP (IO6, gpioo.dout(6), gpioo.oen(6), gpioi.din(6)); |
|
501 | 501 | --pio_pad_7 : iopad |
|
502 | 502 | -- GENERIC MAP (tech => CFG_PADTECH) |
|
503 | 503 | -- PORT MAP (IO7, gpioo.dout(7), gpioo.oen(7), gpioi.din(7)); |
|
504 | 504 | |
|
505 | 505 | PROCESS (clk_25, reset) |
|
506 | 506 | BEGIN -- PROCESS |
|
507 | 507 | IF reset = '0' THEN -- asynchronous reset (active low) |
|
508 | 508 | IO0 <= '0'; |
|
509 | 509 | IO1 <= '0'; |
|
510 | 510 | IO2 <= '0'; |
|
511 | 511 | IO3 <= '0'; |
|
512 | 512 | IO4 <= '0'; |
|
513 | 513 | IO5 <= '0'; |
|
514 | 514 | IO6 <= '0'; |
|
515 | 515 | IO7 <= '0'; |
|
516 | 516 | IO8 <= '0'; |
|
517 | 517 | IO9 <= '0'; |
|
518 | 518 | IO10 <= '0'; |
|
519 | 519 | IO11 <= '0'; |
|
520 | 520 | ELSIF clk_25'event AND clk_25 = '1' THEN -- rising clock edge |
|
521 | 521 | CASE gpioo.dout(1 DOWNTO 0) IS |
|
522 | 522 | WHEN "00" => |
|
523 | 523 | IO0 <= observation_reg(0 ); |
|
524 | 524 | IO1 <= observation_reg(1 ); |
|
525 | 525 | IO2 <= observation_reg(2 ); |
|
526 | 526 | IO3 <= observation_reg(3 ); |
|
527 | 527 | IO4 <= observation_reg(4 ); |
|
528 | 528 | IO5 <= observation_reg(5 ); |
|
529 | 529 | IO6 <= observation_reg(6 ); |
|
530 | 530 | IO7 <= observation_reg(7 ); |
|
531 | 531 | IO8 <= observation_reg(8 ); |
|
532 | 532 | IO9 <= observation_reg(9 ); |
|
533 | 533 | IO10 <= observation_reg(10); |
|
534 | 534 | IO11 <= observation_reg(11); |
|
535 | 535 | WHEN "01" => |
|
536 | 536 | IO0 <= observation_reg(0 + 12); |
|
537 | 537 | IO1 <= observation_reg(1 + 12); |
|
538 | 538 | IO2 <= observation_reg(2 + 12); |
|
539 | 539 | IO3 <= observation_reg(3 + 12); |
|
540 | 540 | IO4 <= observation_reg(4 + 12); |
|
541 | 541 | IO5 <= observation_reg(5 + 12); |
|
542 | 542 | IO6 <= observation_reg(6 + 12); |
|
543 | 543 | IO7 <= observation_reg(7 + 12); |
|
544 | 544 | IO8 <= observation_reg(8 + 12); |
|
545 | 545 | IO9 <= observation_reg(9 + 12); |
|
546 | 546 | IO10 <= observation_reg(10 + 12); |
|
547 | 547 | IO11 <= observation_reg(11 + 12); |
|
548 | 548 | WHEN "10" => |
|
549 | 549 | IO0 <= observation_reg(0 + 12 + 12); |
|
550 | 550 | IO1 <= observation_reg(1 + 12 + 12); |
|
551 | 551 | IO2 <= observation_reg(2 + 12 + 12); |
|
552 | 552 | IO3 <= observation_reg(3 + 12 + 12); |
|
553 | 553 | IO4 <= observation_reg(4 + 12 + 12); |
|
554 | 554 | IO5 <= observation_reg(5 + 12 + 12); |
|
555 | 555 | IO6 <= observation_reg(6 + 12 + 12); |
|
556 | 556 | IO7 <= observation_reg(7 + 12 + 12); |
|
557 | 557 | IO8 <= '0'; |
|
558 | 558 | IO9 <= '0'; |
|
559 | 559 | IO10 <= '0'; |
|
560 | 560 | IO11 <= '0'; |
|
561 | 561 | WHEN "11" => |
|
562 | 562 | IO0 <= '0'; |
|
563 | 563 | IO1 <= '0'; |
|
564 | 564 | IO2 <= '0'; |
|
565 | 565 | IO3 <= '0'; |
|
566 | 566 | IO4 <= '0'; |
|
567 | 567 | IO5 <= '0'; |
|
568 | 568 | IO6 <= '0'; |
|
569 | 569 | IO7 <= '0'; |
|
570 | 570 | IO8 <= '0'; |
|
571 | 571 | IO9 <= '0'; |
|
572 | 572 | IO10 <= '0'; |
|
573 | 573 | IO11 <= '0'; |
|
574 | 574 | WHEN OTHERS => NULL; |
|
575 | 575 | END CASE; |
|
576 | 576 | |
|
577 | 577 | END IF; |
|
578 | 578 | END PROCESS; |
|
579 | 579 | |
|
580 | 580 | END beh; |
@@ -1,95 +1,100 | |||
|
1 | 1 | ------------------------------------------------------------------------------ |
|
2 | 2 | -- This file is a part of the LPP VHDL IP LIBRARY |
|
3 | 3 | -- Copyright (C) 2009 - 2012, Laboratory of Plasmas Physic - CNRS |
|
4 | 4 | -- |
|
5 | 5 | -- This program is free software; you can redistribute it and/or modify |
|
6 | 6 | -- it under the terms of the GNU General Public License as published by |
|
7 | 7 | -- the Free Software Foundation; either version 3 of the License, or |
|
8 | 8 | -- (at your option) any later version. |
|
9 | 9 | -- |
|
10 | 10 | -- This program is distributed in the hope that it will be useful, |
|
11 | 11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of |
|
12 | 12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
|
13 | 13 | -- GNU General Public License for more details. |
|
14 | 14 | -- |
|
15 | 15 | -- You should have received a copy of the GNU General Public License |
|
16 | 16 | -- along with this program; if not, write to the Free Software |
|
17 | 17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
|
18 | 18 | ------------------------------------------------------------------------------ |
|
19 | 19 | -- Author : Martin Morlot |
|
20 | 20 | -- Mail : martin.morlot@lpp.polytechnique.fr |
|
21 | 21 | ------------------------------------------------------------------------------ |
|
22 | 22 | library IEEE; |
|
23 | 23 | use IEEE.std_logic_1164.all; |
|
24 | 24 | use IEEE.numeric_std.all; |
|
25 | 25 | library lpp; |
|
26 | 26 | use lpp.lpp_fft.all; |
|
27 | 27 | use lpp.fft_components.all; |
|
28 | 28 | |
|
29 | 29 | -- Update possible lecture (ren) de fifo en continu, pendant un Load, au lieu d'une lecture "crοΏ½neau" |
|
30 | 30 | |
|
31 | 31 | entity FFT is |
|
32 | 32 | generic( |
|
33 | 33 | Data_sz : integer := 16; |
|
34 | 34 | NbData : integer := 256); |
|
35 | 35 | port( |
|
36 | 36 | clkm : in std_logic; |
|
37 | 37 | rstn : in std_logic; |
|
38 | 38 | FifoIN_Empty : in std_logic_vector(4 downto 0); |
|
39 | 39 | FifoIN_Data : in std_logic_vector(79 downto 0); |
|
40 | 40 | FifoOUT_Full : in std_logic_vector(4 downto 0); |
|
41 | 41 | Load : out std_logic; |
|
42 | 42 | Read : out std_logic_vector(4 downto 0); |
|
43 | 43 | Write : out std_logic_vector(4 downto 0); |
|
44 | 44 | ReUse : out std_logic_vector(4 downto 0); |
|
45 | 45 | Data : out std_logic_vector(79 downto 0) |
|
46 | 46 | ); |
|
47 | 47 | end entity; |
|
48 | 48 | |
|
49 | 49 | |
|
50 | 50 | architecture ar_FFT of FFT is |
|
51 | 51 | |
|
52 | 52 | signal Drive_Write : std_logic; |
|
53 | 53 | signal Drive_DataRE : std_logic_vector(15 downto 0); |
|
54 | 54 | signal Drive_DataIM : std_logic_vector(15 downto 0); |
|
55 | 55 | |
|
56 | 56 | signal Start : std_logic; |
|
57 | 57 | signal FFT_Load : std_logic; |
|
58 | 58 | signal FFT_Ready : std_logic; |
|
59 | 59 | signal FFT_Valid : std_logic; |
|
60 | 60 | signal FFT_DataRE : std_logic_vector(15 downto 0); |
|
61 | 61 | signal FFT_DataIM : std_logic_vector(15 downto 0); |
|
62 | 62 | |
|
63 | 63 | signal Link_Read : std_logic; |
|
64 | 64 | |
|
65 | 65 | begin |
|
66 | 66 | |
|
67 | 67 | Start <= '0'; |
|
68 | 68 | Load <= FFT_Load; |
|
69 | 69 | |
|
70 | 70 | DRIVE : Driver_FFT |
|
71 | 71 | generic map(Data_sz,NbData) |
|
72 | 72 | port map(clkm,rstn,FFT_Load,FifoIN_Empty,FifoIN_Data,Drive_Write,Read,Drive_DataRE,Drive_DataIM); |
|
73 | 73 | |
|
74 | 74 | FFT0 : CoreFFT |
|
75 | 75 | generic map( |
|
76 | 76 | LOGPTS => gLOGPTS, |
|
77 | 77 | LOGLOGPTS => gLOGLOGPTS, |
|
78 | 78 | WSIZE => gWSIZE, |
|
79 | 79 | TWIDTH => gTWIDTH, |
|
80 | 80 | DWIDTH => gDWIDTH, |
|
81 | 81 | TDWIDTH => gTDWIDTH, |
|
82 | 82 | RND_MODE => gRND_MODE, |
|
83 | 83 | SCALE_MODE => gSCALE_MODE, |
|
84 | 84 | PTS => gPTS, |
|
85 | 85 | HALFPTS => gHALFPTS, |
|
86 | 86 | inBuf_RWDLY => gInBuf_RWDLY) |
|
87 | port map(clkm,start,rstn,Drive_Write,Link_Read,Drive_DataIM,Drive_DataRE,FFT_Load,open,FFT_DataIM,FFT_DataRE,FFT_Valid,FFT_Ready); | |
|
87 | port map(clkm,start,rstn, | |
|
88 | Drive_Write,Link_Read, | |
|
89 | Drive_DataIM,Drive_DataRE, | |
|
90 | FFT_Load,open, | |
|
91 | FFT_DataIM,FFT_DataRE, | |
|
92 | FFT_Valid,FFT_Ready); | |
|
88 | 93 | |
|
89 | 94 | |
|
90 | 95 | LINK : Linker_FFT |
|
91 | 96 | generic map(Data_sz,NbData) |
|
92 | 97 | port map(clkm,rstn,FFT_Ready,FFT_Valid,FifoOUT_Full,FFT_DataRE,FFT_DataIM,Link_Read,Write,ReUse,Data); |
|
93 | 98 | |
|
94 | 99 | |
|
95 | end architecture; No newline at end of file | |
|
100 | end architecture; |
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@@ -1,544 +1,544 | |||
|
1 | ------------------------------------------------------------------------------ | |
|
2 | -- This file is a part of the LPP VHDL IP LIBRARY | |
|
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS | |
|
4 | -- | |
|
5 | -- This program is free software; you can redistribute it and/or modify | |
|
6 | -- it under the terms of the GNU General Public License as published by | |
|
7 | -- the Free Software Foundation; either version 3 of the License, or | |
|
8 | -- (at your option) any later version. | |
|
9 | -- | |
|
10 | -- This program is distributed in the hope that it will be useful, | |
|
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of | |
|
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
|
13 | -- GNU General Public License for more details. | |
|
14 | -- | |
|
15 | -- You should have received a copy of the GNU General Public License | |
|
16 | -- along with this program; if not, write to the Free Software | |
|
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
|
18 | ------------------------------------------------------------------------------- | |
|
19 | -- Author : Jean-christophe Pellion | |
|
20 | -- Mail : jean-christophe.pellion@lpp.polytechnique.fr | |
|
21 | -- jean-christophe.pellion@easii-ic.com | |
|
22 | ---------------------------------------------------------------------------- | |
|
23 | LIBRARY ieee; | |
|
24 | USE ieee.std_logic_1164.ALL; | |
|
25 | USE ieee.numeric_std.ALL; | |
|
26 | LIBRARY grlib; | |
|
27 | USE grlib.amba.ALL; | |
|
28 | USE grlib.stdlib.ALL; | |
|
29 | USE grlib.devices.ALL; | |
|
30 | LIBRARY lpp; | |
|
31 | USE lpp.lpp_amba.ALL; | |
|
32 | USE lpp.apb_devices_list.ALL; | |
|
33 | USE lpp.lpp_memory.ALL; | |
|
34 | LIBRARY techmap; | |
|
35 | USE techmap.gencomp.ALL; | |
|
36 | ||
|
37 | ENTITY lpp_lfr_apbreg IS | |
|
38 | GENERIC ( | |
|
39 | nb_data_by_buffer_size : INTEGER := 11; | |
|
40 | nb_word_by_buffer_size : INTEGER := 11; | |
|
41 | nb_snapshot_param_size : INTEGER := 11; | |
|
42 | delta_vector_size : INTEGER := 20; | |
|
43 | delta_vector_size_f0_2 : INTEGER := 3; | |
|
44 | ||
|
45 | pindex : INTEGER := 4; | |
|
46 | paddr : INTEGER := 4; | |
|
47 | pmask : INTEGER := 16#fff#; | |
|
48 | pirq_ms : INTEGER := 0; | |
|
49 | pirq_wfp : INTEGER := 1; | |
|
50 | top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0)); | |
|
51 | PORT ( | |
|
52 | -- AMBA AHB system signals | |
|
53 | HCLK : IN STD_ULOGIC; | |
|
54 | HRESETn : IN STD_ULOGIC; | |
|
55 | ||
|
56 | -- AMBA APB Slave Interface | |
|
57 | apbi : IN apb_slv_in_type; | |
|
58 | apbo : OUT apb_slv_out_type; | |
|
59 | ||
|
60 | --------------------------------------------------------------------------- | |
|
61 | -- Spectral Matrix Reg | |
|
62 | run_ms : OUT STD_LOGIC; | |
|
63 | -- IN | |
|
64 | ready_matrix_f0_0 : IN STD_LOGIC; | |
|
65 | ready_matrix_f0_1 : IN STD_LOGIC; | |
|
66 | ready_matrix_f1 : IN STD_LOGIC; | |
|
67 | ready_matrix_f2 : IN STD_LOGIC; | |
|
68 | error_anticipating_empty_fifo : IN STD_LOGIC; | |
|
69 | error_bad_component_error : IN STD_LOGIC; | |
|
70 | debug_reg : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
71 | ||
|
72 | -- OUT | |
|
73 | status_ready_matrix_f0_0 : OUT STD_LOGIC; | |
|
74 | status_ready_matrix_f0_1 : OUT STD_LOGIC; | |
|
75 | status_ready_matrix_f1 : OUT STD_LOGIC; | |
|
76 | status_ready_matrix_f2 : OUT STD_LOGIC; | |
|
77 | status_error_anticipating_empty_fifo : OUT STD_LOGIC; | |
|
78 | status_error_bad_component_error : OUT STD_LOGIC; | |
|
79 | ||
|
80 | config_active_interruption_onNewMatrix : OUT STD_LOGIC; | |
|
81 | config_active_interruption_onError : OUT STD_LOGIC; | |
|
82 | ||
|
83 | addr_matrix_f0_0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
84 | addr_matrix_f0_1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
85 | addr_matrix_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
86 | addr_matrix_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
87 | ||
|
88 | matrix_time_f0_0 : IN STD_LOGIC_VECTOR(47 DOWNTO 0); | |
|
89 | matrix_time_f0_1 : IN STD_LOGIC_VECTOR(47 DOWNTO 0); | |
|
90 | matrix_time_f1 : IN STD_LOGIC_VECTOR(47 DOWNTO 0); | |
|
91 | matrix_time_f2 : IN STD_LOGIC_VECTOR(47 DOWNTO 0); | |
|
92 | ||
|
93 | --------------------------------------------------------------------------- | |
|
94 | --------------------------------------------------------------------------- | |
|
95 | -- WaveForm picker Reg | |
|
96 | status_full : IN STD_LOGIC_VECTOR(3 DOWNTO 0); | |
|
97 | status_full_ack : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); | |
|
98 | status_full_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0); | |
|
99 | status_new_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0); | |
|
100 | ||
|
101 | -- OUT | |
|
102 | data_shaping_BW : OUT STD_LOGIC; | |
|
103 | data_shaping_SP0 : OUT STD_LOGIC; | |
|
104 | data_shaping_SP1 : OUT STD_LOGIC; | |
|
105 | data_shaping_R0 : OUT STD_LOGIC; | |
|
106 | data_shaping_R1 : OUT STD_LOGIC; | |
|
107 | ||
|
108 | delta_snapshot : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); | |
|
109 | delta_f0 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); | |
|
110 | delta_f0_2 : OUT STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0); | |
|
111 | delta_f1 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); | |
|
112 | delta_f2 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); | |
|
113 | nb_data_by_buffer : OUT STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0); | |
|
114 | nb_word_by_buffer : OUT STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0); | |
|
115 | nb_snapshot_param : OUT STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0); | |
|
116 | ||
|
117 | enable_f0 : OUT STD_LOGIC; | |
|
118 | enable_f1 : OUT STD_LOGIC; | |
|
119 | enable_f2 : OUT STD_LOGIC; | |
|
120 | enable_f3 : OUT STD_LOGIC; | |
|
121 | ||
|
122 | burst_f0 : OUT STD_LOGIC; | |
|
123 | burst_f1 : OUT STD_LOGIC; | |
|
124 | burst_f2 : OUT STD_LOGIC; | |
|
125 | ||
|
126 | run : OUT STD_LOGIC; | |
|
127 | ||
|
128 | addr_data_f0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
129 | addr_data_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
130 | addr_data_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
131 | addr_data_f3 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
132 | start_date : OUT STD_LOGIC_VECTOR(30 DOWNTO 0); | |
|
133 | --------------------------------------------------------------------------- | |
|
134 | debug_reg0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
135 | debug_reg1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
136 | debug_reg2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
137 | debug_reg3 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
138 | debug_reg4 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
139 | debug_reg5 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
140 | debug_reg6 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
141 | debug_reg7 : IN STD_LOGIC_VECTOR(31 DOWNTO 0) | |
|
142 | ||
|
143 | --------------------------------------------------------------------------- | |
|
144 | ); | |
|
145 | ||
|
146 | END lpp_lfr_apbreg; | |
|
147 | ||
|
148 | ARCHITECTURE beh OF lpp_lfr_apbreg IS | |
|
149 | ||
|
150 | CONSTANT REVISION : INTEGER := 1; | |
|
151 | ||
|
152 | CONSTANT pconfig : apb_config_type := ( | |
|
153 | 0 => ahb_device_reg (VENDOR_LPP, LPP_LFR, 0, REVISION, pirq_wfp), | |
|
154 | 1 => apb_iobar(paddr, pmask)); | |
|
155 | ||
|
156 | TYPE lpp_SpectralMatrix_regs IS RECORD | |
|
157 | config_active_interruption_onNewMatrix : STD_LOGIC; | |
|
158 | config_active_interruption_onError : STD_LOGIC; | |
|
159 | config_ms_run : STD_LOGIC; | |
|
160 | status_ready_matrix_f0_0 : STD_LOGIC; | |
|
161 | status_ready_matrix_f0_1 : STD_LOGIC; | |
|
162 | status_ready_matrix_f1 : STD_LOGIC; | |
|
163 | status_ready_matrix_f2 : STD_LOGIC; | |
|
164 | status_error_anticipating_empty_fifo : STD_LOGIC; | |
|
165 | status_error_bad_component_error : STD_LOGIC; | |
|
166 | addr_matrix_f0_0 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
167 | addr_matrix_f0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
168 | addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
169 | addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
170 | ||
|
171 | coarse_time_f0_0 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
172 | coarse_time_f0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
173 | coarse_time_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
174 | coarse_time_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
175 | ||
|
176 | -- fine_time_f0_0 : STD_LOGIC_VECTOR(15 DOWNTO 0); | |
|
177 | -- fine_time_f0_1 : STD_LOGIC_VECTOR(15 DOWNTO 0); | |
|
178 | -- fine_time_f1 : STD_LOGIC_VECTOR(15 DOWNTO 0); | |
|
179 | -- fine_time_f2 : STD_LOGIC_VECTOR(15 DOWNTO 0); | |
|
180 | END RECORD; | |
|
181 | SIGNAL reg_sp : lpp_SpectralMatrix_regs; | |
|
182 | ||
|
183 | TYPE lpp_WaveformPicker_regs IS RECORD | |
|
184 | status_full : STD_LOGIC_VECTOR(3 DOWNTO 0); | |
|
185 | status_full_err : STD_LOGIC_VECTOR(3 DOWNTO 0); | |
|
186 | status_new_err : STD_LOGIC_VECTOR(3 DOWNTO 0); | |
|
187 | data_shaping_BW : STD_LOGIC; | |
|
188 | data_shaping_SP0 : STD_LOGIC; | |
|
189 | data_shaping_SP1 : STD_LOGIC; | |
|
190 | data_shaping_R0 : STD_LOGIC; | |
|
191 | data_shaping_R1 : STD_LOGIC; | |
|
192 | delta_snapshot : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); | |
|
193 | delta_f0 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); | |
|
194 | delta_f0_2 : STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0); | |
|
195 | delta_f1 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); | |
|
196 | delta_f2 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); | |
|
197 | nb_data_by_buffer : STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0); | |
|
198 | nb_word_by_buffer : STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0); | |
|
199 | nb_snapshot_param : STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0); | |
|
200 | enable_f0 : STD_LOGIC; | |
|
201 | enable_f1 : STD_LOGIC; | |
|
202 | enable_f2 : STD_LOGIC; | |
|
203 | enable_f3 : STD_LOGIC; | |
|
204 | burst_f0 : STD_LOGIC; | |
|
205 | burst_f1 : STD_LOGIC; | |
|
206 | burst_f2 : STD_LOGIC; | |
|
207 | run : STD_LOGIC; | |
|
208 | addr_data_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
209 | addr_data_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
210 | addr_data_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
211 | addr_data_f3 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
212 | start_date : STD_LOGIC_VECTOR(30 DOWNTO 0); | |
|
213 | END RECORD; | |
|
214 | SIGNAL reg_wp : lpp_WaveformPicker_regs; | |
|
215 | ||
|
216 | SIGNAL prdata : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
217 | ||
|
218 | ----------------------------------------------------------------------------- | |
|
219 | -- IRQ | |
|
220 | ----------------------------------------------------------------------------- | |
|
221 | CONSTANT IRQ_WFP_SIZE : INTEGER := 12; | |
|
222 | SIGNAL irq_wfp_ZERO : STD_LOGIC_VECTOR(IRQ_WFP_SIZE-1 DOWNTO 0); | |
|
223 | SIGNAL irq_wfp_reg_s : STD_LOGIC_VECTOR(IRQ_WFP_SIZE-1 DOWNTO 0); | |
|
224 | SIGNAL irq_wfp_reg : STD_LOGIC_VECTOR(IRQ_WFP_SIZE-1 DOWNTO 0); | |
|
225 | SIGNAL irq_wfp : STD_LOGIC_VECTOR(IRQ_WFP_SIZE-1 DOWNTO 0); | |
|
226 | SIGNAL ored_irq_wfp : STD_LOGIC; | |
|
227 | ||
|
228 | BEGIN -- beh | |
|
229 | ||
|
230 | status_ready_matrix_f0_0 <= reg_sp.status_ready_matrix_f0_0; | |
|
231 | status_ready_matrix_f0_1 <= reg_sp.status_ready_matrix_f0_1; | |
|
232 | status_ready_matrix_f1 <= reg_sp.status_ready_matrix_f1; | |
|
233 | status_ready_matrix_f2 <= reg_sp.status_ready_matrix_f2; | |
|
234 | status_error_anticipating_empty_fifo <= reg_sp.status_error_anticipating_empty_fifo; | |
|
235 | status_error_bad_component_error <= reg_sp.status_error_bad_component_error; | |
|
236 | ||
|
237 | config_active_interruption_onNewMatrix <= reg_sp.config_active_interruption_onNewMatrix; | |
|
238 | config_active_interruption_onError <= reg_sp.config_active_interruption_onError; | |
|
239 | addr_matrix_f0_0 <= reg_sp.addr_matrix_f0_0; | |
|
240 | addr_matrix_f0_1 <= reg_sp.addr_matrix_f0_1; | |
|
241 | addr_matrix_f1 <= reg_sp.addr_matrix_f1; | |
|
242 | addr_matrix_f2 <= reg_sp.addr_matrix_f2; | |
|
243 | ||
|
244 | ||
|
245 | data_shaping_BW <= NOT reg_wp.data_shaping_BW; | |
|
246 | data_shaping_SP0 <= reg_wp.data_shaping_SP0; | |
|
247 | data_shaping_SP1 <= reg_wp.data_shaping_SP1; | |
|
248 | data_shaping_R0 <= reg_wp.data_shaping_R0; | |
|
249 | data_shaping_R1 <= reg_wp.data_shaping_R1; | |
|
250 | ||
|
251 | delta_snapshot <= reg_wp.delta_snapshot; | |
|
252 | delta_f0 <= reg_wp.delta_f0; | |
|
253 | delta_f0_2 <= reg_wp.delta_f0_2; | |
|
254 | delta_f1 <= reg_wp.delta_f1; | |
|
255 | delta_f2 <= reg_wp.delta_f2; | |
|
256 | nb_data_by_buffer <= reg_wp.nb_data_by_buffer; | |
|
257 | nb_word_by_buffer <= reg_wp.nb_word_by_buffer; | |
|
258 | nb_snapshot_param <= reg_wp.nb_snapshot_param; | |
|
259 | ||
|
260 | enable_f0 <= reg_wp.enable_f0; | |
|
261 | enable_f1 <= reg_wp.enable_f1; | |
|
262 | enable_f2 <= reg_wp.enable_f2; | |
|
263 | enable_f3 <= reg_wp.enable_f3; | |
|
264 | ||
|
265 | burst_f0 <= reg_wp.burst_f0; | |
|
266 | burst_f1 <= reg_wp.burst_f1; | |
|
267 | burst_f2 <= reg_wp.burst_f2; | |
|
268 | ||
|
269 | run <= reg_wp.run; | |
|
270 | ||
|
271 | addr_data_f0 <= reg_wp.addr_data_f0; | |
|
272 | addr_data_f1 <= reg_wp.addr_data_f1; | |
|
273 | addr_data_f2 <= reg_wp.addr_data_f2; | |
|
274 | addr_data_f3 <= reg_wp.addr_data_f3; | |
|
275 | ||
|
276 | start_date <= reg_wp.start_date; | |
|
277 | ||
|
278 | lpp_lfr_apbreg : PROCESS (HCLK, HRESETn) | |
|
279 | VARIABLE paddr : STD_LOGIC_VECTOR(7 DOWNTO 2); | |
|
280 | BEGIN -- PROCESS lpp_dma_top | |
|
281 | IF HRESETn = '0' THEN -- asynchronous reset (active low) | |
|
282 | reg_sp.config_active_interruption_onNewMatrix <= '0'; | |
|
283 | reg_sp.config_active_interruption_onError <= '0'; | |
|
284 | reg_sp.config_ms_run <= '1'; | |
|
285 | reg_sp.status_ready_matrix_f0_0 <= '0'; | |
|
286 | reg_sp.status_ready_matrix_f0_1 <= '0'; | |
|
287 | reg_sp.status_ready_matrix_f1 <= '0'; | |
|
288 | reg_sp.status_ready_matrix_f2 <= '0'; | |
|
289 | reg_sp.status_error_anticipating_empty_fifo <= '0'; | |
|
290 | reg_sp.status_error_bad_component_error <= '0'; | |
|
291 | reg_sp.addr_matrix_f0_0 <= (OTHERS => '0'); | |
|
292 | reg_sp.addr_matrix_f0_1 <= (OTHERS => '0'); | |
|
293 | reg_sp.addr_matrix_f1 <= (OTHERS => '0'); | |
|
294 | reg_sp.addr_matrix_f2 <= (OTHERS => '0'); | |
|
295 | ||
|
296 | reg_sp.coarse_time_f0_0 <= (OTHERS => '0'); | |
|
297 | reg_sp.coarse_time_f0_1 <= (OTHERS => '0'); | |
|
298 | reg_sp.coarse_time_f1 <= (OTHERS => '0'); | |
|
299 | reg_sp.coarse_time_f2 <= (OTHERS => '0'); | |
|
300 | --reg_sp.fine_time_f0_0 <= (OTHERS => '0'); | |
|
301 | --reg_sp.fine_time_f0_1 <= (OTHERS => '0'); | |
|
302 | --reg_sp.fine_time_f1 <= (OTHERS => '0'); | |
|
303 | --reg_sp.fine_time_f2 <= (OTHERS => '0'); | |
|
304 | ||
|
305 | prdata <= (OTHERS => '0'); | |
|
306 | ||
|
307 | apbo.pirq <= (OTHERS => '0'); | |
|
308 | ||
|
309 | status_full_ack <= (OTHERS => '0'); | |
|
310 | ||
|
311 | reg_wp.data_shaping_BW <= '0'; | |
|
312 | reg_wp.data_shaping_SP0 <= '0'; | |
|
313 | reg_wp.data_shaping_SP1 <= '0'; | |
|
314 | reg_wp.data_shaping_R0 <= '0'; | |
|
315 | reg_wp.data_shaping_R1 <= '0'; | |
|
316 | reg_wp.enable_f0 <= '0'; | |
|
317 | reg_wp.enable_f1 <= '0'; | |
|
318 | reg_wp.enable_f2 <= '0'; | |
|
319 | reg_wp.enable_f3 <= '0'; | |
|
320 | reg_wp.burst_f0 <= '0'; | |
|
321 | reg_wp.burst_f1 <= '0'; | |
|
322 | reg_wp.burst_f2 <= '0'; | |
|
323 | reg_wp.run <= '0'; | |
|
324 | reg_wp.addr_data_f0 <= (OTHERS => '0'); | |
|
325 | reg_wp.addr_data_f1 <= (OTHERS => '0'); | |
|
326 | reg_wp.addr_data_f2 <= (OTHERS => '0'); | |
|
327 | reg_wp.addr_data_f3 <= (OTHERS => '0'); | |
|
328 | reg_wp.status_full <= (OTHERS => '0'); | |
|
329 | reg_wp.status_full_err <= (OTHERS => '0'); | |
|
330 | reg_wp.status_new_err <= (OTHERS => '0'); | |
|
331 | reg_wp.delta_snapshot <= (OTHERS => '0'); | |
|
332 | reg_wp.delta_f0 <= (OTHERS => '0'); | |
|
333 | reg_wp.delta_f0_2 <= (OTHERS => '0'); | |
|
334 | reg_wp.delta_f1 <= (OTHERS => '0'); | |
|
335 | reg_wp.delta_f2 <= (OTHERS => '0'); | |
|
336 | reg_wp.nb_data_by_buffer <= (OTHERS => '0'); | |
|
337 | reg_wp.nb_snapshot_param <= (OTHERS => '0'); | |
|
338 | reg_wp.start_date <= (OTHERS => '0'); | |
|
339 | ||
|
340 | ELSIF HCLK'EVENT AND HCLK = '1' THEN -- rising clock edge | |
|
341 | ||
|
342 | reg_sp.coarse_time_f0_0 <= matrix_time_f0_0(31 DOWNTO 0); | |
|
343 | reg_sp.coarse_time_f0_1 <= matrix_time_f0_1(31 DOWNTO 0); | |
|
344 | reg_sp.coarse_time_f1 <= matrix_time_f1 (31 DOWNTO 0); | |
|
345 | reg_sp.coarse_time_f2 <= matrix_time_f2 (31 DOWNTO 0); | |
|
346 | ||
|
347 | --reg_sp.fine_time_f0_0 <= matrix_time_f0_0(15 DOWNTO 0); | |
|
348 | --reg_sp.fine_time_f0_1 <= matrix_time_f0_1(15 DOWNTO 0); | |
|
349 | --reg_sp.fine_time_f1 <= matrix_time_f1 (15 DOWNTO 0); | |
|
350 | --reg_sp.fine_time_f2 <= matrix_time_f2 (15 DOWNTO 0); | |
|
351 | ||
|
352 | status_full_ack <= (OTHERS => '0'); | |
|
353 | ||
|
354 | reg_sp.status_ready_matrix_f0_0 <= reg_sp.status_ready_matrix_f0_0 OR ready_matrix_f0_0; | |
|
355 | reg_sp.status_ready_matrix_f0_1 <= reg_sp.status_ready_matrix_f0_1 OR ready_matrix_f0_1; | |
|
356 | reg_sp.status_ready_matrix_f1 <= reg_sp.status_ready_matrix_f1 OR ready_matrix_f1; | |
|
357 | reg_sp.status_ready_matrix_f2 <= reg_sp.status_ready_matrix_f2 OR ready_matrix_f2; | |
|
358 | ||
|
359 | reg_sp.status_error_anticipating_empty_fifo <= reg_sp.status_error_anticipating_empty_fifo OR error_anticipating_empty_fifo; | |
|
360 | reg_sp.status_error_bad_component_error <= reg_sp.status_error_bad_component_error OR error_bad_component_error; | |
|
361 | all_status: FOR I IN 3 DOWNTO 0 LOOP | |
|
362 | --reg_wp.status_full(I) <= (reg_wp.status_full(I) OR status_full(I)) AND reg_wp.run; | |
|
363 | --reg_wp.status_full_err(I) <= (reg_wp.status_full_err(I) OR status_full_err(I)) AND reg_wp.run; | |
|
364 | --reg_wp.status_new_err(I) <= (reg_wp.status_new_err(I) OR status_new_err(I)) AND reg_wp.run ; | |
|
365 | reg_wp.status_full(I) <= status_full(I) AND reg_wp.run; | |
|
366 | reg_wp.status_full_err(I) <= status_full_err(I) AND reg_wp.run; | |
|
367 | reg_wp.status_new_err(I) <= status_new_err(I) AND reg_wp.run ; | |
|
368 | END LOOP all_status; | |
|
369 | ||
|
370 | paddr := "000000"; | |
|
371 | paddr(7 DOWNTO 2) := apbi.paddr(7 DOWNTO 2); | |
|
372 | prdata <= (OTHERS => '0'); | |
|
373 | IF apbi.psel(pindex) = '1' THEN | |
|
374 | -- APB DMA READ -- | |
|
375 | CASE paddr(7 DOWNTO 2) IS | |
|
376 | -- | |
|
377 | WHEN "000000" => prdata(0) <= reg_sp.config_active_interruption_onNewMatrix; | |
|
378 | prdata(1) <= reg_sp.config_active_interruption_onError; | |
|
379 | prdata(2) <= reg_sp.config_ms_run; | |
|
380 | WHEN "000001" => prdata(0) <= reg_sp.status_ready_matrix_f0_0; | |
|
381 | prdata(1) <= reg_sp.status_ready_matrix_f0_1; | |
|
382 | prdata(2) <= reg_sp.status_ready_matrix_f1; | |
|
383 | prdata(3) <= reg_sp.status_ready_matrix_f2; | |
|
384 | prdata(4) <= reg_sp.status_error_anticipating_empty_fifo; | |
|
385 | prdata(5) <= reg_sp.status_error_bad_component_error; | |
|
386 | WHEN "000010" => prdata <= reg_sp.addr_matrix_f0_0; | |
|
387 | WHEN "000011" => prdata <= reg_sp.addr_matrix_f0_1; | |
|
388 | WHEN "000100" => prdata <= reg_sp.addr_matrix_f1; | |
|
389 | WHEN "000101" => prdata <= reg_sp.addr_matrix_f2; | |
|
390 | ||
|
391 | WHEN "000110" => prdata <= reg_sp.coarse_time_f0_0; | |
|
392 | WHEN "000111" => prdata <= reg_sp.coarse_time_f0_1; | |
|
393 | WHEN "001000" => prdata <= reg_sp.coarse_time_f1; | |
|
394 | WHEN "001001" => prdata <= reg_sp.coarse_time_f2; | |
|
395 | WHEN "001010" => prdata(15 downto 0) <= matrix_time_f0_0(15 DOWNTO 0);--reg_sp.fine_time_f0_0; | |
|
396 | WHEN "001011" => prdata(15 downto 0) <= matrix_time_f0_1(15 DOWNTO 0);--reg_sp.fine_time_f0_1; | |
|
397 | WHEN "001100" => prdata(15 downto 0) <= matrix_time_f1 (15 DOWNTO 0);--reg_sp.fine_time_f1; | |
|
398 | WHEN "001101" => prdata(15 downto 0) <= matrix_time_f2 (15 DOWNTO 0);--reg_sp.fine_time_f2; | |
|
399 | ||
|
400 | WHEN "001111" => prdata <= debug_reg; | |
|
401 | --------------------------------------------------------------------- | |
|
402 | WHEN "010000" => prdata(0) <= reg_wp.data_shaping_BW; | |
|
403 | prdata(1) <= reg_wp.data_shaping_SP0; | |
|
404 | prdata(2) <= reg_wp.data_shaping_SP1; | |
|
405 | prdata(3) <= reg_wp.data_shaping_R0; | |
|
406 | prdata(4) <= reg_wp.data_shaping_R1; | |
|
407 | WHEN "010001" => prdata(0) <= reg_wp.enable_f0; | |
|
408 | prdata(1) <= reg_wp.enable_f1; | |
|
409 | prdata(2) <= reg_wp.enable_f2; | |
|
410 | prdata(3) <= reg_wp.enable_f3; | |
|
411 | prdata(4) <= reg_wp.burst_f0; | |
|
412 | prdata(5) <= reg_wp.burst_f1; | |
|
413 | prdata(6) <= reg_wp.burst_f2; | |
|
414 | prdata(7) <= reg_wp.run; | |
|
415 | WHEN "010010" => prdata <= reg_wp.addr_data_f0; | |
|
416 | WHEN "010011" => prdata <= reg_wp.addr_data_f1; | |
|
417 | WHEN "010100" => prdata <= reg_wp.addr_data_f2; | |
|
418 | WHEN "010101" => prdata <= reg_wp.addr_data_f3; | |
|
419 | WHEN "010110" => prdata(3 DOWNTO 0) <= reg_wp.status_full; | |
|
420 | prdata(7 DOWNTO 4) <= reg_wp.status_full_err; | |
|
421 | prdata(11 DOWNTO 8) <= reg_wp.status_new_err; | |
|
422 | WHEN "010111" => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_snapshot; | |
|
423 | WHEN "011000" => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_f0; | |
|
424 | WHEN "011001" => prdata(delta_vector_size_f0_2-1 DOWNTO 0) <= reg_wp.delta_f0_2; | |
|
425 | WHEN "011010" => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_f1; | |
|
426 | WHEN "011011" => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_f2; | |
|
427 | WHEN "011100" => prdata(nb_data_by_buffer_size-1 DOWNTO 0) <= reg_wp.nb_data_by_buffer; | |
|
428 | WHEN "011101" => prdata(nb_snapshot_param_size-1 DOWNTO 0) <= reg_wp.nb_snapshot_param; | |
|
429 | WHEN "011110" => prdata(30 DOWNTO 0) <= reg_wp.start_date; | |
|
430 | WHEN "011111" => prdata(nb_word_by_buffer_size-1 DOWNTO 0) <= reg_wp.nb_word_by_buffer; | |
|
431 | ---------------------------------------------------- | |
|
432 | WHEN "100000" => prdata(31 DOWNTO 0) <= debug_reg0(31 DOWNTO 0); | |
|
433 | WHEN "100001" => prdata(31 DOWNTO 0) <= debug_reg1(31 DOWNTO 0); | |
|
434 | WHEN "100010" => prdata(31 DOWNTO 0) <= debug_reg2(31 DOWNTO 0); | |
|
435 | WHEN "100011" => prdata(31 DOWNTO 0) <= debug_reg3(31 DOWNTO 0); | |
|
436 | WHEN "100100" => prdata(31 DOWNTO 0) <= debug_reg4(31 DOWNTO 0); | |
|
437 | WHEN "100101" => prdata(31 DOWNTO 0) <= debug_reg5(31 DOWNTO 0); | |
|
438 | WHEN "100110" => prdata(31 DOWNTO 0) <= debug_reg6(31 DOWNTO 0); | |
|
439 | WHEN "100111" => prdata(31 DOWNTO 0) <= debug_reg7(31 DOWNTO 0); | |
|
440 | ---------------------------------------------------- | |
|
441 | WHEN "111100" => prdata(23 DOWNTO 0) <= top_lfr_version(23 DOWNTO 0); | |
|
442 | WHEN OTHERS => NULL; | |
|
443 | ||
|
444 | END CASE; | |
|
445 | IF (apbi.pwrite AND apbi.penable) = '1' THEN | |
|
446 | -- APB DMA WRITE -- | |
|
447 | CASE paddr(7 DOWNTO 2) IS | |
|
448 | -- | |
|
449 | WHEN "000000" => reg_sp.config_active_interruption_onNewMatrix <= apbi.pwdata(0); | |
|
450 | reg_sp.config_active_interruption_onError <= apbi.pwdata(1); | |
|
451 | reg_sp.config_ms_run <= apbi.pwdata(2); | |
|
452 | WHEN "000001" => reg_sp.status_ready_matrix_f0_0 <= apbi.pwdata(0); | |
|
453 | reg_sp.status_ready_matrix_f0_1 <= apbi.pwdata(1); | |
|
454 | reg_sp.status_ready_matrix_f1 <= apbi.pwdata(2); | |
|
455 | reg_sp.status_ready_matrix_f2 <= apbi.pwdata(3); | |
|
456 | reg_sp.status_error_anticipating_empty_fifo <= apbi.pwdata(4); | |
|
457 | reg_sp.status_error_bad_component_error <= apbi.pwdata(5); | |
|
458 | WHEN "000010" => reg_sp.addr_matrix_f0_0 <= apbi.pwdata; | |
|
459 | WHEN "000011" => reg_sp.addr_matrix_f0_1 <= apbi.pwdata; | |
|
460 | WHEN "000100" => reg_sp.addr_matrix_f1 <= apbi.pwdata; | |
|
461 | WHEN "000101" => reg_sp.addr_matrix_f2 <= apbi.pwdata; | |
|
462 | -- | |
|
463 | WHEN "010000" => reg_wp.data_shaping_BW <= apbi.pwdata(0); | |
|
464 | reg_wp.data_shaping_SP0 <= apbi.pwdata(1); | |
|
465 | reg_wp.data_shaping_SP1 <= apbi.pwdata(2); | |
|
466 | reg_wp.data_shaping_R0 <= apbi.pwdata(3); | |
|
467 | reg_wp.data_shaping_R1 <= apbi.pwdata(4); | |
|
468 | WHEN "010001" => reg_wp.enable_f0 <= apbi.pwdata(0); | |
|
469 | reg_wp.enable_f1 <= apbi.pwdata(1); | |
|
470 | reg_wp.enable_f2 <= apbi.pwdata(2); | |
|
471 | reg_wp.enable_f3 <= apbi.pwdata(3); | |
|
472 | reg_wp.burst_f0 <= apbi.pwdata(4); | |
|
473 | reg_wp.burst_f1 <= apbi.pwdata(5); | |
|
474 | reg_wp.burst_f2 <= apbi.pwdata(6); | |
|
475 | reg_wp.run <= apbi.pwdata(7); | |
|
476 | WHEN "010010" => reg_wp.addr_data_f0 <= apbi.pwdata; | |
|
477 | WHEN "010011" => reg_wp.addr_data_f1 <= apbi.pwdata; | |
|
478 | WHEN "010100" => reg_wp.addr_data_f2 <= apbi.pwdata; | |
|
479 | WHEN "010101" => reg_wp.addr_data_f3 <= apbi.pwdata; | |
|
480 | WHEN "010110" => reg_wp.status_full <= apbi.pwdata(3 DOWNTO 0); | |
|
481 | reg_wp.status_full_err <= apbi.pwdata(7 DOWNTO 4); | |
|
482 | reg_wp.status_new_err <= apbi.pwdata(11 DOWNTO 8); | |
|
483 | status_full_ack(0) <= reg_wp.status_full(0) AND NOT apbi.pwdata(0); | |
|
484 | status_full_ack(1) <= reg_wp.status_full(1) AND NOT apbi.pwdata(1); | |
|
485 | status_full_ack(2) <= reg_wp.status_full(2) AND NOT apbi.pwdata(2); | |
|
486 | status_full_ack(3) <= reg_wp.status_full(3) AND NOT apbi.pwdata(3); | |
|
487 | WHEN "010111" => reg_wp.delta_snapshot <= apbi.pwdata(delta_vector_size-1 DOWNTO 0); | |
|
488 | WHEN "011000" => reg_wp.delta_f0 <= apbi.pwdata(delta_vector_size-1 DOWNTO 0); | |
|
489 | WHEN "011001" => reg_wp.delta_f0_2 <= apbi.pwdata(delta_vector_size_f0_2-1 DOWNTO 0); | |
|
490 | WHEN "011010" => reg_wp.delta_f1 <= apbi.pwdata(delta_vector_size-1 DOWNTO 0); | |
|
491 | WHEN "011011" => reg_wp.delta_f2 <= apbi.pwdata(delta_vector_size-1 DOWNTO 0); | |
|
492 | WHEN "011100" => reg_wp.nb_data_by_buffer <= apbi.pwdata(nb_data_by_buffer_size-1 DOWNTO 0); | |
|
493 | WHEN "011101" => reg_wp.nb_snapshot_param <= apbi.pwdata(nb_snapshot_param_size-1 DOWNTO 0); | |
|
494 | WHEN "011110" => reg_wp.start_date <= apbi.pwdata(30 DOWNTO 0); | |
|
495 | WHEN "011111" => reg_wp.nb_word_by_buffer <= apbi.pwdata(nb_word_by_buffer_size-1 DOWNTO 0); | |
|
496 | -- | |
|
497 | WHEN OTHERS => NULL; | |
|
498 | END CASE; | |
|
499 | END IF; | |
|
500 | END IF; | |
|
501 | ||
|
502 | apbo.pirq(pirq_ms) <= ((reg_sp.config_active_interruption_onNewMatrix AND (ready_matrix_f0_0 OR | |
|
503 | ready_matrix_f0_1 OR | |
|
504 | ready_matrix_f1 OR | |
|
505 | ready_matrix_f2) | |
|
506 | ) | |
|
507 | OR | |
|
508 | (reg_sp.config_active_interruption_onError AND (error_anticipating_empty_fifo OR | |
|
509 | error_bad_component_error) | |
|
510 | )); | |
|
511 | ||
|
512 | apbo.pirq(pirq_wfp) <= ored_irq_wfp; | |
|
513 | ||
|
514 | END IF; | |
|
515 | END PROCESS lpp_lfr_apbreg; | |
|
516 | ||
|
517 | apbo.pindex <= pindex; | |
|
518 | apbo.pconfig <= pconfig; | |
|
519 | apbo.prdata <= prdata; | |
|
520 | ||
|
521 | ----------------------------------------------------------------------------- | |
|
522 | -- IRQ | |
|
523 | ----------------------------------------------------------------------------- | |
|
524 | irq_wfp_reg_s <= status_full & status_full_err & status_new_err; | |
|
525 | ||
|
526 | PROCESS (HCLK, HRESETn) | |
|
527 | BEGIN -- PROCESS | |
|
528 | IF HRESETn = '0' THEN -- asynchronous reset (active low) | |
|
529 | irq_wfp_reg <= (OTHERS => '0'); | |
|
530 | ELSIF HCLK'event AND HCLK = '1' THEN -- rising clock edge | |
|
531 | irq_wfp_reg <= irq_wfp_reg_s; | |
|
532 | END IF; | |
|
533 | END PROCESS; | |
|
534 | ||
|
535 | all_irq_wfp: FOR I IN IRQ_WFP_SIZE-1 DOWNTO 0 GENERATE | |
|
536 | irq_wfp(I) <= (NOT irq_wfp_reg(I)) AND irq_wfp_reg_s(I); | |
|
537 | END GENERATE all_irq_wfp; | |
|
538 | ||
|
539 | irq_wfp_ZERO <= (OTHERS => '0'); | |
|
540 | ored_irq_wfp <= '0' WHEN irq_wfp = irq_wfp_ZERO ELSE '1'; | |
|
541 | ||
|
542 | run_ms <= reg_sp.config_ms_run; | |
|
543 | ||
|
544 |
END beh; |
|
|
1 | ------------------------------------------------------------------------------ | |
|
2 | -- This file is a part of the LPP VHDL IP LIBRARY | |
|
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS | |
|
4 | -- | |
|
5 | -- This program is free software; you can redistribute it and/or modify | |
|
6 | -- it under the terms of the GNU General Public License as published by | |
|
7 | -- the Free Software Foundation; either version 3 of the License, or | |
|
8 | -- (at your option) any later version. | |
|
9 | -- | |
|
10 | -- This program is distributed in the hope that it will be useful, | |
|
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of | |
|
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
|
13 | -- GNU General Public License for more details. | |
|
14 | -- | |
|
15 | -- You should have received a copy of the GNU General Public License | |
|
16 | -- along with this program; if not, write to the Free Software | |
|
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
|
18 | ------------------------------------------------------------------------------- | |
|
19 | -- Author : Jean-christophe Pellion | |
|
20 | -- Mail : jean-christophe.pellion@lpp.polytechnique.fr | |
|
21 | -- jean-christophe.pellion@easii-ic.com | |
|
22 | ---------------------------------------------------------------------------- | |
|
23 | LIBRARY ieee; | |
|
24 | USE ieee.std_logic_1164.ALL; | |
|
25 | USE ieee.numeric_std.ALL; | |
|
26 | LIBRARY grlib; | |
|
27 | USE grlib.amba.ALL; | |
|
28 | USE grlib.stdlib.ALL; | |
|
29 | USE grlib.devices.ALL; | |
|
30 | LIBRARY lpp; | |
|
31 | USE lpp.lpp_amba.ALL; | |
|
32 | USE lpp.apb_devices_list.ALL; | |
|
33 | USE lpp.lpp_memory.ALL; | |
|
34 | LIBRARY techmap; | |
|
35 | USE techmap.gencomp.ALL; | |
|
36 | ||
|
37 | ENTITY lpp_lfr_apbreg IS | |
|
38 | GENERIC ( | |
|
39 | nb_data_by_buffer_size : INTEGER := 11; | |
|
40 | nb_word_by_buffer_size : INTEGER := 11; | |
|
41 | nb_snapshot_param_size : INTEGER := 11; | |
|
42 | delta_vector_size : INTEGER := 20; | |
|
43 | delta_vector_size_f0_2 : INTEGER := 3; | |
|
44 | ||
|
45 | pindex : INTEGER := 4; | |
|
46 | paddr : INTEGER := 4; | |
|
47 | pmask : INTEGER := 16#fff#; | |
|
48 | pirq_ms : INTEGER := 0; | |
|
49 | pirq_wfp : INTEGER := 1; | |
|
50 | top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0) := X"000000"); | |
|
51 | PORT ( | |
|
52 | -- AMBA AHB system signals | |
|
53 | HCLK : IN STD_ULOGIC; | |
|
54 | HRESETn : IN STD_ULOGIC; | |
|
55 | ||
|
56 | -- AMBA APB Slave Interface | |
|
57 | apbi : IN apb_slv_in_type; | |
|
58 | apbo : OUT apb_slv_out_type; | |
|
59 | ||
|
60 | --------------------------------------------------------------------------- | |
|
61 | -- Spectral Matrix Reg | |
|
62 | run_ms : OUT STD_LOGIC; | |
|
63 | -- IN | |
|
64 | ready_matrix_f0_0 : IN STD_LOGIC; | |
|
65 | ready_matrix_f0_1 : IN STD_LOGIC; | |
|
66 | ready_matrix_f1 : IN STD_LOGIC; | |
|
67 | ready_matrix_f2 : IN STD_LOGIC; | |
|
68 | error_anticipating_empty_fifo : IN STD_LOGIC; | |
|
69 | error_bad_component_error : IN STD_LOGIC; | |
|
70 | debug_reg : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
71 | ||
|
72 | -- OUT | |
|
73 | status_ready_matrix_f0_0 : OUT STD_LOGIC; | |
|
74 | status_ready_matrix_f0_1 : OUT STD_LOGIC; | |
|
75 | status_ready_matrix_f1 : OUT STD_LOGIC; | |
|
76 | status_ready_matrix_f2 : OUT STD_LOGIC; | |
|
77 | status_error_anticipating_empty_fifo : OUT STD_LOGIC; | |
|
78 | status_error_bad_component_error : OUT STD_LOGIC; | |
|
79 | ||
|
80 | config_active_interruption_onNewMatrix : OUT STD_LOGIC; | |
|
81 | config_active_interruption_onError : OUT STD_LOGIC; | |
|
82 | ||
|
83 | addr_matrix_f0_0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
84 | addr_matrix_f0_1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
85 | addr_matrix_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
86 | addr_matrix_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
87 | ||
|
88 | matrix_time_f0_0 : IN STD_LOGIC_VECTOR(47 DOWNTO 0); | |
|
89 | matrix_time_f0_1 : IN STD_LOGIC_VECTOR(47 DOWNTO 0); | |
|
90 | matrix_time_f1 : IN STD_LOGIC_VECTOR(47 DOWNTO 0); | |
|
91 | matrix_time_f2 : IN STD_LOGIC_VECTOR(47 DOWNTO 0); | |
|
92 | ||
|
93 | --------------------------------------------------------------------------- | |
|
94 | --------------------------------------------------------------------------- | |
|
95 | -- WaveForm picker Reg | |
|
96 | status_full : IN STD_LOGIC_VECTOR(3 DOWNTO 0); | |
|
97 | status_full_ack : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); | |
|
98 | status_full_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0); | |
|
99 | status_new_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0); | |
|
100 | ||
|
101 | -- OUT | |
|
102 | data_shaping_BW : OUT STD_LOGIC; | |
|
103 | data_shaping_SP0 : OUT STD_LOGIC; | |
|
104 | data_shaping_SP1 : OUT STD_LOGIC; | |
|
105 | data_shaping_R0 : OUT STD_LOGIC; | |
|
106 | data_shaping_R1 : OUT STD_LOGIC; | |
|
107 | ||
|
108 | delta_snapshot : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); | |
|
109 | delta_f0 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); | |
|
110 | delta_f0_2 : OUT STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0); | |
|
111 | delta_f1 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); | |
|
112 | delta_f2 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); | |
|
113 | nb_data_by_buffer : OUT STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0); | |
|
114 | nb_word_by_buffer : OUT STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0); | |
|
115 | nb_snapshot_param : OUT STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0); | |
|
116 | ||
|
117 | enable_f0 : OUT STD_LOGIC; | |
|
118 | enable_f1 : OUT STD_LOGIC; | |
|
119 | enable_f2 : OUT STD_LOGIC; | |
|
120 | enable_f3 : OUT STD_LOGIC; | |
|
121 | ||
|
122 | burst_f0 : OUT STD_LOGIC; | |
|
123 | burst_f1 : OUT STD_LOGIC; | |
|
124 | burst_f2 : OUT STD_LOGIC; | |
|
125 | ||
|
126 | run : OUT STD_LOGIC; | |
|
127 | ||
|
128 | addr_data_f0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
129 | addr_data_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
130 | addr_data_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
131 | addr_data_f3 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
132 | start_date : OUT STD_LOGIC_VECTOR(30 DOWNTO 0); | |
|
133 | --------------------------------------------------------------------------- | |
|
134 | debug_reg0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
135 | debug_reg1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
136 | debug_reg2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
137 | debug_reg3 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
138 | debug_reg4 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
139 | debug_reg5 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
140 | debug_reg6 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
141 | debug_reg7 : IN STD_LOGIC_VECTOR(31 DOWNTO 0) | |
|
142 | ||
|
143 | --------------------------------------------------------------------------- | |
|
144 | ); | |
|
145 | ||
|
146 | END lpp_lfr_apbreg; | |
|
147 | ||
|
148 | ARCHITECTURE beh OF lpp_lfr_apbreg IS | |
|
149 | ||
|
150 | CONSTANT REVISION : INTEGER := 1; | |
|
151 | ||
|
152 | CONSTANT pconfig : apb_config_type := ( | |
|
153 | 0 => ahb_device_reg (VENDOR_LPP, LPP_LFR, 0, REVISION, pirq_wfp), | |
|
154 | 1 => apb_iobar(paddr, pmask)); | |
|
155 | ||
|
156 | TYPE lpp_SpectralMatrix_regs IS RECORD | |
|
157 | config_active_interruption_onNewMatrix : STD_LOGIC; | |
|
158 | config_active_interruption_onError : STD_LOGIC; | |
|
159 | config_ms_run : STD_LOGIC; | |
|
160 | status_ready_matrix_f0_0 : STD_LOGIC; | |
|
161 | status_ready_matrix_f0_1 : STD_LOGIC; | |
|
162 | status_ready_matrix_f1 : STD_LOGIC; | |
|
163 | status_ready_matrix_f2 : STD_LOGIC; | |
|
164 | status_error_anticipating_empty_fifo : STD_LOGIC; | |
|
165 | status_error_bad_component_error : STD_LOGIC; | |
|
166 | addr_matrix_f0_0 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
167 | addr_matrix_f0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
168 | addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
169 | addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
170 | ||
|
171 | coarse_time_f0_0 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
172 | coarse_time_f0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
173 | coarse_time_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
174 | coarse_time_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
175 | ||
|
176 | -- fine_time_f0_0 : STD_LOGIC_VECTOR(15 DOWNTO 0); | |
|
177 | -- fine_time_f0_1 : STD_LOGIC_VECTOR(15 DOWNTO 0); | |
|
178 | -- fine_time_f1 : STD_LOGIC_VECTOR(15 DOWNTO 0); | |
|
179 | -- fine_time_f2 : STD_LOGIC_VECTOR(15 DOWNTO 0); | |
|
180 | END RECORD; | |
|
181 | SIGNAL reg_sp : lpp_SpectralMatrix_regs; | |
|
182 | ||
|
183 | TYPE lpp_WaveformPicker_regs IS RECORD | |
|
184 | status_full : STD_LOGIC_VECTOR(3 DOWNTO 0); | |
|
185 | status_full_err : STD_LOGIC_VECTOR(3 DOWNTO 0); | |
|
186 | status_new_err : STD_LOGIC_VECTOR(3 DOWNTO 0); | |
|
187 | data_shaping_BW : STD_LOGIC; | |
|
188 | data_shaping_SP0 : STD_LOGIC; | |
|
189 | data_shaping_SP1 : STD_LOGIC; | |
|
190 | data_shaping_R0 : STD_LOGIC; | |
|
191 | data_shaping_R1 : STD_LOGIC; | |
|
192 | delta_snapshot : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); | |
|
193 | delta_f0 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); | |
|
194 | delta_f0_2 : STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0); | |
|
195 | delta_f1 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); | |
|
196 | delta_f2 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); | |
|
197 | nb_data_by_buffer : STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0); | |
|
198 | nb_word_by_buffer : STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0); | |
|
199 | nb_snapshot_param : STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0); | |
|
200 | enable_f0 : STD_LOGIC; | |
|
201 | enable_f1 : STD_LOGIC; | |
|
202 | enable_f2 : STD_LOGIC; | |
|
203 | enable_f3 : STD_LOGIC; | |
|
204 | burst_f0 : STD_LOGIC; | |
|
205 | burst_f1 : STD_LOGIC; | |
|
206 | burst_f2 : STD_LOGIC; | |
|
207 | run : STD_LOGIC; | |
|
208 | addr_data_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
209 | addr_data_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
210 | addr_data_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
211 | addr_data_f3 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
212 | start_date : STD_LOGIC_VECTOR(30 DOWNTO 0); | |
|
213 | END RECORD; | |
|
214 | SIGNAL reg_wp : lpp_WaveformPicker_regs; | |
|
215 | ||
|
216 | SIGNAL prdata : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
217 | ||
|
218 | ----------------------------------------------------------------------------- | |
|
219 | -- IRQ | |
|
220 | ----------------------------------------------------------------------------- | |
|
221 | CONSTANT IRQ_WFP_SIZE : INTEGER := 12; | |
|
222 | SIGNAL irq_wfp_ZERO : STD_LOGIC_VECTOR(IRQ_WFP_SIZE-1 DOWNTO 0); | |
|
223 | SIGNAL irq_wfp_reg_s : STD_LOGIC_VECTOR(IRQ_WFP_SIZE-1 DOWNTO 0); | |
|
224 | SIGNAL irq_wfp_reg : STD_LOGIC_VECTOR(IRQ_WFP_SIZE-1 DOWNTO 0); | |
|
225 | SIGNAL irq_wfp : STD_LOGIC_VECTOR(IRQ_WFP_SIZE-1 DOWNTO 0); | |
|
226 | SIGNAL ored_irq_wfp : STD_LOGIC; | |
|
227 | ||
|
228 | BEGIN -- beh | |
|
229 | ||
|
230 | status_ready_matrix_f0_0 <= reg_sp.status_ready_matrix_f0_0; | |
|
231 | status_ready_matrix_f0_1 <= reg_sp.status_ready_matrix_f0_1; | |
|
232 | status_ready_matrix_f1 <= reg_sp.status_ready_matrix_f1; | |
|
233 | status_ready_matrix_f2 <= reg_sp.status_ready_matrix_f2; | |
|
234 | status_error_anticipating_empty_fifo <= reg_sp.status_error_anticipating_empty_fifo; | |
|
235 | status_error_bad_component_error <= reg_sp.status_error_bad_component_error; | |
|
236 | ||
|
237 | config_active_interruption_onNewMatrix <= reg_sp.config_active_interruption_onNewMatrix; | |
|
238 | config_active_interruption_onError <= reg_sp.config_active_interruption_onError; | |
|
239 | addr_matrix_f0_0 <= reg_sp.addr_matrix_f0_0; | |
|
240 | addr_matrix_f0_1 <= reg_sp.addr_matrix_f0_1; | |
|
241 | addr_matrix_f1 <= reg_sp.addr_matrix_f1; | |
|
242 | addr_matrix_f2 <= reg_sp.addr_matrix_f2; | |
|
243 | ||
|
244 | ||
|
245 | data_shaping_BW <= NOT reg_wp.data_shaping_BW; | |
|
246 | data_shaping_SP0 <= reg_wp.data_shaping_SP0; | |
|
247 | data_shaping_SP1 <= reg_wp.data_shaping_SP1; | |
|
248 | data_shaping_R0 <= reg_wp.data_shaping_R0; | |
|
249 | data_shaping_R1 <= reg_wp.data_shaping_R1; | |
|
250 | ||
|
251 | delta_snapshot <= reg_wp.delta_snapshot; | |
|
252 | delta_f0 <= reg_wp.delta_f0; | |
|
253 | delta_f0_2 <= reg_wp.delta_f0_2; | |
|
254 | delta_f1 <= reg_wp.delta_f1; | |
|
255 | delta_f2 <= reg_wp.delta_f2; | |
|
256 | nb_data_by_buffer <= reg_wp.nb_data_by_buffer; | |
|
257 | nb_word_by_buffer <= reg_wp.nb_word_by_buffer; | |
|
258 | nb_snapshot_param <= reg_wp.nb_snapshot_param; | |
|
259 | ||
|
260 | enable_f0 <= reg_wp.enable_f0; | |
|
261 | enable_f1 <= reg_wp.enable_f1; | |
|
262 | enable_f2 <= reg_wp.enable_f2; | |
|
263 | enable_f3 <= reg_wp.enable_f3; | |
|
264 | ||
|
265 | burst_f0 <= reg_wp.burst_f0; | |
|
266 | burst_f1 <= reg_wp.burst_f1; | |
|
267 | burst_f2 <= reg_wp.burst_f2; | |
|
268 | ||
|
269 | run <= reg_wp.run; | |
|
270 | ||
|
271 | addr_data_f0 <= reg_wp.addr_data_f0; | |
|
272 | addr_data_f1 <= reg_wp.addr_data_f1; | |
|
273 | addr_data_f2 <= reg_wp.addr_data_f2; | |
|
274 | addr_data_f3 <= reg_wp.addr_data_f3; | |
|
275 | ||
|
276 | start_date <= reg_wp.start_date; | |
|
277 | ||
|
278 | lpp_lfr_apbreg : PROCESS (HCLK, HRESETn) | |
|
279 | VARIABLE paddr : STD_LOGIC_VECTOR(7 DOWNTO 2); | |
|
280 | BEGIN -- PROCESS lpp_dma_top | |
|
281 | IF HRESETn = '0' THEN -- asynchronous reset (active low) | |
|
282 | reg_sp.config_active_interruption_onNewMatrix <= '0'; | |
|
283 | reg_sp.config_active_interruption_onError <= '0'; | |
|
284 | reg_sp.config_ms_run <= '1'; | |
|
285 | reg_sp.status_ready_matrix_f0_0 <= '0'; | |
|
286 | reg_sp.status_ready_matrix_f0_1 <= '0'; | |
|
287 | reg_sp.status_ready_matrix_f1 <= '0'; | |
|
288 | reg_sp.status_ready_matrix_f2 <= '0'; | |
|
289 | reg_sp.status_error_anticipating_empty_fifo <= '0'; | |
|
290 | reg_sp.status_error_bad_component_error <= '0'; | |
|
291 | reg_sp.addr_matrix_f0_0 <= (OTHERS => '0'); | |
|
292 | reg_sp.addr_matrix_f0_1 <= (OTHERS => '0'); | |
|
293 | reg_sp.addr_matrix_f1 <= (OTHERS => '0'); | |
|
294 | reg_sp.addr_matrix_f2 <= (OTHERS => '0'); | |
|
295 | ||
|
296 | reg_sp.coarse_time_f0_0 <= (OTHERS => '0'); | |
|
297 | reg_sp.coarse_time_f0_1 <= (OTHERS => '0'); | |
|
298 | reg_sp.coarse_time_f1 <= (OTHERS => '0'); | |
|
299 | reg_sp.coarse_time_f2 <= (OTHERS => '0'); | |
|
300 | --reg_sp.fine_time_f0_0 <= (OTHERS => '0'); | |
|
301 | --reg_sp.fine_time_f0_1 <= (OTHERS => '0'); | |
|
302 | --reg_sp.fine_time_f1 <= (OTHERS => '0'); | |
|
303 | --reg_sp.fine_time_f2 <= (OTHERS => '0'); | |
|
304 | ||
|
305 | prdata <= (OTHERS => '0'); | |
|
306 | ||
|
307 | apbo.pirq <= (OTHERS => '0'); | |
|
308 | ||
|
309 | status_full_ack <= (OTHERS => '0'); | |
|
310 | ||
|
311 | reg_wp.data_shaping_BW <= '0'; | |
|
312 | reg_wp.data_shaping_SP0 <= '0'; | |
|
313 | reg_wp.data_shaping_SP1 <= '0'; | |
|
314 | reg_wp.data_shaping_R0 <= '0'; | |
|
315 | reg_wp.data_shaping_R1 <= '0'; | |
|
316 | reg_wp.enable_f0 <= '0'; | |
|
317 | reg_wp.enable_f1 <= '0'; | |
|
318 | reg_wp.enable_f2 <= '0'; | |
|
319 | reg_wp.enable_f3 <= '0'; | |
|
320 | reg_wp.burst_f0 <= '0'; | |
|
321 | reg_wp.burst_f1 <= '0'; | |
|
322 | reg_wp.burst_f2 <= '0'; | |
|
323 | reg_wp.run <= '0'; | |
|
324 | reg_wp.addr_data_f0 <= (OTHERS => '0'); | |
|
325 | reg_wp.addr_data_f1 <= (OTHERS => '0'); | |
|
326 | reg_wp.addr_data_f2 <= (OTHERS => '0'); | |
|
327 | reg_wp.addr_data_f3 <= (OTHERS => '0'); | |
|
328 | reg_wp.status_full <= (OTHERS => '0'); | |
|
329 | reg_wp.status_full_err <= (OTHERS => '0'); | |
|
330 | reg_wp.status_new_err <= (OTHERS => '0'); | |
|
331 | reg_wp.delta_snapshot <= (OTHERS => '0'); | |
|
332 | reg_wp.delta_f0 <= (OTHERS => '0'); | |
|
333 | reg_wp.delta_f0_2 <= (OTHERS => '0'); | |
|
334 | reg_wp.delta_f1 <= (OTHERS => '0'); | |
|
335 | reg_wp.delta_f2 <= (OTHERS => '0'); | |
|
336 | reg_wp.nb_data_by_buffer <= (OTHERS => '0'); | |
|
337 | reg_wp.nb_snapshot_param <= (OTHERS => '0'); | |
|
338 | reg_wp.start_date <= (OTHERS => '0'); | |
|
339 | ||
|
340 | ELSIF HCLK'EVENT AND HCLK = '1' THEN -- rising clock edge | |
|
341 | ||
|
342 | reg_sp.coarse_time_f0_0 <= matrix_time_f0_0(31 DOWNTO 0); | |
|
343 | reg_sp.coarse_time_f0_1 <= matrix_time_f0_1(31 DOWNTO 0); | |
|
344 | reg_sp.coarse_time_f1 <= matrix_time_f1 (31 DOWNTO 0); | |
|
345 | reg_sp.coarse_time_f2 <= matrix_time_f2 (31 DOWNTO 0); | |
|
346 | ||
|
347 | --reg_sp.fine_time_f0_0 <= matrix_time_f0_0(15 DOWNTO 0); | |
|
348 | --reg_sp.fine_time_f0_1 <= matrix_time_f0_1(15 DOWNTO 0); | |
|
349 | --reg_sp.fine_time_f1 <= matrix_time_f1 (15 DOWNTO 0); | |
|
350 | --reg_sp.fine_time_f2 <= matrix_time_f2 (15 DOWNTO 0); | |
|
351 | ||
|
352 | status_full_ack <= (OTHERS => '0'); | |
|
353 | ||
|
354 | reg_sp.status_ready_matrix_f0_0 <= reg_sp.status_ready_matrix_f0_0 OR ready_matrix_f0_0; | |
|
355 | reg_sp.status_ready_matrix_f0_1 <= reg_sp.status_ready_matrix_f0_1 OR ready_matrix_f0_1; | |
|
356 | reg_sp.status_ready_matrix_f1 <= reg_sp.status_ready_matrix_f1 OR ready_matrix_f1; | |
|
357 | reg_sp.status_ready_matrix_f2 <= reg_sp.status_ready_matrix_f2 OR ready_matrix_f2; | |
|
358 | ||
|
359 | reg_sp.status_error_anticipating_empty_fifo <= reg_sp.status_error_anticipating_empty_fifo OR error_anticipating_empty_fifo; | |
|
360 | reg_sp.status_error_bad_component_error <= reg_sp.status_error_bad_component_error OR error_bad_component_error; | |
|
361 | all_status: FOR I IN 3 DOWNTO 0 LOOP | |
|
362 | --reg_wp.status_full(I) <= (reg_wp.status_full(I) OR status_full(I)) AND reg_wp.run; | |
|
363 | --reg_wp.status_full_err(I) <= (reg_wp.status_full_err(I) OR status_full_err(I)) AND reg_wp.run; | |
|
364 | --reg_wp.status_new_err(I) <= (reg_wp.status_new_err(I) OR status_new_err(I)) AND reg_wp.run ; | |
|
365 | reg_wp.status_full(I) <= status_full(I) AND reg_wp.run; | |
|
366 | reg_wp.status_full_err(I) <= status_full_err(I) AND reg_wp.run; | |
|
367 | reg_wp.status_new_err(I) <= status_new_err(I) AND reg_wp.run ; | |
|
368 | END LOOP all_status; | |
|
369 | ||
|
370 | paddr := "000000"; | |
|
371 | paddr(7 DOWNTO 2) := apbi.paddr(7 DOWNTO 2); | |
|
372 | prdata <= (OTHERS => '0'); | |
|
373 | IF apbi.psel(pindex) = '1' THEN | |
|
374 | -- APB DMA READ -- | |
|
375 | CASE paddr(7 DOWNTO 2) IS | |
|
376 | -- | |
|
377 | WHEN "000000" => prdata(0) <= reg_sp.config_active_interruption_onNewMatrix; | |
|
378 | prdata(1) <= reg_sp.config_active_interruption_onError; | |
|
379 | prdata(2) <= reg_sp.config_ms_run; | |
|
380 | WHEN "000001" => prdata(0) <= reg_sp.status_ready_matrix_f0_0; | |
|
381 | prdata(1) <= reg_sp.status_ready_matrix_f0_1; | |
|
382 | prdata(2) <= reg_sp.status_ready_matrix_f1; | |
|
383 | prdata(3) <= reg_sp.status_ready_matrix_f2; | |
|
384 | prdata(4) <= reg_sp.status_error_anticipating_empty_fifo; | |
|
385 | prdata(5) <= reg_sp.status_error_bad_component_error; | |
|
386 | WHEN "000010" => prdata <= reg_sp.addr_matrix_f0_0; | |
|
387 | WHEN "000011" => prdata <= reg_sp.addr_matrix_f0_1; | |
|
388 | WHEN "000100" => prdata <= reg_sp.addr_matrix_f1; | |
|
389 | WHEN "000101" => prdata <= reg_sp.addr_matrix_f2; | |
|
390 | ||
|
391 | WHEN "000110" => prdata <= reg_sp.coarse_time_f0_0; | |
|
392 | WHEN "000111" => prdata <= reg_sp.coarse_time_f0_1; | |
|
393 | WHEN "001000" => prdata <= reg_sp.coarse_time_f1; | |
|
394 | WHEN "001001" => prdata <= reg_sp.coarse_time_f2; | |
|
395 | WHEN "001010" => prdata(15 downto 0) <= matrix_time_f0_0(15 DOWNTO 0);--reg_sp.fine_time_f0_0; | |
|
396 | WHEN "001011" => prdata(15 downto 0) <= matrix_time_f0_1(15 DOWNTO 0);--reg_sp.fine_time_f0_1; | |
|
397 | WHEN "001100" => prdata(15 downto 0) <= matrix_time_f1 (15 DOWNTO 0);--reg_sp.fine_time_f1; | |
|
398 | WHEN "001101" => prdata(15 downto 0) <= matrix_time_f2 (15 DOWNTO 0);--reg_sp.fine_time_f2; | |
|
399 | ||
|
400 | WHEN "001111" => prdata <= debug_reg; | |
|
401 | --------------------------------------------------------------------- | |
|
402 | WHEN "010000" => prdata(0) <= reg_wp.data_shaping_BW; | |
|
403 | prdata(1) <= reg_wp.data_shaping_SP0; | |
|
404 | prdata(2) <= reg_wp.data_shaping_SP1; | |
|
405 | prdata(3) <= reg_wp.data_shaping_R0; | |
|
406 | prdata(4) <= reg_wp.data_shaping_R1; | |
|
407 | WHEN "010001" => prdata(0) <= reg_wp.enable_f0; | |
|
408 | prdata(1) <= reg_wp.enable_f1; | |
|
409 | prdata(2) <= reg_wp.enable_f2; | |
|
410 | prdata(3) <= reg_wp.enable_f3; | |
|
411 | prdata(4) <= reg_wp.burst_f0; | |
|
412 | prdata(5) <= reg_wp.burst_f1; | |
|
413 | prdata(6) <= reg_wp.burst_f2; | |
|
414 | prdata(7) <= reg_wp.run; | |
|
415 | WHEN "010010" => prdata <= reg_wp.addr_data_f0; | |
|
416 | WHEN "010011" => prdata <= reg_wp.addr_data_f1; | |
|
417 | WHEN "010100" => prdata <= reg_wp.addr_data_f2; | |
|
418 | WHEN "010101" => prdata <= reg_wp.addr_data_f3; | |
|
419 | WHEN "010110" => prdata(3 DOWNTO 0) <= reg_wp.status_full; | |
|
420 | prdata(7 DOWNTO 4) <= reg_wp.status_full_err; | |
|
421 | prdata(11 DOWNTO 8) <= reg_wp.status_new_err; | |
|
422 | WHEN "010111" => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_snapshot; | |
|
423 | WHEN "011000" => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_f0; | |
|
424 | WHEN "011001" => prdata(delta_vector_size_f0_2-1 DOWNTO 0) <= reg_wp.delta_f0_2; | |
|
425 | WHEN "011010" => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_f1; | |
|
426 | WHEN "011011" => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_f2; | |
|
427 | WHEN "011100" => prdata(nb_data_by_buffer_size-1 DOWNTO 0) <= reg_wp.nb_data_by_buffer; | |
|
428 | WHEN "011101" => prdata(nb_snapshot_param_size-1 DOWNTO 0) <= reg_wp.nb_snapshot_param; | |
|
429 | WHEN "011110" => prdata(30 DOWNTO 0) <= reg_wp.start_date; | |
|
430 | WHEN "011111" => prdata(nb_word_by_buffer_size-1 DOWNTO 0) <= reg_wp.nb_word_by_buffer; | |
|
431 | ---------------------------------------------------- | |
|
432 | WHEN "100000" => prdata(31 DOWNTO 0) <= debug_reg0(31 DOWNTO 0); | |
|
433 | WHEN "100001" => prdata(31 DOWNTO 0) <= debug_reg1(31 DOWNTO 0); | |
|
434 | WHEN "100010" => prdata(31 DOWNTO 0) <= debug_reg2(31 DOWNTO 0); | |
|
435 | WHEN "100011" => prdata(31 DOWNTO 0) <= debug_reg3(31 DOWNTO 0); | |
|
436 | WHEN "100100" => prdata(31 DOWNTO 0) <= debug_reg4(31 DOWNTO 0); | |
|
437 | WHEN "100101" => prdata(31 DOWNTO 0) <= debug_reg5(31 DOWNTO 0); | |
|
438 | WHEN "100110" => prdata(31 DOWNTO 0) <= debug_reg6(31 DOWNTO 0); | |
|
439 | WHEN "100111" => prdata(31 DOWNTO 0) <= debug_reg7(31 DOWNTO 0); | |
|
440 | ---------------------------------------------------- | |
|
441 | WHEN "111100" => prdata(23 DOWNTO 0) <= top_lfr_version(23 DOWNTO 0); | |
|
442 | WHEN OTHERS => NULL; | |
|
443 | ||
|
444 | END CASE; | |
|
445 | IF (apbi.pwrite AND apbi.penable) = '1' THEN | |
|
446 | -- APB DMA WRITE -- | |
|
447 | CASE paddr(7 DOWNTO 2) IS | |
|
448 | -- | |
|
449 | WHEN "000000" => reg_sp.config_active_interruption_onNewMatrix <= apbi.pwdata(0); | |
|
450 | reg_sp.config_active_interruption_onError <= apbi.pwdata(1); | |
|
451 | reg_sp.config_ms_run <= apbi.pwdata(2); | |
|
452 | WHEN "000001" => reg_sp.status_ready_matrix_f0_0 <= apbi.pwdata(0); | |
|
453 | reg_sp.status_ready_matrix_f0_1 <= apbi.pwdata(1); | |
|
454 | reg_sp.status_ready_matrix_f1 <= apbi.pwdata(2); | |
|
455 | reg_sp.status_ready_matrix_f2 <= apbi.pwdata(3); | |
|
456 | reg_sp.status_error_anticipating_empty_fifo <= apbi.pwdata(4); | |
|
457 | reg_sp.status_error_bad_component_error <= apbi.pwdata(5); | |
|
458 | WHEN "000010" => reg_sp.addr_matrix_f0_0 <= apbi.pwdata; | |
|
459 | WHEN "000011" => reg_sp.addr_matrix_f0_1 <= apbi.pwdata; | |
|
460 | WHEN "000100" => reg_sp.addr_matrix_f1 <= apbi.pwdata; | |
|
461 | WHEN "000101" => reg_sp.addr_matrix_f2 <= apbi.pwdata; | |
|
462 | -- | |
|
463 | WHEN "010000" => reg_wp.data_shaping_BW <= apbi.pwdata(0); | |
|
464 | reg_wp.data_shaping_SP0 <= apbi.pwdata(1); | |
|
465 | reg_wp.data_shaping_SP1 <= apbi.pwdata(2); | |
|
466 | reg_wp.data_shaping_R0 <= apbi.pwdata(3); | |
|
467 | reg_wp.data_shaping_R1 <= apbi.pwdata(4); | |
|
468 | WHEN "010001" => reg_wp.enable_f0 <= apbi.pwdata(0); | |
|
469 | reg_wp.enable_f1 <= apbi.pwdata(1); | |
|
470 | reg_wp.enable_f2 <= apbi.pwdata(2); | |
|
471 | reg_wp.enable_f3 <= apbi.pwdata(3); | |
|
472 | reg_wp.burst_f0 <= apbi.pwdata(4); | |
|
473 | reg_wp.burst_f1 <= apbi.pwdata(5); | |
|
474 | reg_wp.burst_f2 <= apbi.pwdata(6); | |
|
475 | reg_wp.run <= apbi.pwdata(7); | |
|
476 | WHEN "010010" => reg_wp.addr_data_f0 <= apbi.pwdata; | |
|
477 | WHEN "010011" => reg_wp.addr_data_f1 <= apbi.pwdata; | |
|
478 | WHEN "010100" => reg_wp.addr_data_f2 <= apbi.pwdata; | |
|
479 | WHEN "010101" => reg_wp.addr_data_f3 <= apbi.pwdata; | |
|
480 | WHEN "010110" => reg_wp.status_full <= apbi.pwdata(3 DOWNTO 0); | |
|
481 | reg_wp.status_full_err <= apbi.pwdata(7 DOWNTO 4); | |
|
482 | reg_wp.status_new_err <= apbi.pwdata(11 DOWNTO 8); | |
|
483 | status_full_ack(0) <= reg_wp.status_full(0) AND NOT apbi.pwdata(0); | |
|
484 | status_full_ack(1) <= reg_wp.status_full(1) AND NOT apbi.pwdata(1); | |
|
485 | status_full_ack(2) <= reg_wp.status_full(2) AND NOT apbi.pwdata(2); | |
|
486 | status_full_ack(3) <= reg_wp.status_full(3) AND NOT apbi.pwdata(3); | |
|
487 | WHEN "010111" => reg_wp.delta_snapshot <= apbi.pwdata(delta_vector_size-1 DOWNTO 0); | |
|
488 | WHEN "011000" => reg_wp.delta_f0 <= apbi.pwdata(delta_vector_size-1 DOWNTO 0); | |
|
489 | WHEN "011001" => reg_wp.delta_f0_2 <= apbi.pwdata(delta_vector_size_f0_2-1 DOWNTO 0); | |
|
490 | WHEN "011010" => reg_wp.delta_f1 <= apbi.pwdata(delta_vector_size-1 DOWNTO 0); | |
|
491 | WHEN "011011" => reg_wp.delta_f2 <= apbi.pwdata(delta_vector_size-1 DOWNTO 0); | |
|
492 | WHEN "011100" => reg_wp.nb_data_by_buffer <= apbi.pwdata(nb_data_by_buffer_size-1 DOWNTO 0); | |
|
493 | WHEN "011101" => reg_wp.nb_snapshot_param <= apbi.pwdata(nb_snapshot_param_size-1 DOWNTO 0); | |
|
494 | WHEN "011110" => reg_wp.start_date <= apbi.pwdata(30 DOWNTO 0); | |
|
495 | WHEN "011111" => reg_wp.nb_word_by_buffer <= apbi.pwdata(nb_word_by_buffer_size-1 DOWNTO 0); | |
|
496 | -- | |
|
497 | WHEN OTHERS => NULL; | |
|
498 | END CASE; | |
|
499 | END IF; | |
|
500 | END IF; | |
|
501 | ||
|
502 | apbo.pirq(pirq_ms) <= ((reg_sp.config_active_interruption_onNewMatrix AND (ready_matrix_f0_0 OR | |
|
503 | ready_matrix_f0_1 OR | |
|
504 | ready_matrix_f1 OR | |
|
505 | ready_matrix_f2) | |
|
506 | ) | |
|
507 | OR | |
|
508 | (reg_sp.config_active_interruption_onError AND (error_anticipating_empty_fifo OR | |
|
509 | error_bad_component_error) | |
|
510 | )); | |
|
511 | ||
|
512 | apbo.pirq(pirq_wfp) <= ored_irq_wfp; | |
|
513 | ||
|
514 | END IF; | |
|
515 | END PROCESS lpp_lfr_apbreg; | |
|
516 | ||
|
517 | apbo.pindex <= pindex; | |
|
518 | apbo.pconfig <= pconfig; | |
|
519 | apbo.prdata <= prdata; | |
|
520 | ||
|
521 | ----------------------------------------------------------------------------- | |
|
522 | -- IRQ | |
|
523 | ----------------------------------------------------------------------------- | |
|
524 | irq_wfp_reg_s <= status_full & status_full_err & status_new_err; | |
|
525 | ||
|
526 | PROCESS (HCLK, HRESETn) | |
|
527 | BEGIN -- PROCESS | |
|
528 | IF HRESETn = '0' THEN -- asynchronous reset (active low) | |
|
529 | irq_wfp_reg <= (OTHERS => '0'); | |
|
530 | ELSIF HCLK'event AND HCLK = '1' THEN -- rising clock edge | |
|
531 | irq_wfp_reg <= irq_wfp_reg_s; | |
|
532 | END IF; | |
|
533 | END PROCESS; | |
|
534 | ||
|
535 | all_irq_wfp: FOR I IN IRQ_WFP_SIZE-1 DOWNTO 0 GENERATE | |
|
536 | irq_wfp(I) <= (NOT irq_wfp_reg(I)) AND irq_wfp_reg_s(I); | |
|
537 | END GENERATE all_irq_wfp; | |
|
538 | ||
|
539 | irq_wfp_ZERO <= (OTHERS => '0'); | |
|
540 | ored_irq_wfp <= '0' WHEN irq_wfp = irq_wfp_ZERO ELSE '1'; | |
|
541 | ||
|
542 | run_ms <= reg_sp.config_ms_run; | |
|
543 | ||
|
544 | END beh; No newline at end of file |
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@@ -1,374 +1,394 | |||
|
1 | LIBRARY ieee; | |
|
2 | USE ieee.std_logic_1164.ALL; | |
|
3 | ||
|
4 | LIBRARY lpp; | |
|
5 | USE lpp.lpp_amba.ALL; | |
|
6 | USE lpp.lpp_memory.ALL; | |
|
7 | --USE lpp.lpp_uart.ALL; | |
|
8 | USE lpp.lpp_matrix.ALL; | |
|
9 | --USE lpp.lpp_delay.ALL; | |
|
10 | USE lpp.lpp_fft.ALL; | |
|
11 | USE lpp.fft_components.ALL; | |
|
12 | USE lpp.lpp_ad_conv.ALL; | |
|
13 | USE lpp.iir_filter.ALL; | |
|
14 | USE lpp.general_purpose.ALL; | |
|
15 | USE lpp.Filtercfg.ALL; | |
|
16 | USE lpp.lpp_demux.ALL; | |
|
17 | USE lpp.lpp_top_lfr_pkg.ALL; | |
|
18 | USE lpp.lpp_dma_pkg.ALL; | |
|
19 | USE lpp.lpp_Header.ALL; | |
|
20 | USE lpp.lpp_lfr_pkg.ALL; | |
|
21 | ||
|
22 | LIBRARY grlib; | |
|
23 | USE grlib.amba.ALL; | |
|
24 | USE grlib.stdlib.ALL; | |
|
25 | USE grlib.devices.ALL; | |
|
26 | USE GRLIB.DMA2AHB_Package.ALL; | |
|
27 | ||
|
28 | ||
|
29 | ENTITY lpp_lfr_ms IS | |
|
30 | GENERIC ( | |
|
31 | Mem_use : INTEGER | |
|
32 | ); | |
|
33 | PORT ( | |
|
34 | clk : IN STD_LOGIC; | |
|
35 | rstn : IN STD_LOGIC; | |
|
36 | ||
|
37 | --------------------------------------------------------------------------- | |
|
38 | -- DATA INPUT | |
|
39 | --------------------------------------------------------------------------- | |
|
40 | -- TIME | |
|
41 | coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- todo | |
|
42 | fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); -- todo | |
|
43 | -- | |
|
44 | sample_f0_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0); | |
|
45 | sample_f0_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); | |
|
46 | -- | |
|
47 | sample_f1_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0); | |
|
48 | sample_f1_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); | |
|
49 | -- | |
|
50 | sample_f3_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0); | |
|
51 | sample_f3_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); | |
|
52 | ||
|
53 | --------------------------------------------------------------------------- | |
|
54 | -- DMA | |
|
55 | --------------------------------------------------------------------------- | |
|
56 | dma_addr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
57 | dma_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
58 | dma_valid : OUT STD_LOGIC; | |
|
59 | dma_valid_burst : OUT STD_LOGIC; | |
|
60 | dma_ren : IN STD_LOGIC; | |
|
61 | dma_done : IN STD_LOGIC; | |
|
62 | ||
|
63 | -- Reg out | |
|
64 | ready_matrix_f0_0 : OUT STD_LOGIC; | |
|
65 | ready_matrix_f0_1 : OUT STD_LOGIC; | |
|
66 | ready_matrix_f1 : OUT STD_LOGIC; | |
|
67 | ready_matrix_f2 : OUT STD_LOGIC; | |
|
68 | error_anticipating_empty_fifo : OUT STD_LOGIC; | |
|
69 | error_bad_component_error : OUT STD_LOGIC; | |
|
70 | debug_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
71 | ||
|
72 | -- Reg In | |
|
73 | status_ready_matrix_f0_0 :IN STD_LOGIC; | |
|
74 | status_ready_matrix_f0_1 :IN STD_LOGIC; | |
|
75 | status_ready_matrix_f1 :IN STD_LOGIC; | |
|
76 | status_ready_matrix_f2 :IN STD_LOGIC; | |
|
77 | status_error_anticipating_empty_fifo :IN STD_LOGIC; | |
|
78 | status_error_bad_component_error :IN STD_LOGIC; | |
|
79 | ||
|
80 | config_active_interruption_onNewMatrix : IN STD_LOGIC; | |
|
81 | config_active_interruption_onError : IN STD_LOGIC; | |
|
82 | addr_matrix_f0_0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
83 | addr_matrix_f0_1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
84 | addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
85 | addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
86 | ||
|
87 | matrix_time_f0_0 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); | |
|
88 | matrix_time_f0_1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); | |
|
89 | matrix_time_f1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); | |
|
90 | matrix_time_f2 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0) | |
|
91 | ||
|
92 | ); | |
|
93 | END; | |
|
94 | ||
|
95 | ARCHITECTURE Behavioral OF lpp_lfr_ms IS | |
|
96 | ----------------------------------------------------------------------------- | |
|
97 | SIGNAL FifoF0_Empty : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
|
98 | SIGNAL FifoF1_Empty : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
|
99 | SIGNAL FifoF3_Empty : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
|
100 | SIGNAL FifoF0_Data : STD_LOGIC_VECTOR(79 DOWNTO 0); | |
|
101 | SIGNAL FifoF1_Data : STD_LOGIC_VECTOR(79 DOWNTO 0); | |
|
102 | SIGNAL FifoF3_Data : STD_LOGIC_VECTOR(79 DOWNTO 0); | |
|
103 | ||
|
104 | ----------------------------------------------------------------------------- | |
|
105 | SIGNAL DMUX_Read : STD_LOGIC_VECTOR(14 DOWNTO 0); | |
|
106 | SIGNAL DMUX_Empty : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
|
107 | SIGNAL DMUX_Data : STD_LOGIC_VECTOR(79 DOWNTO 0); | |
|
108 | SIGNAL DMUX_WorkFreq : STD_LOGIC_VECTOR(1 DOWNTO 0); | |
|
109 | ||
|
110 | ----------------------------------------------------------------------------- | |
|
111 | SIGNAL FFT_Load : STD_LOGIC; | |
|
112 | SIGNAL FFT_Read : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
|
113 | SIGNAL FFT_Write : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
|
114 | SIGNAL FFT_ReUse : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
|
115 | SIGNAL FFT_Data : STD_LOGIC_VECTOR(79 DOWNTO 0); | |
|
116 | ||
|
117 | ----------------------------------------------------------------------------- | |
|
118 | SIGNAL FifoINT_Full : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
|
119 | SIGNAL FifoINT_Data : STD_LOGIC_VECTOR(79 DOWNTO 0); | |
|
120 | ||
|
121 | ----------------------------------------------------------------------------- | |
|
122 | SIGNAL SM_FlagError : STD_LOGIC; | |
|
123 | -- SIGNAL SM_Pong : STD_LOGIC; | |
|
124 | SIGNAL SM_Wen : STD_LOGIC; | |
|
125 | SIGNAL SM_Read : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
|
126 | SIGNAL SM_Write : STD_LOGIC_VECTOR(1 DOWNTO 0); | |
|
127 | SIGNAL SM_ReUse : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
|
128 | SIGNAL SM_Param : STD_LOGIC_VECTOR(3 DOWNTO 0); | |
|
129 | SIGNAL SM_Data : STD_LOGIC_VECTOR(63 DOWNTO 0); | |
|
130 | ||
|
131 | ----------------------------------------------------------------------------- | |
|
132 | SIGNAL FifoOUT_Full : STD_LOGIC_VECTOR(1 DOWNTO 0); | |
|
133 | SIGNAL FifoOUT_Empty : STD_LOGIC_VECTOR(1 DOWNTO 0); | |
|
134 | SIGNAL FifoOUT_Data : STD_LOGIC_VECTOR(63 DOWNTO 0); | |
|
135 | ||
|
136 | ----------------------------------------------------------------------------- | |
|
137 | SIGNAL Head_Read : STD_LOGIC_VECTOR(1 DOWNTO 0); | |
|
138 | SIGNAL Head_Data : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
139 | SIGNAL Head_Empty : STD_LOGIC; | |
|
140 | SIGNAL Head_Header : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
141 | SIGNAL Head_Valid : STD_LOGIC; | |
|
142 | SIGNAL Head_Val : STD_LOGIC; | |
|
143 | ||
|
144 | ----------------------------------------------------------------------------- | |
|
145 | SIGNAL DMA_Read : STD_LOGIC; | |
|
146 | SIGNAL DMA_ack : STD_LOGIC; | |
|
147 | ||
|
148 | ----------------------------------------------------------------------------- | |
|
149 | SIGNAL data_time : STD_LOGIC_VECTOR(47 DOWNTO 0); | |
|
150 | ||
|
151 | BEGIN | |
|
152 | ||
|
153 | ----------------------------------------------------------------------------- | |
|
154 | Memf0: lppFIFOxN | |
|
155 | GENERIC MAP ( | |
|
156 | tech => 0, Mem_use => Mem_use, Data_sz => 16, | |
|
157 | Addr_sz => 9, FifoCnt => 5, Enable_ReUse => '0') | |
|
158 | PORT MAP ( | |
|
159 | rstn => rstn, wclk => clk, rclk => clk, | |
|
160 | ReUse => (OTHERS => '0'), | |
|
161 | wen => sample_f0_wen, ren => DMUX_Read(4 DOWNTO 0), | |
|
162 | wdata => sample_f0_wdata, rdata => FifoF0_Data, | |
|
163 | full => OPEN, empty => FifoF0_Empty); | |
|
164 | ||
|
165 | Memf1: lppFIFOxN | |
|
166 | GENERIC MAP ( | |
|
167 | tech => 0, Mem_use => Mem_use, Data_sz => 16, | |
|
168 | Addr_sz => 8, FifoCnt => 5, Enable_ReUse => '0') | |
|
169 | PORT MAP ( | |
|
170 | rstn => rstn, wclk => clk, rclk => clk, | |
|
171 | ReUse => (OTHERS => '0'), | |
|
172 | wen => sample_f1_wen, ren => DMUX_Read(9 DOWNTO 5), | |
|
173 | wdata => sample_f1_wdata, rdata => FifoF1_Data, | |
|
174 | full => OPEN, empty => FifoF1_Empty); | |
|
175 | ||
|
176 | ||
|
177 | Memf2: lppFIFOxN | |
|
178 | GENERIC MAP ( | |
|
179 | tech => 0, Mem_use => Mem_use, Data_sz => 16, | |
|
180 | Addr_sz => 8, FifoCnt => 5, Enable_ReUse => '0') | |
|
181 | PORT MAP ( | |
|
182 | rstn => rstn, wclk => clk, rclk => clk, | |
|
183 | ReUse => (OTHERS => '0'), | |
|
184 | wen => sample_f3_wen, ren => DMUX_Read(14 DOWNTO 10), | |
|
185 | wdata => sample_f3_wdata, rdata => FifoF3_Data, | |
|
186 | full => OPEN, empty => FifoF3_Empty); | |
|
187 | ----------------------------------------------------------------------------- | |
|
188 | ||
|
189 | ||
|
190 | ----------------------------------------------------------------------------- | |
|
191 | DMUX0 : DEMUX | |
|
192 | GENERIC MAP ( | |
|
193 | Data_sz => 16) | |
|
194 | PORT MAP ( | |
|
195 | clk => clk, | |
|
196 | rstn => rstn, | |
|
197 | Read => FFT_Read, | |
|
198 | Load => FFT_Load, | |
|
199 | EmptyF0 => FifoF0_Empty, | |
|
200 | EmptyF1 => FifoF1_Empty, | |
|
201 | EmptyF2 => FifoF3_Empty, | |
|
202 |
|
|
|
203 |
|
|
|
204 |
|
|
|
205 | WorkFreq => DMUX_WorkFreq, | |
|
206 | Read_DEMUX => DMUX_Read, | |
|
207 | Empty => DMUX_Empty, | |
|
208 |
Data |
|
|
209 | ----------------------------------------------------------------------------- | |
|
210 | ||
|
211 | ||
|
212 | ----------------------------------------------------------------------------- | |
|
213 | FFT0: FFT | |
|
214 | GENERIC MAP ( | |
|
215 | Data_sz => 16, | |
|
216 | NbData => 256) | |
|
217 | PORT MAP ( | |
|
218 | clkm => clk, | |
|
219 | rstn => rstn, | |
|
220 | FifoIN_Empty => DMUX_Empty, | |
|
221 | FifoIN_Data => DMUX_Data, | |
|
222 | FifoOUT_Full => FifoINT_Full, | |
|
223 |
|
|
|
224 | Read => FFT_Read, | |
|
225 | Write => FFT_Write, | |
|
226 | ReUse => FFT_ReUse, | |
|
227 |
|
|
|
228 | ----------------------------------------------------------------------------- | |
|
229 | ||
|
230 | ||
|
231 | ----------------------------------------------------------------------------- | |
|
232 | MemInt : lppFIFOxN | |
|
233 | GENERIC MAP ( | |
|
234 | tech => 0, | |
|
235 | Mem_use => Mem_use, | |
|
236 | Data_sz => 16, | |
|
237 | Addr_sz => 8, | |
|
238 |
|
|
|
239 | Enable_ReUse => '1') | |
|
240 | PORT MAP ( | |
|
241 |
|
|
|
242 | wclk => clk, | |
|
243 | rclk => clk, | |
|
244 | ReUse => SM_ReUse, | |
|
245 |
|
|
|
246 | ren => SM_Read, | |
|
247 | wdata => FFT_Data, | |
|
248 | rdata => FifoINT_Data, | |
|
249 | full => FifoINT_Full, | |
|
250 | empty => OPEN); | |
|
251 | ----------------------------------------------------------------------------- | |
|
252 | ||
|
253 | ----------------------------------------------------------------------------- | |
|
254 | SM0 : MatriceSpectrale | |
|
255 | GENERIC MAP ( | |
|
256 | Input_SZ => 16, | |
|
257 | Result_SZ => 32) | |
|
258 | PORT MAP ( | |
|
259 | clkm => clk, | |
|
260 | rstn => rstn, | |
|
261 | FifoIN_Full => FifoINT_Full, | |
|
262 | SetReUse => FFT_ReUse, | |
|
263 |
|
|
|
264 | Data_IN => FifoINT_Data, | |
|
265 | ACK => DMA_ack, | |
|
266 | SM_Write => SM_Wen, | |
|
267 | FlagError => SM_FlagError, | |
|
268 | -- Pong => SM_Pong, | |
|
269 |
|
|
|
270 |
Write |
|
|
271 | Read => SM_Read, | |
|
272 | ReUse => SM_ReUse, | |
|
273 |
|
|
|
274 | ----------------------------------------------------------------------------- | |
|
275 | ||
|
276 | ----------------------------------------------------------------------------- | |
|
277 | MemOut : lppFIFOxN | |
|
278 | GENERIC MAP ( | |
|
279 | tech => 0, | |
|
280 | Mem_use => Mem_use, | |
|
281 | Data_sz => 32, | |
|
282 | Addr_sz => 8, | |
|
283 |
|
|
|
284 | Enable_ReUse => '0') | |
|
285 | PORT MAP ( | |
|
286 |
|
|
|
287 | wclk => clk, | |
|
288 | rclk => clk, | |
|
289 | ReUse => (OTHERS => '0'), | |
|
290 |
|
|
|
291 | ren => Head_Read, | |
|
292 | wdata => SM_Data, | |
|
293 | rdata => FifoOUT_Data, | |
|
294 | full => FifoOUT_Full, | |
|
295 | empty => FifoOUT_Empty); | |
|
296 | ----------------------------------------------------------------------------- | |
|
297 | ||
|
298 | ----------------------------------------------------------------------------- | |
|
299 | Head0 : HeaderBuilder | |
|
300 | GENERIC MAP ( | |
|
301 | Data_sz => 32) | |
|
302 | PORT MAP ( | |
|
303 | clkm => clk, | |
|
304 | rstn => rstn, | |
|
305 | -- pong => SM_Pong, | |
|
306 | Statu => SM_Param, | |
|
307 | Matrix_Type => DMUX_WorkFreq, | |
|
308 | Matrix_Write => SM_Wen, | |
|
309 | Valid => Head_Valid, | |
|
310 | ||
|
311 | dataIN => FifoOUT_Data, | |
|
312 | emptyIN => FifoOUT_Empty, | |
|
313 |
|
|
|
314 | ||
|
315 |
data |
|
|
316 |
empty |
|
|
317 |
Ren |
|
|
318 | ||
|
319 |
|
|
|
320 | header_val => Head_Val, | |
|
321 | header_ack => DMA_ack ); | |
|
322 | ----------------------------------------------------------------------------- | |
|
323 | data_time(31 DOWNTO 0) <= coarse_time; | |
|
324 | data_time(47 DOWNTO 32) <= fine_time; | |
|
325 | ||
|
326 | lpp_lfr_ms_fsmdma_1: lpp_lfr_ms_fsmdma | |
|
327 | PORT MAP ( | |
|
328 | HCLK => clk, | |
|
329 | HRESETn => rstn, | |
|
330 | ||
|
331 | data_time => data_time, | |
|
332 | ||
|
333 |
|
|
|
334 | fifo_empty => Head_Empty, | |
|
335 |
|
|
|
336 | ||
|
337 |
|
|
|
338 |
|
|
|
339 |
|
|
|
340 | ||
|
341 |
|
|
|
342 |
|
|
|
343 |
|
|
|
344 | dma_valid_burst => dma_valid_burst, | |
|
345 |
|
|
|
346 |
dma_d |
|
|
347 | ||
|
348 |
|
|
|
349 | ready_matrix_f0_1 => ready_matrix_f0_1, | |
|
350 |
|
|
|
351 | ready_matrix_f2 => ready_matrix_f2, | |
|
352 | error_anticipating_empty_fifo => error_anticipating_empty_fifo, | |
|
353 | error_bad_component_error => error_bad_component_error, | |
|
354 |
|
|
|
355 |
|
|
|
356 | status_ready_matrix_f0_1 => status_ready_matrix_f0_1, | |
|
357 | status_ready_matrix_f1 => status_ready_matrix_f1, | |
|
358 | status_ready_matrix_f2 => status_ready_matrix_f2, | |
|
359 | status_error_anticipating_empty_fifo => status_error_anticipating_empty_fifo, | |
|
360 | status_error_bad_component_error => status_error_bad_component_error, | |
|
361 | config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix, | |
|
362 | config_active_interruption_onError => config_active_interruption_onError, | |
|
363 | addr_matrix_f0_0 => addr_matrix_f0_0, | |
|
364 | addr_matrix_f0_1 => addr_matrix_f0_1, | |
|
365 | addr_matrix_f1 => addr_matrix_f1, | |
|
366 | addr_matrix_f2 => addr_matrix_f2, | |
|
367 | ||
|
368 |
matrix_ |
|
|
369 |
matrix_ |
|
|
370 |
matrix_ |
|
|
371 | matrix_time_f2 => matrix_time_f2 | |
|
372 | ); | |
|
373 | ||
|
374 | END Behavioral; | |
|
1 | LIBRARY ieee; | |
|
2 | USE ieee.std_logic_1164.ALL; | |
|
3 | ||
|
4 | LIBRARY lpp; | |
|
5 | USE lpp.lpp_amba.ALL; | |
|
6 | USE lpp.lpp_memory.ALL; | |
|
7 | --USE lpp.lpp_uart.ALL; | |
|
8 | USE lpp.lpp_matrix.ALL; | |
|
9 | --USE lpp.lpp_delay.ALL; | |
|
10 | USE lpp.lpp_fft.ALL; | |
|
11 | USE lpp.fft_components.ALL; | |
|
12 | USE lpp.lpp_ad_conv.ALL; | |
|
13 | USE lpp.iir_filter.ALL; | |
|
14 | USE lpp.general_purpose.ALL; | |
|
15 | USE lpp.Filtercfg.ALL; | |
|
16 | USE lpp.lpp_demux.ALL; | |
|
17 | USE lpp.lpp_top_lfr_pkg.ALL; | |
|
18 | USE lpp.lpp_dma_pkg.ALL; | |
|
19 | USE lpp.lpp_Header.ALL; | |
|
20 | USE lpp.lpp_lfr_pkg.ALL; | |
|
21 | ||
|
22 | LIBRARY grlib; | |
|
23 | USE grlib.amba.ALL; | |
|
24 | USE grlib.stdlib.ALL; | |
|
25 | USE grlib.devices.ALL; | |
|
26 | USE GRLIB.DMA2AHB_Package.ALL; | |
|
27 | ||
|
28 | ||
|
29 | ENTITY lpp_lfr_ms IS | |
|
30 | GENERIC ( | |
|
31 | Mem_use : INTEGER := use_RAM | |
|
32 | ); | |
|
33 | PORT ( | |
|
34 | clk : IN STD_LOGIC; | |
|
35 | rstn : IN STD_LOGIC; | |
|
36 | ||
|
37 | --------------------------------------------------------------------------- | |
|
38 | -- DATA INPUT | |
|
39 | --------------------------------------------------------------------------- | |
|
40 | -- TIME | |
|
41 | coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- todo | |
|
42 | fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); -- todo | |
|
43 | -- | |
|
44 | sample_f0_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0); | |
|
45 | sample_f0_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); | |
|
46 | -- | |
|
47 | sample_f1_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0); | |
|
48 | sample_f1_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); | |
|
49 | -- | |
|
50 | sample_f3_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0); | |
|
51 | sample_f3_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); | |
|
52 | ||
|
53 | --------------------------------------------------------------------------- | |
|
54 | -- DMA | |
|
55 | --------------------------------------------------------------------------- | |
|
56 | dma_addr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
57 | dma_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
58 | dma_valid : OUT STD_LOGIC; | |
|
59 | dma_valid_burst : OUT STD_LOGIC; | |
|
60 | dma_ren : IN STD_LOGIC; | |
|
61 | dma_done : IN STD_LOGIC; | |
|
62 | ||
|
63 | -- Reg out | |
|
64 | ready_matrix_f0_0 : OUT STD_LOGIC; | |
|
65 | ready_matrix_f0_1 : OUT STD_LOGIC; | |
|
66 | ready_matrix_f1 : OUT STD_LOGIC; | |
|
67 | ready_matrix_f2 : OUT STD_LOGIC; | |
|
68 | error_anticipating_empty_fifo : OUT STD_LOGIC; | |
|
69 | error_bad_component_error : OUT STD_LOGIC; | |
|
70 | debug_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
71 | ||
|
72 | -- Reg In | |
|
73 | status_ready_matrix_f0_0 :IN STD_LOGIC; | |
|
74 | status_ready_matrix_f0_1 :IN STD_LOGIC; | |
|
75 | status_ready_matrix_f1 :IN STD_LOGIC; | |
|
76 | status_ready_matrix_f2 :IN STD_LOGIC; | |
|
77 | status_error_anticipating_empty_fifo :IN STD_LOGIC; | |
|
78 | status_error_bad_component_error :IN STD_LOGIC; | |
|
79 | ||
|
80 | config_active_interruption_onNewMatrix : IN STD_LOGIC; | |
|
81 | config_active_interruption_onError : IN STD_LOGIC; | |
|
82 | addr_matrix_f0_0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
83 | addr_matrix_f0_1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
84 | addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
85 | addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
86 | ||
|
87 | matrix_time_f0_0 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); | |
|
88 | matrix_time_f0_1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); | |
|
89 | matrix_time_f1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); | |
|
90 | matrix_time_f2 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0) | |
|
91 | ||
|
92 | ); | |
|
93 | END; | |
|
94 | ||
|
95 | ARCHITECTURE Behavioral OF lpp_lfr_ms IS | |
|
96 | ----------------------------------------------------------------------------- | |
|
97 | SIGNAL FifoF0_Empty : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
|
98 | SIGNAL FifoF1_Empty : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
|
99 | SIGNAL FifoF3_Empty : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
|
100 | SIGNAL FifoF0_Data : STD_LOGIC_VECTOR(79 DOWNTO 0); | |
|
101 | SIGNAL FifoF1_Data : STD_LOGIC_VECTOR(79 DOWNTO 0); | |
|
102 | SIGNAL FifoF3_Data : STD_LOGIC_VECTOR(79 DOWNTO 0); | |
|
103 | ||
|
104 | ----------------------------------------------------------------------------- | |
|
105 | SIGNAL DMUX_Read : STD_LOGIC_VECTOR(14 DOWNTO 0); | |
|
106 | SIGNAL DMUX_Empty : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
|
107 | SIGNAL DMUX_Data : STD_LOGIC_VECTOR(79 DOWNTO 0); | |
|
108 | SIGNAL DMUX_WorkFreq : STD_LOGIC_VECTOR(1 DOWNTO 0); | |
|
109 | ||
|
110 | ----------------------------------------------------------------------------- | |
|
111 | SIGNAL FFT_Load : STD_LOGIC; | |
|
112 | SIGNAL FFT_Read : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
|
113 | SIGNAL FFT_Write : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
|
114 | SIGNAL FFT_ReUse : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
|
115 | SIGNAL FFT_Data : STD_LOGIC_VECTOR(79 DOWNTO 0); | |
|
116 | ||
|
117 | ----------------------------------------------------------------------------- | |
|
118 | SIGNAL FifoINT_Full : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
|
119 | SIGNAL FifoINT_Data : STD_LOGIC_VECTOR(79 DOWNTO 0); | |
|
120 | ||
|
121 | ----------------------------------------------------------------------------- | |
|
122 | SIGNAL SM_FlagError : STD_LOGIC; | |
|
123 | -- SIGNAL SM_Pong : STD_LOGIC; | |
|
124 | SIGNAL SM_Wen : STD_LOGIC; | |
|
125 | SIGNAL SM_Read : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
|
126 | SIGNAL SM_Write : STD_LOGIC_VECTOR(1 DOWNTO 0); | |
|
127 | SIGNAL SM_ReUse : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
|
128 | SIGNAL SM_Param : STD_LOGIC_VECTOR(3 DOWNTO 0); | |
|
129 | SIGNAL SM_Data : STD_LOGIC_VECTOR(63 DOWNTO 0); | |
|
130 | ||
|
131 | ----------------------------------------------------------------------------- | |
|
132 | SIGNAL FifoOUT_Full : STD_LOGIC_VECTOR(1 DOWNTO 0); | |
|
133 | SIGNAL FifoOUT_Empty : STD_LOGIC_VECTOR(1 DOWNTO 0); | |
|
134 | SIGNAL FifoOUT_Data : STD_LOGIC_VECTOR(63 DOWNTO 0); | |
|
135 | ||
|
136 | ----------------------------------------------------------------------------- | |
|
137 | SIGNAL Head_Read : STD_LOGIC_VECTOR(1 DOWNTO 0); | |
|
138 | SIGNAL Head_Data : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
139 | SIGNAL Head_Empty : STD_LOGIC; | |
|
140 | SIGNAL Head_Header : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
141 | SIGNAL Head_Valid : STD_LOGIC; | |
|
142 | SIGNAL Head_Val : STD_LOGIC; | |
|
143 | ||
|
144 | ----------------------------------------------------------------------------- | |
|
145 | SIGNAL DMA_Read : STD_LOGIC; | |
|
146 | SIGNAL DMA_ack : STD_LOGIC; | |
|
147 | ||
|
148 | ----------------------------------------------------------------------------- | |
|
149 | SIGNAL data_time : STD_LOGIC_VECTOR(47 DOWNTO 0); | |
|
150 | ||
|
151 | SIGNAL debug_reg_s : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
152 | SIGNAL dma_valid_s : STD_LOGIC; | |
|
153 | SIGNAL dma_valid_burst_s : STD_LOGIC; | |
|
154 | ||
|
155 | BEGIN | |
|
156 | ||
|
157 | ----------------------------------------------------------------------------- | |
|
158 | Memf0: lppFIFOxN | |
|
159 | GENERIC MAP ( | |
|
160 | tech => 0, Mem_use => Mem_use, Data_sz => 16, | |
|
161 | Addr_sz => 9, FifoCnt => 5, Enable_ReUse => '0') | |
|
162 | PORT MAP ( | |
|
163 | rstn => rstn, wclk => clk, rclk => clk, | |
|
164 | ReUse => (OTHERS => '0'), | |
|
165 | wen => sample_f0_wen, ren => DMUX_Read(4 DOWNTO 0), | |
|
166 | wdata => sample_f0_wdata, rdata => FifoF0_Data, | |
|
167 | full => OPEN, empty => FifoF0_Empty); | |
|
168 | ||
|
169 | Memf1: lppFIFOxN | |
|
170 | GENERIC MAP ( | |
|
171 | tech => 0, Mem_use => Mem_use, Data_sz => 16, | |
|
172 | Addr_sz => 8, FifoCnt => 5, Enable_ReUse => '0') | |
|
173 | PORT MAP ( | |
|
174 | rstn => rstn, wclk => clk, rclk => clk, | |
|
175 | ReUse => (OTHERS => '0'), | |
|
176 | wen => sample_f1_wen, ren => DMUX_Read(9 DOWNTO 5), | |
|
177 | wdata => sample_f1_wdata, rdata => FifoF1_Data, | |
|
178 | full => OPEN, empty => FifoF1_Empty); | |
|
179 | ||
|
180 | ||
|
181 | Memf2: lppFIFOxN | |
|
182 | GENERIC MAP ( | |
|
183 | tech => 0, Mem_use => Mem_use, Data_sz => 16, | |
|
184 | Addr_sz => 8, FifoCnt => 5, Enable_ReUse => '0') | |
|
185 | PORT MAP ( | |
|
186 | rstn => rstn, wclk => clk, rclk => clk, | |
|
187 | ReUse => (OTHERS => '0'), | |
|
188 | wen => sample_f3_wen, ren => DMUX_Read(14 DOWNTO 10), | |
|
189 | wdata => sample_f3_wdata, rdata => FifoF3_Data, | |
|
190 | full => OPEN, empty => FifoF3_Empty); | |
|
191 | ----------------------------------------------------------------------------- | |
|
192 | ||
|
193 | ||
|
194 | ----------------------------------------------------------------------------- | |
|
195 | DMUX0 : DEMUX | |
|
196 | GENERIC MAP ( | |
|
197 | Data_sz => 16) | |
|
198 | PORT MAP ( | |
|
199 | clk => clk, | |
|
200 | rstn => rstn, | |
|
201 | Read => FFT_Read, | |
|
202 | Load => FFT_Load, | |
|
203 | EmptyF0 => FifoF0_Empty, | |
|
204 | EmptyF1 => FifoF1_Empty, | |
|
205 | EmptyF2 => FifoF3_Empty, | |
|
206 | DataF0 => FifoF0_Data, | |
|
207 | DataF1 => FifoF1_Data, | |
|
208 | DataF2 => FifoF3_Data, | |
|
209 | WorkFreq => DMUX_WorkFreq, | |
|
210 | Read_DEMUX => DMUX_Read, | |
|
211 | Empty => DMUX_Empty, | |
|
212 | Data => DMUX_Data); | |
|
213 | ----------------------------------------------------------------------------- | |
|
214 | ||
|
215 | ||
|
216 | ----------------------------------------------------------------------------- | |
|
217 | FFT0: FFT | |
|
218 | GENERIC MAP ( | |
|
219 | Data_sz => 16, | |
|
220 | NbData => 256) | |
|
221 | PORT MAP ( | |
|
222 | clkm => clk, | |
|
223 | rstn => rstn, | |
|
224 | FifoIN_Empty => DMUX_Empty, | |
|
225 | FifoIN_Data => DMUX_Data, | |
|
226 | FifoOUT_Full => FifoINT_Full, | |
|
227 | Load => FFT_Load, | |
|
228 | Read => FFT_Read, | |
|
229 | Write => FFT_Write, | |
|
230 | ReUse => FFT_ReUse, | |
|
231 | Data => FFT_Data); | |
|
232 | ----------------------------------------------------------------------------- | |
|
233 | ||
|
234 | ||
|
235 | ----------------------------------------------------------------------------- | |
|
236 | MemInt : lppFIFOxN | |
|
237 | GENERIC MAP ( | |
|
238 | tech => 0, | |
|
239 | Mem_use => Mem_use, | |
|
240 | Data_sz => 16, | |
|
241 | Addr_sz => 8, | |
|
242 | FifoCnt => 5, | |
|
243 | Enable_ReUse => '1') | |
|
244 | PORT MAP ( | |
|
245 | rstn => rstn, | |
|
246 | wclk => clk, | |
|
247 | rclk => clk, | |
|
248 | ReUse => SM_ReUse, | |
|
249 | wen => FFT_Write, | |
|
250 | ren => SM_Read, | |
|
251 | wdata => FFT_Data, | |
|
252 | rdata => FifoINT_Data, | |
|
253 | full => FifoINT_Full, | |
|
254 | empty => OPEN); | |
|
255 | ----------------------------------------------------------------------------- | |
|
256 | ||
|
257 | ----------------------------------------------------------------------------- | |
|
258 | SM0 : MatriceSpectrale | |
|
259 | GENERIC MAP ( | |
|
260 | Input_SZ => 16, | |
|
261 | Result_SZ => 32) | |
|
262 | PORT MAP ( | |
|
263 | clkm => clk, | |
|
264 | rstn => rstn, | |
|
265 | FifoIN_Full => FifoINT_Full, | |
|
266 | SetReUse => FFT_ReUse, | |
|
267 | Valid => Head_Valid, | |
|
268 | Data_IN => FifoINT_Data, | |
|
269 | ACK => DMA_ack, | |
|
270 | SM_Write => SM_Wen, | |
|
271 | FlagError => SM_FlagError, | |
|
272 | -- Pong => SM_Pong, | |
|
273 | Statu => SM_Param, | |
|
274 | Write => SM_Write, | |
|
275 | Read => SM_Read, | |
|
276 | ReUse => SM_ReUse, | |
|
277 | Data_OUT => SM_Data); | |
|
278 | ----------------------------------------------------------------------------- | |
|
279 | ||
|
280 | ----------------------------------------------------------------------------- | |
|
281 | MemOut : lppFIFOxN | |
|
282 | GENERIC MAP ( | |
|
283 | tech => 0, | |
|
284 | Mem_use => Mem_use, | |
|
285 | Data_sz => 32, | |
|
286 | Addr_sz => 8, | |
|
287 | FifoCnt => 2, | |
|
288 | Enable_ReUse => '0') | |
|
289 | PORT MAP ( | |
|
290 | rstn => rstn, | |
|
291 | wclk => clk, | |
|
292 | rclk => clk, | |
|
293 | ReUse => (OTHERS => '0'), | |
|
294 | wen => SM_Write, | |
|
295 | ren => Head_Read, | |
|
296 | wdata => SM_Data, | |
|
297 | rdata => FifoOUT_Data, | |
|
298 | full => FifoOUT_Full, | |
|
299 | empty => FifoOUT_Empty); | |
|
300 | ----------------------------------------------------------------------------- | |
|
301 | ||
|
302 | ----------------------------------------------------------------------------- | |
|
303 | Head0 : HeaderBuilder | |
|
304 | GENERIC MAP ( | |
|
305 | Data_sz => 32) | |
|
306 | PORT MAP ( | |
|
307 | clkm => clk, | |
|
308 | rstn => rstn, | |
|
309 | -- pong => SM_Pong, | |
|
310 | Statu => SM_Param, | |
|
311 | Matrix_Type => DMUX_WorkFreq, | |
|
312 | Matrix_Write => SM_Wen, | |
|
313 | Valid => Head_Valid, | |
|
314 | ||
|
315 | dataIN => FifoOUT_Data, | |
|
316 | emptyIN => FifoOUT_Empty, | |
|
317 | RenOUT => Head_Read, | |
|
318 | ||
|
319 | dataOUT => Head_Data, | |
|
320 | emptyOUT => Head_Empty, | |
|
321 | RenIN => DMA_Read, | |
|
322 | ||
|
323 | header => Head_Header, | |
|
324 | header_val => Head_Val, | |
|
325 | header_ack => DMA_ack ); | |
|
326 | ----------------------------------------------------------------------------- | |
|
327 | data_time(31 DOWNTO 0) <= coarse_time; | |
|
328 | data_time(47 DOWNTO 32) <= fine_time; | |
|
329 | ||
|
330 | lpp_lfr_ms_fsmdma_1: lpp_lfr_ms_fsmdma | |
|
331 | PORT MAP ( | |
|
332 | HCLK => clk, | |
|
333 | HRESETn => rstn, | |
|
334 | ||
|
335 | data_time => data_time, | |
|
336 | ||
|
337 | fifo_data => Head_Data, | |
|
338 | fifo_empty => Head_Empty, | |
|
339 | fifo_ren => DMA_Read, | |
|
340 | ||
|
341 | header => Head_Header, | |
|
342 | header_val => Head_Val, | |
|
343 | header_ack => DMA_ack, | |
|
344 | ||
|
345 | dma_addr => dma_addr, | |
|
346 | dma_data => dma_data, | |
|
347 | dma_valid => dma_valid_s, | |
|
348 | dma_valid_burst => dma_valid_burst_s, | |
|
349 | dma_ren => dma_ren, | |
|
350 | dma_done => dma_done, | |
|
351 | ||
|
352 | ready_matrix_f0_0 => ready_matrix_f0_0, | |
|
353 | ready_matrix_f0_1 => ready_matrix_f0_1, | |
|
354 | ready_matrix_f1 => ready_matrix_f1, | |
|
355 | ready_matrix_f2 => ready_matrix_f2, | |
|
356 | error_anticipating_empty_fifo => error_anticipating_empty_fifo, | |
|
357 | error_bad_component_error => error_bad_component_error, | |
|
358 | debug_reg => debug_reg_s, | |
|
359 | status_ready_matrix_f0_0 => status_ready_matrix_f0_0, | |
|
360 | status_ready_matrix_f0_1 => status_ready_matrix_f0_1, | |
|
361 | status_ready_matrix_f1 => status_ready_matrix_f1, | |
|
362 | status_ready_matrix_f2 => status_ready_matrix_f2, | |
|
363 | status_error_anticipating_empty_fifo => status_error_anticipating_empty_fifo, | |
|
364 | status_error_bad_component_error => status_error_bad_component_error, | |
|
365 | config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix, | |
|
366 | config_active_interruption_onError => config_active_interruption_onError, | |
|
367 | addr_matrix_f0_0 => addr_matrix_f0_0, | |
|
368 | addr_matrix_f0_1 => addr_matrix_f0_1, | |
|
369 | addr_matrix_f1 => addr_matrix_f1, | |
|
370 | addr_matrix_f2 => addr_matrix_f2, | |
|
371 | ||
|
372 | matrix_time_f0_0 => matrix_time_f0_0, | |
|
373 | matrix_time_f0_1 => matrix_time_f0_1, | |
|
374 | matrix_time_f1 => matrix_time_f1, | |
|
375 | matrix_time_f2 => matrix_time_f2 | |
|
376 | ); | |
|
377 | ||
|
378 | dma_valid <= dma_valid_s; | |
|
379 | dma_valid_burst <= dma_valid_burst_s; | |
|
380 | ||
|
381 | debug_reg(9 DOWNTO 0) <= debug_reg_s(9 DOWNTO 0); | |
|
382 | debug_reg(10) <= Head_Empty; | |
|
383 | debug_reg(11) <= DMA_Read; | |
|
384 | debug_reg(12) <= Head_Val; | |
|
385 | debug_reg(13) <= DMA_ack; | |
|
386 | debug_reg(14) <= dma_ren; | |
|
387 | debug_reg(15) <= dma_done; | |
|
388 | debug_reg(16) <= dma_valid_s; | |
|
389 | debug_reg(17) <= dma_valid_burst_s; | |
|
390 | debug_reg(31 DOWNTO 18) <= (OTHERS => '0'); | |
|
391 | ||
|
392 | ||
|
393 | ||
|
394 | END Behavioral; |
@@ -1,383 +1,386 | |||
|
1 | 1 | |
|
2 | 2 | ------------------------------------------------------------------------------ |
|
3 | 3 | -- This file is a part of the LPP VHDL IP LIBRARY |
|
4 | 4 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS |
|
5 | 5 | -- |
|
6 | 6 | -- This program is free software; you can redistribute it and/or modify |
|
7 | 7 | -- it under the terms of the GNU General Public License as published by |
|
8 | 8 | -- the Free Software Foundation; either version 3 of the License, or |
|
9 | 9 | -- (at your option) any later version. |
|
10 | 10 | -- |
|
11 | 11 | -- This program is distributed in the hope that it will be useful, |
|
12 | 12 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of |
|
13 | 13 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
|
14 | 14 | -- GNU General Public License for more details. |
|
15 | 15 | -- |
|
16 | 16 | -- You should have received a copy of the GNU General Public License |
|
17 | 17 | -- along with this program; if not, write to the Free Software |
|
18 | 18 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
|
19 | 19 | ------------------------------------------------------------------------------- |
|
20 | 20 | -- Author : Jean-christophe Pellion |
|
21 | 21 | -- Mail : jean-christophe.pellion@lpp.polytechnique.fr |
|
22 | 22 | -- jean-christophe.pellion@easii-ic.com |
|
23 | 23 | ------------------------------------------------------------------------------- |
|
24 | 24 | -- 1.0 - initial version |
|
25 | 25 | ------------------------------------------------------------------------------- |
|
26 | 26 | LIBRARY ieee; |
|
27 | 27 | USE ieee.std_logic_1164.ALL; |
|
28 | 28 | USE ieee.numeric_std.ALL; |
|
29 | 29 | LIBRARY grlib; |
|
30 | 30 | USE grlib.amba.ALL; |
|
31 | 31 | USE grlib.stdlib.ALL; |
|
32 | 32 | USE grlib.devices.ALL; |
|
33 | 33 | USE GRLIB.DMA2AHB_Package.ALL; |
|
34 | 34 | LIBRARY lpp; |
|
35 | 35 | USE lpp.lpp_amba.ALL; |
|
36 | 36 | USE lpp.apb_devices_list.ALL; |
|
37 | 37 | USE lpp.lpp_memory.ALL; |
|
38 | 38 | USE lpp.lpp_dma_pkg.ALL; |
|
39 | 39 | LIBRARY techmap; |
|
40 | 40 | USE techmap.gencomp.ALL; |
|
41 | 41 | |
|
42 | 42 | |
|
43 | 43 | ENTITY lpp_lfr_ms_fsmdma IS |
|
44 | 44 | PORT ( |
|
45 | 45 | -- AMBA AHB system signals |
|
46 | 46 | HCLK : IN STD_ULOGIC; |
|
47 | 47 | HRESETn : IN STD_ULOGIC; |
|
48 | 48 | |
|
49 | 49 | --TIME |
|
50 | 50 | data_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
51 | 51 | |
|
52 | 52 | -- fifo interface |
|
53 | 53 | fifo_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
54 | 54 | fifo_empty : IN STD_LOGIC; |
|
55 | 55 | fifo_ren : OUT STD_LOGIC; |
|
56 | 56 | |
|
57 | 57 | -- header |
|
58 | 58 | header : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
59 | 59 | header_val : IN STD_LOGIC; |
|
60 | 60 | header_ack : OUT STD_LOGIC; |
|
61 | 61 | |
|
62 | 62 | -- DMA |
|
63 | 63 | dma_addr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
64 | 64 | dma_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
65 | 65 | dma_valid : OUT STD_LOGIC; |
|
66 | 66 | dma_valid_burst : OUT STD_LOGIC; |
|
67 | 67 | dma_ren : IN STD_LOGIC; |
|
68 | 68 | dma_done : IN STD_LOGIC; |
|
69 | 69 | |
|
70 | 70 | -- Reg out |
|
71 | 71 | ready_matrix_f0_0 : OUT STD_LOGIC; |
|
72 | 72 | ready_matrix_f0_1 : OUT STD_LOGIC; |
|
73 | 73 | ready_matrix_f1 : OUT STD_LOGIC; |
|
74 | 74 | ready_matrix_f2 : OUT STD_LOGIC; |
|
75 | 75 | error_anticipating_empty_fifo : OUT STD_LOGIC; |
|
76 | 76 | error_bad_component_error : OUT STD_LOGIC; |
|
77 | 77 | debug_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
78 | 78 | |
|
79 | 79 | -- Reg In |
|
80 | 80 | status_ready_matrix_f0_0 : IN STD_LOGIC; |
|
81 | 81 | status_ready_matrix_f0_1 : IN STD_LOGIC; |
|
82 | 82 | status_ready_matrix_f1 : IN STD_LOGIC; |
|
83 | 83 | status_ready_matrix_f2 : IN STD_LOGIC; |
|
84 | 84 | status_error_anticipating_empty_fifo : IN STD_LOGIC; |
|
85 | 85 | status_error_bad_component_error : IN STD_LOGIC; |
|
86 | 86 | |
|
87 | 87 | config_active_interruption_onNewMatrix : IN STD_LOGIC; |
|
88 | 88 | config_active_interruption_onError : IN STD_LOGIC; |
|
89 | 89 | addr_matrix_f0_0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
90 | 90 | addr_matrix_f0_1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
91 | 91 | addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
92 | 92 | addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
93 | 93 | |
|
94 | 94 | matrix_time_f0_0 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
95 | 95 | matrix_time_f0_1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); |
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96 | 96 | matrix_time_f1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); |
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97 | 97 | matrix_time_f2 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0) |
|
98 | 98 | |
|
99 | 99 | ); |
|
100 | 100 | END; |
|
101 | 101 | |
|
102 | 102 | ARCHITECTURE Behavioral OF lpp_lfr_ms_fsmdma IS |
|
103 | 103 | ----------------------------------------------------------------------------- |
|
104 | 104 | -- SIGNAL DMAIn : DMA_In_Type; |
|
105 | 105 | -- SIGNAL header_dmai : DMA_In_Type; |
|
106 | 106 | -- SIGNAL component_dmai : DMA_In_Type; |
|
107 | 107 | -- SIGNAL DMAOut : DMA_OUt_Type; |
|
108 | 108 | ----------------------------------------------------------------------------- |
|
109 | 109 | |
|
110 | 110 | ----------------------------------------------------------------------------- |
|
111 | 111 | ----------------------------------------------------------------------------- |
|
112 | 112 | TYPE state_DMAWriteBurst IS (IDLE, |
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113 | 113 | CHECK_COMPONENT_TYPE, |
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114 | 114 | WRITE_COARSE_TIME, |
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115 | 115 | WRITE_FINE_TIME, |
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116 | 116 | TRASH_FIFO, |
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117 | 117 | SEND_DATA, |
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118 | 118 | WAIT_DATA_ACK, |
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119 | 119 | CHECK_LENGTH |
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120 | 120 | ); |
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121 | 121 | SIGNAL state : state_DMAWriteBurst; -- := IDLE; |
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122 | 122 | |
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123 | 123 | -- SIGNAL nbSend : INTEGER; |
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124 | 124 | SIGNAL matrix_type : STD_LOGIC_VECTOR(1 DOWNTO 0); |
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125 | 125 | SIGNAL component_type : STD_LOGIC_VECTOR(3 DOWNTO 0); |
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126 | 126 | SIGNAL component_type_pre : STD_LOGIC_VECTOR(3 DOWNTO 0); |
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127 | 127 | SIGNAL header_check_ok : STD_LOGIC; |
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128 | 128 | SIGNAL address_matrix : STD_LOGIC_VECTOR(31 DOWNTO 0); |
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129 | 129 | SIGNAL send_matrix : STD_LOGIC; |
|
130 | 130 | -- SIGNAL request : STD_LOGIC; |
|
131 | 131 | -- SIGNAL remaining_data_request : INTEGER; |
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132 | 132 | SIGNAL Address : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
133 | 133 | ----------------------------------------------------------------------------- |
|
134 | 134 | ----------------------------------------------------------------------------- |
|
135 | 135 | SIGNAL header_select : STD_LOGIC; |
|
136 | 136 | |
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137 | 137 | SIGNAL header_send : STD_LOGIC; |
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138 | 138 | SIGNAL header_data : STD_LOGIC_VECTOR(31 DOWNTO 0); |
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139 | 139 | SIGNAL header_send_ok : STD_LOGIC; |
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140 | 140 | SIGNAL header_send_ko : STD_LOGIC; |
|
141 | 141 | |
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142 | 142 | SIGNAL component_send : STD_LOGIC; |
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143 | 143 | SIGNAL component_send_ok : STD_LOGIC; |
|
144 | 144 | SIGNAL component_send_ko : STD_LOGIC; |
|
145 | 145 | ----------------------------------------------------------------------------- |
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146 | 146 | SIGNAL fifo_ren_trash : STD_LOGIC; |
|
147 | 147 | SIGNAL component_fifo_ren : STD_LOGIC; |
|
148 | 148 | |
|
149 | 149 | ----------------------------------------------------------------------------- |
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150 | 150 | SIGNAL debug_reg_s : STD_LOGIC_VECTOR(31 DOWNTO 0); |
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151 | 151 | SIGNAL fine_time_reg : STD_LOGIC_VECTOR(15 DOWNTO 0); |
|
152 | 152 | |
|
153 | 153 | BEGIN |
|
154 | 154 | |
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155 | 155 | debug_reg <= debug_reg_s; |
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156 | 156 | |
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157 | 157 | |
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158 | 158 | send_matrix <= '1' WHEN matrix_type = "00" AND status_ready_matrix_f0_0 = '0' ELSE |
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159 | 159 | '1' WHEN matrix_type = "01" AND status_ready_matrix_f0_1 = '0' ELSE |
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160 | 160 | '1' WHEN matrix_type = "10" AND status_ready_matrix_f1 = '0' ELSE |
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161 | 161 | '1' WHEN matrix_type = "11" AND status_ready_matrix_f2 = '0' ELSE |
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162 | 162 | '0'; |
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163 | 163 | |
|
164 | 164 | header_check_ok <= '0' WHEN component_type = "1111" ELSE -- ?? component_type_pre = "1111" |
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165 | 165 | '1' WHEN component_type = "0000" AND component_type_pre = "0000" ELSE |
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166 | 166 | '1' WHEN component_type = component_type_pre + "0001" ELSE |
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167 | 167 | '0'; |
|
168 | 168 | |
|
169 | 169 | address_matrix <= addr_matrix_f0_0 WHEN matrix_type = "00" ELSE |
|
170 | 170 | addr_matrix_f0_1 WHEN matrix_type = "01" ELSE |
|
171 | 171 | addr_matrix_f1 WHEN matrix_type = "10" ELSE |
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172 | 172 | addr_matrix_f2 WHEN matrix_type = "11" ELSE |
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173 | 173 | (OTHERS => '0'); |
|
174 | 174 | |
|
175 | 175 | ----------------------------------------------------------------------------- |
|
176 | 176 | -- DMA control |
|
177 | 177 | ----------------------------------------------------------------------------- |
|
178 | 178 | DMAWriteFSM_p : PROCESS (HCLK, HRESETn) |
|
179 | 179 | BEGIN -- PROCESS DMAWriteBurst_p |
|
180 | 180 | IF HRESETn = '0' THEN -- asynchronous reset (active low) |
|
181 | 181 | matrix_type <= (OTHERS => '0'); |
|
182 | 182 | component_type <= (OTHERS => '0'); |
|
183 | 183 | state <= IDLE; |
|
184 | 184 | header_ack <= '0'; |
|
185 | 185 | ready_matrix_f0_0 <= '0'; |
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186 | 186 | ready_matrix_f0_1 <= '0'; |
|
187 | 187 | ready_matrix_f1 <= '0'; |
|
188 | 188 | ready_matrix_f2 <= '0'; |
|
189 | 189 | error_anticipating_empty_fifo <= '0'; |
|
190 | 190 | error_bad_component_error <= '0'; |
|
191 | 191 | component_type_pre <= "0000"; |
|
192 | 192 | fifo_ren_trash <= '1'; |
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193 | 193 | component_send <= '0'; |
|
194 | 194 | address <= (OTHERS => '0'); |
|
195 | 195 | header_select <= '0'; |
|
196 | 196 | header_send <= '0'; |
|
197 | 197 | header_data <= (OTHERS => '0'); |
|
198 | 198 | fine_time_reg <= (OTHERS => '0'); |
|
199 | 199 | |
|
200 | 200 | debug_reg_s(31 DOWNTO 0) <= (OTHERS => '0'); |
|
201 | 201 | |
|
202 | 202 | ELSIF HCLK'EVENT AND HCLK = '1' THEN -- rising clock edge |
|
203 | ||
|
203 | debug_reg_s(31 DOWNTO 10) <= (OTHERS => '0'); | |
|
204 | ||
|
204 | 205 |
|
|
205 | 206 | WHEN IDLE => |
|
206 | 207 | debug_reg_s(2 DOWNTO 0) <= "000"; |
|
207 | 208 | |
|
208 | 209 | matrix_type <= header(1 DOWNTO 0); |
|
209 | 210 | --component_type <= header(5 DOWNTO 2); |
|
210 | 211 | |
|
211 | 212 | ready_matrix_f0_0 <= '0'; |
|
212 | 213 | ready_matrix_f0_1 <= '0'; |
|
213 | 214 | ready_matrix_f1 <= '0'; |
|
214 | 215 | ready_matrix_f2 <= '0'; |
|
215 | 216 | error_bad_component_error <= '0'; |
|
216 | 217 | header_select <= '1'; |
|
218 | IF header_val = '1' THEN | |
|
219 | header_ack <= '1'; | |
|
220 | END IF; | |
|
217 | 221 | IF header_val = '1' AND fifo_empty = '0' AND send_matrix = '1' THEN |
|
218 | 222 | debug_reg_s(5 DOWNTO 4) <= header(1 DOWNTO 0); |
|
219 | 223 | debug_reg_s(9 DOWNTO 6) <= header(5 DOWNTO 2); |
|
220 | 224 | |
|
221 | 225 | matrix_type <= header(1 DOWNTO 0); |
|
222 | 226 | component_type <= header(5 DOWNTO 2); |
|
223 | 227 | component_type_pre <= component_type; |
|
224 | 228 | state <= CHECK_COMPONENT_TYPE; |
|
225 | 229 | END IF; |
|
226 | 230 | |
|
227 | 231 | WHEN CHECK_COMPONENT_TYPE => |
|
228 | 232 | debug_reg_s(2 DOWNTO 0) <= "001"; |
|
233 | header_ack <= '0'; | |
|
229 | 234 | |
|
230 | 235 | IF header_check_ok = '1' THEN |
|
231 | header_ack <= '1'; | |
|
232 | 236 | header_send <= '0'; |
|
233 | 237 | -- |
|
234 | 238 | IF component_type = "0000" THEN |
|
235 | 239 | address <= address_matrix; |
|
236 | 240 | CASE matrix_type IS |
|
237 | 241 | WHEN "00" => matrix_time_f0_0 <= data_time; |
|
238 | 242 | WHEN "01" => matrix_time_f0_1 <= data_time; |
|
239 | 243 | WHEN "10" => matrix_time_f1 <= data_time; |
|
240 | 244 | WHEN "11" => matrix_time_f2 <= data_time ; |
|
241 | 245 | WHEN OTHERS => NULL; |
|
242 | 246 | END CASE; |
|
243 | 247 | |
|
244 | 248 | header_data <= data_time(31 DOWNTO 0); |
|
245 | 249 | fine_time_reg <= data_time(47 DOWNTO 32); |
|
246 | 250 | --state <= WRITE_COARSE_TIME; |
|
247 | 251 | --header_send <= '1'; |
|
248 | 252 | state <= SEND_DATA; |
|
249 | 253 | header_send <= '0'; |
|
250 | 254 | component_send <= '1'; |
|
251 | 255 | header_select <= '0'; |
|
252 | 256 | ELSE |
|
253 | 257 | state <= SEND_DATA; |
|
254 | 258 | END IF; |
|
255 | 259 | -- |
|
256 | 260 | ELSE |
|
257 | 261 | error_bad_component_error <= '1'; |
|
258 | 262 | component_type_pre <= "0000"; |
|
259 | header_ack <= '1'; | |
|
260 | 263 | state <= TRASH_FIFO; |
|
261 | 264 | END IF; |
|
262 | 265 | |
|
263 | 266 | --WHEN WRITE_COARSE_TIME => |
|
264 | 267 | -- debug_reg_s(2 DOWNTO 0) <= "010"; |
|
265 | 268 | |
|
266 | 269 | -- header_ack <= '0'; |
|
267 | 270 | |
|
268 | 271 | -- IF dma_ren = '0' THEN |
|
269 | 272 | -- header_send <= '0'; |
|
270 | 273 | -- ELSE |
|
271 | 274 | -- header_send <= header_send; |
|
272 | 275 | -- END IF; |
|
273 | 276 | |
|
274 | 277 | |
|
275 | 278 | -- IF header_send_ko = '1' THEN |
|
276 | 279 | -- header_send <= '0'; |
|
277 | 280 | -- state <= TRASH_FIFO; |
|
278 | 281 | -- error_anticipating_empty_fifo <= '1'; |
|
279 | 282 | -- -- TODO : error sending header |
|
280 | 283 | -- ELSIF header_send_ok = '1' THEN |
|
281 | 284 | -- header_send <= '1'; |
|
282 | 285 | -- header_select <= '1'; |
|
283 | 286 | -- header_data(15 DOWNTO 0) <= fine_time_reg; |
|
284 | 287 | -- header_data(31 DOWNTO 16) <= (OTHERS => '0'); |
|
285 | 288 | -- state <= WRITE_FINE_TIME; |
|
286 | 289 | -- address <= address + 4; |
|
287 | 290 | -- END IF; |
|
288 | 291 | |
|
289 | 292 | |
|
290 | 293 | --WHEN WRITE_FINE_TIME => |
|
291 | 294 | -- debug_reg_s(2 DOWNTO 0) <= "011"; |
|
292 | 295 | |
|
293 | 296 | -- header_ack <= '0'; |
|
294 | 297 | |
|
295 | 298 | -- IF dma_ren = '0' THEN |
|
296 | 299 | -- header_send <= '0'; |
|
297 | 300 | -- ELSE |
|
298 | 301 | -- header_send <= header_send; |
|
299 | 302 | -- END IF; |
|
300 | 303 | |
|
301 | 304 | -- IF header_send_ko = '1' THEN |
|
302 | 305 | -- header_send <= '0'; |
|
303 | 306 | -- state <= TRASH_FIFO; |
|
304 | 307 | -- error_anticipating_empty_fifo <= '1'; |
|
305 | 308 | -- -- TODO : error sending header |
|
306 | 309 | -- ELSIF header_send_ok = '1' THEN |
|
307 | 310 | -- header_send <= '0'; |
|
308 | 311 | -- header_select <= '0'; |
|
309 | 312 | -- state <= SEND_DATA; |
|
310 | 313 | -- address <= address + 4; |
|
311 | 314 | -- END IF; |
|
312 | 315 | |
|
313 | 316 | WHEN TRASH_FIFO => |
|
314 | 317 | debug_reg_s(2 DOWNTO 0) <= "100"; |
|
315 | 318 | |
|
316 | 319 | header_ack <= '0'; |
|
317 | 320 | error_bad_component_error <= '0'; |
|
318 | 321 | error_anticipating_empty_fifo <= '0'; |
|
319 | 322 | IF fifo_empty = '1' THEN |
|
320 | 323 | state <= IDLE; |
|
321 | 324 | fifo_ren_trash <= '1'; |
|
322 | 325 | ELSE |
|
323 | 326 | fifo_ren_trash <= '0'; |
|
324 | 327 | END IF; |
|
325 | 328 | |
|
326 | 329 | WHEN SEND_DATA => |
|
327 | 330 | header_ack <= '0'; |
|
328 | 331 | debug_reg_s(2 DOWNTO 0) <= "101"; |
|
329 | 332 | |
|
330 | 333 | IF fifo_empty = '1' THEN |
|
331 | 334 | state <= IDLE; |
|
332 | 335 | IF component_type = "1110" THEN --"1110" -- JC |
|
333 | 336 | CASE matrix_type IS |
|
334 | 337 | WHEN "00" => ready_matrix_f0_0 <= '1'; |
|
335 | 338 | WHEN "01" => ready_matrix_f0_1 <= '1'; |
|
336 | 339 | WHEN "10" => ready_matrix_f1 <= '1'; |
|
337 | 340 | WHEN "11" => ready_matrix_f2 <= '1'; |
|
338 | 341 | WHEN OTHERS => NULL; |
|
339 | 342 | END CASE; |
|
340 | 343 | |
|
341 | 344 | END IF; |
|
342 | 345 | ELSE |
|
343 | 346 | component_send <= '1'; |
|
344 | 347 | address <= address; |
|
345 | 348 | state <= WAIT_DATA_ACK; |
|
346 | 349 | END IF; |
|
347 | 350 | |
|
348 | 351 | WHEN WAIT_DATA_ACK => |
|
349 | 352 | debug_reg_s(2 DOWNTO 0) <= "110"; |
|
350 | 353 | |
|
351 | 354 | component_send <= '0'; |
|
352 | 355 | IF component_send_ok = '1' THEN |
|
353 | 356 | address <= address + 64; |
|
354 | 357 | state <= SEND_DATA; |
|
355 | 358 | ELSIF component_send_ko = '1' THEN |
|
356 | 359 | error_anticipating_empty_fifo <= '0'; |
|
357 | 360 | state <= TRASH_FIFO; |
|
358 | 361 | END IF; |
|
359 | 362 | |
|
360 | 363 | WHEN CHECK_LENGTH => |
|
361 | 364 | component_send <= '0'; |
|
362 | 365 | debug_reg_s(2 DOWNTO 0) <= "111"; |
|
363 | 366 | state <= IDLE; |
|
364 | 367 | |
|
365 | 368 | WHEN OTHERS => NULL; |
|
366 | 369 | END CASE; |
|
367 | 370 | |
|
368 | 371 | END IF; |
|
369 | 372 | END PROCESS DMAWriteFSM_p; |
|
370 | 373 | |
|
371 | 374 | dma_valid_burst <= '0' WHEN header_select = '1' ELSE component_send; |
|
372 | 375 | dma_valid <= header_send WHEN header_select = '1' ELSE '0'; |
|
373 | 376 | dma_data <= header_data WHEN header_select = '1' ELSE fifo_data; |
|
374 | 377 | dma_addr <= address; |
|
375 | 378 | fifo_ren <= fifo_ren_trash WHEN header_select = '1' ELSE dma_ren; |
|
376 | 379 | |
|
377 | 380 | component_send_ok <= '0' WHEN header_select = '1' ELSE dma_done; |
|
378 | 381 | component_send_ko <= '0'; |
|
379 | 382 | |
|
380 | 383 | header_send_ok <= '0' WHEN header_select = '0' ELSE dma_done; |
|
381 | 384 | header_send_ko <= '0'; |
|
382 | 385 | |
|
383 | 386 | END Behavioral; |
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