@@ -425,7 +425,7 BEGIN -- beh | |||||
425 | pirq_ms => 6, |
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425 | pirq_ms => 6, | |
426 | pirq_wfp => 14, |
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426 | pirq_wfp => 14, | |
427 | hindex => 2, |
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427 | hindex => 2, | |
428 |
top_lfr_version => X"00010 |
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428 | top_lfr_version => X"000105") -- aa.bb.cc version | |
429 | PORT MAP ( |
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429 | PORT MAP ( | |
430 | clk => clk_25, |
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430 | clk => clk_25, | |
431 | rstn => reset, |
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431 | rstn => reset, |
@@ -84,7 +84,12 Load <= FFT_Load; | |||||
84 | PTS => gPTS, |
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84 | PTS => gPTS, | |
85 | HALFPTS => gHALFPTS, |
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85 | HALFPTS => gHALFPTS, | |
86 | inBuf_RWDLY => gInBuf_RWDLY) |
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86 | inBuf_RWDLY => gInBuf_RWDLY) | |
87 | port map(clkm,start,rstn,Drive_Write,Link_Read,Drive_DataIM,Drive_DataRE,FFT_Load,open,FFT_DataIM,FFT_DataRE,FFT_Valid,FFT_Ready); |
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87 | port map(clkm,start,rstn, | |
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88 | Drive_Write,Link_Read, | |||
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89 | Drive_DataIM,Drive_DataRE, | |||
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90 | FFT_Load,open, | |||
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91 | FFT_DataIM,FFT_DataRE, | |||
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92 | FFT_Valid,FFT_Ready); | |||
88 |
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93 | |||
89 |
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94 | |||
90 | LINK : Linker_FFT |
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95 | LINK : Linker_FFT | |
@@ -92,4 +97,4 Load <= FFT_Load; | |||||
92 | port map(clkm,rstn,FFT_Ready,FFT_Valid,FifoOUT_Full,FFT_DataRE,FFT_DataIM,Link_Read,Write,ReUse,Data); |
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97 | port map(clkm,rstn,FFT_Ready,FFT_Valid,FifoOUT_Full,FFT_DataRE,FFT_DataIM,Link_Read,Write,ReUse,Data); | |
93 |
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98 | |||
94 |
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99 | |||
95 | end architecture; No newline at end of file |
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100 | end architecture; |
@@ -47,7 +47,7 ENTITY lpp_lfr_apbreg IS | |||||
47 | pmask : INTEGER := 16#fff#; |
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47 | pmask : INTEGER := 16#fff#; | |
48 | pirq_ms : INTEGER := 0; |
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48 | pirq_ms : INTEGER := 0; | |
49 | pirq_wfp : INTEGER := 1; |
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49 | pirq_wfp : INTEGER := 1; | |
50 | top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0)); |
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50 | top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0) := X"000000"); | |
51 | PORT ( |
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51 | PORT ( | |
52 | -- AMBA AHB system signals |
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52 | -- AMBA AHB system signals | |
53 | HCLK : IN STD_ULOGIC; |
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53 | HCLK : IN STD_ULOGIC; | |
@@ -541,4 +541,4 BEGIN -- beh | |||||
541 |
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541 | |||
542 | run_ms <= reg_sp.config_ms_run; |
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542 | run_ms <= reg_sp.config_ms_run; | |
543 |
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543 | |||
544 |
END beh; |
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544 | END beh; No newline at end of file |
@@ -28,7 +28,7 USE GRLIB.DMA2AHB_Package.ALL; | |||||
28 |
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28 | |||
29 | ENTITY lpp_lfr_ms IS |
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29 | ENTITY lpp_lfr_ms IS | |
30 | GENERIC ( |
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30 | GENERIC ( | |
31 | Mem_use : INTEGER |
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31 | Mem_use : INTEGER := use_RAM | |
32 | ); |
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32 | ); | |
33 | PORT ( |
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33 | PORT ( | |
34 | clk : IN STD_LOGIC; |
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34 | clk : IN STD_LOGIC; | |
@@ -148,6 +148,10 ARCHITECTURE Behavioral OF lpp_lfr_ms IS | |||||
148 | ----------------------------------------------------------------------------- |
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148 | ----------------------------------------------------------------------------- | |
149 | SIGNAL data_time : STD_LOGIC_VECTOR(47 DOWNTO 0); |
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149 | SIGNAL data_time : STD_LOGIC_VECTOR(47 DOWNTO 0); | |
150 |
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150 | |||
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151 | SIGNAL debug_reg_s : STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
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152 | SIGNAL dma_valid_s : STD_LOGIC; | |||
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153 | SIGNAL dma_valid_burst_s : STD_LOGIC; | |||
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154 | ||||
151 | BEGIN |
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155 | BEGIN | |
152 |
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156 | |||
153 | ----------------------------------------------------------------------------- |
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157 | ----------------------------------------------------------------------------- | |
@@ -340,8 +344,8 BEGIN | |||||
340 |
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344 | |||
341 | dma_addr => dma_addr, |
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345 | dma_addr => dma_addr, | |
342 | dma_data => dma_data, |
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346 | dma_data => dma_data, | |
343 | dma_valid => dma_valid, |
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347 | dma_valid => dma_valid_s, | |
344 | dma_valid_burst => dma_valid_burst, |
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348 | dma_valid_burst => dma_valid_burst_s, | |
345 | dma_ren => dma_ren, |
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349 | dma_ren => dma_ren, | |
346 | dma_done => dma_done, |
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350 | dma_done => dma_done, | |
347 |
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351 | |||
@@ -351,7 +355,7 BEGIN | |||||
351 | ready_matrix_f2 => ready_matrix_f2, |
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355 | ready_matrix_f2 => ready_matrix_f2, | |
352 | error_anticipating_empty_fifo => error_anticipating_empty_fifo, |
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356 | error_anticipating_empty_fifo => error_anticipating_empty_fifo, | |
353 | error_bad_component_error => error_bad_component_error, |
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357 | error_bad_component_error => error_bad_component_error, | |
354 | debug_reg => debug_reg, |
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358 | debug_reg => debug_reg_s, | |
355 | status_ready_matrix_f0_0 => status_ready_matrix_f0_0, |
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359 | status_ready_matrix_f0_0 => status_ready_matrix_f0_0, | |
356 | status_ready_matrix_f0_1 => status_ready_matrix_f0_1, |
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360 | status_ready_matrix_f0_1 => status_ready_matrix_f0_1, | |
357 | status_ready_matrix_f1 => status_ready_matrix_f1, |
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361 | status_ready_matrix_f1 => status_ready_matrix_f1, | |
@@ -371,4 +375,20 BEGIN | |||||
371 | matrix_time_f2 => matrix_time_f2 |
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375 | matrix_time_f2 => matrix_time_f2 | |
372 | ); |
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376 | ); | |
373 |
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377 | |||
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378 | dma_valid <= dma_valid_s; | |||
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379 | dma_valid_burst <= dma_valid_burst_s; | |||
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380 | ||||
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381 | debug_reg(9 DOWNTO 0) <= debug_reg_s(9 DOWNTO 0); | |||
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382 | debug_reg(10) <= Head_Empty; | |||
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383 | debug_reg(11) <= DMA_Read; | |||
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384 | debug_reg(12) <= Head_Val; | |||
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385 | debug_reg(13) <= DMA_ack; | |||
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386 | debug_reg(14) <= dma_ren; | |||
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387 | debug_reg(15) <= dma_done; | |||
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388 | debug_reg(16) <= dma_valid_s; | |||
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389 | debug_reg(17) <= dma_valid_burst_s; | |||
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390 | debug_reg(31 DOWNTO 18) <= (OTHERS => '0'); | |||
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391 | ||||
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392 | ||||
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393 | ||||
374 | END Behavioral; |
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394 | END Behavioral; |
@@ -200,6 +200,7 BEGIN | |||||
200 | debug_reg_s(31 DOWNTO 0) <= (OTHERS => '0'); |
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200 | debug_reg_s(31 DOWNTO 0) <= (OTHERS => '0'); | |
201 |
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201 | |||
202 | ELSIF HCLK'EVENT AND HCLK = '1' THEN -- rising clock edge |
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202 | ELSIF HCLK'EVENT AND HCLK = '1' THEN -- rising clock edge | |
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203 | debug_reg_s(31 DOWNTO 10) <= (OTHERS => '0'); | |||
203 |
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204 | |||
204 |
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205 | CASE state IS | |
205 | WHEN IDLE => |
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206 | WHEN IDLE => | |
@@ -214,6 +215,9 BEGIN | |||||
214 | ready_matrix_f2 <= '0'; |
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215 | ready_matrix_f2 <= '0'; | |
215 | error_bad_component_error <= '0'; |
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216 | error_bad_component_error <= '0'; | |
216 | header_select <= '1'; |
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217 | header_select <= '1'; | |
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218 | IF header_val = '1' THEN | |||
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219 | header_ack <= '1'; | |||
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220 | END IF; | |||
217 | IF header_val = '1' AND fifo_empty = '0' AND send_matrix = '1' THEN |
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221 | IF header_val = '1' AND fifo_empty = '0' AND send_matrix = '1' THEN | |
218 | debug_reg_s(5 DOWNTO 4) <= header(1 DOWNTO 0); |
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222 | debug_reg_s(5 DOWNTO 4) <= header(1 DOWNTO 0); | |
219 | debug_reg_s(9 DOWNTO 6) <= header(5 DOWNTO 2); |
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223 | debug_reg_s(9 DOWNTO 6) <= header(5 DOWNTO 2); | |
@@ -226,9 +230,9 BEGIN | |||||
226 |
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230 | |||
227 | WHEN CHECK_COMPONENT_TYPE => |
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231 | WHEN CHECK_COMPONENT_TYPE => | |
228 | debug_reg_s(2 DOWNTO 0) <= "001"; |
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232 | debug_reg_s(2 DOWNTO 0) <= "001"; | |
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233 | header_ack <= '0'; | |||
229 |
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234 | |||
230 | IF header_check_ok = '1' THEN |
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235 | IF header_check_ok = '1' THEN | |
231 | header_ack <= '1'; |
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232 | header_send <= '0'; |
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236 | header_send <= '0'; | |
233 | -- |
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237 | -- | |
234 | IF component_type = "0000" THEN |
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238 | IF component_type = "0000" THEN | |
@@ -256,7 +260,6 BEGIN | |||||
256 | ELSE |
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260 | ELSE | |
257 | error_bad_component_error <= '1'; |
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261 | error_bad_component_error <= '1'; | |
258 | component_type_pre <= "0000"; |
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262 | component_type_pre <= "0000"; | |
259 | header_ack <= '1'; |
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|||
260 | state <= TRASH_FIFO; |
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263 | state <= TRASH_FIFO; | |
261 | END IF; |
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264 | END IF; | |
262 |
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265 |
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