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1 1 LIBRARY ieee;
2 2 USE ieee.std_logic_1164.ALL;
3 3 USE ieee.numeric_std.ALL;
4 4
5 5 LIBRARY lpp;
6 6 USE lpp.lpp_ad_conv.ALL;
7 7 USE lpp.iir_filter.ALL;
8 8 USE lpp.FILTERcfg.ALL;
9 9 USE lpp.lpp_memory.ALL;
10 10 USE lpp.lpp_waveform_pkg.ALL;
11 11 USE lpp.lpp_dma_pkg.ALL;
12 12 USE lpp.lpp_top_lfr_pkg.ALL;
13 13 USE lpp.lpp_lfr_pkg.ALL;
14 14 USE lpp.general_purpose.ALL;
15 15
16 16 LIBRARY techmap;
17 17 USE techmap.gencomp.ALL;
18 18
19 19 LIBRARY grlib;
20 20 USE grlib.amba.ALL;
21 21 USE grlib.stdlib.ALL;
22 22 USE grlib.devices.ALL;
23 23 USE GRLIB.DMA2AHB_Package.ALL;
24 24
25 25 ENTITY lpp_lfr IS
26 26 GENERIC (
27 27 Mem_use : INTEGER := use_RAM;
28 28 nb_data_by_buffer_size : INTEGER := 11;
29 nb_word_by_buffer_size : INTEGER := 11;
29 -- nb_word_by_buffer_size : INTEGER := 11; -- TODO
30 30 nb_snapshot_param_size : INTEGER := 11;
31 31 delta_vector_size : INTEGER := 20;
32 32 delta_vector_size_f0_2 : INTEGER := 7;
33 33
34 34 pindex : INTEGER := 4;
35 35 paddr : INTEGER := 4;
36 36 pmask : INTEGER := 16#fff#;
37 37 pirq_ms : INTEGER := 0;
38 38 pirq_wfp : INTEGER := 1;
39 39
40 40 hindex : INTEGER := 2;
41 41
42 42 top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0) := (OTHERS => '0')
43 43
44 44 );
45 45 PORT (
46 46 clk : IN STD_LOGIC;
47 47 rstn : IN STD_LOGIC;
48 48 -- SAMPLE
49 49 sample_B : IN Samples(2 DOWNTO 0);
50 50 sample_E : IN Samples(4 DOWNTO 0);
51 51 sample_val : IN STD_LOGIC;
52 52 -- APB
53 53 apbi : IN apb_slv_in_type;
54 54 apbo : OUT apb_slv_out_type;
55 55 -- AHB
56 56 ahbi : IN AHB_Mst_In_Type;
57 57 ahbo : OUT AHB_Mst_Out_Type;
58 58 -- TIME
59 59 coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- todo
60 60 fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); -- todo
61 61 --
62 62 data_shaping_BW : OUT STD_LOGIC
63 63 --
64 64 --
65 65 -- observation_vector_0: OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
66 66 -- observation_vector_1: OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
67 67
68 68 -- observation_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
69 69
70 70 --debug
71 71 --debug_f0_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0);
72 72 --debug_f0_data_valid : OUT STD_LOGIC;
73 73 --debug_f1_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0);
74 74 --debug_f1_data_valid : OUT STD_LOGIC;
75 75 --debug_f2_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0);
76 76 --debug_f2_data_valid : OUT STD_LOGIC;
77 77 --debug_f3_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0);
78 78 --debug_f3_data_valid : OUT STD_LOGIC;
79 79
80 80 ---- debug FIFO_IN
81 81 --debug_f0_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
82 82 --debug_f0_data_fifo_in_valid : OUT STD_LOGIC;
83 83 --debug_f1_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
84 84 --debug_f1_data_fifo_in_valid : OUT STD_LOGIC;
85 85 --debug_f2_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
86 86 --debug_f2_data_fifo_in_valid : OUT STD_LOGIC;
87 87 --debug_f3_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
88 88 --debug_f3_data_fifo_in_valid : OUT STD_LOGIC;
89 89
90 90 ----debug FIFO OUT
91 91 --debug_f0_data_fifo_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
92 92 --debug_f0_data_fifo_out_valid : OUT STD_LOGIC;
93 93 --debug_f1_data_fifo_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
94 94 --debug_f1_data_fifo_out_valid : OUT STD_LOGIC;
95 95 --debug_f2_data_fifo_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
96 96 --debug_f2_data_fifo_out_valid : OUT STD_LOGIC;
97 97 --debug_f3_data_fifo_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
98 98 --debug_f3_data_fifo_out_valid : OUT STD_LOGIC;
99 99
100 100 ----debug DMA IN
101 101 --debug_f0_data_dma_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
102 102 --debug_f0_data_dma_in_valid : OUT STD_LOGIC;
103 103 --debug_f1_data_dma_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
104 104 --debug_f1_data_dma_in_valid : OUT STD_LOGIC;
105 105 --debug_f2_data_dma_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
106 106 --debug_f2_data_dma_in_valid : OUT STD_LOGIC;
107 107 --debug_f3_data_dma_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
108 108 --debug_f3_data_dma_in_valid : OUT STD_LOGIC
109 109 );
110 110 END lpp_lfr;
111 111
112 112 ARCHITECTURE beh OF lpp_lfr IS
113 113 --SIGNAL sample : Samples14v(7 DOWNTO 0);
114 114 SIGNAL sample_s : Samples(7 DOWNTO 0);
115 115 --
116 116 SIGNAL data_shaping_SP0 : STD_LOGIC;
117 117 SIGNAL data_shaping_SP1 : STD_LOGIC;
118 118 SIGNAL data_shaping_R0 : STD_LOGIC;
119 119 SIGNAL data_shaping_R1 : STD_LOGIC;
120 120 SIGNAL data_shaping_R2 : STD_LOGIC;
121 121 --
122 122 SIGNAL sample_f0_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
123 123 SIGNAL sample_f1_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
124 124 SIGNAL sample_f2_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
125 125 --
126 126 SIGNAL sample_f0_val : STD_LOGIC;
127 127 SIGNAL sample_f1_val : STD_LOGIC;
128 128 SIGNAL sample_f2_val : STD_LOGIC;
129 129 SIGNAL sample_f3_val : STD_LOGIC;
130 130 --
131 131 SIGNAL sample_f0_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
132 132 SIGNAL sample_f1_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
133 133 SIGNAL sample_f2_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
134 134 SIGNAL sample_f3_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
135 135 --
136 136 SIGNAL sample_f0_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
137 137 SIGNAL sample_f1_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
138 138 SIGNAL sample_f2_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
139 139
140 140 -- SM
141 141 SIGNAL ready_matrix_f0 : STD_LOGIC;
142 142 SIGNAL ready_matrix_f0_1 : STD_LOGIC;
143 143 SIGNAL ready_matrix_f1 : STD_LOGIC;
144 144 SIGNAL ready_matrix_f2 : STD_LOGIC;
145 145 -- SIGNAL error_anticipating_empty_fifo : STD_LOGIC;
146 146 -- SIGNAL error_bad_component_error : STD_LOGIC;
147 147 -- SIGNAL debug_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
148 148 SIGNAL status_ready_matrix_f0 : STD_LOGIC;
149 149 SIGNAL status_ready_matrix_f0_1 : STD_LOGIC;
150 150 SIGNAL status_ready_matrix_f1 : STD_LOGIC;
151 151 SIGNAL status_ready_matrix_f2 : STD_LOGIC;
152 152 -- SIGNAL status_error_anticipating_empty_fifo : STD_LOGIC;
153 153 -- SIGNAL status_error_bad_component_error : STD_LOGIC;
154 154 --SIGNAL config_active_interruption_onNewMatrix : STD_LOGIC;
155 155 -- SIGNAL config_active_interruption_onError : STD_LOGIC;
156 156 SIGNAL addr_matrix_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
157 157 SIGNAL addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
158 158 SIGNAL addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
159 159 SIGNAL length_matrix_f0 : STD_LOGIC_VECTOR(25 DOWNTO 0);
160 160 SIGNAL length_matrix_f1 : STD_LOGIC_VECTOR(25 DOWNTO 0);
161 161 SIGNAL length_matrix_f2 : STD_LOGIC_VECTOR(25 DOWNTO 0);
162 162
163 163 -- WFP
164 SIGNAL status_full : STD_LOGIC_VECTOR(3 DOWNTO 0);
165 SIGNAL status_full_ack : STD_LOGIC_VECTOR(3 DOWNTO 0);
166 SIGNAL status_full_err : STD_LOGIC_VECTOR(3 DOWNTO 0);
164 --SIGNAL status_full : STD_LOGIC_VECTOR(3 DOWNTO 0);
165 --SIGNAL status_full_ack : STD_LOGIC_VECTOR(3 DOWNTO 0);
166 --SIGNAL status_full_err : STD_LOGIC_VECTOR(3 DOWNTO 0);
167 167 SIGNAL status_new_err : STD_LOGIC_VECTOR(3 DOWNTO 0);
168 168 SIGNAL delta_snapshot : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
169 169 SIGNAL delta_f0 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
170 170 SIGNAL delta_f0_2 : STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0);
171 171 SIGNAL delta_f1 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
172 172 SIGNAL delta_f2 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
173 173
174 174 SIGNAL nb_data_by_buffer : STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
175 SIGNAL nb_word_by_buffer : STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0);
176 175 SIGNAL nb_snapshot_param : STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
177 176 SIGNAL enable_f0 : STD_LOGIC;
178 177 SIGNAL enable_f1 : STD_LOGIC;
179 178 SIGNAL enable_f2 : STD_LOGIC;
180 179 SIGNAL enable_f3 : STD_LOGIC;
181 180 SIGNAL burst_f0 : STD_LOGIC;
182 181 SIGNAL burst_f1 : STD_LOGIC;
183 182 SIGNAL burst_f2 : STD_LOGIC;
184 SIGNAL addr_data_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
185 SIGNAL addr_data_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
186 SIGNAL addr_data_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
187 SIGNAL addr_data_f3 : STD_LOGIC_VECTOR(31 DOWNTO 0);
188 183
189 184 SIGNAL run : STD_LOGIC;
190 185 SIGNAL start_date : STD_LOGIC_VECTOR(30 DOWNTO 0);
191 186
192 SIGNAL data_f0_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
193 SIGNAL data_f0_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
194 SIGNAL data_f0_data_out_valid : STD_LOGIC;
195 SIGNAL data_f0_data_out_valid_burst : STD_LOGIC;
196 SIGNAL data_f0_data_out_ren : STD_LOGIC;
197 --f1
198 SIGNAL data_f1_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
199 SIGNAL data_f1_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
200 SIGNAL data_f1_data_out_valid : STD_LOGIC;
201 SIGNAL data_f1_data_out_valid_burst : STD_LOGIC;
202 SIGNAL data_f1_data_out_ren : STD_LOGIC;
203 --f2
204 SIGNAL data_f2_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
205 SIGNAL data_f2_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
206 SIGNAL data_f2_data_out_valid : STD_LOGIC;
207 SIGNAL data_f2_data_out_valid_burst : STD_LOGIC;
208 SIGNAL data_f2_data_out_ren : STD_LOGIC;
209 --f3
210 SIGNAL data_f3_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
211 SIGNAL data_f3_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
212 SIGNAL data_f3_data_out_valid : STD_LOGIC;
213 SIGNAL data_f3_data_out_valid_burst : STD_LOGIC;
214 SIGNAL data_f3_data_out_ren : STD_LOGIC;
215
216 187 -----------------------------------------------------------------------------
217 188 --
218 189 -----------------------------------------------------------------------------
219 190 SIGNAL data_f0_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
220 191 SIGNAL data_f0_data_out_valid_s : STD_LOGIC;
221 192 SIGNAL data_f0_data_out_valid_burst_s : STD_LOGIC;
222 193 --f1
223 194 SIGNAL data_f1_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
224 195 SIGNAL data_f1_data_out_valid_s : STD_LOGIC;
225 196 SIGNAL data_f1_data_out_valid_burst_s : STD_LOGIC;
226 197 --f2
227 198 SIGNAL data_f2_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
228 199 SIGNAL data_f2_data_out_valid_s : STD_LOGIC;
229 200 SIGNAL data_f2_data_out_valid_burst_s : STD_LOGIC;
230 201 --f3
231 202 SIGNAL data_f3_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
232 203 SIGNAL data_f3_data_out_valid_s : STD_LOGIC;
233 204 SIGNAL data_f3_data_out_valid_burst_s : STD_LOGIC;
234 205
206 SIGNAL wfp_status_buffer_ready : STD_LOGIC_VECTOR(3 DOWNTO 0);
207 SIGNAL wfp_addr_buffer : STD_LOGIC_VECTOR(32*4 DOWNTO 0);
208 SIGNAL wfp_length_buffer : STD_LOGIC_VECTOR(25 DOWNTO 0);
209 SIGNAL wfp_ready_buffer : STD_LOGIC_VECTOR(3 DOWNTO 0);
210 SIGNAL wfp_buffer_time : STD_LOGIC_VECTOR(48*4-1 DOWNTO 0);
211 SIGNAL wfp_error_buffer_full : STD_LOGIC_VECTOR(3 DOWNTO 0);
235 212 -----------------------------------------------------------------------------
236 213 -- DMA RR
237 214 -----------------------------------------------------------------------------
238 215 SIGNAL dma_sel_valid : STD_LOGIC;
239 216 SIGNAL dma_rr_valid : STD_LOGIC_VECTOR(3 DOWNTO 0);
240 217 SIGNAL dma_rr_grant_s : STD_LOGIC_VECTOR(3 DOWNTO 0);
241 218 SIGNAL dma_rr_grant_ms : STD_LOGIC_VECTOR(3 DOWNTO 0);
242 219 SIGNAL dma_rr_valid_ms : STD_LOGIC_VECTOR(3 DOWNTO 0);
243 220
244 221 SIGNAL dma_rr_grant : STD_LOGIC_VECTOR(4 DOWNTO 0);
245 222 SIGNAL dma_sel : STD_LOGIC_VECTOR(4 DOWNTO 0);
246 223
247 224 -----------------------------------------------------------------------------
248 225 -- DMA_REG
249 226 -----------------------------------------------------------------------------
250 227 SIGNAL ongoing_reg : STD_LOGIC;
251 228 SIGNAL dma_sel_reg : STD_LOGIC_VECTOR(3 DOWNTO 0);
252 229 SIGNAL dma_send_reg : STD_LOGIC;
253 230 SIGNAL dma_valid_burst_reg : STD_LOGIC; -- (1 => BURST , 0 => SINGLE)
254 231 SIGNAL dma_address_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
255 232 SIGNAL dma_data_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
256 233
257 234
258 235 -----------------------------------------------------------------------------
259 236 -- DMA
260 237 -----------------------------------------------------------------------------
261 238 SIGNAL dma_send : STD_LOGIC;
262 239 SIGNAL dma_valid_burst : STD_LOGIC; -- (1 => BURST , 0 => SINGLE)
263 240 SIGNAL dma_done : STD_LOGIC;
264 241 SIGNAL dma_ren : STD_LOGIC;
265 242 SIGNAL dma_address : STD_LOGIC_VECTOR(31 DOWNTO 0);
266 243 SIGNAL dma_data : STD_LOGIC_VECTOR(31 DOWNTO 0);
267 244 SIGNAL dma_data_2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
268 245
269 246 -----------------------------------------------------------------------------
270 247 -- MS
271 248 -----------------------------------------------------------------------------
272 249
273 250 SIGNAL data_ms_addr : STD_LOGIC_VECTOR(31 DOWNTO 0);
274 251 SIGNAL data_ms_data : STD_LOGIC_VECTOR(31 DOWNTO 0);
275 252 SIGNAL data_ms_valid : STD_LOGIC;
276 253 SIGNAL data_ms_valid_burst : STD_LOGIC;
277 254 SIGNAL data_ms_ren : STD_LOGIC;
278 255 SIGNAL data_ms_done : STD_LOGIC;
279 256 SIGNAL dma_ms_ongoing : STD_LOGIC;
280 257
281 258 SIGNAL run_ms : STD_LOGIC;
282 259 SIGNAL ms_softandhard_rstn : STD_LOGIC;
283 260
284 261 SIGNAL matrix_time_f0 : STD_LOGIC_VECTOR(47 DOWNTO 0);
285 262 -- SIGNAL matrix_time_f0_1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
286 263 SIGNAL matrix_time_f1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
287 264 SIGNAL matrix_time_f2 : STD_LOGIC_VECTOR(47 DOWNTO 0);
288 265
289 266
290 267 SIGNAL error_buffer_full : STD_LOGIC;
291 268 SIGNAL error_input_fifo_write : STD_LOGIC_VECTOR(2 DOWNTO 0);
292 269
293 270 -- SIGNAL debug_ms : STD_LOGIC_VECTOR(31 DOWNTO 0);
294 271 SIGNAL debug_signal : STD_LOGIC_VECTOR(31 DOWNTO 0);
295 272
296 273 -----------------------------------------------------------------------------
297 274 SIGNAL dma_fifo_burst_valid : STD_LOGIC_VECTOR(4 DOWNTO 0);
298 275 SIGNAL dma_fifo_data : STD_LOGIC_VECTOR(32*5-1 DOWNTO 0);
299 276 SIGNAL dma_fifo_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
300 277 SIGNAL dma_buffer_new : STD_LOGIC_VECTOR(4 DOWNTO 0);
301 278 SIGNAL dma_buffer_addr : STD_LOGIC_VECTOR(32*5-1 DOWNTO 0);
302 279 SIGNAL dma_buffer_length : STD_LOGIC_VECTOR(26*5-1 DOWNTO 0);
303 280 SIGNAL dma_buffer_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
304 281 SIGNAL dma_buffer_full_err : STD_LOGIC_VECTOR(4 DOWNTO 0);
305 282 SIGNAL dma_grant_error : STD_LOGIC;
306 283
307 284 BEGIN
308 285
309 286 sample_s(4 DOWNTO 0) <= sample_E(4 DOWNTO 0);
310 287 sample_s(7 DOWNTO 5) <= sample_B(2 DOWNTO 0);
311 288
312 289 --all_channel : FOR i IN 7 DOWNTO 0 GENERATE
313 290 -- sample_s(i) <= sample(i)(13) & sample(i)(13) & sample(i);
314 291 --END GENERATE all_channel;
315 292
316 293 -----------------------------------------------------------------------------
317 294 lpp_lfr_filter_1 : lpp_lfr_filter
318 295 GENERIC MAP (
319 296 Mem_use => Mem_use)
320 297 PORT MAP (
321 298 sample => sample_s,
322 299 sample_val => sample_val,
323 300 clk => clk,
324 301 rstn => rstn,
325 302 data_shaping_SP0 => data_shaping_SP0,
326 303 data_shaping_SP1 => data_shaping_SP1,
327 304 data_shaping_R0 => data_shaping_R0,
328 305 data_shaping_R1 => data_shaping_R1,
329 306 data_shaping_R2 => data_shaping_R2,
330 307 sample_f0_val => sample_f0_val,
331 308 sample_f1_val => sample_f1_val,
332 309 sample_f2_val => sample_f2_val,
333 310 sample_f3_val => sample_f3_val,
334 311 sample_f0_wdata => sample_f0_data,
335 312 sample_f1_wdata => sample_f1_data,
336 313 sample_f2_wdata => sample_f2_data,
337 314 sample_f3_wdata => sample_f3_data);
338 315
339 316 -----------------------------------------------------------------------------
340 317 lpp_lfr_apbreg_1 : lpp_lfr_apbreg
341 318 GENERIC MAP (
342 319 nb_data_by_buffer_size => nb_data_by_buffer_size,
343 nb_word_by_buffer_size => nb_word_by_buffer_size,
320 -- nb_word_by_buffer_size => nb_word_by_buffer_size, -- TODO
344 321 nb_snapshot_param_size => nb_snapshot_param_size,
345 322 delta_vector_size => delta_vector_size,
346 323 delta_vector_size_f0_2 => delta_vector_size_f0_2,
347 324 pindex => pindex,
348 325 paddr => paddr,
349 326 pmask => pmask,
350 327 pirq_ms => pirq_ms,
351 328 pirq_wfp => pirq_wfp,
352 329 top_lfr_version => top_lfr_version)
353 330 PORT MAP (
354 331 HCLK => clk,
355 332 HRESETn => rstn,
356 333 apbi => apbi,
357 334 apbo => apbo,
358 335
359 336 run_ms => run_ms,
360 337
361 338 ready_matrix_f0 => ready_matrix_f0,
362 339 ready_matrix_f1 => ready_matrix_f1,
363 340 ready_matrix_f2 => ready_matrix_f2,
364 341 error_buffer_full => error_buffer_full, -- TODO
365 342 error_input_fifo_write => error_input_fifo_write, -- TODO
366 343 status_ready_matrix_f0 => status_ready_matrix_f0,
367 344 status_ready_matrix_f1 => status_ready_matrix_f1,
368 345 status_ready_matrix_f2 => status_ready_matrix_f2,
369 346
370 347 matrix_time_f0 => matrix_time_f0,
371 348 matrix_time_f1 => matrix_time_f1,
372 349 matrix_time_f2 => matrix_time_f2,
373 350
374 351 addr_matrix_f0 => addr_matrix_f0,
375 352 addr_matrix_f1 => addr_matrix_f1,
376 353 addr_matrix_f2 => addr_matrix_f2,
377 354
378 355 length_matrix_f0 => length_matrix_f0,
379 356 length_matrix_f1 => length_matrix_f1,
380 357 length_matrix_f2 => length_matrix_f2,
381 358 -------------------------------------------------------------------------
382 status_full => status_full,
383 status_full_ack => status_full_ack,
384 status_full_err => status_full_err,
359 --status_full => status_full, -- TODo
360 --status_full_ack => status_full_ack, -- TODo
361 --status_full_err => status_full_err, -- TODo
385 362 status_new_err => status_new_err,
386 363 data_shaping_BW => data_shaping_BW,
387 364 data_shaping_SP0 => data_shaping_SP0,
388 365 data_shaping_SP1 => data_shaping_SP1,
389 366 data_shaping_R0 => data_shaping_R0,
390 367 data_shaping_R1 => data_shaping_R1,
391 368 data_shaping_R2 => data_shaping_R2,
392 369 delta_snapshot => delta_snapshot,
393 370 delta_f0 => delta_f0,
394 371 delta_f0_2 => delta_f0_2,
395 372 delta_f1 => delta_f1,
396 373 delta_f2 => delta_f2,
397 374 nb_data_by_buffer => nb_data_by_buffer,
398 nb_word_by_buffer => nb_word_by_buffer,
375 -- nb_word_by_buffer => nb_word_by_buffer, -- TODO
399 376 nb_snapshot_param => nb_snapshot_param,
400 377 enable_f0 => enable_f0,
401 378 enable_f1 => enable_f1,
402 379 enable_f2 => enable_f2,
403 380 enable_f3 => enable_f3,
404 381 burst_f0 => burst_f0,
405 382 burst_f1 => burst_f1,
406 383 burst_f2 => burst_f2,
407 384 run => run,
408 addr_data_f0 => addr_data_f0,
409 addr_data_f1 => addr_data_f1,
410 addr_data_f2 => addr_data_f2,
411 addr_data_f3 => addr_data_f3,
412 385 start_date => start_date,
413 debug_signal => debug_signal);
386 -- debug_signal => debug_signal,
387 wfp_status_buffer_ready => wfp_status_buffer_ready,-- TODO
388 wfp_addr_buffer => wfp_addr_buffer,-- TODO
389 wfp_length_buffer => wfp_length_buffer,-- TODO
390
391 wfp_ready_buffer => wfp_ready_buffer,-- TODO
392 wfp_buffer_time => wfp_buffer_time,-- TODO
393 wfp_error_buffer_full => wfp_error_buffer_full -- TODO
394 );
414 395
415 396 -----------------------------------------------------------------------------
416 397 -----------------------------------------------------------------------------
417 398 lpp_waveform_1 : lpp_waveform
418 399 GENERIC MAP (
419 400 tech => inferred,
420 401 data_size => 6*16,
421 402 nb_data_by_buffer_size => nb_data_by_buffer_size,
422 nb_word_by_buffer_size => nb_word_by_buffer_size,
423 403 nb_snapshot_param_size => nb_snapshot_param_size,
424 404 delta_vector_size => delta_vector_size,
425 405 delta_vector_size_f0_2 => delta_vector_size_f0_2
426 406 )
427 407 PORT MAP (
428 408 clk => clk,
429 409 rstn => rstn,
430 410
431 411 reg_run => run,
432 412 reg_start_date => start_date,
433 413 reg_delta_snapshot => delta_snapshot,
434 414 reg_delta_f0 => delta_f0,
435 415 reg_delta_f0_2 => delta_f0_2,
436 416 reg_delta_f1 => delta_f1,
437 417 reg_delta_f2 => delta_f2,
438 418
439 419 enable_f0 => enable_f0,
440 420 enable_f1 => enable_f1,
441 421 enable_f2 => enable_f2,
442 422 enable_f3 => enable_f3,
443 423 burst_f0 => burst_f0,
444 424 burst_f1 => burst_f1,
445 425 burst_f2 => burst_f2,
446 426
447 427 nb_data_by_buffer => nb_data_by_buffer,
448 nb_word_by_buffer => nb_word_by_buffer,
449 428 nb_snapshot_param => nb_snapshot_param,
450 status_full => status_full,
451 status_full_ack => status_full_ack,
452 status_full_err => status_full_err,
453 429 status_new_err => status_new_err,
430
431 status_buffer_ready => wfp_status_buffer_ready,
432 addr_buffer => wfp_addr_buffer,
433 length_buffer => wfp_length_buffer,
434 ready_buffer => wfp_ready_buffer,
435 buffer_time => wfp_buffer_time,
436 error_buffer_full => wfp_error_buffer_full,
454 437
455 438 coarse_time => coarse_time,
456 439 fine_time => fine_time,
457 440
458 441 --f0
459 addr_data_f0 => addr_data_f0,
460 442 data_f0_in_valid => sample_f0_val,
461 443 data_f0_in => sample_f0_data,
462 444 --f1
463 addr_data_f1 => addr_data_f1,
464 445 data_f1_in_valid => sample_f1_val,
465 446 data_f1_in => sample_f1_data,
466 447 --f2
467 addr_data_f2 => addr_data_f2,
468 448 data_f2_in_valid => sample_f2_val,
469 449 data_f2_in => sample_f2_data,
470 450 --f3
471 addr_data_f3 => addr_data_f3,
472 451 data_f3_in_valid => sample_f3_val,
473 452 data_f3_in => sample_f3_data,
474 453 -- OUTPUT -- DMA interface
475 --f0
476 data_f0_addr_out => data_f0_addr_out_s,
477 data_f0_data_out => data_f0_data_out,
478 data_f0_data_out_valid => data_f0_data_out_valid_s,
479 data_f0_data_out_valid_burst => data_f0_data_out_valid_burst_s,
480 data_f0_data_out_ren => data_f0_data_out_ren,
481 --f1
482 data_f1_addr_out => data_f1_addr_out_s,
483 data_f1_data_out => data_f1_data_out,
484 data_f1_data_out_valid => data_f1_data_out_valid_s,
485 data_f1_data_out_valid_burst => data_f1_data_out_valid_burst_s,
486 data_f1_data_out_ren => data_f1_data_out_ren,
487 --f2
488 data_f2_addr_out => data_f2_addr_out_s,
489 data_f2_data_out => data_f2_data_out,
490 data_f2_data_out_valid => data_f2_data_out_valid_s,
491 data_f2_data_out_valid_burst => data_f2_data_out_valid_burst_s,
492 data_f2_data_out_ren => data_f2_data_out_ren,
493 --f3
494 data_f3_addr_out => data_f3_addr_out_s,
495 data_f3_data_out => data_f3_data_out,
496 data_f3_data_out_valid => data_f3_data_out_valid_s,
497 data_f3_data_out_valid_burst => data_f3_data_out_valid_burst_s,
498 data_f3_data_out_ren => data_f3_data_out_ren ,
499
500 -------------------------------------------------------------------------
501 observation_reg => OPEN
502
503 );
504
505
506 -----------------------------------------------------------------------------
507 -- TEMP
508 -----------------------------------------------------------------------------
509
510 PROCESS (clk, rstn)
511 BEGIN -- PROCESS
512 IF rstn = '0' THEN -- asynchronous reset (active low)
513 data_f0_data_out_valid <= '0';
514 data_f0_data_out_valid_burst <= '0';
515 data_f1_data_out_valid <= '0';
516 data_f1_data_out_valid_burst <= '0';
517 data_f2_data_out_valid <= '0';
518 data_f2_data_out_valid_burst <= '0';
519 data_f3_data_out_valid <= '0';
520 data_f3_data_out_valid_burst <= '0';
521 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
522 data_f0_data_out_valid <= data_f0_data_out_valid_s;
523 data_f0_data_out_valid_burst <= data_f0_data_out_valid_burst_s;
524 data_f1_data_out_valid <= data_f1_data_out_valid_s;
525 data_f1_data_out_valid_burst <= data_f1_data_out_valid_burst_s;
526 data_f2_data_out_valid <= data_f2_data_out_valid_s;
527 data_f2_data_out_valid_burst <= data_f2_data_out_valid_burst_s;
528 data_f3_data_out_valid <= data_f3_data_out_valid_s;
529 data_f3_data_out_valid_burst <= data_f3_data_out_valid_burst_s;
530 END IF;
531 END PROCESS;
532
533 data_f0_addr_out <= data_f0_addr_out_s;
534 data_f1_addr_out <= data_f1_addr_out_s;
535 data_f2_addr_out <= data_f2_addr_out_s;
536 data_f3_addr_out <= data_f3_addr_out_s;
537
538 -----------------------------------------------------------------------------
539 -- RoundRobin Selection For DMA
540 -----------------------------------------------------------------------------
541
542 dma_rr_valid(0) <= data_f0_data_out_valid OR data_f0_data_out_valid_burst;
543 dma_rr_valid(1) <= data_f1_data_out_valid OR data_f1_data_out_valid_burst;
544 dma_rr_valid(2) <= data_f2_data_out_valid OR data_f2_data_out_valid_burst;
545 dma_rr_valid(3) <= data_f3_data_out_valid OR data_f3_data_out_valid_burst;
546
547 RR_Arbiter_4_1 : RR_Arbiter_4
548 PORT MAP (
549 clk => clk,
550 rstn => rstn,
551 in_valid => dma_rr_valid,
552 out_grant => dma_rr_grant_s);
553
554 dma_rr_valid_ms(0) <= data_ms_valid OR data_ms_valid_burst;
555 dma_rr_valid_ms(1) <= '0' WHEN dma_rr_grant_s = "0000" ELSE '1';
556 dma_rr_valid_ms(2) <= '0';
557 dma_rr_valid_ms(3) <= '0';
558
559 RR_Arbiter_4_2 : RR_Arbiter_4
560 PORT MAP (
561 clk => clk,
562 rstn => rstn,
563 in_valid => dma_rr_valid_ms,
564 out_grant => dma_rr_grant_ms);
565
566 dma_rr_grant <= dma_rr_grant_ms(0) & "0000" WHEN dma_rr_grant_ms(0) = '1' ELSE '0' & dma_rr_grant_s;
567
454
455 dma_fifo_valid_burst => dma_fifo_burst_valid(3 DOWNTO 0),
456 dma_fifo_data => dma_fifo_data(32*4-1 DOWNTO 0),
457 dma_fifo_ren => dma_fifo_ren(3 DOWNTO 0),
458 dma_buffer_new => dma_buffer_new(3 DOWNTO 0),
459 dma_buffer_addr => dma_buffer_addr(32*4-1 DOWNTO 0),
460 dma_buffer_length => dma_buffer_length(26*4-1 DOWNTO 0),
461 dma_buffer_full => dma_buffer_full(3 DOWNTO 0),
462 dma_buffer_full_err => dma_buffer_full_err(3 DOWNTO 0)
568 463
569 -----------------------------------------------------------------------------
570 -- in : dma_rr_grant
571 -- send
572 -- out : dma_sel
573 -- dma_valid_burst
574 -- dma_sel_valid
575 -----------------------------------------------------------------------------
576 PROCESS (clk, rstn)
577 BEGIN -- PROCESS
578 IF rstn = '0' THEN -- asynchronous reset (active low)
579 dma_sel <= (OTHERS => '0');
580 dma_send <= '0';
581 dma_valid_burst <= '0';
582 data_ms_done <= '0';
583 dma_ms_ongoing <= '0';
584 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
585 IF run = '1' THEN
586 data_ms_done <= '0';
587 IF dma_sel = "00000" OR dma_done = '1' THEN
588 dma_sel <= dma_rr_grant;
589 IF dma_rr_grant(0) = '1' THEN
590 dma_ms_ongoing <= '0';
591 dma_send <= '1';
592 dma_valid_burst <= data_f0_data_out_valid_burst;
593 dma_sel_valid <= data_f0_data_out_valid;
594 ELSIF dma_rr_grant(1) = '1' THEN
595 dma_ms_ongoing <= '0';
596 dma_send <= '1';
597 dma_valid_burst <= data_f1_data_out_valid_burst;
598 dma_sel_valid <= data_f1_data_out_valid;
599 ELSIF dma_rr_grant(2) = '1' THEN
600 dma_ms_ongoing <= '0';
601 dma_send <= '1';
602 dma_valid_burst <= data_f2_data_out_valid_burst;
603 dma_sel_valid <= data_f2_data_out_valid;
604 ELSIF dma_rr_grant(3) = '1' THEN
605 dma_ms_ongoing <= '0';
606 dma_send <= '1';
607 dma_valid_burst <= data_f3_data_out_valid_burst;
608 dma_sel_valid <= data_f3_data_out_valid;
609 ELSIF dma_rr_grant(4) = '1' THEN
610 dma_ms_ongoing <= '1';
611 dma_send <= '1';
612 dma_valid_burst <= data_ms_valid_burst;
613 dma_sel_valid <= data_ms_valid;
614 --ELSE
615 --dma_ms_ongoing <= '0';
616 END IF;
617
618 IF dma_ms_ongoing = '1' AND dma_done = '1' THEN
619 data_ms_done <= '1';
620 END IF;
621 ELSE
622 dma_sel <= dma_sel;
623 dma_send <= '0';
624 END IF;
625 ELSE
626 data_ms_done <= '0';
627 dma_sel <= (OTHERS => '0');
628 dma_send <= '0';
629 dma_valid_burst <= '0';
630 END IF;
631 END IF;
632 END PROCESS;
633
634
635 dma_address <= data_f0_addr_out WHEN dma_sel(0) = '1' ELSE
636 data_f1_addr_out WHEN dma_sel(1) = '1' ELSE
637 data_f2_addr_out WHEN dma_sel(2) = '1' ELSE
638 data_f3_addr_out WHEN dma_sel(3) = '1' ELSE
639 data_ms_addr;
640
641 dma_data <= data_f0_data_out WHEN dma_sel(0) = '1' ELSE
642 data_f1_data_out WHEN dma_sel(1) = '1' ELSE
643 data_f2_data_out WHEN dma_sel(2) = '1' ELSE
644 data_f3_data_out WHEN dma_sel(3) = '1' ELSE
645 data_ms_data;
646
647 data_f0_data_out_ren <= dma_ren WHEN dma_sel(0) = '1' ELSE '1';
648 data_f1_data_out_ren <= dma_ren WHEN dma_sel(1) = '1' ELSE '1';
649 data_f2_data_out_ren <= dma_ren WHEN dma_sel(2) = '1' ELSE '1';
650 data_f3_data_out_ren <= dma_ren WHEN dma_sel(3) = '1' ELSE '1';
651 data_ms_ren <= dma_ren WHEN dma_sel(4) = '1' ELSE '1';
652
653 dma_data_2 <= dma_data;
654
655
656 -----------------------------------------------------------------------------
657 -- DMA
658 -----------------------------------------------------------------------------
659 lpp_dma_singleOrBurst_1 : lpp_dma_singleOrBurst
660 GENERIC MAP (
661 tech => inferred,
662 hindex => hindex)
663 PORT MAP (
664 HCLK => clk,
665 HRESETn => rstn,
666 run => run,
667 AHB_Master_In => OPEN,
668 AHB_Master_Out => OPEN,
669
670 send => dma_send,
671 valid_burst => dma_valid_burst,
672 done => dma_done,
673 ren => dma_ren,
674 address => dma_address,
675 data => dma_data_2);
464 );
676 465
677 466 -----------------------------------------------------------------------------
678 467 -- Matrix Spectral
679 468 -----------------------------------------------------------------------------
680 469 sample_f0_wen <= NOT(sample_f0_val) & NOT(sample_f0_val) & NOT(sample_f0_val) &
681 470 NOT(sample_f0_val) & NOT(sample_f0_val);
682 471 sample_f1_wen <= NOT(sample_f1_val) & NOT(sample_f1_val) & NOT(sample_f1_val) &
683 472 NOT(sample_f1_val) & NOT(sample_f1_val);
684 473 sample_f2_wen <= NOT(sample_f2_val) & NOT(sample_f2_val) & NOT(sample_f2_val) &
685 474 NOT(sample_f2_val) & NOT(sample_f2_val);
686 475
687 476 sample_f0_wdata <= sample_f0_data((3*16)-1 DOWNTO (1*16)) & sample_f0_data((6*16)-1 DOWNTO (3*16)); -- (MSB) E2 E1 B2 B1 B0 (LSB)
688 477 sample_f1_wdata <= sample_f1_data((3*16)-1 DOWNTO (1*16)) & sample_f1_data((6*16)-1 DOWNTO (3*16));
689 478 sample_f2_wdata <= sample_f2_data((3*16)-1 DOWNTO (1*16)) & sample_f2_data((6*16)-1 DOWNTO (3*16));
690 479
691 480 -------------------------------------------------------------------------------
692 481
693 482 ms_softandhard_rstn <= rstn AND run_ms AND run;
694 483
695 484 -----------------------------------------------------------------------------
696 485 lpp_lfr_ms_1 : lpp_lfr_ms
697 486 GENERIC MAP (
698 487 Mem_use => Mem_use)
699 488 PORT MAP (
700 489 clk => clk,
701 490 rstn => ms_softandhard_rstn, --rstn,
702 491 run => run_ms,
703 492
704 493 coarse_time => coarse_time,
705 494 fine_time => fine_time,
706 495
707 496 sample_f0_wen => sample_f0_wen,
708 497 sample_f0_wdata => sample_f0_wdata,
709 498 sample_f1_wen => sample_f1_wen,
710 499 sample_f1_wdata => sample_f1_wdata,
711 500 sample_f2_wen => sample_f2_wen,
712 501 sample_f2_wdata => sample_f2_wdata,
713 502
714 503 --DMA
715 504 dma_fifo_burst_valid => dma_fifo_burst_valid(4), -- OUT
716 505 dma_fifo_data => dma_fifo_data((4+1)*32-1 DOWNTO 4*32), -- OUT
717 506 dma_fifo_ren => dma_fifo_ren(4), -- IN
718 507 dma_buffer_new => dma_buffer_new(4), -- OUT
719 508 dma_buffer_addr => dma_buffer_addr((4+1)*32-1 DOWNTO 4*32), -- OUT
720 509 dma_buffer_length => dma_buffer_length((4+1)*26-1 DOWNTO 4*26), -- OUT
721 510 dma_buffer_full => dma_buffer_full(4), -- IN
722 511 dma_buffer_full_err => dma_buffer_full_err(4), -- IN
723 512
724 513
725 514
726 515 --REG
727 516 ready_matrix_f0 => ready_matrix_f0,
728 517 ready_matrix_f1 => ready_matrix_f1,
729 518 ready_matrix_f2 => ready_matrix_f2,
730 519 error_buffer_full => error_buffer_full,
731 520 error_input_fifo_write => error_input_fifo_write,
732 521
733 522 status_ready_matrix_f0 => status_ready_matrix_f0,
734 523 status_ready_matrix_f1 => status_ready_matrix_f1,
735 524 status_ready_matrix_f2 => status_ready_matrix_f2,
736 525 addr_matrix_f0 => addr_matrix_f0,
737 526 addr_matrix_f1 => addr_matrix_f1,
738 527 addr_matrix_f2 => addr_matrix_f2,
739 528
740 529 length_matrix_f0 => length_matrix_f0,
741 530 length_matrix_f1 => length_matrix_f1,
742 531 length_matrix_f2 => length_matrix_f2,
743 532
744 533 matrix_time_f0 => matrix_time_f0,
745 534 matrix_time_f1 => matrix_time_f1,
746 535 matrix_time_f2 => matrix_time_f2);
747 536
748 537 -----------------------------------------------------------------------------
749 538
750 539 DMA_SubSystem_1 : DMA_SubSystem
751 540 GENERIC MAP (
752 541 hindex => hindex)
753 542 PORT MAP (
754 543 clk => clk,
755 544 rstn => rstn,
756 545 run => run_ms,
757 546 ahbi => ahbi,
758 547 ahbo => ahbo,
759 548
760 549 fifo_burst_valid => dma_fifo_burst_valid, --fifo_burst_valid,
761 550 fifo_data => dma_fifo_data, --fifo_data,
762 551 fifo_ren => dma_fifo_ren, --fifo_ren,
763 552
764 553 buffer_new => dma_buffer_new, --buffer_new,
765 554 buffer_addr => dma_buffer_addr, --buffer_addr,
766 555 buffer_length => dma_buffer_length, --buffer_length,
767 556 buffer_full => dma_buffer_full, --buffer_full,
768 557 buffer_full_err => dma_buffer_full_err, --buffer_full_err,
769 558 grant_error => dma_grant_error); --grant_error);
770 559
771 560 END beh;
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@@ -1,721 +1,770
1 1 ------------------------------------------------------------------------------
2 2 -- This file is a part of the LPP VHDL IP LIBRARY
3 3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 3 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 -------------------------------------------------------------------------------
19 19 -- Author : Jean-christophe Pellion
20 20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 21 -- jean-christophe.pellion@easii-ic.com
22 22 ----------------------------------------------------------------------------
23 23 LIBRARY ieee;
24 24 USE ieee.std_logic_1164.ALL;
25 25 USE ieee.numeric_std.ALL;
26 26 LIBRARY grlib;
27 27 USE grlib.amba.ALL;
28 28 USE grlib.stdlib.ALL;
29 29 USE grlib.devices.ALL;
30 30 LIBRARY lpp;
31 31 USE lpp.lpp_lfr_pkg.ALL;
32 32 --USE lpp.lpp_amba.ALL;
33 33 USE lpp.apb_devices_list.ALL;
34 34 USE lpp.lpp_memory.ALL;
35 35 LIBRARY techmap;
36 36 USE techmap.gencomp.ALL;
37 37
38 38 ENTITY lpp_lfr_apbreg IS
39 39 GENERIC (
40 40 nb_data_by_buffer_size : INTEGER := 11;
41 nb_word_by_buffer_size : INTEGER := 11;
41 -- nb_word_by_buffer_size : INTEGER := 11;
42 42 nb_snapshot_param_size : INTEGER := 11;
43 43 delta_vector_size : INTEGER := 20;
44 44 delta_vector_size_f0_2 : INTEGER := 3;
45 45
46 46 pindex : INTEGER := 4;
47 47 paddr : INTEGER := 4;
48 48 pmask : INTEGER := 16#fff#;
49 49 pirq_ms : INTEGER := 0;
50 50 pirq_wfp : INTEGER := 1;
51 51 top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0) := X"000000");
52 52 PORT (
53 53 -- AMBA AHB system signals
54 54 HCLK : IN STD_ULOGIC;
55 55 HRESETn : IN STD_ULOGIC;
56 56
57 57 -- AMBA APB Slave Interface
58 58 apbi : IN apb_slv_in_type;
59 59 apbo : OUT apb_slv_out_type;
60 60
61 61 ---------------------------------------------------------------------------
62 62 -- Spectral Matrix Reg
63 63 run_ms : OUT STD_LOGIC;
64 64 -- IN
65 65 ready_matrix_f0 : IN STD_LOGIC;
66 66 ready_matrix_f1 : IN STD_LOGIC;
67 67 ready_matrix_f2 : IN STD_LOGIC;
68 68
69 69 -- error_bad_component_error : IN STD_LOGIC;
70 70 error_buffer_full : IN STD_LOGIC; -- TODO
71 71 error_input_fifo_write : IN STD_LOGIC_VECTOR(2 DOWNTO 0); -- TODO
72 72
73 73 -- debug_reg : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
74 74
75 75 -- OUT
76 76 status_ready_matrix_f0 : OUT STD_LOGIC;
77 77 status_ready_matrix_f1 : OUT STD_LOGIC;
78 78 status_ready_matrix_f2 : OUT STD_LOGIC;
79 79
80 80 --config_active_interruption_onNewMatrix : OUT STD_LOGIC;
81 81 --config_active_interruption_onError : OUT STD_LOGIC;
82 82
83 83 addr_matrix_f0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
84 84 addr_matrix_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
85 85 addr_matrix_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
86 86
87 87 length_matrix_f0 : OUT STD_LOGIC_VECTOR(25 DOWNTO 0);
88 88 length_matrix_f1 : OUT STD_LOGIC_VECTOR(25 DOWNTO 0);
89 89 length_matrix_f2 : OUT STD_LOGIC_VECTOR(25 DOWNTO 0);
90 90
91 91 matrix_time_f0 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
92 92 matrix_time_f1 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
93 93 matrix_time_f2 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
94 94
95 95 ---------------------------------------------------------------------------
96 96 ---------------------------------------------------------------------------
97 97 -- WaveForm picker Reg
98 status_full : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
99 status_full_ack : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
100 status_full_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
98 --status_full : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
99 --status_full_ack : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
100 --status_full_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
101 101 status_new_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
102
102
103 103 -- OUT
104 104 data_shaping_BW : OUT STD_LOGIC;
105 105 data_shaping_SP0 : OUT STD_LOGIC;
106 106 data_shaping_SP1 : OUT STD_LOGIC;
107 107 data_shaping_R0 : OUT STD_LOGIC;
108 108 data_shaping_R1 : OUT STD_LOGIC;
109 109 data_shaping_R2 : OUT STD_LOGIC;
110 110
111 111 delta_snapshot : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
112 112 delta_f0 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
113 113 delta_f0_2 : OUT STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0);
114 114 delta_f1 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
115 115 delta_f2 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
116 116 nb_data_by_buffer : OUT STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
117 nb_word_by_buffer : OUT STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0);
117 --nb_word_by_buffer : OUT STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0);
118 118 nb_snapshot_param : OUT STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
119 119
120 120 enable_f0 : OUT STD_LOGIC;
121 121 enable_f1 : OUT STD_LOGIC;
122 122 enable_f2 : OUT STD_LOGIC;
123 123 enable_f3 : OUT STD_LOGIC;
124 124
125 125 burst_f0 : OUT STD_LOGIC;
126 126 burst_f1 : OUT STD_LOGIC;
127 127 burst_f2 : OUT STD_LOGIC;
128 128
129 129 run : OUT STD_LOGIC;
130 130
131 addr_data_f0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
132 addr_data_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
133 addr_data_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
134 addr_data_f3 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
135 131 start_date : OUT STD_LOGIC_VECTOR(30 DOWNTO 0);
136 ---------------------------------------------------------------------------
137 debug_signal : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
138 ---------------------------------------------------------------------------
132
133 wfp_status_buffer_ready : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
134 wfp_addr_buffer : OUT STD_LOGIC_VECTOR(32*4 DOWNTO 0);
135 wfp_length_buffer : OUT STD_LOGIC_VECTOR(25 DOWNTO 0);
136 wfp_ready_buffer : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
137 wfp_buffer_time : IN STD_LOGIC_VECTOR(48*4-1 DOWNTO 0);
138 wfp_error_buffer_full : IN STD_LOGIC_VECTOR(3 DOWNTO 0)
139
139 140 );
140 141
141 142 END lpp_lfr_apbreg;
142 143
143 144 ARCHITECTURE beh OF lpp_lfr_apbreg IS
144 145
145 146 CONSTANT REVISION : INTEGER := 1;
146 147
147 148 CONSTANT pconfig : apb_config_type := (
148 149 0 => ahb_device_reg (VENDOR_LPP, LPP_LFR, 0, REVISION, pirq_wfp),
149 150 1 => apb_iobar(paddr, pmask));
150 151
151 152 TYPE lpp_SpectralMatrix_regs IS RECORD
152 153 config_active_interruption_onNewMatrix : STD_LOGIC;
153 154 config_active_interruption_onError : STD_LOGIC;
154 155 config_ms_run : STD_LOGIC;
155 156 status_ready_matrix_f0_0 : STD_LOGIC;
156 157 status_ready_matrix_f1_0 : STD_LOGIC;
157 158 status_ready_matrix_f2_0 : STD_LOGIC;
158 159 status_ready_matrix_f0_1 : STD_LOGIC;
159 160 status_ready_matrix_f1_1 : STD_LOGIC;
160 161 status_ready_matrix_f2_1 : STD_LOGIC;
161 162 -- status_error_bad_component_error : STD_LOGIC;
162 163 status_error_buffer_full : STD_LOGIC;
163 164 status_error_input_fifo_write : STD_LOGIC_VECTOR(2 DOWNTO 0);
164 165
165 166 addr_matrix_f0_0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
166 167 addr_matrix_f0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
167 168 addr_matrix_f1_0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
168 169 addr_matrix_f1_1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
169 170 addr_matrix_f2_0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
170 171 addr_matrix_f2_1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
171 172
172 173 length_matrix : STD_LOGIC_VECTOR(25 DOWNTO 0);
173 174
174 175 time_matrix_f0_0 : STD_LOGIC_VECTOR(47 DOWNTO 0);
175 176 time_matrix_f0_1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
176 177 time_matrix_f1_0 : STD_LOGIC_VECTOR(47 DOWNTO 0);
177 178 time_matrix_f1_1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
178 179 time_matrix_f2_0 : STD_LOGIC_VECTOR(47 DOWNTO 0);
179 180 time_matrix_f2_1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
180 181 END RECORD;
181 182 SIGNAL reg_sp : lpp_SpectralMatrix_regs;
182 183
183 184 TYPE lpp_WaveformPicker_regs IS RECORD
184 status_full : STD_LOGIC_VECTOR(3 DOWNTO 0);
185 status_full_err : STD_LOGIC_VECTOR(3 DOWNTO 0);
185 -- status_full : STD_LOGIC_VECTOR(3 DOWNTO 0);
186 -- status_full_err : STD_LOGIC_VECTOR(3 DOWNTO 0);
186 187 status_new_err : STD_LOGIC_VECTOR(3 DOWNTO 0);
187 188 data_shaping_BW : STD_LOGIC;
188 189 data_shaping_SP0 : STD_LOGIC;
189 190 data_shaping_SP1 : STD_LOGIC;
190 191 data_shaping_R0 : STD_LOGIC;
191 192 data_shaping_R1 : STD_LOGIC;
192 193 data_shaping_R2 : STD_LOGIC;
193 194 delta_snapshot : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
194 195 delta_f0 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
195 196 delta_f0_2 : STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0);
196 197 delta_f1 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
197 198 delta_f2 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
198 199 nb_data_by_buffer : STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
199 nb_word_by_buffer : STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0);
200 -- nb_word_by_buffer : STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0);
200 201 nb_snapshot_param : STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
201 202 enable_f0 : STD_LOGIC;
202 203 enable_f1 : STD_LOGIC;
203 204 enable_f2 : STD_LOGIC;
204 205 enable_f3 : STD_LOGIC;
205 206 burst_f0 : STD_LOGIC;
206 207 burst_f1 : STD_LOGIC;
207 208 burst_f2 : STD_LOGIC;
208 209 run : STD_LOGIC;
209 addr_data_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
210 addr_data_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
211 addr_data_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
212 addr_data_f3 : STD_LOGIC_VECTOR(31 DOWNTO 0);
210 status_ready_buffer_f : STD_LOGIC_VECTOR(4*2-1 DOWNTO 0);
211 addr_buffer_f : STD_LOGIC_VECTOR(4*2*32-1 DOWNTO 0);
212 time_buffer_f : STD_LOGIC_VECTOR(4*2*48-1 DOWNTO 0);
213 length_buffer : STD_LOGIC_VECTOR(25 DOWNTO 0);
214 error_buffer_full : STD_LOGIC_VECTOR(3 DOWNTO 0);
213 215 start_date : STD_LOGIC_VECTOR(30 DOWNTO 0);
214 216 END RECORD;
215 217 SIGNAL reg_wp : lpp_WaveformPicker_regs;
216 218
217 219 SIGNAL prdata : STD_LOGIC_VECTOR(31 DOWNTO 0);
218 220
219 221 -----------------------------------------------------------------------------
220 222 -- IRQ
221 223 -----------------------------------------------------------------------------
222 224 CONSTANT IRQ_WFP_SIZE : INTEGER := 12;
223 225 SIGNAL irq_wfp_ZERO : STD_LOGIC_VECTOR(IRQ_WFP_SIZE-1 DOWNTO 0);
224 226 SIGNAL irq_wfp_reg_s : STD_LOGIC_VECTOR(IRQ_WFP_SIZE-1 DOWNTO 0);
225 227 SIGNAL irq_wfp_reg : STD_LOGIC_VECTOR(IRQ_WFP_SIZE-1 DOWNTO 0);
226 228 SIGNAL irq_wfp : STD_LOGIC_VECTOR(IRQ_WFP_SIZE-1 DOWNTO 0);
227 229 SIGNAL ored_irq_wfp : STD_LOGIC;
228 230
229 231 -----------------------------------------------------------------------------
230 232 --
231 233 -----------------------------------------------------------------------------
232 234 SIGNAL reg0_ready_matrix_f0 : STD_LOGIC;
233 235 SIGNAL reg0_addr_matrix_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
234 236 SIGNAL reg0_matrix_time_f0 : STD_LOGIC_VECTOR(47 DOWNTO 0);
235 237
236 238 SIGNAL reg1_ready_matrix_f0 : STD_LOGIC;
237 239 SIGNAL reg1_addr_matrix_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
238 240 SIGNAL reg1_matrix_time_f0 : STD_LOGIC_VECTOR(47 DOWNTO 0);
239 241
240 242 SIGNAL reg0_ready_matrix_f1 : STD_LOGIC;
241 243 SIGNAL reg0_addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
242 244 SIGNAL reg0_matrix_time_f1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
243 245
244 246 SIGNAL reg1_ready_matrix_f1 : STD_LOGIC;
245 247 SIGNAL reg1_addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
246 248 SIGNAL reg1_matrix_time_f1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
247 249
248 250 SIGNAL reg0_ready_matrix_f2 : STD_LOGIC;
249 251 SIGNAL reg0_addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
250 252 SIGNAL reg0_matrix_time_f2 : STD_LOGIC_VECTOR(47 DOWNTO 0);
251 253
252 254 SIGNAL reg1_ready_matrix_f2 : STD_LOGIC;
253 255 SIGNAL reg1_addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
254 256 SIGNAL reg1_matrix_time_f2 : STD_LOGIC_VECTOR(47 DOWNTO 0);
255 257 SIGNAL apbo_irq_ms : STD_LOGIC;
256 258 SIGNAL apbo_irq_wfp : STD_LOGIC;
259 -----------------------------------------------------------------------------
260 SIGNAL reg_ready_buffer_f : STD_LOGIC_VECTOR( 2*4-1 DOWNTO 0);
257 261
258 262 BEGIN -- beh
259 263
260 264 -- status_ready_matrix_f0 <= reg_sp.status_ready_matrix_f0;
261 265 -- status_ready_matrix_f1 <= reg_sp.status_ready_matrix_f1;
262 266 -- status_ready_matrix_f2 <= reg_sp.status_ready_matrix_f2;
263 267
264 268 -- config_active_interruption_onNewMatrix <= reg_sp.config_active_interruption_onNewMatrix;
265 269 -- config_active_interruption_onError <= reg_sp.config_active_interruption_onError;
266 270
267 271
268 272 -- addr_matrix_f0 <= reg_sp.addr_matrix_f0;
269 273 -- addr_matrix_f1 <= reg_sp.addr_matrix_f1;
270 274 -- addr_matrix_f2 <= reg_sp.addr_matrix_f2;
271 275
272 276
273 277 data_shaping_BW <= NOT reg_wp.data_shaping_BW;
274 278 data_shaping_SP0 <= reg_wp.data_shaping_SP0;
275 279 data_shaping_SP1 <= reg_wp.data_shaping_SP1;
276 280 data_shaping_R0 <= reg_wp.data_shaping_R0;
277 281 data_shaping_R1 <= reg_wp.data_shaping_R1;
278 282 data_shaping_R2 <= reg_wp.data_shaping_R2;
279 283
280 284 delta_snapshot <= reg_wp.delta_snapshot;
281 285 delta_f0 <= reg_wp.delta_f0;
282 286 delta_f0_2 <= reg_wp.delta_f0_2;
283 287 delta_f1 <= reg_wp.delta_f1;
284 288 delta_f2 <= reg_wp.delta_f2;
285 289 nb_data_by_buffer <= reg_wp.nb_data_by_buffer;
286 nb_word_by_buffer <= reg_wp.nb_word_by_buffer;
287 290 nb_snapshot_param <= reg_wp.nb_snapshot_param;
288 291
289 292 enable_f0 <= reg_wp.enable_f0;
290 293 enable_f1 <= reg_wp.enable_f1;
291 294 enable_f2 <= reg_wp.enable_f2;
292 295 enable_f3 <= reg_wp.enable_f3;
293 296
294 297 burst_f0 <= reg_wp.burst_f0;
295 298 burst_f1 <= reg_wp.burst_f1;
296 299 burst_f2 <= reg_wp.burst_f2;
297 300
298 301 run <= reg_wp.run;
299 302
300 addr_data_f0 <= reg_wp.addr_data_f0;
301 addr_data_f1 <= reg_wp.addr_data_f1;
302 addr_data_f2 <= reg_wp.addr_data_f2;
303 addr_data_f3 <= reg_wp.addr_data_f3;
303 --addr_data_f0 <= reg_wp.addr_data_f0;
304 --addr_data_f1 <= reg_wp.addr_data_f1;
305 --addr_data_f2 <= reg_wp.addr_data_f2;
306 --addr_data_f3 <= reg_wp.addr_data_f3;
304 307
305 308 start_date <= reg_wp.start_date;
306 309
307 length_matrix_f0 <= reg_sp.length_matrix;
308 length_matrix_f1 <= reg_sp.length_matrix;
309 length_matrix_f2 <= reg_sp.length_matrix;
310 --length_matrix_f0 <= reg_sp.length_matrix;
311 --length_matrix_f1 <= reg_sp.length_matrix;
312 --length_matrix_f2 <= reg_sp.length_matrix;
310 313
311 314
312 315 lpp_lfr_apbreg : PROCESS (HCLK, HRESETn)
313 316 VARIABLE paddr : STD_LOGIC_VECTOR(7 DOWNTO 2);
314 317 BEGIN -- PROCESS lpp_dma_top
315 318 IF HRESETn = '0' THEN -- asynchronous reset (active low)
316 319 reg_sp.config_active_interruption_onNewMatrix <= '0';
317 320 reg_sp.config_active_interruption_onError <= '0';
318 321 reg_sp.config_ms_run <= '1';
319 322 reg_sp.status_ready_matrix_f0_0 <= '0';
320 323 reg_sp.status_ready_matrix_f1_0 <= '0';
321 324 reg_sp.status_ready_matrix_f2_0 <= '0';
322 325 reg_sp.status_ready_matrix_f0_1 <= '0';
323 326 reg_sp.status_ready_matrix_f1_1 <= '0';
324 327 reg_sp.status_ready_matrix_f2_1 <= '0';
325 -- reg_sp.status_error_bad_component_error <= '0';
326 328 reg_sp.status_error_buffer_full <= '0';
327 329 reg_sp.status_error_input_fifo_write <= (OTHERS => '0');
328 330
329 331 reg_sp.addr_matrix_f0_0 <= (OTHERS => '0');
330 332 reg_sp.addr_matrix_f1_0 <= (OTHERS => '0');
331 333 reg_sp.addr_matrix_f2_0 <= (OTHERS => '0');
332 334
333 335 reg_sp.addr_matrix_f0_1 <= (OTHERS => '0');
334 336 reg_sp.addr_matrix_f1_1 <= (OTHERS => '0');
335 337 reg_sp.addr_matrix_f2_1 <= (OTHERS => '0');
336 338
337 339 reg_sp.length_matrix <= (OTHERS => '0');
338 340
339 341 -- reg_sp.time_matrix_f0_0 <= (OTHERS => '0'); -- ok
340 342 -- reg_sp.time_matrix_f1_0 <= (OTHERS => '0'); -- ok
341 343 -- reg_sp.time_matrix_f2_0 <= (OTHERS => '0'); -- ok
342 344
343 345 -- reg_sp.time_matrix_f0_1 <= (OTHERS => '0'); -- ok
344 346 --reg_sp.time_matrix_f1_1 <= (OTHERS => '0'); -- ok
345 347 -- reg_sp.time_matrix_f2_1 <= (OTHERS => '0'); -- ok
346 348
347 349 prdata <= (OTHERS => '0');
348 350
349 351
350 352 apbo_irq_ms <= '0';
351 353 apbo_irq_wfp <= '0';
352 354
353 355
354 status_full_ack <= (OTHERS => '0');
356 -- status_full_ack <= (OTHERS => '0');
355 357
356 358 reg_wp.data_shaping_BW <= '0';
357 359 reg_wp.data_shaping_SP0 <= '0';
358 360 reg_wp.data_shaping_SP1 <= '0';
359 361 reg_wp.data_shaping_R0 <= '0';
360 362 reg_wp.data_shaping_R1 <= '0';
361 363 reg_wp.data_shaping_R2 <= '0';
362 364 reg_wp.enable_f0 <= '0';
363 365 reg_wp.enable_f1 <= '0';
364 366 reg_wp.enable_f2 <= '0';
365 367 reg_wp.enable_f3 <= '0';
366 368 reg_wp.burst_f0 <= '0';
367 369 reg_wp.burst_f1 <= '0';
368 370 reg_wp.burst_f2 <= '0';
369 371 reg_wp.run <= '0';
370 reg_wp.addr_data_f0 <= (OTHERS => '0');
371 reg_wp.addr_data_f1 <= (OTHERS => '0');
372 reg_wp.addr_data_f2 <= (OTHERS => '0');
373 reg_wp.addr_data_f3 <= (OTHERS => '0');
374 reg_wp.status_full <= (OTHERS => '0');
375 reg_wp.status_full_err <= (OTHERS => '0');
372 -- reg_wp.status_full <= (OTHERS => '0');
373 -- reg_wp.status_full_err <= (OTHERS => '0');
376 374 reg_wp.status_new_err <= (OTHERS => '0');
375 reg_wp.error_buffer_full <= (OTHERS => '0');
377 376 reg_wp.delta_snapshot <= (OTHERS => '0');
378 377 reg_wp.delta_f0 <= (OTHERS => '0');
379 378 reg_wp.delta_f0_2 <= (OTHERS => '0');
380 379 reg_wp.delta_f1 <= (OTHERS => '0');
381 380 reg_wp.delta_f2 <= (OTHERS => '0');
382 381 reg_wp.nb_data_by_buffer <= (OTHERS => '0');
383 382 reg_wp.nb_snapshot_param <= (OTHERS => '0');
384 383 reg_wp.start_date <= (OTHERS => '0');
385 384
386 385 ELSIF HCLK'EVENT AND HCLK = '1' THEN -- rising clock edge
387 386
388 status_full_ack <= (OTHERS => '0');
387 -- status_full_ack <= (OTHERS => '0');
389 388
390 389 reg_sp.status_ready_matrix_f0_0 <= reg_sp.status_ready_matrix_f0_0 OR reg0_ready_matrix_f0;
391 390 reg_sp.status_ready_matrix_f1_0 <= reg_sp.status_ready_matrix_f1_0 OR reg0_ready_matrix_f1;
392 391 reg_sp.status_ready_matrix_f2_0 <= reg_sp.status_ready_matrix_f2_0 OR reg0_ready_matrix_f2;
393 392
394 393 reg_sp.status_ready_matrix_f0_1 <= reg_sp.status_ready_matrix_f0_1 OR reg1_ready_matrix_f0;
395 394 reg_sp.status_ready_matrix_f1_1 <= reg_sp.status_ready_matrix_f1_1 OR reg1_ready_matrix_f1;
396 395 reg_sp.status_ready_matrix_f2_1 <= reg_sp.status_ready_matrix_f2_1 OR reg1_ready_matrix_f2;
397 396
398 -- reg_sp.status_error_bad_component_error <= reg_sp.status_error_bad_component_error OR error_bad_component_error;
397 all_status_ready_buffer_bit: FOR I IN 4*2-1 DOWNTO 0 LOOP
398 reg_wp.status_ready_buffer_f(I) <= reg_wp.status_ready_buffer_f(I) OR reg_ready_buffer_f(I);
399 END LOOP all_status_ready_buffer_bit;
400
399 401
400 402 reg_sp.status_error_buffer_full <= reg_sp.status_error_buffer_full OR error_buffer_full;
401 403 reg_sp.status_error_input_fifo_write(0) <= reg_sp.status_error_input_fifo_write(0) OR error_input_fifo_write(0);
402 404 reg_sp.status_error_input_fifo_write(1) <= reg_sp.status_error_input_fifo_write(1) OR error_input_fifo_write(1);
403 405 reg_sp.status_error_input_fifo_write(2) <= reg_sp.status_error_input_fifo_write(2) OR error_input_fifo_write(2);
404 406
405 407
406 408
407 409 all_status : FOR I IN 3 DOWNTO 0 LOOP
408 reg_wp.status_full(I) <= status_full(I) AND reg_wp.run;
409 reg_wp.status_full_err(I) <= status_full_err(I) AND reg_wp.run;
410 reg_wp.status_new_err(I) <= status_new_err(I) AND reg_wp.run;
410 reg_wp.error_buffer_full(I) <= reg_wp.error_buffer_full(I) OR wfp_error_buffer_full(I);
411 reg_wp.status_new_err(I) <= reg_wp.status_new_err(I) OR status_new_err(I);
411 412 END LOOP all_status;
412 413
413 414 paddr := "000000";
414 415 paddr(7 DOWNTO 2) := apbi.paddr(7 DOWNTO 2);
415 416 prdata <= (OTHERS => '0');
416 417 IF apbi.psel(pindex) = '1' THEN
417 418 -- APB DMA READ --
418 419 CASE paddr(7 DOWNTO 2) IS
419 420 --0
420 421 WHEN "000000" => prdata(0) <= reg_sp.config_active_interruption_onNewMatrix;
421 422 prdata(1) <= reg_sp.config_active_interruption_onError;
422 423 prdata(2) <= reg_sp.config_ms_run;
423 424 --1
424 425 WHEN "000001" => prdata(0) <= reg_sp.status_ready_matrix_f0_0;
425 426 prdata(1) <= reg_sp.status_ready_matrix_f0_1;
426 427 prdata(2) <= reg_sp.status_ready_matrix_f1_0;
427 428 prdata(3) <= reg_sp.status_ready_matrix_f1_1;
428 429 prdata(4) <= reg_sp.status_ready_matrix_f2_0;
429 430 prdata(5) <= reg_sp.status_ready_matrix_f2_1;
430 431 -- prdata(6) <= reg_sp.status_error_bad_component_error;
431 432 prdata(7) <= reg_sp.status_error_buffer_full;
432 433 prdata(8) <= reg_sp.status_error_input_fifo_write(0);
433 434 prdata(9) <= reg_sp.status_error_input_fifo_write(1);
434 435 prdata(10) <= reg_sp.status_error_input_fifo_write(2);
435 436 --2
436 437 WHEN "000010" => prdata <= reg_sp.addr_matrix_f0_0;
437 438 --3
438 439 WHEN "000011" => prdata <= reg_sp.addr_matrix_f0_1;
439 440 --4
440 441 WHEN "000100" => prdata <= reg_sp.addr_matrix_f1_0;
441 442 --5
442 443 WHEN "000101" => prdata <= reg_sp.addr_matrix_f1_1;
443 444 --6
444 445 WHEN "000110" => prdata <= reg_sp.addr_matrix_f2_0;
445 446 --7
446 447 WHEN "000111" => prdata <= reg_sp.addr_matrix_f2_1;
447 448 --8
448 449 WHEN "001000" => prdata <= reg_sp.time_matrix_f0_0(47 DOWNTO 16);
449 450 --9
450 451 WHEN "001001" => prdata(15 DOWNTO 0) <= reg_sp.time_matrix_f0_0(15 DOWNTO 0);
451 452 --10
452 453 WHEN "001010" => prdata <= reg_sp.time_matrix_f0_1(47 DOWNTO 16);
453 454 --11
454 455 WHEN "001011" => prdata(15 DOWNTO 0) <= reg_sp.time_matrix_f0_1(15 DOWNTO 0);
455 456 --12
456 457 WHEN "001100" => prdata <= reg_sp.time_matrix_f1_0(47 DOWNTO 16);
457 458 --13
458 459 WHEN "001101" => prdata(15 DOWNTO 0) <= reg_sp.time_matrix_f1_0(15 DOWNTO 0);
459 460 --14
460 461 WHEN "001110" => prdata <= reg_sp.time_matrix_f1_1(47 DOWNTO 16);
461 462 --15
462 463 WHEN "001111" => prdata(15 DOWNTO 0) <= reg_sp.time_matrix_f1_1(15 DOWNTO 0);
463 464 --16
464 465 WHEN "010000" => prdata <= reg_sp.time_matrix_f2_0(47 DOWNTO 16);
465 466 --17
466 467 WHEN "010001" => prdata(15 DOWNTO 0) <= reg_sp.time_matrix_f2_0(15 DOWNTO 0);
467 468 --18
468 469 WHEN "010010" => prdata <= reg_sp.time_matrix_f2_1(47 DOWNTO 16);
469 470 --19
470 471 WHEN "010011" => prdata(15 DOWNTO 0) <= reg_sp.time_matrix_f2_1(15 DOWNTO 0);
471 472 --20
472 473 WHEN "010100" => prdata(25 DOWNTO 0) <= reg_sp.length_matrix;
473 474 ---------------------------------------------------------------------
474 475 --20
475 476 WHEN "010101" => prdata(0) <= reg_wp.data_shaping_BW;
476 477 prdata(1) <= reg_wp.data_shaping_SP0;
477 478 prdata(2) <= reg_wp.data_shaping_SP1;
478 479 prdata(3) <= reg_wp.data_shaping_R0;
479 480 prdata(4) <= reg_wp.data_shaping_R1;
480 481 prdata(5) <= reg_wp.data_shaping_R2;
481 482 --21
482 483 WHEN "010110" => prdata(0) <= reg_wp.enable_f0;
483 484 prdata(1) <= reg_wp.enable_f1;
484 485 prdata(2) <= reg_wp.enable_f2;
485 486 prdata(3) <= reg_wp.enable_f3;
486 487 prdata(4) <= reg_wp.burst_f0;
487 488 prdata(5) <= reg_wp.burst_f1;
488 489 prdata(6) <= reg_wp.burst_f2;
489 490 prdata(7) <= reg_wp.run;
490 491 --22
491 WHEN "010111" => prdata <= reg_wp.addr_data_f0;
492 --23
493 WHEN "011000" => prdata <= reg_wp.addr_data_f1;
494 --24
495 WHEN "011001" => prdata <= reg_wp.addr_data_f2;
496 --25
497 WHEN "011010" => prdata <= reg_wp.addr_data_f3;
498 --26
499 WHEN "011011" => prdata(3 DOWNTO 0) <= reg_wp.status_full;
500 prdata(7 DOWNTO 4) <= reg_wp.status_full_err;
501 prdata(11 DOWNTO 8) <= reg_wp.status_new_err;
492 --ON GOING \/
493 WHEN "010111" => prdata <= reg_wp.addr_buffer_f(32*1-1 DOWNTO 32*0);
494 WHEN "011000" => prdata <= reg_wp.addr_buffer_f(32*2-1 DOWNTO 32*1);
495 WHEN "011001" => prdata <= reg_wp.addr_buffer_f(32*3-1 DOWNTO 32*2);
496 WHEN "011010" => prdata <= reg_wp.addr_buffer_f(32*4-1 DOWNTO 32*3);
497 WHEN "011011" => prdata <= reg_wp.addr_buffer_f(32*5-1 DOWNTO 32*4);
498 WHEN "011100" => prdata <= reg_wp.addr_buffer_f(32*6-1 DOWNTO 32*5);
499 WHEN "011101" => prdata <= reg_wp.addr_buffer_f(32*7-1 DOWNTO 32*6);
500 WHEN "011110" => prdata <= reg_wp.addr_buffer_f(32*8-1 DOWNTO 32*7);
501 --ON GOING /\
502 WHEN "011111" => prdata(7 DOWNTO 0) <= reg_wp.status_ready_buffer_f;
503 prdata(11 DOWNTO 8) <= reg_wp.error_buffer_full;
504 prdata(15 DOWNTO 12) <= reg_wp.status_new_err;
505 --prdata(3 DOWNTO 0) <= reg_wp.status_full;
506 -- prdata(7 DOWNTO 4) <= reg_wp.status_full_err;
502 507 --27
503 WHEN "011100" => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_snapshot;
508 WHEN "100000" => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_snapshot;
504 509 --28
505 WHEN "011101" => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_f0;
510 WHEN "100001" => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_f0;
506 511 --29
507 WHEN "011110" => prdata(delta_vector_size_f0_2-1 DOWNTO 0) <= reg_wp.delta_f0_2;
512 WHEN "100010" => prdata(delta_vector_size_f0_2-1 DOWNTO 0) <= reg_wp.delta_f0_2;
508 513 --30
509 WHEN "011111" => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_f1;
514 WHEN "100011" => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_f1;
510 515 --31
511 WHEN "100000" => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_f2;
516 WHEN "100100" => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_f2;
512 517 --32
513 WHEN "100001" => prdata(nb_data_by_buffer_size-1 DOWNTO 0) <= reg_wp.nb_data_by_buffer;
518 WHEN "100101" => prdata(nb_data_by_buffer_size-1 DOWNTO 0) <= reg_wp.nb_data_by_buffer;
514 519 --33
515 WHEN "100010" => prdata(nb_snapshot_param_size-1 DOWNTO 0) <= reg_wp.nb_snapshot_param;
520 WHEN "100110" => prdata(nb_snapshot_param_size-1 DOWNTO 0) <= reg_wp.nb_snapshot_param;
516 521 --34
517 WHEN "100011" => prdata(30 DOWNTO 0) <= reg_wp.start_date;
522 WHEN "100111" => prdata(30 DOWNTO 0) <= reg_wp.start_date;
518 523 --35
519 WHEN "100100" => prdata(nb_word_by_buffer_size-1 DOWNTO 0) <= reg_wp.nb_word_by_buffer;
524 WHEN "101000" => prdata(15 DOWNTO 0) <= reg_wp.time_buffer_f(48*0+15 DOWNTO 48*0);
525 WHEN "101001" => prdata(31 DOWNTO 0) <= reg_wp.time_buffer_f(48*0+47 DOWNTO 48*0+16);
526 WHEN "101010" => prdata(15 DOWNTO 0) <= reg_wp.time_buffer_f(48*1+15 DOWNTO 48*1);
527 WHEN "101011" => prdata(31 DOWNTO 0) <= reg_wp.time_buffer_f(48*1+47 DOWNTO 48*1+16);
528 WHEN "101100" => prdata(15 DOWNTO 0) <= reg_wp.time_buffer_f(48*2+15 DOWNTO 48*2);
529 WHEN "101110" => prdata(31 DOWNTO 0) <= reg_wp.time_buffer_f(48*2+47 DOWNTO 48*2+16);
530 WHEN "101111" => prdata(15 DOWNTO 0) <= reg_wp.time_buffer_f(48*3+15 DOWNTO 48*3);
531 WHEN "110000" => prdata(31 DOWNTO 0) <= reg_wp.time_buffer_f(48*3+47 DOWNTO 48*3+16);
532
533 WHEN "110001" => prdata(15 DOWNTO 0) <= reg_wp.time_buffer_f(48*4+15 DOWNTO 48*4);
534 WHEN "111010" => prdata(31 DOWNTO 0) <= reg_wp.time_buffer_f(48*4+47 DOWNTO 48*4+16);
535 WHEN "110011" => prdata(15 DOWNTO 0) <= reg_wp.time_buffer_f(48*5+15 DOWNTO 48*5);
536 WHEN "110100" => prdata(31 DOWNTO 0) <= reg_wp.time_buffer_f(48*5+47 DOWNTO 48*5+16);
537 WHEN "110101" => prdata(15 DOWNTO 0) <= reg_wp.time_buffer_f(48*6+15 DOWNTO 48*6);
538 WHEN "110110" => prdata(31 DOWNTO 0) <= reg_wp.time_buffer_f(48*6+47 DOWNTO 48*6+16);
539 WHEN "110111" => prdata(15 DOWNTO 0) <= reg_wp.time_buffer_f(48*7+15 DOWNTO 48*7);
540 WHEN "111000" => prdata(31 DOWNTO 0) <= reg_wp.time_buffer_f(48*7+47 DOWNTO 48*7+16);
541 WHEN "111001" => prdata(25 DOWNTO 0) <= reg_wp.length_buffer;
542
543 -- WHEN "100100" => prdata(nb_word_by_buffer_size-1 DOWNTO 0) <= reg_wp.nb_word_by_buffer;
520 544 ----------------------------------------------------
521 545 WHEN "111100" => prdata(23 DOWNTO 0) <= top_lfr_version(23 DOWNTO 0);
522 546 WHEN OTHERS => NULL;
523 547
524 548 END CASE;
525 549 IF (apbi.pwrite AND apbi.penable) = '1' THEN
526 550 -- APB DMA WRITE --
527 551 CASE paddr(7 DOWNTO 2) IS
528 552 --
529 553 WHEN "000000" => reg_sp.config_active_interruption_onNewMatrix <= apbi.pwdata(0);
530 reg_sp.config_active_interruption_onError <= apbi.pwdata(1);
531 reg_sp.config_ms_run <= apbi.pwdata(2);
554 reg_sp.config_active_interruption_onError <= apbi.pwdata(1);
555 reg_sp.config_ms_run <= apbi.pwdata(2);
532 556
533 557 WHEN "000001" =>
534 558 reg_sp.status_ready_matrix_f0_0 <= ((NOT apbi.pwdata(0) ) AND reg_sp.status_ready_matrix_f0_0 ) OR reg0_ready_matrix_f0;
535 559 reg_sp.status_ready_matrix_f0_1 <= ((NOT apbi.pwdata(1) ) AND reg_sp.status_ready_matrix_f0_1 ) OR reg1_ready_matrix_f0;
536 560 reg_sp.status_ready_matrix_f1_0 <= ((NOT apbi.pwdata(2) ) AND reg_sp.status_ready_matrix_f1_0 ) OR reg0_ready_matrix_f1;
537 561 reg_sp.status_ready_matrix_f1_1 <= ((NOT apbi.pwdata(3) ) AND reg_sp.status_ready_matrix_f1_1 ) OR reg1_ready_matrix_f1;
538 562 reg_sp.status_ready_matrix_f2_0 <= ((NOT apbi.pwdata(4) ) AND reg_sp.status_ready_matrix_f2_0 ) OR reg0_ready_matrix_f2;
539 563 reg_sp.status_ready_matrix_f2_1 <= ((NOT apbi.pwdata(5) ) AND reg_sp.status_ready_matrix_f2_1 ) OR reg1_ready_matrix_f2;
540 564 reg_sp.status_error_buffer_full <= ((NOT apbi.pwdata(7) ) AND reg_sp.status_error_buffer_full ) OR error_buffer_full;
541 565 reg_sp.status_error_input_fifo_write(0) <= ((NOT apbi.pwdata(8) ) AND reg_sp.status_error_input_fifo_write(0)) OR error_input_fifo_write(0);
542 566 reg_sp.status_error_input_fifo_write(1) <= ((NOT apbi.pwdata(9) ) AND reg_sp.status_error_input_fifo_write(1)) OR error_input_fifo_write(1);
543 567 reg_sp.status_error_input_fifo_write(2) <= ((NOT apbi.pwdata(10)) AND reg_sp.status_error_input_fifo_write(2)) OR error_input_fifo_write(2);
544 568 --2
545 569 WHEN "000010" => reg_sp.addr_matrix_f0_0 <= apbi.pwdata;
546 570 WHEN "000011" => reg_sp.addr_matrix_f0_1 <= apbi.pwdata;
547 571 WHEN "000100" => reg_sp.addr_matrix_f1_0 <= apbi.pwdata;
548 572 WHEN "000101" => reg_sp.addr_matrix_f1_1 <= apbi.pwdata;
549 573 WHEN "000110" => reg_sp.addr_matrix_f2_0 <= apbi.pwdata;
550 574 WHEN "000111" => reg_sp.addr_matrix_f2_1 <= apbi.pwdata;
551 575 --8 to 19
552 576 --20
553 577 WHEN "010100" => reg_sp.length_matrix <= apbi.pwdata(25 DOWNTO 0);
554 578 --20
555 579 WHEN "010101" => reg_wp.data_shaping_BW <= apbi.pwdata(0);
556 580 reg_wp.data_shaping_SP0 <= apbi.pwdata(1);
557 581 reg_wp.data_shaping_SP1 <= apbi.pwdata(2);
558 582 reg_wp.data_shaping_R0 <= apbi.pwdata(3);
559 583 reg_wp.data_shaping_R1 <= apbi.pwdata(4);
560 584 reg_wp.data_shaping_R2 <= apbi.pwdata(5);
561 585 WHEN "010110" => reg_wp.enable_f0 <= apbi.pwdata(0);
562 586 reg_wp.enable_f1 <= apbi.pwdata(1);
563 587 reg_wp.enable_f2 <= apbi.pwdata(2);
564 588 reg_wp.enable_f3 <= apbi.pwdata(3);
565 589 reg_wp.burst_f0 <= apbi.pwdata(4);
566 590 reg_wp.burst_f1 <= apbi.pwdata(5);
567 591 reg_wp.burst_f2 <= apbi.pwdata(6);
568 592 reg_wp.run <= apbi.pwdata(7);
569 593 --22
570 WHEN "010111" => reg_wp.addr_data_f0 <= apbi.pwdata;
571 WHEN "011000" => reg_wp.addr_data_f1 <= apbi.pwdata;
572 WHEN "011001" => reg_wp.addr_data_f2 <= apbi.pwdata;
573 WHEN "011010" => reg_wp.addr_data_f3 <= apbi.pwdata;
594 WHEN "010111" => reg_wp.addr_buffer_f(32*1-1 DOWNTO 32*0) <= apbi.pwdata;
595 WHEN "011000" => reg_wp.addr_buffer_f(32*2-1 DOWNTO 32*1) <= apbi.pwdata;
596 WHEN "011001" => reg_wp.addr_buffer_f(32*3-1 DOWNTO 32*2) <= apbi.pwdata;
597 WHEN "011010" => reg_wp.addr_buffer_f(32*4-1 DOWNTO 32*3) <= apbi.pwdata;
598 WHEN "011011" => reg_wp.addr_buffer_f(32*5-1 DOWNTO 32*4) <= apbi.pwdata;
599 WHEN "011100" => reg_wp.addr_buffer_f(32*6-1 DOWNTO 32*5) <= apbi.pwdata;
600 WHEN "011101" => reg_wp.addr_buffer_f(32*7-1 DOWNTO 32*6) <= apbi.pwdata;
601 WHEN "011110" => reg_wp.addr_buffer_f(32*8-1 DOWNTO 32*7) <= apbi.pwdata;
574 602 --26
575 WHEN "011011" => reg_wp.status_full <= apbi.pwdata(3 DOWNTO 0);
576 reg_wp.status_full_err <= apbi.pwdata(7 DOWNTO 4);
577 reg_wp.status_new_err <= apbi.pwdata(11 DOWNTO 8);
578 status_full_ack(0) <= reg_wp.status_full(0) AND NOT apbi.pwdata(0);
579 status_full_ack(1) <= reg_wp.status_full(1) AND NOT apbi.pwdata(1);
580 status_full_ack(2) <= reg_wp.status_full(2) AND NOT apbi.pwdata(2);
581 status_full_ack(3) <= reg_wp.status_full(3) AND NOT apbi.pwdata(3);
582 WHEN "011100" => reg_wp.delta_snapshot <= apbi.pwdata(delta_vector_size-1 DOWNTO 0);
583 WHEN "011101" => reg_wp.delta_f0 <= apbi.pwdata(delta_vector_size-1 DOWNTO 0);
584 WHEN "011110" => reg_wp.delta_f0_2 <= apbi.pwdata(delta_vector_size_f0_2-1 DOWNTO 0);
585 WHEN "011111" => reg_wp.delta_f1 <= apbi.pwdata(delta_vector_size-1 DOWNTO 0);
586 WHEN "100000" => reg_wp.delta_f2 <= apbi.pwdata(delta_vector_size-1 DOWNTO 0);
587 WHEN "100001" => reg_wp.nb_data_by_buffer <= apbi.pwdata(nb_data_by_buffer_size-1 DOWNTO 0);
588 WHEN "100010" => reg_wp.nb_snapshot_param <= apbi.pwdata(nb_snapshot_param_size-1 DOWNTO 0);
589 WHEN "100011" => reg_wp.start_date <= apbi.pwdata(30 DOWNTO 0);
590 WHEN "100100" => reg_wp.nb_word_by_buffer <= apbi.pwdata(nb_word_by_buffer_size-1 DOWNTO 0);
603 WHEN "011111" =>
604 all_reg_wp_status_bit: FOR I IN 3 DOWNTO 0 LOOP
605 reg_wp.status_ready_buffer_f(I) <= ((NOT apbi.pwdata(I) ) AND reg_wp.status_ready_buffer_f(I) ) OR reg_ready_buffer_f(I);
606 reg_wp.status_ready_buffer_f(I*2+1) <= ((NOT apbi.pwdata(I*2+1)) AND reg_wp.status_ready_buffer_f(I*2+1)) OR reg_ready_buffer_f(I*2+1);
607 reg_wp.error_buffer_full(I) <= ((NOT apbi.pwdata(I+8) ) AND reg_wp.error_buffer_full(I) ) OR wfp_error_buffer_full(I);
608 reg_wp.status_new_err(I) <= ((NOT apbi.pwdata(I+12) ) AND reg_wp.status_new_err(I) ) OR status_new_err(I);
609 END LOOP all_reg_wp_status_bit;
610
611 WHEN "100000" => reg_wp.delta_snapshot <= apbi.pwdata(delta_vector_size-1 DOWNTO 0);
612 WHEN "100001" => reg_wp.delta_f0 <= apbi.pwdata(delta_vector_size-1 DOWNTO 0);
613 WHEN "100010" => reg_wp.delta_f0_2 <= apbi.pwdata(delta_vector_size_f0_2-1 DOWNTO 0);
614 WHEN "100011" => reg_wp.delta_f1 <= apbi.pwdata(delta_vector_size-1 DOWNTO 0);
615 WHEN "100100" => reg_wp.delta_f2 <= apbi.pwdata(delta_vector_size-1 DOWNTO 0);
616 WHEN "100101" => reg_wp.nb_data_by_buffer <= apbi.pwdata(nb_data_by_buffer_size-1 DOWNTO 0);
617 WHEN "100110" => reg_wp.nb_snapshot_param <= apbi.pwdata(nb_snapshot_param_size-1 DOWNTO 0);
618 WHEN "100111" => reg_wp.start_date <= apbi.pwdata(30 DOWNTO 0);
619
620 WHEN "111001" => reg_wp.length_buffer <= apbi.pwdata(25 DOWNTO 0);
621
622
623
624
625
626 -- WHEN "100100" => reg_wp.nb_word_by_buffer <= apbi.pwdata(nb_word_by_buffer_size-1 DOWNTO 0);
591 627 --
592 628 WHEN OTHERS => NULL;
593 629 END CASE;
594 630 END IF;
595 631 END IF;
596 632 --apbo.pirq(pirq_ms) <=
597 633 apbo_irq_ms <= ((reg_sp.config_active_interruption_onNewMatrix AND (ready_matrix_f0 OR
598 634 ready_matrix_f1 OR
599 635 ready_matrix_f2)
600 636 )
601 637 OR
602 638 (reg_sp.config_active_interruption_onError AND (
603 639 -- error_bad_component_error OR
604 640 error_buffer_full
605 641 OR error_input_fifo_write(0)
606 642 OR error_input_fifo_write(1)
607 643 OR error_input_fifo_write(2))
608 644 ));
609 645 -- apbo.pirq(pirq_wfp)
610 646 apbo_irq_wfp<= ored_irq_wfp;
611 647
612 648 END IF;
613 649 END PROCESS lpp_lfr_apbreg;
614 650
615 651 apbo.pirq(pirq_ms) <= apbo_irq_ms;
616 652 apbo.pirq(pirq_wfp) <= apbo_irq_wfp;
617 653
618 654 apbo.pindex <= pindex;
619 655 apbo.pconfig <= pconfig;
620 656 apbo.prdata <= prdata;
621 657
622 658 -----------------------------------------------------------------------------
623 659 -- IRQ
624 660 -----------------------------------------------------------------------------
625 irq_wfp_reg_s <= status_full & status_full_err & status_new_err;
661 irq_wfp_reg_s <= wfp_status_buffer_ready & wfp_error_buffer_full & status_new_err;
626 662
627 663 PROCESS (HCLK, HRESETn)
628 664 BEGIN -- PROCESS
629 665 IF HRESETn = '0' THEN -- asynchronous reset (active low)
630 666 irq_wfp_reg <= (OTHERS => '0');
631 667 ELSIF HCLK'EVENT AND HCLK = '1' THEN -- rising clock edge
632 668 irq_wfp_reg <= irq_wfp_reg_s;
633 669 END IF;
634 670 END PROCESS;
635 671
636 672 all_irq_wfp : FOR I IN IRQ_WFP_SIZE-1 DOWNTO 0 GENERATE
637 673 irq_wfp(I) <= (NOT irq_wfp_reg(I)) AND irq_wfp_reg_s(I);
638 674 END GENERATE all_irq_wfp;
639 675
640 676 irq_wfp_ZERO <= (OTHERS => '0');
641 677 ored_irq_wfp <= '0' WHEN irq_wfp = irq_wfp_ZERO ELSE '1';
642 678
643 679 run_ms <= reg_sp.config_ms_run;
644 680
645 681 -----------------------------------------------------------------------------
646 682 --
647 683 -----------------------------------------------------------------------------
648 684 lpp_apbreg_ms_pointer_f0 : lpp_apbreg_ms_pointer
649 685 PORT MAP (
650 686 clk => HCLK,
651 687 rstn => HRESETn,
652 688
653 689 reg0_status_ready_matrix => reg_sp.status_ready_matrix_f0_0,
654 690 reg0_ready_matrix => reg0_ready_matrix_f0,
655 691 reg0_addr_matrix => reg_sp.addr_matrix_f0_0, --reg0_addr_matrix_f0,
656 692 reg0_matrix_time => reg_sp.time_matrix_f0_0, --reg0_matrix_time_f0,
657 693
658 694 reg1_status_ready_matrix => reg_sp.status_ready_matrix_f0_1,
659 695 reg1_ready_matrix => reg1_ready_matrix_f0,
660 696 reg1_addr_matrix => reg_sp.addr_matrix_f0_1, --reg1_addr_matrix_f0,
661 697 reg1_matrix_time => reg_sp.time_matrix_f0_1, --reg1_matrix_time_f0,
662 698
663 699 ready_matrix => ready_matrix_f0,
664 700 status_ready_matrix => status_ready_matrix_f0,
665 701 addr_matrix => addr_matrix_f0,
666 702 matrix_time => matrix_time_f0);
667 703
668 704 lpp_apbreg_ms_pointer_f1 : lpp_apbreg_ms_pointer
669 705 PORT MAP (
670 706 clk => HCLK,
671 707 rstn => HRESETn,
672 708
673 709 reg0_status_ready_matrix => reg_sp.status_ready_matrix_f1_0,
674 710 reg0_ready_matrix => reg0_ready_matrix_f1,
675 711 reg0_addr_matrix => reg_sp.addr_matrix_f1_0, --reg0_addr_matrix_f1,
676 712 reg0_matrix_time => reg_sp.time_matrix_f1_0, --reg0_matrix_time_f1,
677 713
678 714 reg1_status_ready_matrix => reg_sp.status_ready_matrix_f1_1,
679 715 reg1_ready_matrix => reg1_ready_matrix_f1,
680 716 reg1_addr_matrix => reg_sp.addr_matrix_f1_1, --reg1_addr_matrix_f1,
681 717 reg1_matrix_time => reg_sp.time_matrix_f1_1, --reg1_matrix_time_f1,
682 718
683 719 ready_matrix => ready_matrix_f1,
684 720 status_ready_matrix => status_ready_matrix_f1,
685 721 addr_matrix => addr_matrix_f1,
686 722 matrix_time => matrix_time_f1);
687 723
688 724 lpp_apbreg_ms_pointer_f2 : lpp_apbreg_ms_pointer
689 725 PORT MAP (
690 726 clk => HCLK,
691 727 rstn => HRESETn,
692 728
693 729 reg0_status_ready_matrix => reg_sp.status_ready_matrix_f2_0,
694 730 reg0_ready_matrix => reg0_ready_matrix_f2,
695 731 reg0_addr_matrix => reg_sp.addr_matrix_f2_0, --reg0_addr_matrix_f2,
696 732 reg0_matrix_time => reg_sp.time_matrix_f2_0, --reg0_matrix_time_f2,
697 733
698 734 reg1_status_ready_matrix => reg_sp.status_ready_matrix_f2_1,
699 735 reg1_ready_matrix => reg1_ready_matrix_f2,
700 736 reg1_addr_matrix => reg_sp.addr_matrix_f2_1, --reg1_addr_matrix_f2,
701 737 reg1_matrix_time => reg_sp.time_matrix_f2_1, --reg1_matrix_time_f2,
702 738
703 739 ready_matrix => ready_matrix_f2,
704 740 status_ready_matrix => status_ready_matrix_f2,
705 741 addr_matrix => addr_matrix_f2,
706 742 matrix_time => matrix_time_f2);
707 743
708 744 -----------------------------------------------------------------------------
709 debug_signal(31 DOWNTO 12) <= (OTHERS => '0');
710 debug_signal(11 DOWNTO 0) <= apbo_irq_ms & --11
711 reg_sp.status_error_input_fifo_write(2) &--10
712 reg_sp.status_error_input_fifo_write(1) &--9
713 reg_sp.status_error_input_fifo_write(0) &--8
714 reg_sp.status_error_buffer_full &
715 '0' &
716 -- reg_sp.status_error_bad_component_error & --7 6
717 reg_sp.status_ready_matrix_f2_1 & reg_sp.status_ready_matrix_f2_0 &--5 4
718 reg_sp.status_ready_matrix_f1_1 & reg_sp.status_ready_matrix_f1_0 &--3 2
719 reg_sp.status_ready_matrix_f0_1 & reg_sp.status_ready_matrix_f0_0; --1 0
745 all_wfp_pointer: FOR I IN 3 DOWNTO 0 GENERATE
746 lpp_apbreg_wfp_pointer_fi : lpp_apbreg_ms_pointer
747 PORT MAP (
748 clk => HCLK,
749 rstn => HRESETn,
750
751 reg0_status_ready_matrix => reg_wp.status_ready_buffer_f(2*I),
752 reg0_ready_matrix => reg_ready_buffer_f(2*I),
753 reg0_addr_matrix => reg_wp.addr_buffer_f((2*I+1)*32-1 DOWNTO (2*I)*32),
754 reg0_matrix_time => reg_wp.time_buffer_f((2*I+1)*48-1 DOWNTO (2*I)*48),
755
756 reg1_status_ready_matrix => reg_wp.status_ready_buffer_f(2*I+1),
757 reg1_ready_matrix => reg_ready_buffer_f(2*I+1),
758 reg1_addr_matrix => reg_wp.addr_buffer_f((2*I+2)*32-1 DOWNTO (2*I+1)*32),
759 reg1_matrix_time => reg_wp.time_buffer_f((2*I+2)*48-1 DOWNTO (2*I+1)*48),
760
761 ready_matrix => wfp_ready_buffer(I),
762 status_ready_matrix => wfp_status_buffer_ready(I),
763 addr_matrix => wfp_addr_buffer((I+1)*32-1 DOWNTO I*32),
764 matrix_time => wfp_buffer_time((I+1)*48-1 DOWNTO I*48)
765 );
766
767 END GENERATE all_wfp_pointer;
768 -----------------------------------------------------------------------------
720 769
721 END beh;
770 END beh; No newline at end of file
Show file before | Show file after | Hide comments
@@ -1,393 +1,389
1 1 LIBRARY ieee;
2 2 USE ieee.std_logic_1164.ALL;
3 3
4 4 LIBRARY grlib;
5 5 USE grlib.amba.ALL;
6 6
7 7 LIBRARY lpp;
8 8 USE lpp.lpp_ad_conv.ALL;
9 9 USE lpp.iir_filter.ALL;
10 10 USE lpp.FILTERcfg.ALL;
11 11 USE lpp.lpp_memory.ALL;
12 12 LIBRARY techmap;
13 13 USE techmap.gencomp.ALL;
14 14
15 15 PACKAGE lpp_lfr_pkg IS
16 16 -----------------------------------------------------------------------------
17 17 -- TEMP
18 18 -----------------------------------------------------------------------------
19 19 COMPONENT lpp_lfr_ms_test
20 20 GENERIC (
21 21 Mem_use : INTEGER);
22 22 PORT (
23 23 clk : IN STD_LOGIC;
24 24 rstn : IN STD_LOGIC;
25 25
26 26 -- TIME
27 27 coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- todo
28 28 fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); -- todo
29 29 --
30 30 sample_f0_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
31 31 sample_f0_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
32 32 --
33 33 sample_f1_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
34 34 sample_f1_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
35 35 --
36 36 sample_f2_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
37 37 sample_f2_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
38 38
39 39
40 40
41 41 ---------------------------------------------------------------------------
42 42 error_input_fifo_write : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
43 43
44 44 --
45 45 --sample_ren : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
46 46 --sample_full : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
47 47 --sample_empty : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
48 48 --sample_rdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
49 49
50 50 --status_channel : IN STD_LOGIC_VECTOR(49 DOWNTO 0);
51 51
52 52 -- IN
53 53 MEM_IN_SM_locked : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
54 54
55 55 -----------------------------------------------------------------------------
56 56
57 57 status_component : OUT STD_LOGIC_VECTOR(53 DOWNTO 0);
58 58 SM_in_data : OUT STD_LOGIC_VECTOR(32*2-1 DOWNTO 0);
59 59 SM_in_ren : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
60 60 SM_in_empty : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
61 61
62 62 SM_correlation_start : OUT STD_LOGIC;
63 63 SM_correlation_auto : OUT STD_LOGIC;
64 64 SM_correlation_done : IN STD_LOGIC
65 65 );
66 66 END COMPONENT;
67 67
68 68
69 69 -----------------------------------------------------------------------------
70 70 COMPONENT lpp_lfr_ms
71 71 GENERIC (
72 72 Mem_use : INTEGER);
73 73 PORT (
74 74 clk : IN STD_LOGIC;
75 75 rstn : IN STD_LOGIC;
76 76 run : IN STD_LOGIC;
77 77 coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
78 78 fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
79 79 sample_f0_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
80 80 sample_f0_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
81 81 sample_f1_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
82 82 sample_f1_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
83 83 sample_f2_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
84 84 sample_f2_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
85 85 dma_fifo_burst_valid : OUT STD_LOGIC;
86 86 dma_fifo_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
87 87 dma_fifo_ren : IN STD_LOGIC;
88 88 dma_buffer_new : OUT STD_LOGIC;
89 89 dma_buffer_addr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
90 90 dma_buffer_length : OUT STD_LOGIC_VECTOR(25 DOWNTO 0);
91 91 dma_buffer_full : IN STD_LOGIC;
92 92 dma_buffer_full_err : IN STD_LOGIC;
93 93 ready_matrix_f0 : OUT STD_LOGIC;
94 94 ready_matrix_f1 : OUT STD_LOGIC;
95 95 ready_matrix_f2 : OUT STD_LOGIC;
96 96 error_buffer_full : OUT STD_LOGIC;
97 97 error_input_fifo_write : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
98 98 status_ready_matrix_f0 : IN STD_LOGIC;
99 99 status_ready_matrix_f1 : IN STD_LOGIC;
100 100 status_ready_matrix_f2 : IN STD_LOGIC;
101 101 addr_matrix_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
102 102 addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
103 103 addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
104 104 length_matrix_f0 : IN STD_LOGIC_VECTOR(25 DOWNTO 0);
105 105 length_matrix_f1 : IN STD_LOGIC_VECTOR(25 DOWNTO 0);
106 106 length_matrix_f2 : IN STD_LOGIC_VECTOR(25 DOWNTO 0);
107 107 matrix_time_f0 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
108 108 matrix_time_f1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
109 109 matrix_time_f2 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0));
110 110 END COMPONENT;
111 111
112 112 COMPONENT lpp_lfr_ms_fsmdma
113 113 PORT (
114 114 clk : IN STD_ULOGIC;
115 115 rstn : IN STD_ULOGIC;
116 116 run : IN STD_LOGIC;
117 117 fifo_matrix_type : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
118 118 fifo_matrix_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
119 119 fifo_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
120 120 fifo_empty : IN STD_LOGIC;
121 121 fifo_empty_threshold : IN STD_LOGIC;
122 122 fifo_ren : OUT STD_LOGIC;
123 123 dma_fifo_valid_burst : OUT STD_LOGIC;
124 124 dma_fifo_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
125 125 dma_fifo_ren : IN STD_LOGIC;
126 126 dma_buffer_new : OUT STD_LOGIC;
127 127 dma_buffer_addr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
128 128 dma_buffer_length : OUT STD_LOGIC_VECTOR(25 DOWNTO 0);
129 129 dma_buffer_full : IN STD_LOGIC;
130 130 dma_buffer_full_err : IN STD_LOGIC;
131 131 status_ready_matrix_f0 : IN STD_LOGIC;
132 132 status_ready_matrix_f1 : IN STD_LOGIC;
133 133 status_ready_matrix_f2 : IN STD_LOGIC;
134 134 addr_matrix_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
135 135 addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
136 136 addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
137 137 length_matrix_f0 : IN STD_LOGIC_VECTOR(25 DOWNTO 0);
138 138 length_matrix_f1 : IN STD_LOGIC_VECTOR(25 DOWNTO 0);
139 139 length_matrix_f2 : IN STD_LOGIC_VECTOR(25 DOWNTO 0);
140 140 ready_matrix_f0 : OUT STD_LOGIC;
141 141 ready_matrix_f1 : OUT STD_LOGIC;
142 142 ready_matrix_f2 : OUT STD_LOGIC;
143 143 matrix_time_f0 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
144 144 matrix_time_f1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
145 145 matrix_time_f2 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
146 146 error_buffer_full : OUT STD_LOGIC);
147 147 END COMPONENT;
148 148
149 149 COMPONENT lpp_lfr_ms_FFT
150 150 PORT (
151 151 clk : IN STD_LOGIC;
152 152 rstn : IN STD_LOGIC;
153 153 sample_valid : IN STD_LOGIC;
154 154 fft_read : IN STD_LOGIC;
155 155 sample_data : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
156 156 sample_load : OUT STD_LOGIC;
157 157 fft_pong : OUT STD_LOGIC;
158 158 fft_data_im : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
159 159 fft_data_re : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
160 160 fft_data_valid : OUT STD_LOGIC;
161 161 fft_ready : OUT STD_LOGIC);
162 162 END COMPONENT;
163 163
164 164 COMPONENT lpp_lfr_filter
165 165 GENERIC (
166 166 Mem_use : INTEGER);
167 167 PORT (
168 168 sample : IN Samples(7 DOWNTO 0);
169 169 sample_val : IN STD_LOGIC;
170 170 clk : IN STD_LOGIC;
171 171 rstn : IN STD_LOGIC;
172 172 data_shaping_SP0 : IN STD_LOGIC;
173 173 data_shaping_SP1 : IN STD_LOGIC;
174 174 data_shaping_R0 : IN STD_LOGIC;
175 175 data_shaping_R1 : IN STD_LOGIC;
176 176 data_shaping_R2 : IN STD_LOGIC;
177 177 sample_f0_val : OUT STD_LOGIC;
178 178 sample_f1_val : OUT STD_LOGIC;
179 179 sample_f2_val : OUT STD_LOGIC;
180 180 sample_f3_val : OUT STD_LOGIC;
181 181 sample_f0_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
182 182 sample_f1_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
183 183 sample_f2_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
184 184 sample_f3_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0));
185 185 END COMPONENT;
186 186
187 187 COMPONENT lpp_lfr
188 188 GENERIC (
189 189 Mem_use : INTEGER;
190 190 nb_data_by_buffer_size : INTEGER;
191 191 nb_word_by_buffer_size : INTEGER;
192 192 nb_snapshot_param_size : INTEGER;
193 193 delta_vector_size : INTEGER;
194 194 delta_vector_size_f0_2 : INTEGER;
195 195 pindex : INTEGER;
196 196 paddr : INTEGER;
197 197 pmask : INTEGER;
198 198 pirq_ms : INTEGER;
199 199 pirq_wfp : INTEGER;
200 200 hindex : INTEGER;
201 201 top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0)
202 202 );
203 203 PORT (
204 204 clk : IN STD_LOGIC;
205 205 rstn : IN STD_LOGIC;
206 206 sample_B : IN Samples(2 DOWNTO 0);
207 207 sample_E : IN Samples(4 DOWNTO 0);
208 208 sample_val : IN STD_LOGIC;
209 209 apbi : IN apb_slv_in_type;
210 210 apbo : OUT apb_slv_out_type;
211 211 ahbi : IN AHB_Mst_In_Type;
212 212 ahbo : OUT AHB_Mst_Out_Type;
213 213 coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
214 214 fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
215 215 data_shaping_BW : OUT STD_LOGIC;
216 216 --
217 217 observation_vector_0: OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
218 218 observation_vector_1: OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
219 219 observation_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
220 220 );
221 221 END COMPONENT;
222 222
223 223 -----------------------------------------------------------------------------
224 224 -- LPP_LFR with only WaveForm Picker (and without Spectral Matrix Sub System)
225 225 -----------------------------------------------------------------------------
226 226 COMPONENT lpp_lfr_WFP_nMS
227 227 GENERIC (
228 228 Mem_use : INTEGER;
229 229 nb_data_by_buffer_size : INTEGER;
230 230 nb_word_by_buffer_size : INTEGER;
231 231 nb_snapshot_param_size : INTEGER;
232 232 delta_vector_size : INTEGER;
233 233 delta_vector_size_f0_2 : INTEGER;
234 234 pindex : INTEGER;
235 235 paddr : INTEGER;
236 236 pmask : INTEGER;
237 237 pirq_ms : INTEGER;
238 238 pirq_wfp : INTEGER;
239 239 hindex : INTEGER;
240 240 top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0));
241 241 PORT (
242 242 clk : IN STD_LOGIC;
243 243 rstn : IN STD_LOGIC;
244 244 sample_B : IN Samples(2 DOWNTO 0);
245 245 sample_E : IN Samples(4 DOWNTO 0);
246 246 sample_val : IN STD_LOGIC;
247 247 apbi : IN apb_slv_in_type;
248 248 apbo : OUT apb_slv_out_type;
249 249 ahbi : IN AHB_Mst_In_Type;
250 250 ahbo : OUT AHB_Mst_Out_Type;
251 251 coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
252 252 fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
253 253 data_shaping_BW : OUT STD_LOGIC;
254 254 observation_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0));
255 255 END COMPONENT;
256 256 -----------------------------------------------------------------------------
257 257
258 258 COMPONENT lpp_lfr_apbreg
259 259 GENERIC (
260 260 nb_data_by_buffer_size : INTEGER;
261 nb_word_by_buffer_size : INTEGER;
262 261 nb_snapshot_param_size : INTEGER;
263 262 delta_vector_size : INTEGER;
264 263 delta_vector_size_f0_2 : INTEGER;
265 264 pindex : INTEGER;
266 265 paddr : INTEGER;
267 266 pmask : INTEGER;
268 267 pirq_ms : INTEGER;
269 268 pirq_wfp : INTEGER;
270 269 top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0));
271 270 PORT (
272 HCLK : IN STD_ULOGIC;
273 HRESETn : IN STD_ULOGIC;
274 apbi : IN apb_slv_in_type;
275 apbo : OUT apb_slv_out_type;
276 run_ms : OUT STD_LOGIC;
277 ready_matrix_f0 : IN STD_LOGIC;
278 ready_matrix_f1 : IN STD_LOGIC;
279 ready_matrix_f2 : IN STD_LOGIC;
280 error_buffer_full : IN STD_LOGIC;
281 error_input_fifo_write : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
282 status_ready_matrix_f0 : OUT STD_LOGIC;
283 status_ready_matrix_f1 : OUT STD_LOGIC;
284 status_ready_matrix_f2 : OUT STD_LOGIC;
285 addr_matrix_f0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
286 addr_matrix_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
287 addr_matrix_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
288 length_matrix_f0 : OUT STD_LOGIC_VECTOR(25 DOWNTO 0);
289 length_matrix_f1 : OUT STD_LOGIC_VECTOR(25 DOWNTO 0);
290 length_matrix_f2 : OUT STD_LOGIC_VECTOR(25 DOWNTO 0);
291 matrix_time_f0 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
292 matrix_time_f1 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
293 matrix_time_f2 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
294 status_full : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
295 status_full_ack : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
296 status_full_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
297 status_new_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
298 data_shaping_BW : OUT STD_LOGIC;
299 data_shaping_SP0 : OUT STD_LOGIC;
300 data_shaping_SP1 : OUT STD_LOGIC;
301 data_shaping_R0 : OUT STD_LOGIC;
302 data_shaping_R1 : OUT STD_LOGIC;
303 data_shaping_R2 : OUT STD_LOGIC;
304 delta_snapshot : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
305 delta_f0 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
306 delta_f0_2 : OUT STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0);
307 delta_f1 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
308 delta_f2 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
309 nb_data_by_buffer : OUT STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
310 nb_word_by_buffer : OUT STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0);
311 nb_snapshot_param : OUT STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
312 enable_f0 : OUT STD_LOGIC;
313 enable_f1 : OUT STD_LOGIC;
314 enable_f2 : OUT STD_LOGIC;
315 enable_f3 : OUT STD_LOGIC;
316 burst_f0 : OUT STD_LOGIC;
317 burst_f1 : OUT STD_LOGIC;
318 burst_f2 : OUT STD_LOGIC;
319 run : OUT STD_LOGIC;
320 addr_data_f0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
321 addr_data_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
322 addr_data_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
323 addr_data_f3 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
324 start_date : OUT STD_LOGIC_VECTOR(30 DOWNTO 0);
325 debug_signal : OUT STD_LOGIC_VECTOR(31 DOWNTO 0));
271 HCLK : IN STD_ULOGIC;
272 HRESETn : IN STD_ULOGIC;
273 apbi : IN apb_slv_in_type;
274 apbo : OUT apb_slv_out_type;
275 run_ms : OUT STD_LOGIC;
276 ready_matrix_f0 : IN STD_LOGIC;
277 ready_matrix_f1 : IN STD_LOGIC;
278 ready_matrix_f2 : IN STD_LOGIC;
279 error_buffer_full : IN STD_LOGIC;
280 error_input_fifo_write : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
281 status_ready_matrix_f0 : OUT STD_LOGIC;
282 status_ready_matrix_f1 : OUT STD_LOGIC;
283 status_ready_matrix_f2 : OUT STD_LOGIC;
284 addr_matrix_f0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
285 addr_matrix_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
286 addr_matrix_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
287 length_matrix_f0 : OUT STD_LOGIC_VECTOR(25 DOWNTO 0);
288 length_matrix_f1 : OUT STD_LOGIC_VECTOR(25 DOWNTO 0);
289 length_matrix_f2 : OUT STD_LOGIC_VECTOR(25 DOWNTO 0);
290 matrix_time_f0 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
291 matrix_time_f1 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
292 matrix_time_f2 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
293 status_new_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
294 data_shaping_BW : OUT STD_LOGIC;
295 data_shaping_SP0 : OUT STD_LOGIC;
296 data_shaping_SP1 : OUT STD_LOGIC;
297 data_shaping_R0 : OUT STD_LOGIC;
298 data_shaping_R1 : OUT STD_LOGIC;
299 data_shaping_R2 : OUT STD_LOGIC;
300 delta_snapshot : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
301 delta_f0 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
302 delta_f0_2 : OUT STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0);
303 delta_f1 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
304 delta_f2 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
305 nb_data_by_buffer : OUT STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
306 nb_snapshot_param : OUT STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
307 enable_f0 : OUT STD_LOGIC;
308 enable_f1 : OUT STD_LOGIC;
309 enable_f2 : OUT STD_LOGIC;
310 enable_f3 : OUT STD_LOGIC;
311 burst_f0 : OUT STD_LOGIC;
312 burst_f1 : OUT STD_LOGIC;
313 burst_f2 : OUT STD_LOGIC;
314 run : OUT STD_LOGIC;
315 start_date : OUT STD_LOGIC_VECTOR(30 DOWNTO 0);
316 wfp_status_buffer_ready : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
317 wfp_addr_buffer : OUT STD_LOGIC_VECTOR(32*4 DOWNTO 0);
318 wfp_length_buffer : OUT STD_LOGIC_VECTOR(25 DOWNTO 0);
319 wfp_ready_buffer : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
320 wfp_buffer_time : IN STD_LOGIC_VECTOR(48*4-1 DOWNTO 0);
321 wfp_error_buffer_full : IN STD_LOGIC_VECTOR(3 DOWNTO 0));
326 322 END COMPONENT;
327 323
328 324 COMPONENT lpp_top_ms
329 325 GENERIC (
330 326 Mem_use : INTEGER;
331 327 nb_burst_available_size : INTEGER;
332 328 nb_snapshot_param_size : INTEGER;
333 329 delta_snapshot_size : INTEGER;
334 330 delta_f2_f0_size : INTEGER;
335 331 delta_f2_f1_size : INTEGER;
336 332 pindex : INTEGER;
337 333 paddr : INTEGER;
338 334 pmask : INTEGER;
339 335 pirq_ms : INTEGER;
340 336 pirq_wfp : INTEGER;
341 337 hindex_wfp : INTEGER;
342 338 hindex_ms : INTEGER);
343 339 PORT (
344 340 clk : IN STD_LOGIC;
345 341 rstn : IN STD_LOGIC;
346 342 sample_B : IN Samples14v(2 DOWNTO 0);
347 343 sample_E : IN Samples14v(4 DOWNTO 0);
348 344 sample_val : IN STD_LOGIC;
349 345 apbi : IN apb_slv_in_type;
350 346 apbo : OUT apb_slv_out_type;
351 347 ahbi_ms : IN AHB_Mst_In_Type;
352 348 ahbo_ms : OUT AHB_Mst_Out_Type;
353 349 data_shaping_BW : OUT STD_LOGIC;
354 350 matrix_time_f0_0 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
355 351 matrix_time_f0_1 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
356 352 matrix_time_f1 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
357 353 matrix_time_f2 : IN STD_LOGIC_VECTOR(47 DOWNTO 0)
358 354
359 355 );
360 356 END COMPONENT;
361 357
362 358 COMPONENT lpp_apbreg_ms_pointer
363 359 PORT (
364 360 clk : IN STD_LOGIC;
365 361 rstn : IN STD_LOGIC;
366 362 reg0_status_ready_matrix : IN STD_LOGIC;
367 363 reg0_ready_matrix : OUT STD_LOGIC;
368 364 reg0_addr_matrix : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
369 365 reg0_matrix_time : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
370 366 reg1_status_ready_matrix : IN STD_LOGIC;
371 367 reg1_ready_matrix : OUT STD_LOGIC;
372 368 reg1_addr_matrix : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
373 369 reg1_matrix_time : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
374 370 ready_matrix : IN STD_LOGIC;
375 371 status_ready_matrix : OUT STD_LOGIC;
376 372 addr_matrix : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
377 373 matrix_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0));
378 374 END COMPONENT;
379 375
380 376 COMPONENT lpp_lfr_ms_reg_head
381 377 PORT (
382 378 clk : IN STD_LOGIC;
383 379 rstn : IN STD_LOGIC;
384 380 in_wen : IN STD_LOGIC;
385 381 in_data : IN STD_LOGIC_VECTOR(5*16-1 DOWNTO 0);
386 382 in_full : IN STD_LOGIC;
387 383 in_empty : IN STD_LOGIC;
388 384 out_wen : OUT STD_LOGIC;
389 385 out_data : OUT STD_LOGIC_VECTOR(5*16-1 DOWNTO 0);
390 386 out_full : OUT STD_LOGIC);
391 387 END COMPONENT;
392 388
393 389 END lpp_lfr_pkg;
Show file before | Show file after | Hide comments
@@ -1,576 +1,471
1 1 ------------------------------------------------------------------------------
2 2 -- This file is a part of the LPP VHDL IP LIBRARY
3 3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 3 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 -------------------------------------------------------------------------------
19 19 -- Author : Jean-christophe Pellion
20 20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 21 -- jean-christophe.pellion@easii-ic.com
22 22 -------------------------------------------------------------------------------
23 23 LIBRARY IEEE;
24 24 USE IEEE.STD_LOGIC_1164.ALL;
25 25 USE ieee.numeric_std.ALL;
26 26
27 27 LIBRARY grlib;
28 28 USE grlib.amba.ALL;
29 29 USE grlib.stdlib.ALL;
30 30 USE grlib.devices.ALL;
31 31 USE GRLIB.DMA2AHB_Package.ALL;
32 32
33 33 LIBRARY lpp;
34 34 USE lpp.lpp_waveform_pkg.ALL;
35 35 USE lpp.iir_filter.ALL;
36 36 USE lpp.lpp_memory.ALL;
37 37
38 38 LIBRARY techmap;
39 39 USE techmap.gencomp.ALL;
40 40
41 41 ENTITY lpp_waveform IS
42 42
43 43 GENERIC (
44 44 tech : INTEGER := inferred;
45 45 data_size : INTEGER := 96; --16*6
46 46 nb_data_by_buffer_size : INTEGER := 11;
47 nb_word_by_buffer_size : INTEGER := 11;
47 -- nb_word_by_buffer_size : INTEGER := 11;
48 48 nb_snapshot_param_size : INTEGER := 11;
49 49 delta_vector_size : INTEGER := 20;
50 50 delta_vector_size_f0_2 : INTEGER := 3);
51 51
52 52 PORT (
53 53 clk : IN STD_LOGIC;
54 54 rstn : IN STD_LOGIC;
55 55
56 56 ---- AMBA AHB Master Interface
57 57 --AHB_Master_In : IN AHB_Mst_In_Type; -- TODO
58 58 --AHB_Master_Out : OUT AHB_Mst_Out_Type; -- TODO
59 59
60 60 --config
61 61 reg_run : IN STD_LOGIC;
62 62 reg_start_date : IN STD_LOGIC_VECTOR(30 DOWNTO 0);
63 63 reg_delta_snapshot : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
64 64 reg_delta_f0 : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
65 65 reg_delta_f0_2 : IN STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0);
66 66 reg_delta_f1 : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
67 67 reg_delta_f2 : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
68 68
69 69 enable_f0 : IN STD_LOGIC;
70 70 enable_f1 : IN STD_LOGIC;
71 71 enable_f2 : IN STD_LOGIC;
72 72 enable_f3 : IN STD_LOGIC;
73 73
74 74 burst_f0 : IN STD_LOGIC;
75 75 burst_f1 : IN STD_LOGIC;
76 76 burst_f2 : IN STD_LOGIC;
77 77
78 78 nb_data_by_buffer : IN STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
79 nb_word_by_buffer : IN STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0);
79 -- nb_word_by_buffer : IN STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0);
80 80 nb_snapshot_param : IN STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
81 status_full : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
82 status_full_ack : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
83 status_full_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
81
84 82 status_new_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); -- New data f(i) before the current data is write by dma
83
84
85 -- REG DMA
86 status_buffer_ready : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
87 addr_buffer : IN STD_LOGIC_VECTOR(32*4 DOWNTO 0);
88 length_buffer : IN STD_LOGIC_VECTOR(25 DOWNTO 0);
89
90 ready_buffer : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
91 buffer_time : OUT STD_LOGIC_VECTOR(48*4-1 DOWNTO 0);
92 error_buffer_full : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
93
85 94 ---------------------------------------------------------------------------
86 95 -- INPUT
87 96 coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
88 97 fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
89 98
90 99 --f0
91 addr_data_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
92 100 data_f0_in_valid : IN STD_LOGIC;
93 101 data_f0_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
94 102 --f1
95 addr_data_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
96 103 data_f1_in_valid : IN STD_LOGIC;
97 104 data_f1_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
98 105 --f2
99 addr_data_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
100 106 data_f2_in_valid : IN STD_LOGIC;
101 107 data_f2_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
102 108 --f3
103 addr_data_f3 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
104 109 data_f3_in_valid : IN STD_LOGIC;
105 110 data_f3_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
106 111
107 112 ---------------------------------------------------------------------------
108 113 -- DMA --------------------------------------------------------------------
109 114
110 115 dma_fifo_valid_burst : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
111 116 dma_fifo_data : OUT STD_LOGIC_VECTOR(32*4-1 DOWNTO 0);
112 117 dma_fifo_ren : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
113 dma_buffer_new : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
118 dma_buffer_new : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
114 119 dma_buffer_addr : OUT STD_LOGIC_VECTOR(32*4-1 DOWNTO 0);
115 120 dma_buffer_length : OUT STD_LOGIC_VECTOR(26*4-1 DOWNTO 0);
116 121 dma_buffer_full : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
117 122 dma_buffer_full_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0)
118 123
119 124 );
120 125
121 126 END lpp_waveform;
122 127
123 128 ARCHITECTURE beh OF lpp_waveform IS
124 129 SIGNAL start_snapshot_f0 : STD_LOGIC;
125 130 SIGNAL start_snapshot_f1 : STD_LOGIC;
126 131 SIGNAL start_snapshot_f2 : STD_LOGIC;
127 132
128 133 SIGNAL data_f0_out : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
129 134 SIGNAL data_f1_out : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
130 135 SIGNAL data_f2_out : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
131 136 SIGNAL data_f3_out : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
132 137
133 138 SIGNAL data_f0_out_swap : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
134 139 SIGNAL data_f1_out_swap : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
135 140 SIGNAL data_f2_out_swap : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
136 141 SIGNAL data_f3_out_swap : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
137 142
138 143 SIGNAL data_f0_out_valid : STD_LOGIC;
139 144 SIGNAL data_f1_out_valid : STD_LOGIC;
140 145 SIGNAL data_f2_out_valid : STD_LOGIC;
141 146 SIGNAL data_f3_out_valid : STD_LOGIC;
142 147 SIGNAL nb_snapshot_param_more_one : STD_LOGIC_VECTOR(nb_snapshot_param_size DOWNTO 0);
143 148 --
144 149 SIGNAL valid_in : STD_LOGIC_VECTOR(3 DOWNTO 0);
145 150 SIGNAL valid_out : STD_LOGIC_VECTOR(3 DOWNTO 0);
146 151 SIGNAL valid_ack : STD_LOGIC_VECTOR(3 DOWNTO 0);
147 152 SIGNAL time_ready : STD_LOGIC_VECTOR(3 DOWNTO 0);
148 153 SIGNAL data_ready : STD_LOGIC_VECTOR(3 DOWNTO 0);
149 154 SIGNAL ready_arb : STD_LOGIC_VECTOR(3 DOWNTO 0);
150 155 SIGNAL data_wen : STD_LOGIC_VECTOR(3 DOWNTO 0);
151 156 SIGNAL time_wen : STD_LOGIC_VECTOR(3 DOWNTO 0);
152 157 SIGNAL wdata : STD_LOGIC_VECTOR(31 DOWNTO 0);
153 158 SIGNAL full_almost : STD_LOGIC_VECTOR(3 DOWNTO 0);
154 159 SIGNAL full : STD_LOGIC_VECTOR(3 DOWNTO 0);
155 160 SIGNAL empty_almost : STD_LOGIC_VECTOR(3 DOWNTO 0);
156 161 SIGNAL empty : STD_LOGIC_VECTOR(3 DOWNTO 0);
157 162 --
158 163 SIGNAL data_ren : STD_LOGIC_VECTOR(3 DOWNTO 0);
159 164 SIGNAL time_ren : STD_LOGIC_VECTOR(3 DOWNTO 0);
160 165 SIGNAL rdata : STD_LOGIC_VECTOR(31 DOWNTO 0);
161 166 SIGNAL enable : STD_LOGIC_VECTOR(3 DOWNTO 0);
162 167 --
163 168 SIGNAL run : STD_LOGIC;
164 169 --
165 170 TYPE TIME_VECTOR IS ARRAY (NATURAL RANGE <>) OF STD_LOGIC_VECTOR(47 DOWNTO 0);
166 171 SIGNAL data_out : Data_Vector(3 DOWNTO 0, 95 DOWNTO 0);
167 172 SIGNAL time_out_2 : Data_Vector(3 DOWNTO 0, 47 DOWNTO 0);
168 173 SIGNAL time_out : TIME_VECTOR(3 DOWNTO 0);
169 174 SIGNAL time_out_debug : TIME_VECTOR(3 DOWNTO 0); -- TODO : debug
170 175 SIGNAL time_reg1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
171 176 SIGNAL time_reg2 : STD_LOGIC_VECTOR(47 DOWNTO 0);
172 177 --
173 178
174 179 SIGNAL s_empty_almost : STD_LOGIC_VECTOR(3 DOWNTO 0); --occupancy is lesser than 16 * 32b
175 180 SIGNAL s_empty : STD_LOGIC_VECTOR(3 DOWNTO 0);
176 181 SIGNAL s_data_ren : STD_LOGIC_VECTOR(3 DOWNTO 0);
177 182 -- SIGNAL s_rdata : STD_LOGIC_VECTOR(31 DOWNTO 0);
178 183 SIGNAL s_rdata_v : STD_LOGIC_VECTOR(32*4-1 DOWNTO 0);
179 184
180 185 --
186 SIGNAL arbiter_time_out : STD_LOGIC_VECTOR(47 DOWNTO 0);
187 SIGNAL arbiter_time_out_new : STD_LOGIC_VECTOR(3 DOWNTO 0);
181 188
182 SIGNAL status_full_s : STD_LOGIC_VECTOR(3 DOWNTO 0);
183
189 SIGNAL fifo_buffer_time : STD_LOGIC_VECTOR(48*4-1 DOWNTO 0);
184 190
185 191 BEGIN -- beh
186 192
187 193 -----------------------------------------------------------------------------
188 194
189 195 lpp_waveform_snapshot_controler_1 : lpp_waveform_snapshot_controler
190 196 GENERIC MAP (
191 197 delta_vector_size => delta_vector_size,
192 198 delta_vector_size_f0_2 => delta_vector_size_f0_2
193 199 )
194 200 PORT MAP (
195 201 clk => clk,
196 202 rstn => rstn,
197 203 reg_run => reg_run,
198 204 reg_start_date => reg_start_date,
199 205 reg_delta_snapshot => reg_delta_snapshot,
200 206 reg_delta_f0 => reg_delta_f0,
201 207 reg_delta_f0_2 => reg_delta_f0_2,
202 208 reg_delta_f1 => reg_delta_f1,
203 209 reg_delta_f2 => reg_delta_f2,
204 210 coarse_time => coarse_time(30 DOWNTO 0),
205 211 data_f0_valid => data_f0_in_valid,
206 212 data_f2_valid => data_f2_in_valid,
207 213 start_snapshot_f0 => start_snapshot_f0,
208 214 start_snapshot_f1 => start_snapshot_f1,
209 215 start_snapshot_f2 => start_snapshot_f2,
210 216 wfp_on => run);
211 217
212 218 lpp_waveform_snapshot_f0 : lpp_waveform_snapshot
213 219 GENERIC MAP (
214 220 data_size => data_size,
215 221 nb_snapshot_param_size => nb_snapshot_param_size)
216 222 PORT MAP (
217 223 clk => clk,
218 224 rstn => rstn,
219 225 run => run,
220 226 enable => enable_f0,
221 227 burst_enable => burst_f0,
222 228 nb_snapshot_param => nb_snapshot_param,
223 229 start_snapshot => start_snapshot_f0,
224 230 data_in => data_f0_in,
225 231 data_in_valid => data_f0_in_valid,
226 232 data_out => data_f0_out,
227 233 data_out_valid => data_f0_out_valid);
228 234
229 235 nb_snapshot_param_more_one <= ('0' & nb_snapshot_param) ;--+ 1;
230 236
231 237 lpp_waveform_snapshot_f1 : lpp_waveform_snapshot
232 238 GENERIC MAP (
233 239 data_size => data_size,
234 240 nb_snapshot_param_size => nb_snapshot_param_size+1)
235 241 PORT MAP (
236 242 clk => clk,
237 243 rstn => rstn,
238 244 run => run,
239 245 enable => enable_f1,
240 246 burst_enable => burst_f1,
241 247 nb_snapshot_param => nb_snapshot_param_more_one,
242 248 start_snapshot => start_snapshot_f1,
243 249 data_in => data_f1_in,
244 250 data_in_valid => data_f1_in_valid,
245 251 data_out => data_f1_out,
246 252 data_out_valid => data_f1_out_valid);
247 253
248 254 lpp_waveform_snapshot_f2 : lpp_waveform_snapshot
249 255 GENERIC MAP (
250 256 data_size => data_size,
251 257 nb_snapshot_param_size => nb_snapshot_param_size+1)
252 258 PORT MAP (
253 259 clk => clk,
254 260 rstn => rstn,
255 261 run => run,
256 262 enable => enable_f2,
257 263 burst_enable => burst_f2,
258 264 nb_snapshot_param => nb_snapshot_param_more_one,
259 265 start_snapshot => start_snapshot_f2,
260 266 data_in => data_f2_in,
261 267 data_in_valid => data_f2_in_valid,
262 268 data_out => data_f2_out,
263 269 data_out_valid => data_f2_out_valid);
264 270
265 271 lpp_waveform_burst_f3 : lpp_waveform_burst
266 272 GENERIC MAP (
267 273 data_size => data_size)
268 274 PORT MAP (
269 275 clk => clk,
270 276 rstn => rstn,
271 277 run => run,
272 278 enable => enable_f3,
273 279 data_in => data_f3_in,
274 280 data_in_valid => data_f3_in_valid,
275 281 data_out => data_f3_out,
276 282 data_out_valid => data_f3_out_valid);
277 283
278 284 -----------------------------------------------------------------------------
279 285 -- DEBUG -- SNAPSHOT OUT
280 286 --debug_f0_data_valid <= data_f0_out_valid;
281 287 --debug_f0_data <= data_f0_out;
282 288 --debug_f1_data_valid <= data_f1_out_valid;
283 289 --debug_f1_data <= data_f1_out;
284 290 --debug_f2_data_valid <= data_f2_out_valid;
285 291 --debug_f2_data <= data_f2_out;
286 292 --debug_f3_data_valid <= data_f3_out_valid;
287 293 --debug_f3_data <= data_f3_out;
288 294 -----------------------------------------------------------------------------
289 295
290 296 PROCESS (clk, rstn)
291 297 BEGIN -- PROCESS
292 298 IF rstn = '0' THEN -- asynchronous reset (active low)
293 299 time_reg1 <= (OTHERS => '0');
294 300 time_reg2 <= (OTHERS => '0');
295 301 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
296 302 time_reg1 <= fine_time & coarse_time;
297 303 time_reg2 <= time_reg1;
298 304 END IF;
299 305 END PROCESS;
300 306
301 307 valid_in <= data_f3_out_valid & data_f2_out_valid & data_f1_out_valid & data_f0_out_valid;
302 308 all_input_valid : FOR i IN 3 DOWNTO 0 GENERATE
303 309 lpp_waveform_dma_genvalid_I : lpp_waveform_dma_genvalid
304 310 PORT MAP (
305 311 HCLK => clk,
306 312 HRESETn => rstn,
307 313 run => run,
308 314 valid_in => valid_in(I),
309 315 ack_in => valid_ack(I),
310 316 time_in => time_reg2, -- Todo
311 317 valid_out => valid_out(I),
312 318 time_out => time_out(I), -- Todo
313 319 error => status_new_err(I));
314 320 END GENERATE all_input_valid;
315 321
316 322 data_f0_out_swap <= data_f0_out((16*5)-1 DOWNTO 16*4) &
317 323 data_f0_out((16*6)-1 DOWNTO 16*5) &
318 324 data_f0_out((16*3)-1 DOWNTO 16*2) &
319 325 data_f0_out((16*4)-1 DOWNTO 16*3) &
320 326 data_f0_out((16*1)-1 DOWNTO 16*0) &
321 327 data_f0_out((16*2)-1 DOWNTO 16*1) ;
322 328
323 329 data_f1_out_swap <= data_f1_out((16*5)-1 DOWNTO 16*4) &
324 330 data_f1_out((16*6)-1 DOWNTO 16*5) &
325 331 data_f1_out((16*3)-1 DOWNTO 16*2) &
326 332 data_f1_out((16*4)-1 DOWNTO 16*3) &
327 333 data_f1_out((16*1)-1 DOWNTO 16*0) &
328 334 data_f1_out((16*2)-1 DOWNTO 16*1) ;
329 335
330 336 data_f2_out_swap <= data_f2_out((16*5)-1 DOWNTO 16*4) &
331 337 data_f2_out((16*6)-1 DOWNTO 16*5) &
332 338 data_f2_out((16*3)-1 DOWNTO 16*2) &
333 339 data_f2_out((16*4)-1 DOWNTO 16*3) &
334 340 data_f2_out((16*1)-1 DOWNTO 16*0) &
335 341 data_f2_out((16*2)-1 DOWNTO 16*1) ;
336 342
337 343 data_f3_out_swap <= data_f3_out((16*5)-1 DOWNTO 16*4) &
338 344 data_f3_out((16*6)-1 DOWNTO 16*5) &
339 345 data_f3_out((16*3)-1 DOWNTO 16*2) &
340 346 data_f3_out((16*4)-1 DOWNTO 16*3) &
341 347 data_f3_out((16*1)-1 DOWNTO 16*0) &
342 348 data_f3_out((16*2)-1 DOWNTO 16*1) ;
343 349
344 350 all_bit_of_data_out : FOR I IN 95 DOWNTO 0 GENERATE
345 351 data_out(0, I) <= data_f0_out_swap(I);
346 352 data_out(1, I) <= data_f1_out_swap(I);
347 353 data_out(2, I) <= data_f2_out_swap(I);
348 354 data_out(3, I) <= data_f3_out_swap(I);
349 355 END GENERATE all_bit_of_data_out;
350 356
351 357 -----------------------------------------------------------------------------
352 358 -- TODO : debug
353 359 -----------------------------------------------------------------------------
354 360 all_bit_of_time_out : FOR I IN 47 DOWNTO 0 GENERATE
355 361 all_sample_of_time_out : FOR J IN 3 DOWNTO 0 GENERATE
356 362 time_out_2(J, I) <= time_out(J)(I);
357 363 END GENERATE all_sample_of_time_out;
358 364 END GENERATE all_bit_of_time_out;
359 365
360 -- DEBUG --
361 --time_out_debug(0) <= x"0A0A" & x"0A0A0A0A";
362 --time_out_debug(1) <= x"1B1B" & x"1B1B1B1B";
363 --time_out_debug(2) <= x"2C2C" & x"2C2C2C2C";
364 --time_out_debug(3) <= x"3D3D" & x"3D3D3D3D";
365
366 --all_bit_of_time_out : FOR I IN 47 DOWNTO 0 GENERATE
367 -- all_sample_of_time_out : FOR J IN 3 DOWNTO 0 GENERATE
368 -- time_out_2(J, I) <= time_out_debug(J)(I);
369 -- END GENERATE all_sample_of_time_out;
370 --END GENERATE all_bit_of_time_out;
371 -- DEBUG --
372
373 366 lpp_waveform_fifo_arbiter_1 : lpp_waveform_fifo_arbiter
374 367 GENERIC MAP (tech => tech,
375 368 nb_data_by_buffer_size => nb_data_by_buffer_size)
376 369 PORT MAP (
377 370 clk => clk,
378 371 rstn => rstn,
379 372 run => run,
380 373 nb_data_by_buffer => nb_data_by_buffer,
381 374 data_in_valid => valid_out,
382 375 data_in_ack => valid_ack,
383 376 data_in => data_out,
384 377 time_in => time_out_2,
385 378
386 379 data_out => wdata,
387 380 data_out_wen => data_wen,
388 381 full_almost => full_almost,
389 full => full);
382 full => full,
383
384 time_out => arbiter_time_out,
385 time_out_new => arbiter_time_out_new
386
387 );
390 388
391 389 -----------------------------------------------------------------------------
392 -- DEBUG -- SNAPSHOT IN
393 --debug_f0_data_fifo_in_valid <= NOT data_wen(0);
394 --debug_f0_data_fifo_in <= wdata;
395 --debug_f1_data_fifo_in_valid <= NOT data_wen(1);
396 --debug_f1_data_fifo_in <= wdata;
397 --debug_f2_data_fifo_in_valid <= NOT data_wen(2);
398 --debug_f2_data_fifo_in <= wdata;
399 --debug_f3_data_fifo_in_valid <= NOT data_wen(3);
400 --debug_f3_data_fifo_in <= wdata;s
401 390 -----------------------------------------------------------------------------
402 391
403
404 -- lpp_fifo_4_shared_1: lpp_fifo_4_shared
405 -- GENERIC MAP (
406 -- tech => tech,
407 -- Mem_use => use_RAM,
408 -- EMPTY_ALMOST_LIMIT => 16,
409 -- FULL_ALMOST_LIMIT => 5,
410 -- DataSz => 32,
411 -- AddrSz => 7
412 -- )
413 -- PORT MAP (
414 -- clk => clk,
415 -- rstn => rstn,
416 -- run => run,
417 -- empty_almost => s_empty_almost,
418 -- empty => s_empty,
419 -- r_en => s_data_ren,
420 -- r_data => s_rdata,
421 -- full_almost => full_almost,
422 -- full => full,
423 -- w_en => data_wen,
424 -- w_data => wdata);
425
426 --lpp_waveform_fifo_headreg_1 : lpp_fifo_4_shared_headreg_latency_1
427 -- PORT MAP (
428 -- clk => clk,
429 -- rstn => rstn,
430 -- run => run,
431 -- o_empty_almost => empty_almost,
432 -- o_empty => empty,
433
434 -- o_data_ren => data_ren,
435 -- o_rdata_0 => data_f0_data_out,
436 -- o_rdata_1 => data_f1_data_out,
437 -- o_rdata_2 => data_f2_data_out,
438 -- o_rdata_3 => data_f3_data_out,
439
440 -- i_empty_almost => s_empty_almost,
441 -- i_empty => s_empty,
442 -- i_data_ren => s_data_ren,
443 -- i_rdata => s_rdata);
444
445 392 generate_all_fifo: FOR I IN 0 TO 3 GENERATE
446 393 lpp_fifo_1: lpp_fifo
447 394 GENERIC MAP (
448 395 tech => tech,
449 396 Mem_use => use_RAM,
450 397 EMPTY_THRESHOLD_LIMIT => 15,
451 398 FULL_THRESHOLD_LIMIT => 3,
452 399 DataSz => 32,
453 400 AddrSz => 7)
454 401 PORT MAP (
455 402 clk => clk,
456 403 rstn => rstn,
457 404 reUse => '0',
458 405 run => run,
459 406 ren => data_ren(I),
460 407 rdata => s_rdata_v((I+1)*32-1 downto I*32),
461 408 wen => data_wen(I),
462 409 wdata => wdata,
463 410 empty => empty(I),
464 411 full => full(I),
465 412 full_almost => OPEN,
466 413 empty_threshold => empty_almost(I),
467 414 full_threshold => full_almost(I) );
468 415
469 416 END GENERATE generate_all_fifo;
470 417
471
472 ----empty <= s_empty;
473 ----empty_almost <= s_empty_almost;
474 ----s_data_ren <= data_ren;
475
476 --data_f0_data_out <= s_rdata_v(31 downto 0);
477 --data_f1_data_out <= s_rdata_v(31+32 downto 0+32);
478 --data_f2_data_out <= s_rdata_v(31+32*2 downto 32*2);
479 --data_f3_data_out <= s_rdata_v(31+32*3 downto 32*3);
480
481 --data_ren <= data_f3_data_out_ren &
482 -- data_f2_data_out_ren &
483 -- data_f1_data_out_ren &
484 -- data_f0_data_out_ren;
485
486 --lpp_waveform_gen_address_1 : lpp_waveform_genaddress
487 -- GENERIC MAP (
488 -- nb_data_by_buffer_size => nb_word_by_buffer_size)
489 -- PORT MAP (
490 -- clk => clk,
491 -- rstn => rstn,
492 -- run => run,
493
494 -- -------------------------------------------------------------------------
495 -- -- CONFIG
496 -- -------------------------------------------------------------------------
497 -- nb_data_by_buffer => nb_word_by_buffer,
498
499 -- addr_data_f0 => addr_data_f0,
500 -- addr_data_f1 => addr_data_f1,
501 -- addr_data_f2 => addr_data_f2,
502 -- addr_data_f3 => addr_data_f3,
503 -- -------------------------------------------------------------------------
504 -- -- CTRL
505 -- -------------------------------------------------------------------------
506 -- -- IN
507 -- empty => empty,
508 -- empty_almost => empty_almost,
509 -- data_ren => data_ren,
510
511 -- -------------------------------------------------------------------------
512 -- -- STATUS
513 -- -------------------------------------------------------------------------
514 -- status_full => status_full_s,
515 -- status_full_ack => status_full_ack,
516 -- status_full_err => status_full_err,
517
518 -- -------------------------------------------------------------------------
519 -- -- ADDR DATA OUT
520 -- -------------------------------------------------------------------------
521 -- data_f0_data_out_valid_burst => data_f0_data_out_valid_burst,
522 -- data_f1_data_out_valid_burst => data_f1_data_out_valid_burst,
523 -- data_f2_data_out_valid_burst => data_f2_data_out_valid_burst,
524 -- data_f3_data_out_valid_burst => data_f3_data_out_valid_burst,
525
526 -- data_f0_data_out_valid => data_f0_data_out_valid,
527 -- data_f1_data_out_valid => data_f1_data_out_valid,
528 -- data_f2_data_out_valid => data_f2_data_out_valid,
529 -- data_f3_data_out_valid => data_f3_data_out_valid,
530
531 -- data_f0_addr_out => data_f0_addr_out,
532 -- data_f1_addr_out => data_f1_addr_out,
533 -- data_f2_addr_out => data_f2_addr_out,
534 -- data_f3_addr_out => data_f3_addr_out
535 -- );
536 --status_full <= status_full_s;
537
538
539 418 -----------------------------------------------------------------------------
540 419 --
541 420 -----------------------------------------------------------------------------
542 421
543 422 all_channel: FOR I IN 3 DOWNTO 0 GENERATE
423
424 PROCESS (clk, rstn)
425 BEGIN
426 IF rstn = '0' THEN
427 fifo_buffer_time(48*(I+1)-1 DOWNTO 48*I) <= (OTHERS => '0');
428 ELSIF clk'event AND clk = '1' THEN
429 IF run = '0' THEN
430 fifo_buffer_time(48*(I+1)-1 DOWNTO 48*I) <= (OTHERS => '0');
431 ELSE
432 IF arbiter_time_out_new(I) = '0' THEN
433 fifo_buffer_time(48*(I+1)-1 DOWNTO 48*I) <= arbiter_time_out;
434 END IF;
435 END IF;
436 END IF;
437 END PROCESS;
438
544 439 lpp_waveform_fsmdma_I: lpp_waveform_fsmdma
545 440 PORT MAP (
546 441 clk => clk,
547 442 rstn => rstn,
548 443 run => run,
549 444
550 fifo_buffer_time => fifo_buffer_time(48*(I+1)-1 DOWNTO 48*I), -- TODO
445 fifo_buffer_time => fifo_buffer_time(48*(I+1)-1 DOWNTO 48*I),
551 446
552 447 fifo_data => s_rdata_v(32*(I+1)-1 DOWNTO 32*I),
553 448 fifo_empty => empty(I),
554 449 fifo_empty_threshold => empty_almost(I),
555 450 fifo_ren => data_ren(I),
556 451
557 452 dma_fifo_valid_burst => dma_fifo_valid_burst(I),
558 453 dma_fifo_data => dma_fifo_data(32*(I+1)-1 DOWNTO 32*I),
559 454 dma_fifo_ren => dma_fifo_ren(I),
560 455 dma_buffer_new => dma_buffer_new(I),
561 456 dma_buffer_addr => dma_buffer_addr(32*(I+1)-1 DOWNTO 32*I),
562 457 dma_buffer_length => dma_buffer_length(26*(I+1)-1 DOWNTO 26*I),
563 458 dma_buffer_full => dma_buffer_full(I),
564 459 dma_buffer_full_err => dma_buffer_full_err(I),
565 460
566 461 status_buffer_ready => status_buffer_ready(I), -- TODO
567 462 addr_buffer => addr_buffer(32*(I+1)-1 DOWNTO 32*I), -- TODO
568 length_buffer => length_buffer(26*(I+1)-1 DOWNTO 26*I), -- TODO
463 length_buffer => length_buffer,--(26*(I+1)-1 DOWNTO 26*I), -- TODO
569 464 ready_buffer => ready_buffer(I), -- TODO
570 465 buffer_time => buffer_time(48*(I+1)-1 DOWNTO 48*I), -- TODO
571 466 error_buffer_full => error_buffer_full(I)); -- TODO
572 467
573 468 END GENERATE all_channel;
574 469
575 470
576 471 END beh;
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@@ -1,98 +1,100
1 1 ------------------------------------------------------------------------------
2 2 -- This file is a part of the LPP VHDL IP LIBRARY
3 3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 3 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 -------------------------------------------------------------------------------
19 19 -- Author : Jean-christophe Pellion
20 20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 21 -- jean-christophe.pellion@easii-ic.com
22 22 -------------------------------------------------------------------------------
23 23 -- 1.0 - initial version
24 24 -------------------------------------------------------------------------------
25 25
26 26 LIBRARY ieee;
27 27 USE ieee.std_logic_1164.ALL;
28 28 USE ieee.numeric_std.ALL;
29 29
30 30
31 31 ENTITY lpp_waveform_dma_genvalid IS
32 32 PORT (
33 33 HCLK : IN STD_LOGIC;
34 34 HRESETn : IN STD_LOGIC;
35 35 run : IN STD_LOGIC;
36 36
37 37 valid_in : IN STD_LOGIC;
38 38 time_in : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
39 39
40 ack_in : IN STD_LOGIC;
40 ack_in : IN STD_LOGIC;
41 41 valid_out : OUT STD_LOGIC;
42 42 time_out : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
43 43 error : OUT STD_LOGIC
44 44 );
45 45 END;
46 46
47 47 ARCHITECTURE Behavioral OF lpp_waveform_dma_genvalid IS
48 48 TYPE state_fsm IS (IDLE, VALID);
49 49 SIGNAL state : state_fsm;
50 50 BEGIN
51 51
52 52 FSM_SELECT_ADDRESS : PROCESS (HCLK, HRESETn)
53 53 BEGIN
54 54 IF HRESETn = '0' THEN
55 55 state <= IDLE;
56 56 valid_out <= '0';
57 57 error <= '0';
58 time_out <= (OTHERS => '0');
58 time_out <= (OTHERS => '0');
59 59 ELSIF HCLK'EVENT AND HCLK = '1' THEN
60 CASE state IS
61 WHEN IDLE =>
62
63 valid_out <= '0';
64 error <= '0';
65 IF run = '1' AND valid_in = '1' THEN
66 state <= VALID;
67 valid_out <= '1';
60 IF run = '1' THEN
61 CASE state IS
62 WHEN IDLE =>
63
64 valid_out <= valid_in;
65 error <= '0';
68 66 time_out <= time_in;
69 END IF;
70 67
71 WHEN VALID =>
72 IF run = '0' THEN
73 state <= IDLE;
74 valid_out <= '0';
75 error <= '0';
76 ELSE
68 IF valid_in = '1' THEN
69 state <= VALID;
70 END IF;
71
72 WHEN VALID =>
77 73 IF valid_in = '1' THEN
78 74 IF ack_in = '1' THEN
79 75 state <= VALID;
80 76 valid_out <= '1';
81 77 time_out <= time_in;
82 78 ELSE
83 79 state <= IDLE;
84 80 error <= '1';
85 81 valid_out <= '0';
86 82 END IF;
87 83 ELSIF ack_in = '1' THEN
88 84 state <= IDLE;
89 85 valid_out <= '0';
90 86 END IF;
91 END IF;
92
93 WHEN OTHERS => NULL;
94 END CASE;
87
88 WHEN OTHERS => NULL;
89 END CASE;
90
91 ELSE
92 state <= IDLE;
93 valid_out <= '0';
94 error <= '0';
95 time_out <= (OTHERS => '0');
96 END IF;
95 97 END IF;
96 98 END PROCESS FSM_SELECT_ADDRESS;
97 99
98 100 END Behavioral;
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@@ -1,394 +1,264
1 1 ------------------------------------------------------------------------------
2 2 -- This file is a part of the LPP VHDL IP LIBRARY
3 3 -- Copyright (C) 2009 - 2012, Laboratory of Plasmas Physic - CNRS
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 3 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 ------------------------------------------------------------------------------
19 19 -- Author : Jean-christophe PELLION
20 20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 21 ------------------------------------------------------------------------------
22 22 LIBRARY IEEE;
23 23 USE IEEE.std_logic_1164.ALL;
24 24 USE IEEE.numeric_std.ALL;
25 25
26 26 LIBRARY lpp;
27 27 USE lpp.lpp_waveform_pkg.ALL;
28 28 USE lpp.general_purpose.ALL;
29 29
30 30 ENTITY lpp_waveform_fifo_arbiter IS
31 31 GENERIC(
32 32 tech : INTEGER := 0;
33 33 nb_data_by_buffer_size : INTEGER := 11
34 34 );
35 35 PORT(
36 36 clk : IN STD_LOGIC;
37 37 rstn : IN STD_LOGIC;
38 38 ---------------------------------------------------------------------------
39 39 run : IN STD_LOGIC;
40 40 nb_data_by_buffer : IN STD_LOGIC_VECTOR(nb_data_by_buffer_size - 1 DOWNTO 0);
41 41 ---------------------------------------------------------------------------
42 42 -- SNAPSHOT INTERFACE (INPUT)
43 43 ---------------------------------------------------------------------------
44 44 data_in_valid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
45 45 data_in_ack : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
46 46 data_in : IN Data_Vector(3 DOWNTO 0, 95 DOWNTO 0);
47
47 48 time_in : IN Data_Vector(3 DOWNTO 0, 47 DOWNTO 0);
48 49
49 50 ---------------------------------------------------------------------------
50 51 -- FIFO INTERFACE (OUTPUT)
51 52 ---------------------------------------------------------------------------
52 53 data_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
53 54 data_out_wen : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
54 55 full_almost : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
55 full : IN STD_LOGIC_VECTOR(3 DOWNTO 0)
56 full : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
57
58 ---------------------------------------------------------------------------
59 -- TIME INTERFACE (OUTPUT)
60 ---------------------------------------------------------------------------
61 time_out : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
62 time_out_new : OUT STD_LOGIC_VECTOR(3 DOWNTO 0)
56 63
57 64 );
58 65 END ENTITY;
59 66
60 67
61 68 ARCHITECTURE ar_lpp_waveform_fifo_arbiter OF lpp_waveform_fifo_arbiter IS
62 TYPE state_type_fifo_arbiter IS (IDLE,TIME1,TIME2,DATA1,DATA2,DATA3,LAST);
69 TYPE state_type_fifo_arbiter IS (IDLE,DATA1,DATA2,DATA3,LAST);
63 70 SIGNAL state : state_type_fifo_arbiter;
64 71
65 72 -----------------------------------------------------------------------------
66 73 -- DATA MUX
67 74 -----------------------------------------------------------------------------
68 SIGNAL data_0_v : STD_LOGIC_VECTOR(32*5-1 DOWNTO 0);
69 SIGNAL data_1_v : STD_LOGIC_VECTOR(32*5-1 DOWNTO 0);
70 SIGNAL data_2_v : STD_LOGIC_VECTOR(32*5-1 DOWNTO 0);
71 SIGNAL data_3_v : STD_LOGIC_VECTOR(32*5-1 DOWNTO 0);
72 75 TYPE WORD_VECTOR IS ARRAY (NATURAL RANGE <>) OF STD_LOGIC_VECTOR(31 DOWNTO 0);
73 SIGNAL data_0 : WORD_VECTOR(4 DOWNTO 0);
74 SIGNAL data_1 : WORD_VECTOR(4 DOWNTO 0);
75 SIGNAL data_2 : WORD_VECTOR(4 DOWNTO 0);
76 SIGNAL data_3 : WORD_VECTOR(4 DOWNTO 0);
77 SIGNAL data_sel : WORD_VECTOR(4 DOWNTO 0);
76 SIGNAL data_0 : WORD_VECTOR(3 DOWNTO 0);
77 SIGNAL data_1 : WORD_VECTOR(3 DOWNTO 0);
78 SIGNAL data_2 : WORD_VECTOR(3 DOWNTO 0);
79 SIGNAL data_3 : WORD_VECTOR(3 DOWNTO 0);
80 SIGNAL data_sel : WORD_VECTOR(3 DOWNTO 0);
78 81
79 82 -----------------------------------------------------------------------------
80 83 -- RR and SELECTION
81 84 -----------------------------------------------------------------------------
82 85 SIGNAL valid_in_rr : STD_LOGIC_VECTOR(3 DOWNTO 0);
83 86 SIGNAL sel : STD_LOGIC_VECTOR(3 DOWNTO 0);
84 87 SIGNAL sel_s : STD_LOGIC_VECTOR(3 DOWNTO 0);
85 88 SIGNAL sel_reg : STD_LOGIC;
86 89 SIGNAL sel_ack : STD_LOGIC;
87 90 SIGNAL no_sel : STD_LOGIC;
88 91
89 92 -----------------------------------------------------------------------------
90 93 -- REG
91 94 -----------------------------------------------------------------------------
92 95 SIGNAL count_enable : STD_LOGIC;
93 96 SIGNAL count : STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
94 97 SIGNAL count_s : STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
95
96 --SIGNAL shift_data_enable : STD_LOGIC;
97 --SIGNAL shift_data : STD_LOGIC_VECTOR(1 DOWNTO 0);
98 --SIGNAL shift_data_s : STD_LOGIC_VECTOR(1 DOWNTO 0);
99
100 --SIGNAL shift_time_enable : STD_LOGIC;
101 --SIGNAL shift_time : STD_LOGIC_VECTOR(1 DOWNTO 0);
102 --SIGNAL shift_time_s : STD_LOGIC_VECTOR(1 DOWNTO 0);
98
99 SIGNAL time_sel : STD_LOGIC_VECTOR(47 DOWNTO 0);
103 100
104 101 BEGIN
105 102
106 103 -----------------------------------------------------------------------------
107 104 -- CONTROL
108 105 -----------------------------------------------------------------------------
109 106 PROCESS (clk, rstn)
110 107 BEGIN -- PROCESS
111 108 IF rstn = '0' THEN -- asynchronous reset (active low)
112 109 count_enable <= '0';
113 110 data_in_ack <= (OTHERS => '0');
114 111 data_out_wen <= (OTHERS => '1');
115 112 sel_ack <= '0';
116 state <= IDLE;
113 state <= IDLE;
114 time_out <= (OTHERS => '0');
115 time_out_new <= (OTHERS => '0');
117 116 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
118 117 count_enable <= '0';
119 118 data_in_ack <= (OTHERS => '0');
120 119 data_out_wen <= (OTHERS => '1');
121 120 sel_ack <= '0';
121 time_out_new <= (OTHERS => '0');
122 122 IF run = '0' THEN
123 123 state <= IDLE;
124 time_out <= (OTHERS => '0');
124 125 ELSE
125 126 CASE state IS
126 127 WHEN IDLE =>
127 128 IF no_sel = '0' THEN
128 state <= TIME1;
129 state <= DATA1;
129 130 END IF;
130 WHEN TIME1 =>
131 WHEN DATA1 =>
131 132 count_enable <= '1';
132 133 IF UNSIGNED(count) = 0 THEN
133 state <= TIME2;
134 data_out_wen <= NOT sel;
135 data_out <= data_sel(0);
136 ELSE
137 state <= DATA1;
134 time_out <= time_sel;
135 time_out_new <= sel;
138 136 END IF;
139 WHEN TIME2 =>
140 137 data_out_wen <= NOT sel;
141 data_out <= data_sel(1) ;
142 state <= DATA1;
143 WHEN DATA1 =>
144 data_out_wen <= NOT sel;
145 data_out <= data_sel(2);
138 data_out <= data_sel(0);
146 139 state <= DATA2;
147 140 WHEN DATA2 =>
148 141 data_out_wen <= NOT sel;
149 data_out <= data_sel(3);
142 data_out <= data_sel(1);
150 143 state <= DATA3;
151 144 WHEN DATA3 =>
152 145 data_out_wen <= NOT sel;
153 data_out <= data_sel(4);
146 data_out <= data_sel(2);
154 147 state <= LAST;
155 148 data_in_ack <= sel;
156 149 WHEN LAST =>
157 150 state <= IDLE;
158 151 sel_ack <= '1';
159 152
160 153 WHEN OTHERS => NULL;
161 154 END CASE;
162 155 END IF;
163 156 END IF;
164 157 END PROCESS;
165 158 -----------------------------------------------------------------------------
166
167
168 --PROCESS (clk, rstn)
169 --BEGIN -- PROCESS
170 -- IF rstn = '0' THEN -- asynchronous reset (active low)
171 -- count_enable <= '0';
172 -- shift_time_enable <= '0';
173 -- shift_data_enable <= '0';
174 -- data_in_ack <= (OTHERS => '0');
175 -- data_out_wen <= (OTHERS => '1');
176 -- sel_ack <= '0';
177 -- ELSIF clk'event AND clk = '1' THEN -- rising clock edge
178 -- IF run = '0' OR no_sel = '1' THEN
179 -- count_enable <= '0';
180 -- shift_time_enable <= '0';
181 -- shift_data_enable <= '0';
182 -- data_in_ack <= (OTHERS => '0');
183 -- data_out_wen <= (OTHERS => '1');
184 -- sel_ack <= '0';
185 -- ELSE
186 -- --COUNT
187 -- IF shift_data_s = "10" THEN
188 -- count_enable <= '1';
189 -- ELSE
190 -- count_enable <= '0';
191 -- END IF;
192 -- --DATA
193 -- IF shift_time_s = "10" THEN
194 -- shift_data_enable <= '1';
195 -- ELSE
196 -- shift_data_enable <= '0';
197 -- END IF;
198
199 -- --TIME
200 -- IF ((shift_data_s = "10") AND (count = nb_data_by_buffer)) OR
201 -- shift_time_s = "00" OR
202 -- shift_time_s = "01"
203 -- THEN
204 -- shift_time_enable <= '1';
205 -- ELSE
206 -- shift_time_enable <= '0';
207 -- END IF;
208
209 -- --ACK
210 -- IF shift_data_s = "10" THEN
211 -- data_in_ack <= sel;
212 -- sel_ack <= '1';
213 -- ELSE
214 -- data_in_ack <= (OTHERS => '0');
215 -- sel_ack <= '0';
216 -- END IF;
217
218 -- --VALID OUT
219 -- all_wen: FOR I IN 3 DOWNTO 0 LOOP
220 -- IF sel(I) = '1' AND count_enable = '0' THEN
221 -- data_out_wen(I) <= '0';
222 -- ELSE
223 -- data_out_wen(I) <= '1';
224 -- END IF;
225 -- END LOOP all_wen;
226
227 -- END IF;
228 -- END IF;
229 --END PROCESS;
230 159
231 160 -----------------------------------------------------------------------------
232 161 -- DATA MUX
233 162 -----------------------------------------------------------------------------
234 all_bit_data_in: FOR I IN 32*5-1 DOWNTO 0 GENERATE
235 I_time_in: IF I < 48 GENERATE
236 data_0_v(I) <= time_in(0,I);
237 data_1_v(I) <= time_in(1,I);
238 data_2_v(I) <= time_in(2,I);
239 data_3_v(I) <= time_in(3,I);
240 END GENERATE I_time_in;
241 I_null: IF (I > 47) AND (I < 32*2) GENERATE
242 data_0_v(I) <= '0';
243 data_1_v(I) <= '0';
244 data_2_v(I) <= '0';
245 data_3_v(I) <= '0';
246 END GENERATE I_null;
247 I_data_in: IF I > 32*2-1 GENERATE
248 data_0_v(I) <= data_in(0,I-32*2);
249 data_1_v(I) <= data_in(1,I-32*2);
250 data_2_v(I) <= data_in(2,I-32*2);
251 data_3_v(I) <= data_in(3,I-32*2);
252 END GENERATE I_data_in;
253 END GENERATE all_bit_data_in;
254 163
255 all_word: FOR J IN 4 DOWNTO 0 GENERATE
164 all_word: FOR J IN 2 DOWNTO 0 GENERATE
256 165 all_data_bit: FOR I IN 31 DOWNTO 0 GENERATE
257 data_0(J)(I) <= data_0_v(J*32+I);
258 data_1(J)(I) <= data_1_v(J*32+I);
259 data_2(J)(I) <= data_2_v(J*32+I);
260 data_3(J)(I) <= data_3_v(J*32+I);
166 data_0(J)(I) <= data_in(0,I+32*J);
167 data_1(J)(I) <= data_in(1,I+32*J);
168 data_2(J)(I) <= data_in(2,I+32*J);
169 data_3(J)(I) <= data_in(3,I+32*J);
261 170 END GENERATE all_data_bit;
262 171 END GENERATE all_word;
263 172
264 173 data_sel <= data_0 WHEN sel(0) = '1' ELSE
265 174 data_1 WHEN sel(1) = '1' ELSE
266 175 data_2 WHEN sel(2) = '1' ELSE
267 176 data_3;
268 177
269 --data_out <= data_sel(0) WHEN shift_time = "00" ELSE
270 -- data_sel(1) WHEN shift_time = "01" ELSE
271 -- data_sel(2) WHEN shift_data = "00" ELSE
272 -- data_sel(3) WHEN shift_data = "01" ELSE
273 -- data_sel(4);
178 all_time_bit: FOR I IN 3 DOWNTO 0 GENERATE
179 time_sel(I) <= time_in(0,I) WHEN sel(0) = '1' ELSE
180 time_in(1,I) WHEN sel(1) = '1' ELSE
181 time_in(2,I) WHEN sel(2) = '1' ELSE
182 time_in(3,I);
183 END GENERATE all_time_bit;
274 184
275 185
276 186 -----------------------------------------------------------------------------
277 187 -- RR and SELECTION
278 188 -----------------------------------------------------------------------------
279 189 all_input_rr : FOR I IN 3 DOWNTO 0 GENERATE
280 -- valid_in_rr(I) <= data_in_valid(I) AND NOT full(I);
281 190 valid_in_rr(I) <= data_in_valid(I) AND NOT full_almost(I);
282 191 END GENERATE all_input_rr;
283 192
284 193 RR_Arbiter_4_1 : RR_Arbiter_4
285 194 PORT MAP (
286 195 clk => clk,
287 196 rstn => rstn,
288 197 in_valid => valid_in_rr,
289 out_grant => sel_s); --sel_s);
290
291 -- sel <= sel_s;
198 out_grant => sel_s);
292 199
293 200 PROCESS (clk, rstn)
294 201 BEGIN -- PROCESS
295 202 IF rstn = '0' THEN -- asynchronous reset (active low)
296 203 sel <= "0000";
297 204 sel_reg <= '0';
298 205 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
299 -- sel_reg
300 -- sel_ack
301 -- sel_s
302 -- sel = "0000 "
303 --sel <= sel_s;
304 IF sel_reg = '0' OR sel_ack = '1'
305 --OR shift_data_s = "10"
306 THEN
206 IF sel_reg = '0' OR sel_ack = '1' THEN
307 207 sel <= sel_s;
308 208 IF sel_s = "0000" THEN
309 209 sel_reg <= '0';
310 210 ELSE
311 211 sel_reg <= '1';
312 212 END IF;
313 213 END IF;
314 214 END IF;
315 215 END PROCESS;
316 216
317 217 no_sel <= '1' WHEN sel = "0000" ELSE '0';
318 218
319 219 -----------------------------------------------------------------------------
320 220 -- REG
321 221 -----------------------------------------------------------------------------
322 222 reg_count_i: lpp_waveform_fifo_arbiter_reg
323 223 GENERIC MAP (
324 224 data_size => nb_data_by_buffer_size,
325 225 data_nb => 4)
326 226 PORT MAP (
327 227 clk => clk,
328 228 rstn => rstn,
329 229 run => run,
330 230 max_count => nb_data_by_buffer,
331 231 enable => count_enable,
332 232 sel => sel,
333 233 data => count,
334 234 data_s => count_s);
335
336 --reg_shift_data_i: lpp_waveform_fifo_arbiter_reg
337 -- GENERIC MAP (
338 -- data_size => 2,
339 -- data_nb => 4)
340 -- PORT MAP (
341 -- clk => clk,
342 -- rstn => rstn,
343 -- run => run,
344 -- max_count => "10", -- 2
345 -- enable => shift_data_enable,
346 -- sel => sel,
347 -- data => shift_data,
348 -- data_s => shift_data_s);
349
350
351 --reg_shift_time_i: lpp_waveform_fifo_arbiter_reg
352 -- GENERIC MAP (
353 -- data_size => 2,
354 -- data_nb => 4)
355 -- PORT MAP (
356 -- clk => clk,
357 -- rstn => rstn,
358 -- run => run,
359 -- max_count => "10", -- 2
360 -- enable => shift_time_enable,
361 -- sel => sel,
362 -- data => shift_time,
363 -- data_s => shift_time_s);
364 235
365 236
366 237
367 238
368 239 END ARCHITECTURE;
369 240
370 241
371 242
372 243
373 244
374 245
375 246
376 247
377 248
378 249
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@@ -1,402 +1,392
1 1 ------------------------------------------------------------------------------
2 2 -- This file is a part of the LPP VHDL IP LIBRARY
3 3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 3 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 -------------------------------------------------------------------------------
19 19 -- Author : Jean-christophe Pellion
20 20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 21 -- jean-christophe.pellion@easii-ic.com
22 22 -------------------------------------------------------------------------------
23 23 LIBRARY IEEE;
24 24 USE IEEE.STD_LOGIC_1164.ALL;
25 25
26 26 LIBRARY grlib;
27 27 USE grlib.amba.ALL;
28 28 USE grlib.stdlib.ALL;
29 29 USE grlib.devices.ALL;
30 30 USE GRLIB.DMA2AHB_Package.ALL;
31 31
32 32 LIBRARY techmap;
33 33 USE techmap.gencomp.ALL;
34 34
35 35 PACKAGE lpp_waveform_pkg IS
36 36
37 37 TYPE LPP_TYPE_ADDR_FIFO_WAVEFORM IS ARRAY (NATURAL RANGE <>) OF STD_LOGIC_VECTOR(6 DOWNTO 0);
38 38
39 39 TYPE Data_Vector IS ARRAY (NATURAL RANGE <>, NATURAL RANGE <>) OF STD_LOGIC;
40 40
41 41 -----------------------------------------------------------------------------
42 42 -- SNAPSHOT
43 43 -----------------------------------------------------------------------------
44 44
45 45 COMPONENT lpp_waveform_snapshot
46 46 GENERIC (
47 47 data_size : INTEGER;
48 48 nb_snapshot_param_size : INTEGER);
49 49 PORT (
50 50 clk : IN STD_LOGIC;
51 51 rstn : IN STD_LOGIC;
52 52 run : IN STD_LOGIC;
53 53 enable : IN STD_LOGIC;
54 54 burst_enable : IN STD_LOGIC;
55 55 nb_snapshot_param : IN STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
56 56 start_snapshot : IN STD_LOGIC;
57 57 data_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
58 58 data_in_valid : IN STD_LOGIC;
59 59 data_out : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
60 60 data_out_valid : OUT STD_LOGIC);
61 61 END COMPONENT;
62 62
63 63 COMPONENT lpp_waveform_burst
64 64 GENERIC (
65 65 data_size : INTEGER);
66 66 PORT (
67 67 clk : IN STD_LOGIC;
68 68 rstn : IN STD_LOGIC;
69 69 run : IN STD_LOGIC;
70 70 enable : IN STD_LOGIC;
71 71 data_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
72 72 data_in_valid : IN STD_LOGIC;
73 73 data_out : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
74 74 data_out_valid : OUT STD_LOGIC);
75 75 END COMPONENT;
76 76
77 77 COMPONENT lpp_waveform_snapshot_controler
78 78 GENERIC (
79 79 delta_vector_size : INTEGER;
80 80 delta_vector_size_f0_2 : INTEGER);
81 81 PORT (
82 82 clk : IN STD_LOGIC;
83 83 rstn : IN STD_LOGIC;
84 84 reg_run : IN STD_LOGIC;
85 85 reg_start_date : IN STD_LOGIC_VECTOR(30 DOWNTO 0);
86 86 reg_delta_snapshot : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
87 87 reg_delta_f0 : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
88 88 reg_delta_f0_2 : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
89 89 reg_delta_f1 : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
90 90 reg_delta_f2 : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
91 91 coarse_time : IN STD_LOGIC_VECTOR(30 DOWNTO 0);
92 92 data_f0_valid : IN STD_LOGIC;
93 93 data_f2_valid : IN STD_LOGIC;
94 94 start_snapshot_f0 : OUT STD_LOGIC;
95 95 start_snapshot_f1 : OUT STD_LOGIC;
96 96 start_snapshot_f2 : OUT STD_LOGIC;
97 97 wfp_on : OUT STD_LOGIC);
98 98 END COMPONENT;
99 99
100 100 -----------------------------------------------------------------------------
101 101 --
102 102 -----------------------------------------------------------------------------
103 103 COMPONENT lpp_waveform
104 104 GENERIC (
105 105 tech : INTEGER;
106 106 data_size : INTEGER;
107 107 nb_data_by_buffer_size : INTEGER;
108 nb_word_by_buffer_size : INTEGER;
109 108 nb_snapshot_param_size : INTEGER;
110 109 delta_vector_size : INTEGER;
111 110 delta_vector_size_f0_2 : INTEGER);
112 111 PORT (
113 112 clk : IN STD_LOGIC;
114 113 rstn : IN STD_LOGIC;
115 114 reg_run : IN STD_LOGIC;
116 115 reg_start_date : IN STD_LOGIC_VECTOR(30 DOWNTO 0);
117 116 reg_delta_snapshot : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
118 117 reg_delta_f0 : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
119 118 reg_delta_f0_2 : IN STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0);
120 119 reg_delta_f1 : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
121 120 reg_delta_f2 : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
122 121 enable_f0 : IN STD_LOGIC;
123 122 enable_f1 : IN STD_LOGIC;
124 123 enable_f2 : IN STD_LOGIC;
125 124 enable_f3 : IN STD_LOGIC;
126 125 burst_f0 : IN STD_LOGIC;
127 126 burst_f1 : IN STD_LOGIC;
128 127 burst_f2 : IN STD_LOGIC;
129 128 nb_data_by_buffer : IN STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
130 nb_word_by_buffer : IN STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
131 129 nb_snapshot_param : IN STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
132 status_full : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
133 status_full_ack : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
134 status_full_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
135 130 status_new_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
131 status_buffer_ready : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
132 addr_buffer : IN STD_LOGIC_VECTOR(32*4 DOWNTO 0);
133 length_buffer : IN STD_LOGIC_VECTOR(25 DOWNTO 0);
134 ready_buffer : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
135 buffer_time : OUT STD_LOGIC_VECTOR(48*4-1 DOWNTO 0);
136 error_buffer_full : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
136 137 coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
137 138 fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
138 addr_data_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
139 139 data_f0_in_valid : IN STD_LOGIC;
140 140 data_f0_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
141 addr_data_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
142 141 data_f1_in_valid : IN STD_LOGIC;
143 142 data_f1_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
144 addr_data_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
145 143 data_f2_in_valid : IN STD_LOGIC;
146 144 data_f2_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
147 addr_data_f3 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
148 145 data_f3_in_valid : IN STD_LOGIC;
149 146 data_f3_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
150 147 data_f0_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
151 148 data_f0_data_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
152 149 data_f0_data_out_valid : OUT STD_LOGIC;
153 150 data_f0_data_out_valid_burst : OUT STD_LOGIC;
154 151 data_f0_data_out_ren : IN STD_LOGIC;
155 152 data_f1_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
156 153 data_f1_data_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
157 154 data_f1_data_out_valid : OUT STD_LOGIC;
158 155 data_f1_data_out_valid_burst : OUT STD_LOGIC;
159 156 data_f1_data_out_ren : IN STD_LOGIC;
160 157 data_f2_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
161 158 data_f2_data_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
162 159 data_f2_data_out_valid : OUT STD_LOGIC;
163 160 data_f2_data_out_valid_burst : OUT STD_LOGIC;
164 161 data_f2_data_out_ren : IN STD_LOGIC;
165 162 data_f3_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
166 163 data_f3_data_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
167 164 data_f3_data_out_valid : OUT STD_LOGIC;
168 165 data_f3_data_out_valid_burst : OUT STD_LOGIC;
169 166 data_f3_data_out_ren : IN STD_LOGIC;
170
171 --debug
172 observation_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
173 --debug_f0_data : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
174 --debug_f0_data_valid : OUT STD_LOGIC;
175 --debug_f1_data : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
176 --debug_f1_data_valid : OUT STD_LOGIC;
177 --debug_f2_data : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
178 --debug_f2_data_valid : OUT STD_LOGIC;
179 --debug_f3_data : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
180 --debug_f3_data_valid : OUT STD_LOGIC;
181
182 ----debug FIFO IN
183 --debug_f0_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
184 --debug_f0_data_fifo_in_valid : OUT STD_LOGIC;
185 --debug_f1_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
186 --debug_f1_data_fifo_in_valid : OUT STD_LOGIC;
187 --debug_f2_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
188 --debug_f2_data_fifo_in_valid : OUT STD_LOGIC;
189 --debug_f3_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
190 --debug_f3_data_fifo_in_valid : OUT STD_LOGIC
167
168 dma_fifo_valid_burst : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
169 dma_fifo_data : OUT STD_LOGIC_VECTOR(32*4-1 DOWNTO 0);
170 dma_fifo_ren : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
171 dma_buffer_new : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
172 dma_buffer_addr : OUT STD_LOGIC_VECTOR(32*4-1 DOWNTO 0);
173 dma_buffer_length : OUT STD_LOGIC_VECTOR(26*4-1 DOWNTO 0);
174 dma_buffer_full : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
175 dma_buffer_full_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0)
191 176 );
192 177 END COMPONENT;
193 178
194 179 COMPONENT lpp_waveform_dma_genvalid
195 180 PORT (
196 181 HCLK : IN STD_LOGIC;
197 182 HRESETn : IN STD_LOGIC;
198 183 run : IN STD_LOGIC;
199 184 valid_in : IN STD_LOGIC;
200 185 ack_in : IN STD_LOGIC;
201 186 time_in : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
202 187 valid_out : OUT STD_LOGIC;
203 188 time_out : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
204 189 error : OUT STD_LOGIC);
205 190 END COMPONENT;
206 191
207 192 -----------------------------------------------------------------------------
208 193 -- FIFO
209 194 -----------------------------------------------------------------------------
210 195 COMPONENT lpp_waveform_fifo_ctrl
211 196 GENERIC (
212 197 offset : INTEGER;
213 198 length : INTEGER);
214 199 PORT (
215 200 clk : IN STD_LOGIC;
216 201 rstn : IN STD_LOGIC;
217 202 run : IN STD_LOGIC;
218 203 ren : IN STD_LOGIC;
219 204 wen : IN STD_LOGIC;
220 205 mem_re : OUT STD_LOGIC;
221 206 mem_we : OUT STD_LOGIC;
222 207 mem_addr_ren : OUT STD_LOGIC_VECTOR(6 DOWNTO 0);
223 208 mem_addr_wen : OUT STD_LOGIC_VECTOR(6 DOWNTO 0);
224 209 empty_almost : OUT STD_LOGIC;
225 210 empty : OUT STD_LOGIC;
226 211 full_almost : OUT STD_LOGIC;
227 212 full : OUT STD_LOGIC);
228 213 END COMPONENT;
229 214
230 215 COMPONENT lpp_waveform_fifo_arbiter
231 216 GENERIC (
232 217 tech : INTEGER;
233 218 nb_data_by_buffer_size : INTEGER);
234 219 PORT (
235 220 clk : IN STD_LOGIC;
236 221 rstn : IN STD_LOGIC;
237 222 run : IN STD_LOGIC;
238 223 nb_data_by_buffer : IN STD_LOGIC_VECTOR(nb_data_by_buffer_size - 1 DOWNTO 0);
239 224 data_in_valid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
240 225 data_in_ack : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
241 226 data_in : IN Data_Vector(3 DOWNTO 0, 95 DOWNTO 0);
242 227 time_in : IN Data_Vector(3 DOWNTO 0, 47 DOWNTO 0);
243 228 data_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
244 229 data_out_wen : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
245 230 full_almost : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
246 full : IN STD_LOGIC_VECTOR(3 DOWNTO 0));
231 full : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
232 time_out : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
233 time_out_new : OUT STD_LOGIC_VECTOR(3 DOWNTO 0)
234 );
247 235 END COMPONENT;
248 236
249 237 COMPONENT lpp_waveform_fifo
250 238 GENERIC (
251 239 tech : INTEGER);
252 240 PORT (
253 241 clk : IN STD_LOGIC;
254 242 rstn : IN STD_LOGIC;
255 243 run : IN STD_LOGIC;
256 244 empty_almost : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
257 245 empty : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
258 246 data_ren : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
259 247 rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
260 248 full_almost : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
261 249 full : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
262 250 data_wen : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
263 251 wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0));
264 252 END COMPONENT;
265 253
266 254 COMPONENT lpp_waveform_fifo_headreg
267 255 GENERIC (
268 256 tech : INTEGER);
269 257 PORT (
270 258 clk : IN STD_LOGIC;
271 259 rstn : IN STD_LOGIC;
272 260 run : IN STD_LOGIC;
273 261 o_empty_almost : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
274 262 o_empty : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
275 263 o_data_ren : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
276 264 o_rdata_0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
277 265 o_rdata_1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
278 266 o_rdata_2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
279 267 o_rdata_3 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
280 268 i_empty_almost : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
281 269 i_empty : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
282 270 i_data_ren : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
283 271 i_rdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0));
284 272 END COMPONENT;
285 273
286 274 COMPONENT lpp_waveform_fifo_latencyCorrection
287 275 GENERIC (
288 276 tech : INTEGER);
289 277 PORT (
290 278 clk : IN STD_LOGIC;
291 279 rstn : IN STD_LOGIC;
292 280 run : IN STD_LOGIC;
293 281 empty_almost : OUT STD_LOGIC;
294 282 empty : OUT STD_LOGIC;
295 283 data_ren : IN STD_LOGIC;
296 284 rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
297 285 empty_almost_fifo : IN STD_LOGIC;
298 286 empty_fifo : IN STD_LOGIC;
299 287 data_ren_fifo : OUT STD_LOGIC;
300 288 rdata_fifo : IN STD_LOGIC_VECTOR(31 DOWNTO 0));
301 289 END COMPONENT;
302 290
303 291 COMPONENT lpp_waveform_fifo_withoutLatency
304 292 GENERIC (
305 293 tech : INTEGER);
306 294 PORT (
307 295 clk : IN STD_LOGIC;
308 296 rstn : IN STD_LOGIC;
309 297 run : IN STD_LOGIC;
310 298 empty_almost : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
311 299 empty : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
312 300 data_ren : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
313 301 rdata_0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
314 302 rdata_1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
315 303 rdata_2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
316 304 rdata_3 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
317 305 full_almost : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
318 306 full : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
319 307 data_wen : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
320 308 wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0));
321 309 END COMPONENT;
322 310
323 311 -----------------------------------------------------------------------------
324 312 -- GEN ADDRESS
325 313 -----------------------------------------------------------------------------
326 314 COMPONENT lpp_waveform_genaddress
327 315 GENERIC (
328 316 nb_data_by_buffer_size : INTEGER);
329 317 PORT (
330 318 clk : IN STD_LOGIC;
331 319 rstn : IN STD_LOGIC;
332 320 run : IN STD_LOGIC;
333 321 nb_data_by_buffer : IN STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
334 322 addr_data_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
335 323 addr_data_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
336 324 addr_data_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
337 325 addr_data_f3 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
338 326 empty : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
339 327 empty_almost : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
340 328 data_ren : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
341 329 status_full : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
342 330 status_full_ack : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
343 331 status_full_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
344 332 data_f0_data_out_valid_burst : OUT STD_LOGIC;
345 333 data_f1_data_out_valid_burst : OUT STD_LOGIC;
346 334 data_f2_data_out_valid_burst : OUT STD_LOGIC;
347 335 data_f3_data_out_valid_burst : OUT STD_LOGIC;
348 336 data_f0_data_out_valid : OUT STD_LOGIC;
349 337 data_f1_data_out_valid : OUT STD_LOGIC;
350 338 data_f2_data_out_valid : OUT STD_LOGIC;
351 339 data_f3_data_out_valid : OUT STD_LOGIC;
352 340 data_f0_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
353 341 data_f1_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
354 342 data_f2_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
355 343 data_f3_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0));
356 344 END COMPONENT;
357 345
358 346 -----------------------------------------------------------------------------
359 347 -- lpp_waveform_fifo_arbiter_reg
360 348 -----------------------------------------------------------------------------
361 349 COMPONENT lpp_waveform_fifo_arbiter_reg
362 350 GENERIC (
363 351 data_size : INTEGER;
364 352 data_nb : INTEGER);
365 353 PORT (
366 354 clk : IN STD_LOGIC;
367 355 rstn : IN STD_LOGIC;
368 356 run : IN STD_LOGIC;
369 357 max_count : IN STD_LOGIC_VECTOR(data_size -1 DOWNTO 0);
370 358 enable : IN STD_LOGIC;
371 359 sel : IN STD_LOGIC_VECTOR(data_nb-1 DOWNTO 0);
372 360 data : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
373 data_s : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0));
361 data_s : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
362 time_out : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
363 time_out_new : OUT STD_LOGIC_VECTOR(3 DOWNTO 0));
374 364 END COMPONENT;
375 365
376 366 COMPONENT lpp_waveform_fsmdma
377 367 PORT (
378 368 clk : IN STD_ULOGIC;
379 369 rstn : IN STD_ULOGIC;
380 370 run : IN STD_LOGIC;
381 371 fifo_buffer_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
382 372 fifo_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
383 373 fifo_empty : IN STD_LOGIC;
384 374 fifo_empty_threshold : IN STD_LOGIC;
385 375 fifo_ren : OUT STD_LOGIC;
386 376 dma_fifo_valid_burst : OUT STD_LOGIC;
387 377 dma_fifo_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
388 378 dma_fifo_ren : IN STD_LOGIC;
389 379 dma_buffer_new : OUT STD_LOGIC;
390 380 dma_buffer_addr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
391 381 dma_buffer_length : OUT STD_LOGIC_VECTOR(25 DOWNTO 0);
392 382 dma_buffer_full : IN STD_LOGIC;
393 383 dma_buffer_full_err : IN STD_LOGIC;
394 384 status_buffer_ready : IN STD_LOGIC;
395 385 addr_buffer : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
396 386 length_buffer : IN STD_LOGIC_VECTOR(25 DOWNTO 0);
397 387 ready_buffer : OUT STD_LOGIC;
398 388 buffer_time : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
399 389 error_buffer_full : OUT STD_LOGIC);
400 390 END COMPONENT;
401 391
402 392 END lpp_waveform_pkg;
Show file before | Show file after | Hide comments
@@ -1,14 +1,15
1 1 lpp_waveform_pkg.vhd
2 2 lpp_waveform.vhd
3 3 lpp_waveform_burst.vhd
4 4 lpp_waveform_fifo_withoutLatency.vhd
5 5 lpp_waveform_fifo_latencyCorrection.vhd
6 6 lpp_waveform_fifo.vhd
7 7 lpp_waveform_fifo_arbiter.vhd
8 8 lpp_waveform_fifo_ctrl.vhd
9 9 lpp_waveform_fifo_headreg.vhd
10 10 lpp_waveform_snapshot.vhd
11 11 lpp_waveform_snapshot_controler.vhd
12 12 lpp_waveform_genaddress.vhd
13 13 lpp_waveform_dma_genvalid.vhd
14 14 lpp_waveform_fifo_arbiter_reg.vhd
15 lpp_waveform_fsmdma.vhd
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