# HG changeset patch # User pellion # Date 2014-10-21 12:20:38 # Node ID 051c08efe9e3f0ae92126f130bdd36a52f7c1485 # Parent 0d4ef716262ed0618d6b0214943053fe6d6fbdc4 (temp) new DMA_SubSystem synthesis ok, test ongoing diff --git a/lib/lpp/lpp_top_lfr/lpp_lfr.vhd b/lib/lpp/lpp_top_lfr/lpp_lfr.vhd --- a/lib/lpp/lpp_top_lfr/lpp_lfr.vhd +++ b/lib/lpp/lpp_top_lfr/lpp_lfr.vhd @@ -26,7 +26,7 @@ ENTITY lpp_lfr IS GENERIC ( Mem_use : INTEGER := use_RAM; nb_data_by_buffer_size : INTEGER := 11; - nb_word_by_buffer_size : INTEGER := 11; +-- nb_word_by_buffer_size : INTEGER := 11; -- TODO nb_snapshot_param_size : INTEGER := 11; delta_vector_size : INTEGER := 20; delta_vector_size_f0_2 : INTEGER := 7; @@ -161,9 +161,9 @@ ARCHITECTURE beh OF lpp_lfr IS SIGNAL length_matrix_f2 : STD_LOGIC_VECTOR(25 DOWNTO 0); -- WFP - SIGNAL status_full : STD_LOGIC_VECTOR(3 DOWNTO 0); - SIGNAL status_full_ack : STD_LOGIC_VECTOR(3 DOWNTO 0); - SIGNAL status_full_err : STD_LOGIC_VECTOR(3 DOWNTO 0); + --SIGNAL status_full : STD_LOGIC_VECTOR(3 DOWNTO 0); + --SIGNAL status_full_ack : STD_LOGIC_VECTOR(3 DOWNTO 0); + --SIGNAL status_full_err : STD_LOGIC_VECTOR(3 DOWNTO 0); SIGNAL status_new_err : STD_LOGIC_VECTOR(3 DOWNTO 0); SIGNAL delta_snapshot : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); SIGNAL delta_f0 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); @@ -172,7 +172,6 @@ ARCHITECTURE beh OF lpp_lfr IS SIGNAL delta_f2 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); SIGNAL nb_data_by_buffer : STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0); - SIGNAL nb_word_by_buffer : STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0); SIGNAL nb_snapshot_param : STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0); SIGNAL enable_f0 : STD_LOGIC; SIGNAL enable_f1 : STD_LOGIC; @@ -181,38 +180,10 @@ ARCHITECTURE beh OF lpp_lfr IS SIGNAL burst_f0 : STD_LOGIC; SIGNAL burst_f1 : STD_LOGIC; SIGNAL burst_f2 : STD_LOGIC; - SIGNAL addr_data_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0); - SIGNAL addr_data_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0); - SIGNAL addr_data_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0); - SIGNAL addr_data_f3 : STD_LOGIC_VECTOR(31 DOWNTO 0); SIGNAL run : STD_LOGIC; SIGNAL start_date : STD_LOGIC_VECTOR(30 DOWNTO 0); - SIGNAL data_f0_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0); - SIGNAL data_f0_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0); - SIGNAL data_f0_data_out_valid : STD_LOGIC; - SIGNAL data_f0_data_out_valid_burst : STD_LOGIC; - SIGNAL data_f0_data_out_ren : STD_LOGIC; - --f1 - SIGNAL data_f1_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0); - SIGNAL data_f1_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0); - SIGNAL data_f1_data_out_valid : STD_LOGIC; - SIGNAL data_f1_data_out_valid_burst : STD_LOGIC; - SIGNAL data_f1_data_out_ren : STD_LOGIC; - --f2 - SIGNAL data_f2_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0); - SIGNAL data_f2_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0); - SIGNAL data_f2_data_out_valid : STD_LOGIC; - SIGNAL data_f2_data_out_valid_burst : STD_LOGIC; - SIGNAL data_f2_data_out_ren : STD_LOGIC; - --f3 - SIGNAL data_f3_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0); - SIGNAL data_f3_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0); - SIGNAL data_f3_data_out_valid : STD_LOGIC; - SIGNAL data_f3_data_out_valid_burst : STD_LOGIC; - SIGNAL data_f3_data_out_ren : STD_LOGIC; - ----------------------------------------------------------------------------- -- ----------------------------------------------------------------------------- @@ -232,6 +203,12 @@ ARCHITECTURE beh OF lpp_lfr IS SIGNAL data_f3_data_out_valid_s : STD_LOGIC; SIGNAL data_f3_data_out_valid_burst_s : STD_LOGIC; + SIGNAL wfp_status_buffer_ready : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL wfp_addr_buffer : STD_LOGIC_VECTOR(32*4 DOWNTO 0); + SIGNAL wfp_length_buffer : STD_LOGIC_VECTOR(25 DOWNTO 0); + SIGNAL wfp_ready_buffer : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL wfp_buffer_time : STD_LOGIC_VECTOR(48*4-1 DOWNTO 0); + SIGNAL wfp_error_buffer_full : STD_LOGIC_VECTOR(3 DOWNTO 0); ----------------------------------------------------------------------------- -- DMA RR ----------------------------------------------------------------------------- @@ -340,7 +317,7 @@ BEGIN lpp_lfr_apbreg_1 : lpp_lfr_apbreg GENERIC MAP ( nb_data_by_buffer_size => nb_data_by_buffer_size, - nb_word_by_buffer_size => nb_word_by_buffer_size, +-- nb_word_by_buffer_size => nb_word_by_buffer_size, -- TODO nb_snapshot_param_size => nb_snapshot_param_size, delta_vector_size => delta_vector_size, delta_vector_size_f0_2 => delta_vector_size_f0_2, @@ -379,9 +356,9 @@ BEGIN length_matrix_f1 => length_matrix_f1, length_matrix_f2 => length_matrix_f2, ------------------------------------------------------------------------- - status_full => status_full, - status_full_ack => status_full_ack, - status_full_err => status_full_err, + --status_full => status_full, -- TODo + --status_full_ack => status_full_ack, -- TODo + --status_full_err => status_full_err, -- TODo status_new_err => status_new_err, data_shaping_BW => data_shaping_BW, data_shaping_SP0 => data_shaping_SP0, @@ -395,7 +372,7 @@ BEGIN delta_f1 => delta_f1, delta_f2 => delta_f2, nb_data_by_buffer => nb_data_by_buffer, - nb_word_by_buffer => nb_word_by_buffer, +-- nb_word_by_buffer => nb_word_by_buffer, -- TODO nb_snapshot_param => nb_snapshot_param, enable_f0 => enable_f0, enable_f1 => enable_f1, @@ -405,12 +382,16 @@ BEGIN burst_f1 => burst_f1, burst_f2 => burst_f2, run => run, - addr_data_f0 => addr_data_f0, - addr_data_f1 => addr_data_f1, - addr_data_f2 => addr_data_f2, - addr_data_f3 => addr_data_f3, start_date => start_date, - debug_signal => debug_signal); +-- debug_signal => debug_signal, + wfp_status_buffer_ready => wfp_status_buffer_ready,-- TODO + wfp_addr_buffer => wfp_addr_buffer,-- TODO + wfp_length_buffer => wfp_length_buffer,-- TODO + + wfp_ready_buffer => wfp_ready_buffer,-- TODO + wfp_buffer_time => wfp_buffer_time,-- TODO + wfp_error_buffer_full => wfp_error_buffer_full -- TODO + ); ----------------------------------------------------------------------------- ----------------------------------------------------------------------------- @@ -419,7 +400,6 @@ BEGIN tech => inferred, data_size => 6*16, nb_data_by_buffer_size => nb_data_by_buffer_size, - nb_word_by_buffer_size => nb_word_by_buffer_size, nb_snapshot_param_size => nb_snapshot_param_size, delta_vector_size => delta_vector_size, delta_vector_size_f0_2 => delta_vector_size_f0_2 @@ -445,234 +425,43 @@ BEGIN burst_f2 => burst_f2, nb_data_by_buffer => nb_data_by_buffer, - nb_word_by_buffer => nb_word_by_buffer, nb_snapshot_param => nb_snapshot_param, - status_full => status_full, - status_full_ack => status_full_ack, - status_full_err => status_full_err, status_new_err => status_new_err, + + status_buffer_ready => wfp_status_buffer_ready, + addr_buffer => wfp_addr_buffer, + length_buffer => wfp_length_buffer, + ready_buffer => wfp_ready_buffer, + buffer_time => wfp_buffer_time, + error_buffer_full => wfp_error_buffer_full, coarse_time => coarse_time, fine_time => fine_time, --f0 - addr_data_f0 => addr_data_f0, data_f0_in_valid => sample_f0_val, data_f0_in => sample_f0_data, --f1 - addr_data_f1 => addr_data_f1, data_f1_in_valid => sample_f1_val, data_f1_in => sample_f1_data, --f2 - addr_data_f2 => addr_data_f2, data_f2_in_valid => sample_f2_val, data_f2_in => sample_f2_data, --f3 - addr_data_f3 => addr_data_f3, data_f3_in_valid => sample_f3_val, data_f3_in => sample_f3_data, -- OUTPUT -- DMA interface - --f0 - data_f0_addr_out => data_f0_addr_out_s, - data_f0_data_out => data_f0_data_out, - data_f0_data_out_valid => data_f0_data_out_valid_s, - data_f0_data_out_valid_burst => data_f0_data_out_valid_burst_s, - data_f0_data_out_ren => data_f0_data_out_ren, - --f1 - data_f1_addr_out => data_f1_addr_out_s, - data_f1_data_out => data_f1_data_out, - data_f1_data_out_valid => data_f1_data_out_valid_s, - data_f1_data_out_valid_burst => data_f1_data_out_valid_burst_s, - data_f1_data_out_ren => data_f1_data_out_ren, - --f2 - data_f2_addr_out => data_f2_addr_out_s, - data_f2_data_out => data_f2_data_out, - data_f2_data_out_valid => data_f2_data_out_valid_s, - data_f2_data_out_valid_burst => data_f2_data_out_valid_burst_s, - data_f2_data_out_ren => data_f2_data_out_ren, - --f3 - data_f3_addr_out => data_f3_addr_out_s, - data_f3_data_out => data_f3_data_out, - data_f3_data_out_valid => data_f3_data_out_valid_s, - data_f3_data_out_valid_burst => data_f3_data_out_valid_burst_s, - data_f3_data_out_ren => data_f3_data_out_ren , - - ------------------------------------------------------------------------- - observation_reg => OPEN - - ); - - - ----------------------------------------------------------------------------- - -- TEMP - ----------------------------------------------------------------------------- - - PROCESS (clk, rstn) - BEGIN -- PROCESS - IF rstn = '0' THEN -- asynchronous reset (active low) - data_f0_data_out_valid <= '0'; - data_f0_data_out_valid_burst <= '0'; - data_f1_data_out_valid <= '0'; - data_f1_data_out_valid_burst <= '0'; - data_f2_data_out_valid <= '0'; - data_f2_data_out_valid_burst <= '0'; - data_f3_data_out_valid <= '0'; - data_f3_data_out_valid_burst <= '0'; - ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge - data_f0_data_out_valid <= data_f0_data_out_valid_s; - data_f0_data_out_valid_burst <= data_f0_data_out_valid_burst_s; - data_f1_data_out_valid <= data_f1_data_out_valid_s; - data_f1_data_out_valid_burst <= data_f1_data_out_valid_burst_s; - data_f2_data_out_valid <= data_f2_data_out_valid_s; - data_f2_data_out_valid_burst <= data_f2_data_out_valid_burst_s; - data_f3_data_out_valid <= data_f3_data_out_valid_s; - data_f3_data_out_valid_burst <= data_f3_data_out_valid_burst_s; - END IF; - END PROCESS; - - data_f0_addr_out <= data_f0_addr_out_s; - data_f1_addr_out <= data_f1_addr_out_s; - data_f2_addr_out <= data_f2_addr_out_s; - data_f3_addr_out <= data_f3_addr_out_s; - - ----------------------------------------------------------------------------- - -- RoundRobin Selection For DMA - ----------------------------------------------------------------------------- - - dma_rr_valid(0) <= data_f0_data_out_valid OR data_f0_data_out_valid_burst; - dma_rr_valid(1) <= data_f1_data_out_valid OR data_f1_data_out_valid_burst; - dma_rr_valid(2) <= data_f2_data_out_valid OR data_f2_data_out_valid_burst; - dma_rr_valid(3) <= data_f3_data_out_valid OR data_f3_data_out_valid_burst; - - RR_Arbiter_4_1 : RR_Arbiter_4 - PORT MAP ( - clk => clk, - rstn => rstn, - in_valid => dma_rr_valid, - out_grant => dma_rr_grant_s); - - dma_rr_valid_ms(0) <= data_ms_valid OR data_ms_valid_burst; - dma_rr_valid_ms(1) <= '0' WHEN dma_rr_grant_s = "0000" ELSE '1'; - dma_rr_valid_ms(2) <= '0'; - dma_rr_valid_ms(3) <= '0'; - - RR_Arbiter_4_2 : RR_Arbiter_4 - PORT MAP ( - clk => clk, - rstn => rstn, - in_valid => dma_rr_valid_ms, - out_grant => dma_rr_grant_ms); - - dma_rr_grant <= dma_rr_grant_ms(0) & "0000" WHEN dma_rr_grant_ms(0) = '1' ELSE '0' & dma_rr_grant_s; - + + dma_fifo_valid_burst => dma_fifo_burst_valid(3 DOWNTO 0), + dma_fifo_data => dma_fifo_data(32*4-1 DOWNTO 0), + dma_fifo_ren => dma_fifo_ren(3 DOWNTO 0), + dma_buffer_new => dma_buffer_new(3 DOWNTO 0), + dma_buffer_addr => dma_buffer_addr(32*4-1 DOWNTO 0), + dma_buffer_length => dma_buffer_length(26*4-1 DOWNTO 0), + dma_buffer_full => dma_buffer_full(3 DOWNTO 0), + dma_buffer_full_err => dma_buffer_full_err(3 DOWNTO 0) - ----------------------------------------------------------------------------- - -- in : dma_rr_grant - -- send - -- out : dma_sel - -- dma_valid_burst - -- dma_sel_valid - ----------------------------------------------------------------------------- - PROCESS (clk, rstn) - BEGIN -- PROCESS - IF rstn = '0' THEN -- asynchronous reset (active low) - dma_sel <= (OTHERS => '0'); - dma_send <= '0'; - dma_valid_burst <= '0'; - data_ms_done <= '0'; - dma_ms_ongoing <= '0'; - ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge - IF run = '1' THEN - data_ms_done <= '0'; - IF dma_sel = "00000" OR dma_done = '1' THEN - dma_sel <= dma_rr_grant; - IF dma_rr_grant(0) = '1' THEN - dma_ms_ongoing <= '0'; - dma_send <= '1'; - dma_valid_burst <= data_f0_data_out_valid_burst; - dma_sel_valid <= data_f0_data_out_valid; - ELSIF dma_rr_grant(1) = '1' THEN - dma_ms_ongoing <= '0'; - dma_send <= '1'; - dma_valid_burst <= data_f1_data_out_valid_burst; - dma_sel_valid <= data_f1_data_out_valid; - ELSIF dma_rr_grant(2) = '1' THEN - dma_ms_ongoing <= '0'; - dma_send <= '1'; - dma_valid_burst <= data_f2_data_out_valid_burst; - dma_sel_valid <= data_f2_data_out_valid; - ELSIF dma_rr_grant(3) = '1' THEN - dma_ms_ongoing <= '0'; - dma_send <= '1'; - dma_valid_burst <= data_f3_data_out_valid_burst; - dma_sel_valid <= data_f3_data_out_valid; - ELSIF dma_rr_grant(4) = '1' THEN - dma_ms_ongoing <= '1'; - dma_send <= '1'; - dma_valid_burst <= data_ms_valid_burst; - dma_sel_valid <= data_ms_valid; - --ELSE - --dma_ms_ongoing <= '0'; - END IF; - - IF dma_ms_ongoing = '1' AND dma_done = '1' THEN - data_ms_done <= '1'; - END IF; - ELSE - dma_sel <= dma_sel; - dma_send <= '0'; - END IF; - ELSE - data_ms_done <= '0'; - dma_sel <= (OTHERS => '0'); - dma_send <= '0'; - dma_valid_burst <= '0'; - END IF; - END IF; - END PROCESS; - - - dma_address <= data_f0_addr_out WHEN dma_sel(0) = '1' ELSE - data_f1_addr_out WHEN dma_sel(1) = '1' ELSE - data_f2_addr_out WHEN dma_sel(2) = '1' ELSE - data_f3_addr_out WHEN dma_sel(3) = '1' ELSE - data_ms_addr; - - dma_data <= data_f0_data_out WHEN dma_sel(0) = '1' ELSE - data_f1_data_out WHEN dma_sel(1) = '1' ELSE - data_f2_data_out WHEN dma_sel(2) = '1' ELSE - data_f3_data_out WHEN dma_sel(3) = '1' ELSE - data_ms_data; - - data_f0_data_out_ren <= dma_ren WHEN dma_sel(0) = '1' ELSE '1'; - data_f1_data_out_ren <= dma_ren WHEN dma_sel(1) = '1' ELSE '1'; - data_f2_data_out_ren <= dma_ren WHEN dma_sel(2) = '1' ELSE '1'; - data_f3_data_out_ren <= dma_ren WHEN dma_sel(3) = '1' ELSE '1'; - data_ms_ren <= dma_ren WHEN dma_sel(4) = '1' ELSE '1'; - - dma_data_2 <= dma_data; - - - ----------------------------------------------------------------------------- - -- DMA - ----------------------------------------------------------------------------- - lpp_dma_singleOrBurst_1 : lpp_dma_singleOrBurst - GENERIC MAP ( - tech => inferred, - hindex => hindex) - PORT MAP ( - HCLK => clk, - HRESETn => rstn, - run => run, - AHB_Master_In => OPEN, - AHB_Master_Out => OPEN, - - send => dma_send, - valid_burst => dma_valid_burst, - done => dma_done, - ren => dma_ren, - address => dma_address, - data => dma_data_2); + ); ----------------------------------------------------------------------------- -- Matrix Spectral diff --git a/lib/lpp/lpp_top_lfr/lpp_lfr_apbreg.vhd b/lib/lpp/lpp_top_lfr/lpp_lfr_apbreg.vhd --- a/lib/lpp/lpp_top_lfr/lpp_lfr_apbreg.vhd +++ b/lib/lpp/lpp_top_lfr/lpp_lfr_apbreg.vhd @@ -38,7 +38,7 @@ USE techmap.gencomp.ALL; ENTITY lpp_lfr_apbreg IS GENERIC ( nb_data_by_buffer_size : INTEGER := 11; - nb_word_by_buffer_size : INTEGER := 11; +-- nb_word_by_buffer_size : INTEGER := 11; nb_snapshot_param_size : INTEGER := 11; delta_vector_size : INTEGER := 20; delta_vector_size_f0_2 : INTEGER := 3; @@ -95,11 +95,11 @@ ENTITY lpp_lfr_apbreg IS --------------------------------------------------------------------------- --------------------------------------------------------------------------- -- WaveForm picker Reg - status_full : IN STD_LOGIC_VECTOR(3 DOWNTO 0); - status_full_ack : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); - status_full_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0); + --status_full : IN STD_LOGIC_VECTOR(3 DOWNTO 0); + --status_full_ack : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + --status_full_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0); status_new_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0); - + -- OUT data_shaping_BW : OUT STD_LOGIC; data_shaping_SP0 : OUT STD_LOGIC; @@ -114,7 +114,7 @@ ENTITY lpp_lfr_apbreg IS delta_f1 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); delta_f2 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); nb_data_by_buffer : OUT STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0); - nb_word_by_buffer : OUT STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0); + --nb_word_by_buffer : OUT STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0); nb_snapshot_param : OUT STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0); enable_f0 : OUT STD_LOGIC; @@ -128,14 +128,15 @@ ENTITY lpp_lfr_apbreg IS run : OUT STD_LOGIC; - addr_data_f0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); - addr_data_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); - addr_data_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); - addr_data_f3 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); start_date : OUT STD_LOGIC_VECTOR(30 DOWNTO 0); - --------------------------------------------------------------------------- - debug_signal : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) - --------------------------------------------------------------------------- + + wfp_status_buffer_ready : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + wfp_addr_buffer : OUT STD_LOGIC_VECTOR(32*4 DOWNTO 0); + wfp_length_buffer : OUT STD_LOGIC_VECTOR(25 DOWNTO 0); + wfp_ready_buffer : IN STD_LOGIC_VECTOR(3 DOWNTO 0); + wfp_buffer_time : IN STD_LOGIC_VECTOR(48*4-1 DOWNTO 0); + wfp_error_buffer_full : IN STD_LOGIC_VECTOR(3 DOWNTO 0) + ); END lpp_lfr_apbreg; @@ -181,8 +182,8 @@ ARCHITECTURE beh OF lpp_lfr_apbreg IS SIGNAL reg_sp : lpp_SpectralMatrix_regs; TYPE lpp_WaveformPicker_regs IS RECORD - status_full : STD_LOGIC_VECTOR(3 DOWNTO 0); - status_full_err : STD_LOGIC_VECTOR(3 DOWNTO 0); +-- status_full : STD_LOGIC_VECTOR(3 DOWNTO 0); +-- status_full_err : STD_LOGIC_VECTOR(3 DOWNTO 0); status_new_err : STD_LOGIC_VECTOR(3 DOWNTO 0); data_shaping_BW : STD_LOGIC; data_shaping_SP0 : STD_LOGIC; @@ -196,7 +197,7 @@ ARCHITECTURE beh OF lpp_lfr_apbreg IS delta_f1 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); delta_f2 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); nb_data_by_buffer : STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0); - nb_word_by_buffer : STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0); +-- nb_word_by_buffer : STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0); nb_snapshot_param : STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0); enable_f0 : STD_LOGIC; enable_f1 : STD_LOGIC; @@ -206,10 +207,11 @@ ARCHITECTURE beh OF lpp_lfr_apbreg IS burst_f1 : STD_LOGIC; burst_f2 : STD_LOGIC; run : STD_LOGIC; - addr_data_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0); - addr_data_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0); - addr_data_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0); - addr_data_f3 : STD_LOGIC_VECTOR(31 DOWNTO 0); + status_ready_buffer_f : STD_LOGIC_VECTOR(4*2-1 DOWNTO 0); + addr_buffer_f : STD_LOGIC_VECTOR(4*2*32-1 DOWNTO 0); + time_buffer_f : STD_LOGIC_VECTOR(4*2*48-1 DOWNTO 0); + length_buffer : STD_LOGIC_VECTOR(25 DOWNTO 0); + error_buffer_full : STD_LOGIC_VECTOR(3 DOWNTO 0); start_date : STD_LOGIC_VECTOR(30 DOWNTO 0); END RECORD; SIGNAL reg_wp : lpp_WaveformPicker_regs; @@ -254,6 +256,8 @@ ARCHITECTURE beh OF lpp_lfr_apbreg IS SIGNAL reg1_matrix_time_f2 : STD_LOGIC_VECTOR(47 DOWNTO 0); SIGNAL apbo_irq_ms : STD_LOGIC; SIGNAL apbo_irq_wfp : STD_LOGIC; + ----------------------------------------------------------------------------- + SIGNAL reg_ready_buffer_f : STD_LOGIC_VECTOR( 2*4-1 DOWNTO 0); BEGIN -- beh @@ -283,7 +287,6 @@ BEGIN -- beh delta_f1 <= reg_wp.delta_f1; delta_f2 <= reg_wp.delta_f2; nb_data_by_buffer <= reg_wp.nb_data_by_buffer; - nb_word_by_buffer <= reg_wp.nb_word_by_buffer; nb_snapshot_param <= reg_wp.nb_snapshot_param; enable_f0 <= reg_wp.enable_f0; @@ -297,16 +300,16 @@ BEGIN -- beh run <= reg_wp.run; - addr_data_f0 <= reg_wp.addr_data_f0; - addr_data_f1 <= reg_wp.addr_data_f1; - addr_data_f2 <= reg_wp.addr_data_f2; - addr_data_f3 <= reg_wp.addr_data_f3; + --addr_data_f0 <= reg_wp.addr_data_f0; + --addr_data_f1 <= reg_wp.addr_data_f1; + --addr_data_f2 <= reg_wp.addr_data_f2; + --addr_data_f3 <= reg_wp.addr_data_f3; start_date <= reg_wp.start_date; - length_matrix_f0 <= reg_sp.length_matrix; - length_matrix_f1 <= reg_sp.length_matrix; - length_matrix_f2 <= reg_sp.length_matrix; + --length_matrix_f0 <= reg_sp.length_matrix; + --length_matrix_f1 <= reg_sp.length_matrix; + --length_matrix_f2 <= reg_sp.length_matrix; lpp_lfr_apbreg : PROCESS (HCLK, HRESETn) @@ -322,7 +325,6 @@ BEGIN -- beh reg_sp.status_ready_matrix_f0_1 <= '0'; reg_sp.status_ready_matrix_f1_1 <= '0'; reg_sp.status_ready_matrix_f2_1 <= '0'; --- reg_sp.status_error_bad_component_error <= '0'; reg_sp.status_error_buffer_full <= '0'; reg_sp.status_error_input_fifo_write <= (OTHERS => '0'); @@ -351,7 +353,7 @@ BEGIN -- beh apbo_irq_wfp <= '0'; - status_full_ack <= (OTHERS => '0'); +-- status_full_ack <= (OTHERS => '0'); reg_wp.data_shaping_BW <= '0'; reg_wp.data_shaping_SP0 <= '0'; @@ -367,13 +369,10 @@ BEGIN -- beh reg_wp.burst_f1 <= '0'; reg_wp.burst_f2 <= '0'; reg_wp.run <= '0'; - reg_wp.addr_data_f0 <= (OTHERS => '0'); - reg_wp.addr_data_f1 <= (OTHERS => '0'); - reg_wp.addr_data_f2 <= (OTHERS => '0'); - reg_wp.addr_data_f3 <= (OTHERS => '0'); - reg_wp.status_full <= (OTHERS => '0'); - reg_wp.status_full_err <= (OTHERS => '0'); +-- reg_wp.status_full <= (OTHERS => '0'); +-- reg_wp.status_full_err <= (OTHERS => '0'); reg_wp.status_new_err <= (OTHERS => '0'); + reg_wp.error_buffer_full <= (OTHERS => '0'); reg_wp.delta_snapshot <= (OTHERS => '0'); reg_wp.delta_f0 <= (OTHERS => '0'); reg_wp.delta_f0_2 <= (OTHERS => '0'); @@ -385,7 +384,7 @@ BEGIN -- beh ELSIF HCLK'EVENT AND HCLK = '1' THEN -- rising clock edge - status_full_ack <= (OTHERS => '0'); +-- status_full_ack <= (OTHERS => '0'); reg_sp.status_ready_matrix_f0_0 <= reg_sp.status_ready_matrix_f0_0 OR reg0_ready_matrix_f0; reg_sp.status_ready_matrix_f1_0 <= reg_sp.status_ready_matrix_f1_0 OR reg0_ready_matrix_f1; @@ -395,7 +394,10 @@ BEGIN -- beh reg_sp.status_ready_matrix_f1_1 <= reg_sp.status_ready_matrix_f1_1 OR reg1_ready_matrix_f1; reg_sp.status_ready_matrix_f2_1 <= reg_sp.status_ready_matrix_f2_1 OR reg1_ready_matrix_f2; --- reg_sp.status_error_bad_component_error <= reg_sp.status_error_bad_component_error OR error_bad_component_error; + all_status_ready_buffer_bit: FOR I IN 4*2-1 DOWNTO 0 LOOP + reg_wp.status_ready_buffer_f(I) <= reg_wp.status_ready_buffer_f(I) OR reg_ready_buffer_f(I); + END LOOP all_status_ready_buffer_bit; + reg_sp.status_error_buffer_full <= reg_sp.status_error_buffer_full OR error_buffer_full; reg_sp.status_error_input_fifo_write(0) <= reg_sp.status_error_input_fifo_write(0) OR error_input_fifo_write(0); @@ -405,9 +407,8 @@ BEGIN -- beh all_status : FOR I IN 3 DOWNTO 0 LOOP - reg_wp.status_full(I) <= status_full(I) AND reg_wp.run; - reg_wp.status_full_err(I) <= status_full_err(I) AND reg_wp.run; - reg_wp.status_new_err(I) <= status_new_err(I) AND reg_wp.run; + reg_wp.error_buffer_full(I) <= reg_wp.error_buffer_full(I) OR wfp_error_buffer_full(I); + reg_wp.status_new_err(I) <= reg_wp.status_new_err(I) OR status_new_err(I); END LOOP all_status; paddr := "000000"; @@ -488,35 +489,58 @@ BEGIN -- beh prdata(6) <= reg_wp.burst_f2; prdata(7) <= reg_wp.run; --22 - WHEN "010111" => prdata <= reg_wp.addr_data_f0; - --23 - WHEN "011000" => prdata <= reg_wp.addr_data_f1; - --24 - WHEN "011001" => prdata <= reg_wp.addr_data_f2; - --25 - WHEN "011010" => prdata <= reg_wp.addr_data_f3; - --26 - WHEN "011011" => prdata(3 DOWNTO 0) <= reg_wp.status_full; - prdata(7 DOWNTO 4) <= reg_wp.status_full_err; - prdata(11 DOWNTO 8) <= reg_wp.status_new_err; + --ON GOING \/ + WHEN "010111" => prdata <= reg_wp.addr_buffer_f(32*1-1 DOWNTO 32*0); + WHEN "011000" => prdata <= reg_wp.addr_buffer_f(32*2-1 DOWNTO 32*1); + WHEN "011001" => prdata <= reg_wp.addr_buffer_f(32*3-1 DOWNTO 32*2); + WHEN "011010" => prdata <= reg_wp.addr_buffer_f(32*4-1 DOWNTO 32*3); + WHEN "011011" => prdata <= reg_wp.addr_buffer_f(32*5-1 DOWNTO 32*4); + WHEN "011100" => prdata <= reg_wp.addr_buffer_f(32*6-1 DOWNTO 32*5); + WHEN "011101" => prdata <= reg_wp.addr_buffer_f(32*7-1 DOWNTO 32*6); + WHEN "011110" => prdata <= reg_wp.addr_buffer_f(32*8-1 DOWNTO 32*7); + --ON GOING /\ + WHEN "011111" => prdata(7 DOWNTO 0) <= reg_wp.status_ready_buffer_f; + prdata(11 DOWNTO 8) <= reg_wp.error_buffer_full; + prdata(15 DOWNTO 12) <= reg_wp.status_new_err; + --prdata(3 DOWNTO 0) <= reg_wp.status_full; + -- prdata(7 DOWNTO 4) <= reg_wp.status_full_err; --27 - WHEN "011100" => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_snapshot; + WHEN "100000" => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_snapshot; --28 - WHEN "011101" => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_f0; + WHEN "100001" => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_f0; --29 - WHEN "011110" => prdata(delta_vector_size_f0_2-1 DOWNTO 0) <= reg_wp.delta_f0_2; + WHEN "100010" => prdata(delta_vector_size_f0_2-1 DOWNTO 0) <= reg_wp.delta_f0_2; --30 - WHEN "011111" => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_f1; + WHEN "100011" => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_f1; --31 - WHEN "100000" => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_f2; + WHEN "100100" => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_f2; --32 - WHEN "100001" => prdata(nb_data_by_buffer_size-1 DOWNTO 0) <= reg_wp.nb_data_by_buffer; + WHEN "100101" => prdata(nb_data_by_buffer_size-1 DOWNTO 0) <= reg_wp.nb_data_by_buffer; --33 - WHEN "100010" => prdata(nb_snapshot_param_size-1 DOWNTO 0) <= reg_wp.nb_snapshot_param; + WHEN "100110" => prdata(nb_snapshot_param_size-1 DOWNTO 0) <= reg_wp.nb_snapshot_param; --34 - WHEN "100011" => prdata(30 DOWNTO 0) <= reg_wp.start_date; + WHEN "100111" => prdata(30 DOWNTO 0) <= reg_wp.start_date; --35 - WHEN "100100" => prdata(nb_word_by_buffer_size-1 DOWNTO 0) <= reg_wp.nb_word_by_buffer; + WHEN "101000" => prdata(15 DOWNTO 0) <= reg_wp.time_buffer_f(48*0+15 DOWNTO 48*0); + WHEN "101001" => prdata(31 DOWNTO 0) <= reg_wp.time_buffer_f(48*0+47 DOWNTO 48*0+16); + WHEN "101010" => prdata(15 DOWNTO 0) <= reg_wp.time_buffer_f(48*1+15 DOWNTO 48*1); + WHEN "101011" => prdata(31 DOWNTO 0) <= reg_wp.time_buffer_f(48*1+47 DOWNTO 48*1+16); + WHEN "101100" => prdata(15 DOWNTO 0) <= reg_wp.time_buffer_f(48*2+15 DOWNTO 48*2); + WHEN "101110" => prdata(31 DOWNTO 0) <= reg_wp.time_buffer_f(48*2+47 DOWNTO 48*2+16); + WHEN "101111" => prdata(15 DOWNTO 0) <= reg_wp.time_buffer_f(48*3+15 DOWNTO 48*3); + WHEN "110000" => prdata(31 DOWNTO 0) <= reg_wp.time_buffer_f(48*3+47 DOWNTO 48*3+16); + + WHEN "110001" => prdata(15 DOWNTO 0) <= reg_wp.time_buffer_f(48*4+15 DOWNTO 48*4); + WHEN "111010" => prdata(31 DOWNTO 0) <= reg_wp.time_buffer_f(48*4+47 DOWNTO 48*4+16); + WHEN "110011" => prdata(15 DOWNTO 0) <= reg_wp.time_buffer_f(48*5+15 DOWNTO 48*5); + WHEN "110100" => prdata(31 DOWNTO 0) <= reg_wp.time_buffer_f(48*5+47 DOWNTO 48*5+16); + WHEN "110101" => prdata(15 DOWNTO 0) <= reg_wp.time_buffer_f(48*6+15 DOWNTO 48*6); + WHEN "110110" => prdata(31 DOWNTO 0) <= reg_wp.time_buffer_f(48*6+47 DOWNTO 48*6+16); + WHEN "110111" => prdata(15 DOWNTO 0) <= reg_wp.time_buffer_f(48*7+15 DOWNTO 48*7); + WHEN "111000" => prdata(31 DOWNTO 0) <= reg_wp.time_buffer_f(48*7+47 DOWNTO 48*7+16); + WHEN "111001" => prdata(25 DOWNTO 0) <= reg_wp.length_buffer; + +-- WHEN "100100" => prdata(nb_word_by_buffer_size-1 DOWNTO 0) <= reg_wp.nb_word_by_buffer; ---------------------------------------------------- WHEN "111100" => prdata(23 DOWNTO 0) <= top_lfr_version(23 DOWNTO 0); WHEN OTHERS => NULL; @@ -527,8 +551,8 @@ BEGIN -- beh CASE paddr(7 DOWNTO 2) IS -- WHEN "000000" => reg_sp.config_active_interruption_onNewMatrix <= apbi.pwdata(0); - reg_sp.config_active_interruption_onError <= apbi.pwdata(1); - reg_sp.config_ms_run <= apbi.pwdata(2); + reg_sp.config_active_interruption_onError <= apbi.pwdata(1); + reg_sp.config_ms_run <= apbi.pwdata(2); WHEN "000001" => reg_sp.status_ready_matrix_f0_0 <= ((NOT apbi.pwdata(0) ) AND reg_sp.status_ready_matrix_f0_0 ) OR reg0_ready_matrix_f0; @@ -567,27 +591,39 @@ BEGIN -- beh reg_wp.burst_f2 <= apbi.pwdata(6); reg_wp.run <= apbi.pwdata(7); --22 - WHEN "010111" => reg_wp.addr_data_f0 <= apbi.pwdata; - WHEN "011000" => reg_wp.addr_data_f1 <= apbi.pwdata; - WHEN "011001" => reg_wp.addr_data_f2 <= apbi.pwdata; - WHEN "011010" => reg_wp.addr_data_f3 <= apbi.pwdata; + WHEN "010111" => reg_wp.addr_buffer_f(32*1-1 DOWNTO 32*0) <= apbi.pwdata; + WHEN "011000" => reg_wp.addr_buffer_f(32*2-1 DOWNTO 32*1) <= apbi.pwdata; + WHEN "011001" => reg_wp.addr_buffer_f(32*3-1 DOWNTO 32*2) <= apbi.pwdata; + WHEN "011010" => reg_wp.addr_buffer_f(32*4-1 DOWNTO 32*3) <= apbi.pwdata; + WHEN "011011" => reg_wp.addr_buffer_f(32*5-1 DOWNTO 32*4) <= apbi.pwdata; + WHEN "011100" => reg_wp.addr_buffer_f(32*6-1 DOWNTO 32*5) <= apbi.pwdata; + WHEN "011101" => reg_wp.addr_buffer_f(32*7-1 DOWNTO 32*6) <= apbi.pwdata; + WHEN "011110" => reg_wp.addr_buffer_f(32*8-1 DOWNTO 32*7) <= apbi.pwdata; --26 - WHEN "011011" => reg_wp.status_full <= apbi.pwdata(3 DOWNTO 0); - reg_wp.status_full_err <= apbi.pwdata(7 DOWNTO 4); - reg_wp.status_new_err <= apbi.pwdata(11 DOWNTO 8); - status_full_ack(0) <= reg_wp.status_full(0) AND NOT apbi.pwdata(0); - status_full_ack(1) <= reg_wp.status_full(1) AND NOT apbi.pwdata(1); - status_full_ack(2) <= reg_wp.status_full(2) AND NOT apbi.pwdata(2); - status_full_ack(3) <= reg_wp.status_full(3) AND NOT apbi.pwdata(3); - WHEN "011100" => reg_wp.delta_snapshot <= apbi.pwdata(delta_vector_size-1 DOWNTO 0); - WHEN "011101" => reg_wp.delta_f0 <= apbi.pwdata(delta_vector_size-1 DOWNTO 0); - WHEN "011110" => reg_wp.delta_f0_2 <= apbi.pwdata(delta_vector_size_f0_2-1 DOWNTO 0); - WHEN "011111" => reg_wp.delta_f1 <= apbi.pwdata(delta_vector_size-1 DOWNTO 0); - WHEN "100000" => reg_wp.delta_f2 <= apbi.pwdata(delta_vector_size-1 DOWNTO 0); - WHEN "100001" => reg_wp.nb_data_by_buffer <= apbi.pwdata(nb_data_by_buffer_size-1 DOWNTO 0); - WHEN "100010" => reg_wp.nb_snapshot_param <= apbi.pwdata(nb_snapshot_param_size-1 DOWNTO 0); - WHEN "100011" => reg_wp.start_date <= apbi.pwdata(30 DOWNTO 0); - WHEN "100100" => reg_wp.nb_word_by_buffer <= apbi.pwdata(nb_word_by_buffer_size-1 DOWNTO 0); + WHEN "011111" => + all_reg_wp_status_bit: FOR I IN 3 DOWNTO 0 LOOP + reg_wp.status_ready_buffer_f(I) <= ((NOT apbi.pwdata(I) ) AND reg_wp.status_ready_buffer_f(I) ) OR reg_ready_buffer_f(I); + reg_wp.status_ready_buffer_f(I*2+1) <= ((NOT apbi.pwdata(I*2+1)) AND reg_wp.status_ready_buffer_f(I*2+1)) OR reg_ready_buffer_f(I*2+1); + reg_wp.error_buffer_full(I) <= ((NOT apbi.pwdata(I+8) ) AND reg_wp.error_buffer_full(I) ) OR wfp_error_buffer_full(I); + reg_wp.status_new_err(I) <= ((NOT apbi.pwdata(I+12) ) AND reg_wp.status_new_err(I) ) OR status_new_err(I); + END LOOP all_reg_wp_status_bit; + + WHEN "100000" => reg_wp.delta_snapshot <= apbi.pwdata(delta_vector_size-1 DOWNTO 0); + WHEN "100001" => reg_wp.delta_f0 <= apbi.pwdata(delta_vector_size-1 DOWNTO 0); + WHEN "100010" => reg_wp.delta_f0_2 <= apbi.pwdata(delta_vector_size_f0_2-1 DOWNTO 0); + WHEN "100011" => reg_wp.delta_f1 <= apbi.pwdata(delta_vector_size-1 DOWNTO 0); + WHEN "100100" => reg_wp.delta_f2 <= apbi.pwdata(delta_vector_size-1 DOWNTO 0); + WHEN "100101" => reg_wp.nb_data_by_buffer <= apbi.pwdata(nb_data_by_buffer_size-1 DOWNTO 0); + WHEN "100110" => reg_wp.nb_snapshot_param <= apbi.pwdata(nb_snapshot_param_size-1 DOWNTO 0); + WHEN "100111" => reg_wp.start_date <= apbi.pwdata(30 DOWNTO 0); + + WHEN "111001" => reg_wp.length_buffer <= apbi.pwdata(25 DOWNTO 0); + + + + + +-- WHEN "100100" => reg_wp.nb_word_by_buffer <= apbi.pwdata(nb_word_by_buffer_size-1 DOWNTO 0); -- WHEN OTHERS => NULL; END CASE; @@ -622,7 +658,7 @@ BEGIN -- beh ----------------------------------------------------------------------------- -- IRQ ----------------------------------------------------------------------------- - irq_wfp_reg_s <= status_full & status_full_err & status_new_err; + irq_wfp_reg_s <= wfp_status_buffer_ready & wfp_error_buffer_full & status_new_err; PROCESS (HCLK, HRESETn) BEGIN -- PROCESS @@ -706,16 +742,29 @@ BEGIN -- beh matrix_time => matrix_time_f2); ----------------------------------------------------------------------------- - debug_signal(31 DOWNTO 12) <= (OTHERS => '0'); - debug_signal(11 DOWNTO 0) <= apbo_irq_ms & --11 - reg_sp.status_error_input_fifo_write(2) &--10 - reg_sp.status_error_input_fifo_write(1) &--9 - reg_sp.status_error_input_fifo_write(0) &--8 - reg_sp.status_error_buffer_full & - '0' & --- reg_sp.status_error_bad_component_error & --7 6 - reg_sp.status_ready_matrix_f2_1 & reg_sp.status_ready_matrix_f2_0 &--5 4 - reg_sp.status_ready_matrix_f1_1 & reg_sp.status_ready_matrix_f1_0 &--3 2 - reg_sp.status_ready_matrix_f0_1 & reg_sp.status_ready_matrix_f0_0; --1 0 + all_wfp_pointer: FOR I IN 3 DOWNTO 0 GENERATE + lpp_apbreg_wfp_pointer_fi : lpp_apbreg_ms_pointer + PORT MAP ( + clk => HCLK, + rstn => HRESETn, + + reg0_status_ready_matrix => reg_wp.status_ready_buffer_f(2*I), + reg0_ready_matrix => reg_ready_buffer_f(2*I), + reg0_addr_matrix => reg_wp.addr_buffer_f((2*I+1)*32-1 DOWNTO (2*I)*32), + reg0_matrix_time => reg_wp.time_buffer_f((2*I+1)*48-1 DOWNTO (2*I)*48), + + reg1_status_ready_matrix => reg_wp.status_ready_buffer_f(2*I+1), + reg1_ready_matrix => reg_ready_buffer_f(2*I+1), + reg1_addr_matrix => reg_wp.addr_buffer_f((2*I+2)*32-1 DOWNTO (2*I+1)*32), + reg1_matrix_time => reg_wp.time_buffer_f((2*I+2)*48-1 DOWNTO (2*I+1)*48), + + ready_matrix => wfp_ready_buffer(I), + status_ready_matrix => wfp_status_buffer_ready(I), + addr_matrix => wfp_addr_buffer((I+1)*32-1 DOWNTO I*32), + matrix_time => wfp_buffer_time((I+1)*48-1 DOWNTO I*48) + ); + + END GENERATE all_wfp_pointer; + ----------------------------------------------------------------------------- -END beh; +END beh; \ No newline at end of file diff --git a/lib/lpp/lpp_top_lfr/lpp_lfr_pkg.vhd b/lib/lpp/lpp_top_lfr/lpp_lfr_pkg.vhd --- a/lib/lpp/lpp_top_lfr/lpp_lfr_pkg.vhd +++ b/lib/lpp/lpp_top_lfr/lpp_lfr_pkg.vhd @@ -258,7 +258,6 @@ PACKAGE lpp_lfr_pkg IS COMPONENT lpp_lfr_apbreg GENERIC ( nb_data_by_buffer_size : INTEGER; - nb_word_by_buffer_size : INTEGER; nb_snapshot_param_size : INTEGER; delta_vector_size : INTEGER; delta_vector_size_f0_2 : INTEGER; @@ -269,60 +268,57 @@ PACKAGE lpp_lfr_pkg IS pirq_wfp : INTEGER; top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0)); PORT ( - HCLK : IN STD_ULOGIC; - HRESETn : IN STD_ULOGIC; - apbi : IN apb_slv_in_type; - apbo : OUT apb_slv_out_type; - run_ms : OUT STD_LOGIC; - ready_matrix_f0 : IN STD_LOGIC; - ready_matrix_f1 : IN STD_LOGIC; - ready_matrix_f2 : IN STD_LOGIC; - error_buffer_full : IN STD_LOGIC; - error_input_fifo_write : IN STD_LOGIC_VECTOR(2 DOWNTO 0); - status_ready_matrix_f0 : OUT STD_LOGIC; - status_ready_matrix_f1 : OUT STD_LOGIC; - status_ready_matrix_f2 : OUT STD_LOGIC; - addr_matrix_f0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); - addr_matrix_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); - addr_matrix_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); - length_matrix_f0 : OUT STD_LOGIC_VECTOR(25 DOWNTO 0); - length_matrix_f1 : OUT STD_LOGIC_VECTOR(25 DOWNTO 0); - length_matrix_f2 : OUT STD_LOGIC_VECTOR(25 DOWNTO 0); - matrix_time_f0 : IN STD_LOGIC_VECTOR(47 DOWNTO 0); - matrix_time_f1 : IN STD_LOGIC_VECTOR(47 DOWNTO 0); - matrix_time_f2 : IN STD_LOGIC_VECTOR(47 DOWNTO 0); - status_full : IN STD_LOGIC_VECTOR(3 DOWNTO 0); - status_full_ack : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); - status_full_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0); - status_new_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0); - data_shaping_BW : OUT STD_LOGIC; - data_shaping_SP0 : OUT STD_LOGIC; - data_shaping_SP1 : OUT STD_LOGIC; - data_shaping_R0 : OUT STD_LOGIC; - data_shaping_R1 : OUT STD_LOGIC; - data_shaping_R2 : OUT STD_LOGIC; - delta_snapshot : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); - delta_f0 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); - delta_f0_2 : OUT STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0); - delta_f1 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); - delta_f2 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); - nb_data_by_buffer : OUT STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0); - nb_word_by_buffer : OUT STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0); - nb_snapshot_param : OUT STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0); - enable_f0 : OUT STD_LOGIC; - enable_f1 : OUT STD_LOGIC; - enable_f2 : OUT STD_LOGIC; - enable_f3 : OUT STD_LOGIC; - burst_f0 : OUT STD_LOGIC; - burst_f1 : OUT STD_LOGIC; - burst_f2 : OUT STD_LOGIC; - run : OUT STD_LOGIC; - addr_data_f0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); - addr_data_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); - addr_data_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); - addr_data_f3 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); - start_date : OUT STD_LOGIC_VECTOR(30 DOWNTO 0); - debug_signal : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)); + HCLK : IN STD_ULOGIC; + HRESETn : IN STD_ULOGIC; + apbi : IN apb_slv_in_type; + apbo : OUT apb_slv_out_type; + run_ms : OUT STD_LOGIC; + ready_matrix_f0 : IN STD_LOGIC; + ready_matrix_f1 : IN STD_LOGIC; + ready_matrix_f2 : IN STD_LOGIC; + error_buffer_full : IN STD_LOGIC; + error_input_fifo_write : IN STD_LOGIC_VECTOR(2 DOWNTO 0); + status_ready_matrix_f0 : OUT STD_LOGIC; + status_ready_matrix_f1 : OUT STD_LOGIC; + status_ready_matrix_f2 : OUT STD_LOGIC; + addr_matrix_f0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + addr_matrix_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + addr_matrix_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + length_matrix_f0 : OUT STD_LOGIC_VECTOR(25 DOWNTO 0); + length_matrix_f1 : OUT STD_LOGIC_VECTOR(25 DOWNTO 0); + length_matrix_f2 : OUT STD_LOGIC_VECTOR(25 DOWNTO 0); + matrix_time_f0 : IN STD_LOGIC_VECTOR(47 DOWNTO 0); + matrix_time_f1 : IN STD_LOGIC_VECTOR(47 DOWNTO 0); + matrix_time_f2 : IN STD_LOGIC_VECTOR(47 DOWNTO 0); + status_new_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0); + data_shaping_BW : OUT STD_LOGIC; + data_shaping_SP0 : OUT STD_LOGIC; + data_shaping_SP1 : OUT STD_LOGIC; + data_shaping_R0 : OUT STD_LOGIC; + data_shaping_R1 : OUT STD_LOGIC; + data_shaping_R2 : OUT STD_LOGIC; + delta_snapshot : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); + delta_f0 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); + delta_f0_2 : OUT STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0); + delta_f1 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); + delta_f2 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); + nb_data_by_buffer : OUT STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0); + nb_snapshot_param : OUT STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0); + enable_f0 : OUT STD_LOGIC; + enable_f1 : OUT STD_LOGIC; + enable_f2 : OUT STD_LOGIC; + enable_f3 : OUT STD_LOGIC; + burst_f0 : OUT STD_LOGIC; + burst_f1 : OUT STD_LOGIC; + burst_f2 : OUT STD_LOGIC; + run : OUT STD_LOGIC; + start_date : OUT STD_LOGIC_VECTOR(30 DOWNTO 0); + wfp_status_buffer_ready : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + wfp_addr_buffer : OUT STD_LOGIC_VECTOR(32*4 DOWNTO 0); + wfp_length_buffer : OUT STD_LOGIC_VECTOR(25 DOWNTO 0); + wfp_ready_buffer : IN STD_LOGIC_VECTOR(3 DOWNTO 0); + wfp_buffer_time : IN STD_LOGIC_VECTOR(48*4-1 DOWNTO 0); + wfp_error_buffer_full : IN STD_LOGIC_VECTOR(3 DOWNTO 0)); END COMPONENT; COMPONENT lpp_top_ms diff --git a/lib/lpp/lpp_waveform/lpp_waveform.vhd b/lib/lpp/lpp_waveform/lpp_waveform.vhd --- a/lib/lpp/lpp_waveform/lpp_waveform.vhd +++ b/lib/lpp/lpp_waveform/lpp_waveform.vhd @@ -44,7 +44,7 @@ ENTITY lpp_waveform IS tech : INTEGER := inferred; data_size : INTEGER := 96; --16*6 nb_data_by_buffer_size : INTEGER := 11; - nb_word_by_buffer_size : INTEGER := 11; +-- nb_word_by_buffer_size : INTEGER := 11; nb_snapshot_param_size : INTEGER := 11; delta_vector_size : INTEGER := 20; delta_vector_size_f0_2 : INTEGER := 3); @@ -76,31 +76,36 @@ ENTITY lpp_waveform IS burst_f2 : IN STD_LOGIC; nb_data_by_buffer : IN STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0); - nb_word_by_buffer : IN STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0); +-- nb_word_by_buffer : IN STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0); nb_snapshot_param : IN STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0); - status_full : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); - status_full_ack : IN STD_LOGIC_VECTOR(3 DOWNTO 0); - status_full_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + status_new_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); -- New data f(i) before the current data is write by dma + + + -- REG DMA + status_buffer_ready : IN STD_LOGIC_VECTOR(3 DOWNTO 0); + addr_buffer : IN STD_LOGIC_VECTOR(32*4 DOWNTO 0); + length_buffer : IN STD_LOGIC_VECTOR(25 DOWNTO 0); + + ready_buffer : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + buffer_time : OUT STD_LOGIC_VECTOR(48*4-1 DOWNTO 0); + error_buffer_full : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + --------------------------------------------------------------------------- -- INPUT coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); --f0 - addr_data_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); data_f0_in_valid : IN STD_LOGIC; data_f0_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); --f1 - addr_data_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); data_f1_in_valid : IN STD_LOGIC; data_f1_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); --f2 - addr_data_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); data_f2_in_valid : IN STD_LOGIC; data_f2_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); --f3 - addr_data_f3 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); data_f3_in_valid : IN STD_LOGIC; data_f3_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); @@ -110,7 +115,7 @@ ENTITY lpp_waveform IS dma_fifo_valid_burst : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); dma_fifo_data : OUT STD_LOGIC_VECTOR(32*4-1 DOWNTO 0); dma_fifo_ren : IN STD_LOGIC_VECTOR(3 DOWNTO 0); - dma_buffer_new : IN STD_LOGIC_VECTOR(3 DOWNTO 0); + dma_buffer_new : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); dma_buffer_addr : OUT STD_LOGIC_VECTOR(32*4-1 DOWNTO 0); dma_buffer_length : OUT STD_LOGIC_VECTOR(26*4-1 DOWNTO 0); dma_buffer_full : IN STD_LOGIC_VECTOR(3 DOWNTO 0); @@ -178,9 +183,10 @@ ARCHITECTURE beh OF lpp_waveform IS SIGNAL s_rdata_v : STD_LOGIC_VECTOR(32*4-1 DOWNTO 0); -- + SIGNAL arbiter_time_out : STD_LOGIC_VECTOR(47 DOWNTO 0); + SIGNAL arbiter_time_out_new : STD_LOGIC_VECTOR(3 DOWNTO 0); - SIGNAL status_full_s : STD_LOGIC_VECTOR(3 DOWNTO 0); - + SIGNAL fifo_buffer_time : STD_LOGIC_VECTOR(48*4-1 DOWNTO 0); BEGIN -- beh @@ -357,19 +363,6 @@ BEGIN -- beh END GENERATE all_sample_of_time_out; END GENERATE all_bit_of_time_out; - -- DEBUG -- - --time_out_debug(0) <= x"0A0A" & x"0A0A0A0A"; - --time_out_debug(1) <= x"1B1B" & x"1B1B1B1B"; - --time_out_debug(2) <= x"2C2C" & x"2C2C2C2C"; - --time_out_debug(3) <= x"3D3D" & x"3D3D3D3D"; - - --all_bit_of_time_out : FOR I IN 47 DOWNTO 0 GENERATE - -- all_sample_of_time_out : FOR J IN 3 DOWNTO 0 GENERATE - -- time_out_2(J, I) <= time_out_debug(J)(I); - -- END GENERATE all_sample_of_time_out; - --END GENERATE all_bit_of_time_out; - -- DEBUG -- - lpp_waveform_fifo_arbiter_1 : lpp_waveform_fifo_arbiter GENERIC MAP (tech => tech, nb_data_by_buffer_size => nb_data_by_buffer_size) @@ -386,62 +379,16 @@ BEGIN -- beh data_out => wdata, data_out_wen => data_wen, full_almost => full_almost, - full => full); + full => full, + + time_out => arbiter_time_out, + time_out_new => arbiter_time_out_new + + ); ----------------------------------------------------------------------------- - -- DEBUG -- SNAPSHOT IN - --debug_f0_data_fifo_in_valid <= NOT data_wen(0); - --debug_f0_data_fifo_in <= wdata; - --debug_f1_data_fifo_in_valid <= NOT data_wen(1); - --debug_f1_data_fifo_in <= wdata; - --debug_f2_data_fifo_in_valid <= NOT data_wen(2); - --debug_f2_data_fifo_in <= wdata; - --debug_f3_data_fifo_in_valid <= NOT data_wen(3); - --debug_f3_data_fifo_in <= wdata;s ----------------------------------------------------------------------------- - - -- lpp_fifo_4_shared_1: lpp_fifo_4_shared - -- GENERIC MAP ( - -- tech => tech, - -- Mem_use => use_RAM, - -- EMPTY_ALMOST_LIMIT => 16, - -- FULL_ALMOST_LIMIT => 5, - -- DataSz => 32, - -- AddrSz => 7 - -- ) - -- PORT MAP ( - -- clk => clk, - -- rstn => rstn, - -- run => run, - -- empty_almost => s_empty_almost, - -- empty => s_empty, - -- r_en => s_data_ren, - -- r_data => s_rdata, - -- full_almost => full_almost, - -- full => full, - -- w_en => data_wen, - -- w_data => wdata); - - --lpp_waveform_fifo_headreg_1 : lpp_fifo_4_shared_headreg_latency_1 - -- PORT MAP ( - -- clk => clk, - -- rstn => rstn, - -- run => run, - -- o_empty_almost => empty_almost, - -- o_empty => empty, - - -- o_data_ren => data_ren, - -- o_rdata_0 => data_f0_data_out, - -- o_rdata_1 => data_f1_data_out, - -- o_rdata_2 => data_f2_data_out, - -- o_rdata_3 => data_f3_data_out, - - -- i_empty_almost => s_empty_almost, - -- i_empty => s_empty, - -- i_data_ren => s_data_ren, - -- i_rdata => s_rdata); - generate_all_fifo: FOR I IN 0 TO 3 GENERATE lpp_fifo_1: lpp_fifo GENERIC MAP ( @@ -468,86 +415,34 @@ BEGIN -- beh END GENERATE generate_all_fifo; - - ----empty <= s_empty; - ----empty_almost <= s_empty_almost; - ----s_data_ren <= data_ren; - - --data_f0_data_out <= s_rdata_v(31 downto 0); - --data_f1_data_out <= s_rdata_v(31+32 downto 0+32); - --data_f2_data_out <= s_rdata_v(31+32*2 downto 32*2); - --data_f3_data_out <= s_rdata_v(31+32*3 downto 32*3); - - --data_ren <= data_f3_data_out_ren & - -- data_f2_data_out_ren & - -- data_f1_data_out_ren & - -- data_f0_data_out_ren; - - --lpp_waveform_gen_address_1 : lpp_waveform_genaddress - -- GENERIC MAP ( - -- nb_data_by_buffer_size => nb_word_by_buffer_size) - -- PORT MAP ( - -- clk => clk, - -- rstn => rstn, - -- run => run, - - -- ------------------------------------------------------------------------- - -- -- CONFIG - -- ------------------------------------------------------------------------- - -- nb_data_by_buffer => nb_word_by_buffer, - - -- addr_data_f0 => addr_data_f0, - -- addr_data_f1 => addr_data_f1, - -- addr_data_f2 => addr_data_f2, - -- addr_data_f3 => addr_data_f3, - -- ------------------------------------------------------------------------- - -- -- CTRL - -- ------------------------------------------------------------------------- - -- -- IN - -- empty => empty, - -- empty_almost => empty_almost, - -- data_ren => data_ren, - - -- ------------------------------------------------------------------------- - -- -- STATUS - -- ------------------------------------------------------------------------- - -- status_full => status_full_s, - -- status_full_ack => status_full_ack, - -- status_full_err => status_full_err, - - -- ------------------------------------------------------------------------- - -- -- ADDR DATA OUT - -- ------------------------------------------------------------------------- - -- data_f0_data_out_valid_burst => data_f0_data_out_valid_burst, - -- data_f1_data_out_valid_burst => data_f1_data_out_valid_burst, - -- data_f2_data_out_valid_burst => data_f2_data_out_valid_burst, - -- data_f3_data_out_valid_burst => data_f3_data_out_valid_burst, - - -- data_f0_data_out_valid => data_f0_data_out_valid, - -- data_f1_data_out_valid => data_f1_data_out_valid, - -- data_f2_data_out_valid => data_f2_data_out_valid, - -- data_f3_data_out_valid => data_f3_data_out_valid, - - -- data_f0_addr_out => data_f0_addr_out, - -- data_f1_addr_out => data_f1_addr_out, - -- data_f2_addr_out => data_f2_addr_out, - -- data_f3_addr_out => data_f3_addr_out - -- ); - --status_full <= status_full_s; - - ----------------------------------------------------------------------------- -- ----------------------------------------------------------------------------- all_channel: FOR I IN 3 DOWNTO 0 GENERATE + + PROCESS (clk, rstn) + BEGIN + IF rstn = '0' THEN + fifo_buffer_time(48*(I+1)-1 DOWNTO 48*I) <= (OTHERS => '0'); + ELSIF clk'event AND clk = '1' THEN + IF run = '0' THEN + fifo_buffer_time(48*(I+1)-1 DOWNTO 48*I) <= (OTHERS => '0'); + ELSE + IF arbiter_time_out_new(I) = '0' THEN + fifo_buffer_time(48*(I+1)-1 DOWNTO 48*I) <= arbiter_time_out; + END IF; + END IF; + END IF; + END PROCESS; + lpp_waveform_fsmdma_I: lpp_waveform_fsmdma PORT MAP ( clk => clk, rstn => rstn, run => run, - fifo_buffer_time => fifo_buffer_time(48*(I+1)-1 DOWNTO 48*I), -- TODO + fifo_buffer_time => fifo_buffer_time(48*(I+1)-1 DOWNTO 48*I), fifo_data => s_rdata_v(32*(I+1)-1 DOWNTO 32*I), fifo_empty => empty(I), @@ -565,7 +460,7 @@ BEGIN -- beh status_buffer_ready => status_buffer_ready(I), -- TODO addr_buffer => addr_buffer(32*(I+1)-1 DOWNTO 32*I), -- TODO - length_buffer => length_buffer(26*(I+1)-1 DOWNTO 26*I), -- TODO + length_buffer => length_buffer,--(26*(I+1)-1 DOWNTO 26*I), -- TODO ready_buffer => ready_buffer(I), -- TODO buffer_time => buffer_time(48*(I+1)-1 DOWNTO 48*I), -- TODO error_buffer_full => error_buffer_full(I)); -- TODO diff --git a/lib/lpp/lpp_waveform/lpp_waveform_dma_genvalid.vhd b/lib/lpp/lpp_waveform/lpp_waveform_dma_genvalid.vhd --- a/lib/lpp/lpp_waveform/lpp_waveform_dma_genvalid.vhd +++ b/lib/lpp/lpp_waveform/lpp_waveform_dma_genvalid.vhd @@ -37,7 +37,7 @@ ENTITY lpp_waveform_dma_genvalid IS valid_in : IN STD_LOGIC; time_in : IN STD_LOGIC_VECTOR(47 DOWNTO 0); - ack_in : IN STD_LOGIC; + ack_in : IN STD_LOGIC; valid_out : OUT STD_LOGIC; time_out : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); error : OUT STD_LOGIC @@ -55,25 +55,21 @@ BEGIN state <= IDLE; valid_out <= '0'; error <= '0'; - time_out <= (OTHERS => '0'); + time_out <= (OTHERS => '0'); ELSIF HCLK'EVENT AND HCLK = '1' THEN - CASE state IS - WHEN IDLE => - - valid_out <= '0'; - error <= '0'; - IF run = '1' AND valid_in = '1' THEN - state <= VALID; - valid_out <= '1'; + IF run = '1' THEN + CASE state IS + WHEN IDLE => + + valid_out <= valid_in; + error <= '0'; time_out <= time_in; - END IF; - WHEN VALID => - IF run = '0' THEN - state <= IDLE; - valid_out <= '0'; - error <= '0'; - ELSE + IF valid_in = '1' THEN + state <= VALID; + END IF; + + WHEN VALID => IF valid_in = '1' THEN IF ack_in = '1' THEN state <= VALID; @@ -88,10 +84,16 @@ BEGIN state <= IDLE; valid_out <= '0'; END IF; - END IF; - - WHEN OTHERS => NULL; - END CASE; + + WHEN OTHERS => NULL; + END CASE; + + ELSE + state <= IDLE; + valid_out <= '0'; + error <= '0'; + time_out <= (OTHERS => '0'); + END IF; END IF; END PROCESS FSM_SELECT_ADDRESS; diff --git a/lib/lpp/lpp_waveform/lpp_waveform_fifo_arbiter.vhd b/lib/lpp/lpp_waveform/lpp_waveform_fifo_arbiter.vhd --- a/lib/lpp/lpp_waveform/lpp_waveform_fifo_arbiter.vhd +++ b/lib/lpp/lpp_waveform/lpp_waveform_fifo_arbiter.vhd @@ -44,6 +44,7 @@ ENTITY lpp_waveform_fifo_arbiter IS data_in_valid : IN STD_LOGIC_VECTOR(3 DOWNTO 0); data_in_ack : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); data_in : IN Data_Vector(3 DOWNTO 0, 95 DOWNTO 0); + time_in : IN Data_Vector(3 DOWNTO 0, 47 DOWNTO 0); --------------------------------------------------------------------------- @@ -52,29 +53,31 @@ ENTITY lpp_waveform_fifo_arbiter IS data_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); data_out_wen : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); full_almost : IN STD_LOGIC_VECTOR(3 DOWNTO 0); - full : IN STD_LOGIC_VECTOR(3 DOWNTO 0) + full : IN STD_LOGIC_VECTOR(3 DOWNTO 0); + + --------------------------------------------------------------------------- + -- TIME INTERFACE (OUTPUT) + --------------------------------------------------------------------------- + time_out : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); + time_out_new : OUT STD_LOGIC_VECTOR(3 DOWNTO 0) ); END ENTITY; ARCHITECTURE ar_lpp_waveform_fifo_arbiter OF lpp_waveform_fifo_arbiter IS - TYPE state_type_fifo_arbiter IS (IDLE,TIME1,TIME2,DATA1,DATA2,DATA3,LAST); + TYPE state_type_fifo_arbiter IS (IDLE,DATA1,DATA2,DATA3,LAST); SIGNAL state : state_type_fifo_arbiter; ----------------------------------------------------------------------------- -- DATA MUX ----------------------------------------------------------------------------- - SIGNAL data_0_v : STD_LOGIC_VECTOR(32*5-1 DOWNTO 0); - SIGNAL data_1_v : STD_LOGIC_VECTOR(32*5-1 DOWNTO 0); - SIGNAL data_2_v : STD_LOGIC_VECTOR(32*5-1 DOWNTO 0); - SIGNAL data_3_v : STD_LOGIC_VECTOR(32*5-1 DOWNTO 0); TYPE WORD_VECTOR IS ARRAY (NATURAL RANGE <>) OF STD_LOGIC_VECTOR(31 DOWNTO 0); - SIGNAL data_0 : WORD_VECTOR(4 DOWNTO 0); - SIGNAL data_1 : WORD_VECTOR(4 DOWNTO 0); - SIGNAL data_2 : WORD_VECTOR(4 DOWNTO 0); - SIGNAL data_3 : WORD_VECTOR(4 DOWNTO 0); - SIGNAL data_sel : WORD_VECTOR(4 DOWNTO 0); + SIGNAL data_0 : WORD_VECTOR(3 DOWNTO 0); + SIGNAL data_1 : WORD_VECTOR(3 DOWNTO 0); + SIGNAL data_2 : WORD_VECTOR(3 DOWNTO 0); + SIGNAL data_3 : WORD_VECTOR(3 DOWNTO 0); + SIGNAL data_sel : WORD_VECTOR(3 DOWNTO 0); ----------------------------------------------------------------------------- -- RR and SELECTION @@ -92,14 +95,8 @@ ARCHITECTURE ar_lpp_waveform_fifo_arbite SIGNAL count_enable : STD_LOGIC; SIGNAL count : STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0); SIGNAL count_s : STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0); - - --SIGNAL shift_data_enable : STD_LOGIC; - --SIGNAL shift_data : STD_LOGIC_VECTOR(1 DOWNTO 0); - --SIGNAL shift_data_s : STD_LOGIC_VECTOR(1 DOWNTO 0); - - --SIGNAL shift_time_enable : STD_LOGIC; - --SIGNAL shift_time : STD_LOGIC_VECTOR(1 DOWNTO 0); - --SIGNAL shift_time_s : STD_LOGIC_VECTOR(1 DOWNTO 0); + + SIGNAL time_sel : STD_LOGIC_VECTOR(47 DOWNTO 0); BEGIN @@ -113,44 +110,40 @@ BEGIN data_in_ack <= (OTHERS => '0'); data_out_wen <= (OTHERS => '1'); sel_ack <= '0'; - state <= IDLE; + state <= IDLE; + time_out <= (OTHERS => '0'); + time_out_new <= (OTHERS => '0'); ELSIF clk'event AND clk = '1' THEN -- rising clock edge count_enable <= '0'; data_in_ack <= (OTHERS => '0'); data_out_wen <= (OTHERS => '1'); sel_ack <= '0'; + time_out_new <= (OTHERS => '0'); IF run = '0' THEN state <= IDLE; + time_out <= (OTHERS => '0'); ELSE CASE state IS WHEN IDLE => IF no_sel = '0' THEN - state <= TIME1; + state <= DATA1; END IF; - WHEN TIME1 => + WHEN DATA1 => count_enable <= '1'; IF UNSIGNED(count) = 0 THEN - state <= TIME2; - data_out_wen <= NOT sel; - data_out <= data_sel(0); - ELSE - state <= DATA1; + time_out <= time_sel; + time_out_new <= sel; END IF; - WHEN TIME2 => data_out_wen <= NOT sel; - data_out <= data_sel(1) ; - state <= DATA1; - WHEN DATA1 => - data_out_wen <= NOT sel; - data_out <= data_sel(2); + data_out <= data_sel(0); state <= DATA2; WHEN DATA2 => data_out_wen <= NOT sel; - data_out <= data_sel(3); + data_out <= data_sel(1); state <= DATA3; WHEN DATA3 => data_out_wen <= NOT sel; - data_out <= data_sel(4); + data_out <= data_sel(2); state <= LAST; data_in_ack <= sel; WHEN LAST => @@ -163,101 +156,17 @@ BEGIN END IF; END PROCESS; ----------------------------------------------------------------------------- - - - --PROCESS (clk, rstn) - --BEGIN -- PROCESS - -- IF rstn = '0' THEN -- asynchronous reset (active low) - -- count_enable <= '0'; - -- shift_time_enable <= '0'; - -- shift_data_enable <= '0'; - -- data_in_ack <= (OTHERS => '0'); - -- data_out_wen <= (OTHERS => '1'); - -- sel_ack <= '0'; - -- ELSIF clk'event AND clk = '1' THEN -- rising clock edge - -- IF run = '0' OR no_sel = '1' THEN - -- count_enable <= '0'; - -- shift_time_enable <= '0'; - -- shift_data_enable <= '0'; - -- data_in_ack <= (OTHERS => '0'); - -- data_out_wen <= (OTHERS => '1'); - -- sel_ack <= '0'; - -- ELSE - -- --COUNT - -- IF shift_data_s = "10" THEN - -- count_enable <= '1'; - -- ELSE - -- count_enable <= '0'; - -- END IF; - -- --DATA - -- IF shift_time_s = "10" THEN - -- shift_data_enable <= '1'; - -- ELSE - -- shift_data_enable <= '0'; - -- END IF; - - -- --TIME - -- IF ((shift_data_s = "10") AND (count = nb_data_by_buffer)) OR - -- shift_time_s = "00" OR - -- shift_time_s = "01" - -- THEN - -- shift_time_enable <= '1'; - -- ELSE - -- shift_time_enable <= '0'; - -- END IF; - - -- --ACK - -- IF shift_data_s = "10" THEN - -- data_in_ack <= sel; - -- sel_ack <= '1'; - -- ELSE - -- data_in_ack <= (OTHERS => '0'); - -- sel_ack <= '0'; - -- END IF; - - -- --VALID OUT - -- all_wen: FOR I IN 3 DOWNTO 0 LOOP - -- IF sel(I) = '1' AND count_enable = '0' THEN - -- data_out_wen(I) <= '0'; - -- ELSE - -- data_out_wen(I) <= '1'; - -- END IF; - -- END LOOP all_wen; - - -- END IF; - -- END IF; - --END PROCESS; ----------------------------------------------------------------------------- -- DATA MUX ----------------------------------------------------------------------------- - all_bit_data_in: FOR I IN 32*5-1 DOWNTO 0 GENERATE - I_time_in: IF I < 48 GENERATE - data_0_v(I) <= time_in(0,I); - data_1_v(I) <= time_in(1,I); - data_2_v(I) <= time_in(2,I); - data_3_v(I) <= time_in(3,I); - END GENERATE I_time_in; - I_null: IF (I > 47) AND (I < 32*2) GENERATE - data_0_v(I) <= '0'; - data_1_v(I) <= '0'; - data_2_v(I) <= '0'; - data_3_v(I) <= '0'; - END GENERATE I_null; - I_data_in: IF I > 32*2-1 GENERATE - data_0_v(I) <= data_in(0,I-32*2); - data_1_v(I) <= data_in(1,I-32*2); - data_2_v(I) <= data_in(2,I-32*2); - data_3_v(I) <= data_in(3,I-32*2); - END GENERATE I_data_in; - END GENERATE all_bit_data_in; - all_word: FOR J IN 4 DOWNTO 0 GENERATE + all_word: FOR J IN 2 DOWNTO 0 GENERATE all_data_bit: FOR I IN 31 DOWNTO 0 GENERATE - data_0(J)(I) <= data_0_v(J*32+I); - data_1(J)(I) <= data_1_v(J*32+I); - data_2(J)(I) <= data_2_v(J*32+I); - data_3(J)(I) <= data_3_v(J*32+I); + data_0(J)(I) <= data_in(0,I+32*J); + data_1(J)(I) <= data_in(1,I+32*J); + data_2(J)(I) <= data_in(2,I+32*J); + data_3(J)(I) <= data_in(3,I+32*J); END GENERATE all_data_bit; END GENERATE all_word; @@ -266,18 +175,18 @@ BEGIN data_2 WHEN sel(2) = '1' ELSE data_3; - --data_out <= data_sel(0) WHEN shift_time = "00" ELSE - -- data_sel(1) WHEN shift_time = "01" ELSE - -- data_sel(2) WHEN shift_data = "00" ELSE - -- data_sel(3) WHEN shift_data = "01" ELSE - -- data_sel(4); + all_time_bit: FOR I IN 3 DOWNTO 0 GENERATE + time_sel(I) <= time_in(0,I) WHEN sel(0) = '1' ELSE + time_in(1,I) WHEN sel(1) = '1' ELSE + time_in(2,I) WHEN sel(2) = '1' ELSE + time_in(3,I); + END GENERATE all_time_bit; ----------------------------------------------------------------------------- -- RR and SELECTION ----------------------------------------------------------------------------- all_input_rr : FOR I IN 3 DOWNTO 0 GENERATE --- valid_in_rr(I) <= data_in_valid(I) AND NOT full(I); valid_in_rr(I) <= data_in_valid(I) AND NOT full_almost(I); END GENERATE all_input_rr; @@ -286,9 +195,7 @@ BEGIN clk => clk, rstn => rstn, in_valid => valid_in_rr, - out_grant => sel_s); --sel_s); - --- sel <= sel_s; + out_grant => sel_s); PROCESS (clk, rstn) BEGIN -- PROCESS @@ -296,14 +203,7 @@ BEGIN sel <= "0000"; sel_reg <= '0'; ELSIF clk'event AND clk = '1' THEN -- rising clock edge - -- sel_reg - -- sel_ack - -- sel_s - -- sel = "0000 " - --sel <= sel_s; - IF sel_reg = '0' OR sel_ack = '1' - --OR shift_data_s = "10" - THEN + IF sel_reg = '0' OR sel_ack = '1' THEN sel <= sel_s; IF sel_s = "0000" THEN sel_reg <= '0'; @@ -332,35 +232,6 @@ BEGIN sel => sel, data => count, data_s => count_s); - - --reg_shift_data_i: lpp_waveform_fifo_arbiter_reg - -- GENERIC MAP ( - -- data_size => 2, - -- data_nb => 4) - -- PORT MAP ( - -- clk => clk, - -- rstn => rstn, - -- run => run, - -- max_count => "10", -- 2 - -- enable => shift_data_enable, - -- sel => sel, - -- data => shift_data, - -- data_s => shift_data_s); - - - --reg_shift_time_i: lpp_waveform_fifo_arbiter_reg - -- GENERIC MAP ( - -- data_size => 2, - -- data_nb => 4) - -- PORT MAP ( - -- clk => clk, - -- rstn => rstn, - -- run => run, - -- max_count => "10", -- 2 - -- enable => shift_time_enable, - -- sel => sel, - -- data => shift_time, - -- data_s => shift_time_s); @@ -391,4 +262,3 @@ END ARCHITECTURE; - diff --git a/lib/lpp/lpp_waveform/lpp_waveform_pkg.vhd b/lib/lpp/lpp_waveform/lpp_waveform_pkg.vhd --- a/lib/lpp/lpp_waveform/lpp_waveform_pkg.vhd +++ b/lib/lpp/lpp_waveform/lpp_waveform_pkg.vhd @@ -105,7 +105,6 @@ PACKAGE lpp_waveform_pkg IS tech : INTEGER; data_size : INTEGER; nb_data_by_buffer_size : INTEGER; - nb_word_by_buffer_size : INTEGER; nb_snapshot_param_size : INTEGER; delta_vector_size : INTEGER; delta_vector_size_f0_2 : INTEGER); @@ -127,24 +126,22 @@ PACKAGE lpp_waveform_pkg IS burst_f1 : IN STD_LOGIC; burst_f2 : IN STD_LOGIC; nb_data_by_buffer : IN STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0); - nb_word_by_buffer : IN STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0); nb_snapshot_param : IN STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0); - status_full : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); - status_full_ack : IN STD_LOGIC_VECTOR(3 DOWNTO 0); - status_full_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); status_new_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + status_buffer_ready : IN STD_LOGIC_VECTOR(3 DOWNTO 0); + addr_buffer : IN STD_LOGIC_VECTOR(32*4 DOWNTO 0); + length_buffer : IN STD_LOGIC_VECTOR(25 DOWNTO 0); + ready_buffer : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + buffer_time : OUT STD_LOGIC_VECTOR(48*4-1 DOWNTO 0); + error_buffer_full : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); - addr_data_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); data_f0_in_valid : IN STD_LOGIC; data_f0_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); - addr_data_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); data_f1_in_valid : IN STD_LOGIC; data_f1_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); - addr_data_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); data_f2_in_valid : IN STD_LOGIC; data_f2_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); - addr_data_f3 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); data_f3_in_valid : IN STD_LOGIC; data_f3_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); data_f0_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); @@ -167,27 +164,15 @@ PACKAGE lpp_waveform_pkg IS data_f3_data_out_valid : OUT STD_LOGIC; data_f3_data_out_valid_burst : OUT STD_LOGIC; data_f3_data_out_ren : IN STD_LOGIC; - - --debug - observation_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) - --debug_f0_data : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); - --debug_f0_data_valid : OUT STD_LOGIC; - --debug_f1_data : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); - --debug_f1_data_valid : OUT STD_LOGIC; - --debug_f2_data : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); - --debug_f2_data_valid : OUT STD_LOGIC; - --debug_f3_data : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); - --debug_f3_data_valid : OUT STD_LOGIC; - - ----debug FIFO IN - --debug_f0_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); - --debug_f0_data_fifo_in_valid : OUT STD_LOGIC; - --debug_f1_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); - --debug_f1_data_fifo_in_valid : OUT STD_LOGIC; - --debug_f2_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); - --debug_f2_data_fifo_in_valid : OUT STD_LOGIC; - --debug_f3_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); - --debug_f3_data_fifo_in_valid : OUT STD_LOGIC + + dma_fifo_valid_burst : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + dma_fifo_data : OUT STD_LOGIC_VECTOR(32*4-1 DOWNTO 0); + dma_fifo_ren : IN STD_LOGIC_VECTOR(3 DOWNTO 0); + dma_buffer_new : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + dma_buffer_addr : OUT STD_LOGIC_VECTOR(32*4-1 DOWNTO 0); + dma_buffer_length : OUT STD_LOGIC_VECTOR(26*4-1 DOWNTO 0); + dma_buffer_full : IN STD_LOGIC_VECTOR(3 DOWNTO 0); + dma_buffer_full_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0) ); END COMPONENT; @@ -243,7 +228,10 @@ PACKAGE lpp_waveform_pkg IS data_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); data_out_wen : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); full_almost : IN STD_LOGIC_VECTOR(3 DOWNTO 0); - full : IN STD_LOGIC_VECTOR(3 DOWNTO 0)); + full : IN STD_LOGIC_VECTOR(3 DOWNTO 0); + time_out : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); + time_out_new : OUT STD_LOGIC_VECTOR(3 DOWNTO 0) + ); END COMPONENT; COMPONENT lpp_waveform_fifo @@ -370,7 +358,9 @@ PACKAGE lpp_waveform_pkg IS enable : IN STD_LOGIC; sel : IN STD_LOGIC_VECTOR(data_nb-1 DOWNTO 0); data : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); - data_s : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0)); + data_s : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); + time_out : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); + time_out_new : OUT STD_LOGIC_VECTOR(3 DOWNTO 0)); END COMPONENT; COMPONENT lpp_waveform_fsmdma diff --git a/lib/lpp/lpp_waveform/vhdlsyn.txt b/lib/lpp/lpp_waveform/vhdlsyn.txt --- a/lib/lpp/lpp_waveform/vhdlsyn.txt +++ b/lib/lpp/lpp_waveform/vhdlsyn.txt @@ -12,3 +12,4 @@ lpp_waveform_snapshot_controler.vhd lpp_waveform_genaddress.vhd lpp_waveform_dma_genvalid.vhd lpp_waveform_fifo_arbiter_reg.vhd +lpp_waveform_fsmdma.vhd