@@ -26,7 +26,7 ENTITY lpp_lfr IS | |||||
26 | GENERIC ( |
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26 | GENERIC ( | |
27 | Mem_use : INTEGER := use_RAM; |
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27 | Mem_use : INTEGER := use_RAM; | |
28 | nb_data_by_buffer_size : INTEGER := 11; |
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28 | nb_data_by_buffer_size : INTEGER := 11; | |
29 | nb_word_by_buffer_size : INTEGER := 11; |
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29 | -- nb_word_by_buffer_size : INTEGER := 11; -- TODO | |
30 | nb_snapshot_param_size : INTEGER := 11; |
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30 | nb_snapshot_param_size : INTEGER := 11; | |
31 | delta_vector_size : INTEGER := 20; |
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31 | delta_vector_size : INTEGER := 20; | |
32 | delta_vector_size_f0_2 : INTEGER := 7; |
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32 | delta_vector_size_f0_2 : INTEGER := 7; | |
@@ -161,9 +161,9 ARCHITECTURE beh OF lpp_lfr IS | |||||
161 | SIGNAL length_matrix_f2 : STD_LOGIC_VECTOR(25 DOWNTO 0); |
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161 | SIGNAL length_matrix_f2 : STD_LOGIC_VECTOR(25 DOWNTO 0); | |
162 |
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162 | |||
163 | -- WFP |
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163 | -- WFP | |
164 | SIGNAL status_full : STD_LOGIC_VECTOR(3 DOWNTO 0); |
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164 | --SIGNAL status_full : STD_LOGIC_VECTOR(3 DOWNTO 0); | |
165 | SIGNAL status_full_ack : STD_LOGIC_VECTOR(3 DOWNTO 0); |
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165 | --SIGNAL status_full_ack : STD_LOGIC_VECTOR(3 DOWNTO 0); | |
166 | SIGNAL status_full_err : STD_LOGIC_VECTOR(3 DOWNTO 0); |
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166 | --SIGNAL status_full_err : STD_LOGIC_VECTOR(3 DOWNTO 0); | |
167 | SIGNAL status_new_err : STD_LOGIC_VECTOR(3 DOWNTO 0); |
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167 | SIGNAL status_new_err : STD_LOGIC_VECTOR(3 DOWNTO 0); | |
168 | SIGNAL delta_snapshot : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); |
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168 | SIGNAL delta_snapshot : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); | |
169 | SIGNAL delta_f0 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); |
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169 | SIGNAL delta_f0 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); | |
@@ -172,7 +172,6 ARCHITECTURE beh OF lpp_lfr IS | |||||
172 | SIGNAL delta_f2 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); |
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172 | SIGNAL delta_f2 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); | |
173 |
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173 | |||
174 | SIGNAL nb_data_by_buffer : STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0); |
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174 | SIGNAL nb_data_by_buffer : STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0); | |
175 | SIGNAL nb_word_by_buffer : STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0); |
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176 | SIGNAL nb_snapshot_param : STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0); |
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175 | SIGNAL nb_snapshot_param : STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0); | |
177 | SIGNAL enable_f0 : STD_LOGIC; |
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176 | SIGNAL enable_f0 : STD_LOGIC; | |
178 | SIGNAL enable_f1 : STD_LOGIC; |
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177 | SIGNAL enable_f1 : STD_LOGIC; | |
@@ -181,38 +180,10 ARCHITECTURE beh OF lpp_lfr IS | |||||
181 | SIGNAL burst_f0 : STD_LOGIC; |
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180 | SIGNAL burst_f0 : STD_LOGIC; | |
182 | SIGNAL burst_f1 : STD_LOGIC; |
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181 | SIGNAL burst_f1 : STD_LOGIC; | |
183 | SIGNAL burst_f2 : STD_LOGIC; |
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182 | SIGNAL burst_f2 : STD_LOGIC; | |
184 | SIGNAL addr_data_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
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185 | SIGNAL addr_data_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
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186 | SIGNAL addr_data_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
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187 | SIGNAL addr_data_f3 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
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188 |
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183 | |||
189 | SIGNAL run : STD_LOGIC; |
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184 | SIGNAL run : STD_LOGIC; | |
190 | SIGNAL start_date : STD_LOGIC_VECTOR(30 DOWNTO 0); |
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185 | SIGNAL start_date : STD_LOGIC_VECTOR(30 DOWNTO 0); | |
191 |
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186 | |||
192 | SIGNAL data_f0_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0); |
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193 | SIGNAL data_f0_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0); |
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194 | SIGNAL data_f0_data_out_valid : STD_LOGIC; |
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195 | SIGNAL data_f0_data_out_valid_burst : STD_LOGIC; |
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196 | SIGNAL data_f0_data_out_ren : STD_LOGIC; |
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197 | --f1 |
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198 | SIGNAL data_f1_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0); |
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199 | SIGNAL data_f1_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0); |
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200 | SIGNAL data_f1_data_out_valid : STD_LOGIC; |
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201 | SIGNAL data_f1_data_out_valid_burst : STD_LOGIC; |
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202 | SIGNAL data_f1_data_out_ren : STD_LOGIC; |
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203 | --f2 |
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204 | SIGNAL data_f2_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0); |
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205 | SIGNAL data_f2_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0); |
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206 | SIGNAL data_f2_data_out_valid : STD_LOGIC; |
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207 | SIGNAL data_f2_data_out_valid_burst : STD_LOGIC; |
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208 | SIGNAL data_f2_data_out_ren : STD_LOGIC; |
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209 | --f3 |
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210 | SIGNAL data_f3_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0); |
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211 | SIGNAL data_f3_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0); |
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212 | SIGNAL data_f3_data_out_valid : STD_LOGIC; |
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213 | SIGNAL data_f3_data_out_valid_burst : STD_LOGIC; |
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214 | SIGNAL data_f3_data_out_ren : STD_LOGIC; |
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215 |
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216 | ----------------------------------------------------------------------------- |
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187 | ----------------------------------------------------------------------------- | |
217 | -- |
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188 | -- | |
218 | ----------------------------------------------------------------------------- |
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189 | ----------------------------------------------------------------------------- | |
@@ -232,6 +203,12 ARCHITECTURE beh OF lpp_lfr IS | |||||
232 | SIGNAL data_f3_data_out_valid_s : STD_LOGIC; |
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203 | SIGNAL data_f3_data_out_valid_s : STD_LOGIC; | |
233 | SIGNAL data_f3_data_out_valid_burst_s : STD_LOGIC; |
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204 | SIGNAL data_f3_data_out_valid_burst_s : STD_LOGIC; | |
234 |
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205 | |||
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206 | SIGNAL wfp_status_buffer_ready : STD_LOGIC_VECTOR(3 DOWNTO 0); | |||
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207 | SIGNAL wfp_addr_buffer : STD_LOGIC_VECTOR(32*4 DOWNTO 0); | |||
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208 | SIGNAL wfp_length_buffer : STD_LOGIC_VECTOR(25 DOWNTO 0); | |||
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209 | SIGNAL wfp_ready_buffer : STD_LOGIC_VECTOR(3 DOWNTO 0); | |||
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210 | SIGNAL wfp_buffer_time : STD_LOGIC_VECTOR(48*4-1 DOWNTO 0); | |||
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211 | SIGNAL wfp_error_buffer_full : STD_LOGIC_VECTOR(3 DOWNTO 0); | |||
235 | ----------------------------------------------------------------------------- |
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212 | ----------------------------------------------------------------------------- | |
236 | -- DMA RR |
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213 | -- DMA RR | |
237 | ----------------------------------------------------------------------------- |
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214 | ----------------------------------------------------------------------------- | |
@@ -340,7 +317,7 BEGIN | |||||
340 | lpp_lfr_apbreg_1 : lpp_lfr_apbreg |
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317 | lpp_lfr_apbreg_1 : lpp_lfr_apbreg | |
341 | GENERIC MAP ( |
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318 | GENERIC MAP ( | |
342 | nb_data_by_buffer_size => nb_data_by_buffer_size, |
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319 | nb_data_by_buffer_size => nb_data_by_buffer_size, | |
343 | nb_word_by_buffer_size => nb_word_by_buffer_size, |
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320 | -- nb_word_by_buffer_size => nb_word_by_buffer_size, -- TODO | |
344 | nb_snapshot_param_size => nb_snapshot_param_size, |
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321 | nb_snapshot_param_size => nb_snapshot_param_size, | |
345 | delta_vector_size => delta_vector_size, |
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322 | delta_vector_size => delta_vector_size, | |
346 | delta_vector_size_f0_2 => delta_vector_size_f0_2, |
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323 | delta_vector_size_f0_2 => delta_vector_size_f0_2, | |
@@ -379,9 +356,9 BEGIN | |||||
379 | length_matrix_f1 => length_matrix_f1, |
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356 | length_matrix_f1 => length_matrix_f1, | |
380 | length_matrix_f2 => length_matrix_f2, |
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357 | length_matrix_f2 => length_matrix_f2, | |
381 | ------------------------------------------------------------------------- |
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358 | ------------------------------------------------------------------------- | |
382 | status_full => status_full, |
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359 | --status_full => status_full, -- TODo | |
383 | status_full_ack => status_full_ack, |
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360 | --status_full_ack => status_full_ack, -- TODo | |
384 | status_full_err => status_full_err, |
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361 | --status_full_err => status_full_err, -- TODo | |
385 | status_new_err => status_new_err, |
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362 | status_new_err => status_new_err, | |
386 | data_shaping_BW => data_shaping_BW, |
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363 | data_shaping_BW => data_shaping_BW, | |
387 | data_shaping_SP0 => data_shaping_SP0, |
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364 | data_shaping_SP0 => data_shaping_SP0, | |
@@ -395,7 +372,7 BEGIN | |||||
395 | delta_f1 => delta_f1, |
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372 | delta_f1 => delta_f1, | |
396 | delta_f2 => delta_f2, |
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373 | delta_f2 => delta_f2, | |
397 | nb_data_by_buffer => nb_data_by_buffer, |
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374 | nb_data_by_buffer => nb_data_by_buffer, | |
398 | nb_word_by_buffer => nb_word_by_buffer, |
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375 | -- nb_word_by_buffer => nb_word_by_buffer, -- TODO | |
399 | nb_snapshot_param => nb_snapshot_param, |
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376 | nb_snapshot_param => nb_snapshot_param, | |
400 | enable_f0 => enable_f0, |
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377 | enable_f0 => enable_f0, | |
401 | enable_f1 => enable_f1, |
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378 | enable_f1 => enable_f1, | |
@@ -405,12 +382,16 BEGIN | |||||
405 | burst_f1 => burst_f1, |
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382 | burst_f1 => burst_f1, | |
406 | burst_f2 => burst_f2, |
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383 | burst_f2 => burst_f2, | |
407 | run => run, |
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384 | run => run, | |
408 | addr_data_f0 => addr_data_f0, |
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409 | addr_data_f1 => addr_data_f1, |
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410 | addr_data_f2 => addr_data_f2, |
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411 | addr_data_f3 => addr_data_f3, |
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412 | start_date => start_date, |
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385 | start_date => start_date, | |
413 |
debug_signal => debug_signal |
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386 | -- debug_signal => debug_signal, | |
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387 | wfp_status_buffer_ready => wfp_status_buffer_ready,-- TODO | |||
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388 | wfp_addr_buffer => wfp_addr_buffer,-- TODO | |||
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389 | wfp_length_buffer => wfp_length_buffer,-- TODO | |||
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390 | ||||
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391 | wfp_ready_buffer => wfp_ready_buffer,-- TODO | |||
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392 | wfp_buffer_time => wfp_buffer_time,-- TODO | |||
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393 | wfp_error_buffer_full => wfp_error_buffer_full -- TODO | |||
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394 | ); | |||
414 |
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395 | |||
415 | ----------------------------------------------------------------------------- |
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396 | ----------------------------------------------------------------------------- | |
416 | ----------------------------------------------------------------------------- |
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397 | ----------------------------------------------------------------------------- | |
@@ -419,7 +400,6 BEGIN | |||||
419 | tech => inferred, |
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400 | tech => inferred, | |
420 | data_size => 6*16, |
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401 | data_size => 6*16, | |
421 | nb_data_by_buffer_size => nb_data_by_buffer_size, |
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402 | nb_data_by_buffer_size => nb_data_by_buffer_size, | |
422 | nb_word_by_buffer_size => nb_word_by_buffer_size, |
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423 | nb_snapshot_param_size => nb_snapshot_param_size, |
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403 | nb_snapshot_param_size => nb_snapshot_param_size, | |
424 | delta_vector_size => delta_vector_size, |
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404 | delta_vector_size => delta_vector_size, | |
425 | delta_vector_size_f0_2 => delta_vector_size_f0_2 |
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405 | delta_vector_size_f0_2 => delta_vector_size_f0_2 | |
@@ -445,234 +425,43 BEGIN | |||||
445 | burst_f2 => burst_f2, |
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425 | burst_f2 => burst_f2, | |
446 |
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426 | |||
447 | nb_data_by_buffer => nb_data_by_buffer, |
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427 | nb_data_by_buffer => nb_data_by_buffer, | |
448 | nb_word_by_buffer => nb_word_by_buffer, |
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449 | nb_snapshot_param => nb_snapshot_param, |
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428 | nb_snapshot_param => nb_snapshot_param, | |
450 | status_full => status_full, |
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451 | status_full_ack => status_full_ack, |
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452 | status_full_err => status_full_err, |
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453 | status_new_err => status_new_err, |
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429 | status_new_err => status_new_err, | |
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430 | ||||
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431 | status_buffer_ready => wfp_status_buffer_ready, | |||
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432 | addr_buffer => wfp_addr_buffer, | |||
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433 | length_buffer => wfp_length_buffer, | |||
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434 | ready_buffer => wfp_ready_buffer, | |||
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435 | buffer_time => wfp_buffer_time, | |||
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436 | error_buffer_full => wfp_error_buffer_full, | |||
454 |
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437 | |||
455 | coarse_time => coarse_time, |
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438 | coarse_time => coarse_time, | |
456 | fine_time => fine_time, |
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439 | fine_time => fine_time, | |
457 |
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440 | |||
458 | --f0 |
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441 | --f0 | |
459 | addr_data_f0 => addr_data_f0, |
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460 | data_f0_in_valid => sample_f0_val, |
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442 | data_f0_in_valid => sample_f0_val, | |
461 | data_f0_in => sample_f0_data, |
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443 | data_f0_in => sample_f0_data, | |
462 | --f1 |
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444 | --f1 | |
463 | addr_data_f1 => addr_data_f1, |
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464 | data_f1_in_valid => sample_f1_val, |
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445 | data_f1_in_valid => sample_f1_val, | |
465 | data_f1_in => sample_f1_data, |
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446 | data_f1_in => sample_f1_data, | |
466 | --f2 |
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447 | --f2 | |
467 | addr_data_f2 => addr_data_f2, |
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468 | data_f2_in_valid => sample_f2_val, |
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448 | data_f2_in_valid => sample_f2_val, | |
469 | data_f2_in => sample_f2_data, |
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449 | data_f2_in => sample_f2_data, | |
470 | --f3 |
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450 | --f3 | |
471 | addr_data_f3 => addr_data_f3, |
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472 | data_f3_in_valid => sample_f3_val, |
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451 | data_f3_in_valid => sample_f3_val, | |
473 | data_f3_in => sample_f3_data, |
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452 | data_f3_in => sample_f3_data, | |
474 | -- OUTPUT -- DMA interface |
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453 | -- OUTPUT -- DMA interface | |
475 | --f0 |
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454 | ||
476 | data_f0_addr_out => data_f0_addr_out_s, |
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455 | dma_fifo_valid_burst => dma_fifo_burst_valid(3 DOWNTO 0), | |
477 |
d |
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456 | dma_fifo_data => dma_fifo_data(32*4-1 DOWNTO 0), | |
478 | data_f0_data_out_valid => data_f0_data_out_valid_s, |
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457 | dma_fifo_ren => dma_fifo_ren(3 DOWNTO 0), | |
479 | data_f0_data_out_valid_burst => data_f0_data_out_valid_burst_s, |
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458 | dma_buffer_new => dma_buffer_new(3 DOWNTO 0), | |
480 | data_f0_data_out_ren => data_f0_data_out_ren, |
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459 | dma_buffer_addr => dma_buffer_addr(32*4-1 DOWNTO 0), | |
481 | --f1 |
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460 | dma_buffer_length => dma_buffer_length(26*4-1 DOWNTO 0), | |
482 | data_f1_addr_out => data_f1_addr_out_s, |
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461 | dma_buffer_full => dma_buffer_full(3 DOWNTO 0), | |
483 | data_f1_data_out => data_f1_data_out, |
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462 | dma_buffer_full_err => dma_buffer_full_err(3 DOWNTO 0) | |
484 | data_f1_data_out_valid => data_f1_data_out_valid_s, |
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485 | data_f1_data_out_valid_burst => data_f1_data_out_valid_burst_s, |
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486 | data_f1_data_out_ren => data_f1_data_out_ren, |
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487 | --f2 |
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488 | data_f2_addr_out => data_f2_addr_out_s, |
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489 | data_f2_data_out => data_f2_data_out, |
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490 | data_f2_data_out_valid => data_f2_data_out_valid_s, |
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491 | data_f2_data_out_valid_burst => data_f2_data_out_valid_burst_s, |
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492 | data_f2_data_out_ren => data_f2_data_out_ren, |
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493 | --f3 |
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494 | data_f3_addr_out => data_f3_addr_out_s, |
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495 | data_f3_data_out => data_f3_data_out, |
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496 | data_f3_data_out_valid => data_f3_data_out_valid_s, |
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497 | data_f3_data_out_valid_burst => data_f3_data_out_valid_burst_s, |
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498 | data_f3_data_out_ren => data_f3_data_out_ren , |
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499 |
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500 | ------------------------------------------------------------------------- |
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501 | observation_reg => OPEN |
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502 |
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503 | ); |
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504 |
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505 |
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506 | ----------------------------------------------------------------------------- |
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507 | -- TEMP |
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508 | ----------------------------------------------------------------------------- |
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509 |
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510 | PROCESS (clk, rstn) |
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511 | BEGIN -- PROCESS |
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512 | IF rstn = '0' THEN -- asynchronous reset (active low) |
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513 | data_f0_data_out_valid <= '0'; |
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514 | data_f0_data_out_valid_burst <= '0'; |
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515 | data_f1_data_out_valid <= '0'; |
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516 | data_f1_data_out_valid_burst <= '0'; |
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517 | data_f2_data_out_valid <= '0'; |
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518 | data_f2_data_out_valid_burst <= '0'; |
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519 | data_f3_data_out_valid <= '0'; |
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520 | data_f3_data_out_valid_burst <= '0'; |
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521 | ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge |
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522 | data_f0_data_out_valid <= data_f0_data_out_valid_s; |
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523 | data_f0_data_out_valid_burst <= data_f0_data_out_valid_burst_s; |
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524 | data_f1_data_out_valid <= data_f1_data_out_valid_s; |
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525 | data_f1_data_out_valid_burst <= data_f1_data_out_valid_burst_s; |
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526 | data_f2_data_out_valid <= data_f2_data_out_valid_s; |
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527 | data_f2_data_out_valid_burst <= data_f2_data_out_valid_burst_s; |
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528 | data_f3_data_out_valid <= data_f3_data_out_valid_s; |
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529 | data_f3_data_out_valid_burst <= data_f3_data_out_valid_burst_s; |
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530 | END IF; |
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531 | END PROCESS; |
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532 |
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533 | data_f0_addr_out <= data_f0_addr_out_s; |
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534 | data_f1_addr_out <= data_f1_addr_out_s; |
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535 | data_f2_addr_out <= data_f2_addr_out_s; |
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536 | data_f3_addr_out <= data_f3_addr_out_s; |
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537 |
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538 | ----------------------------------------------------------------------------- |
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539 | -- RoundRobin Selection For DMA |
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540 | ----------------------------------------------------------------------------- |
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541 |
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542 | dma_rr_valid(0) <= data_f0_data_out_valid OR data_f0_data_out_valid_burst; |
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543 | dma_rr_valid(1) <= data_f1_data_out_valid OR data_f1_data_out_valid_burst; |
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544 | dma_rr_valid(2) <= data_f2_data_out_valid OR data_f2_data_out_valid_burst; |
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545 | dma_rr_valid(3) <= data_f3_data_out_valid OR data_f3_data_out_valid_burst; |
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546 |
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547 | RR_Arbiter_4_1 : RR_Arbiter_4 |
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548 | PORT MAP ( |
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549 | clk => clk, |
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550 | rstn => rstn, |
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551 | in_valid => dma_rr_valid, |
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552 | out_grant => dma_rr_grant_s); |
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553 |
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554 | dma_rr_valid_ms(0) <= data_ms_valid OR data_ms_valid_burst; |
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555 | dma_rr_valid_ms(1) <= '0' WHEN dma_rr_grant_s = "0000" ELSE '1'; |
|
|||
556 | dma_rr_valid_ms(2) <= '0'; |
|
|||
557 | dma_rr_valid_ms(3) <= '0'; |
|
|||
558 |
|
||||
559 | RR_Arbiter_4_2 : RR_Arbiter_4 |
|
|||
560 | PORT MAP ( |
|
|||
561 | clk => clk, |
|
|||
562 | rstn => rstn, |
|
|||
563 | in_valid => dma_rr_valid_ms, |
|
|||
564 | out_grant => dma_rr_grant_ms); |
|
|||
565 |
|
||||
566 | dma_rr_grant <= dma_rr_grant_ms(0) & "0000" WHEN dma_rr_grant_ms(0) = '1' ELSE '0' & dma_rr_grant_s; |
|
|||
567 |
|
||||
568 |
|
463 | |||
569 | ----------------------------------------------------------------------------- |
|
464 | ); | |
570 | -- in : dma_rr_grant |
|
|||
571 | -- send |
|
|||
572 | -- out : dma_sel |
|
|||
573 | -- dma_valid_burst |
|
|||
574 | -- dma_sel_valid |
|
|||
575 | ----------------------------------------------------------------------------- |
|
|||
576 | PROCESS (clk, rstn) |
|
|||
577 | BEGIN -- PROCESS |
|
|||
578 | IF rstn = '0' THEN -- asynchronous reset (active low) |
|
|||
579 | dma_sel <= (OTHERS => '0'); |
|
|||
580 | dma_send <= '0'; |
|
|||
581 | dma_valid_burst <= '0'; |
|
|||
582 | data_ms_done <= '0'; |
|
|||
583 | dma_ms_ongoing <= '0'; |
|
|||
584 | ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge |
|
|||
585 | IF run = '1' THEN |
|
|||
586 | data_ms_done <= '0'; |
|
|||
587 | IF dma_sel = "00000" OR dma_done = '1' THEN |
|
|||
588 | dma_sel <= dma_rr_grant; |
|
|||
589 | IF dma_rr_grant(0) = '1' THEN |
|
|||
590 | dma_ms_ongoing <= '0'; |
|
|||
591 | dma_send <= '1'; |
|
|||
592 | dma_valid_burst <= data_f0_data_out_valid_burst; |
|
|||
593 | dma_sel_valid <= data_f0_data_out_valid; |
|
|||
594 | ELSIF dma_rr_grant(1) = '1' THEN |
|
|||
595 | dma_ms_ongoing <= '0'; |
|
|||
596 | dma_send <= '1'; |
|
|||
597 | dma_valid_burst <= data_f1_data_out_valid_burst; |
|
|||
598 | dma_sel_valid <= data_f1_data_out_valid; |
|
|||
599 | ELSIF dma_rr_grant(2) = '1' THEN |
|
|||
600 | dma_ms_ongoing <= '0'; |
|
|||
601 | dma_send <= '1'; |
|
|||
602 | dma_valid_burst <= data_f2_data_out_valid_burst; |
|
|||
603 | dma_sel_valid <= data_f2_data_out_valid; |
|
|||
604 | ELSIF dma_rr_grant(3) = '1' THEN |
|
|||
605 | dma_ms_ongoing <= '0'; |
|
|||
606 | dma_send <= '1'; |
|
|||
607 | dma_valid_burst <= data_f3_data_out_valid_burst; |
|
|||
608 | dma_sel_valid <= data_f3_data_out_valid; |
|
|||
609 | ELSIF dma_rr_grant(4) = '1' THEN |
|
|||
610 | dma_ms_ongoing <= '1'; |
|
|||
611 | dma_send <= '1'; |
|
|||
612 | dma_valid_burst <= data_ms_valid_burst; |
|
|||
613 | dma_sel_valid <= data_ms_valid; |
|
|||
614 | --ELSE |
|
|||
615 | --dma_ms_ongoing <= '0'; |
|
|||
616 | END IF; |
|
|||
617 |
|
||||
618 | IF dma_ms_ongoing = '1' AND dma_done = '1' THEN |
|
|||
619 | data_ms_done <= '1'; |
|
|||
620 | END IF; |
|
|||
621 | ELSE |
|
|||
622 | dma_sel <= dma_sel; |
|
|||
623 | dma_send <= '0'; |
|
|||
624 | END IF; |
|
|||
625 | ELSE |
|
|||
626 | data_ms_done <= '0'; |
|
|||
627 | dma_sel <= (OTHERS => '0'); |
|
|||
628 | dma_send <= '0'; |
|
|||
629 | dma_valid_burst <= '0'; |
|
|||
630 | END IF; |
|
|||
631 | END IF; |
|
|||
632 | END PROCESS; |
|
|||
633 |
|
||||
634 |
|
||||
635 | dma_address <= data_f0_addr_out WHEN dma_sel(0) = '1' ELSE |
|
|||
636 | data_f1_addr_out WHEN dma_sel(1) = '1' ELSE |
|
|||
637 | data_f2_addr_out WHEN dma_sel(2) = '1' ELSE |
|
|||
638 | data_f3_addr_out WHEN dma_sel(3) = '1' ELSE |
|
|||
639 | data_ms_addr; |
|
|||
640 |
|
||||
641 | dma_data <= data_f0_data_out WHEN dma_sel(0) = '1' ELSE |
|
|||
642 | data_f1_data_out WHEN dma_sel(1) = '1' ELSE |
|
|||
643 | data_f2_data_out WHEN dma_sel(2) = '1' ELSE |
|
|||
644 | data_f3_data_out WHEN dma_sel(3) = '1' ELSE |
|
|||
645 | data_ms_data; |
|
|||
646 |
|
||||
647 | data_f0_data_out_ren <= dma_ren WHEN dma_sel(0) = '1' ELSE '1'; |
|
|||
648 | data_f1_data_out_ren <= dma_ren WHEN dma_sel(1) = '1' ELSE '1'; |
|
|||
649 | data_f2_data_out_ren <= dma_ren WHEN dma_sel(2) = '1' ELSE '1'; |
|
|||
650 | data_f3_data_out_ren <= dma_ren WHEN dma_sel(3) = '1' ELSE '1'; |
|
|||
651 | data_ms_ren <= dma_ren WHEN dma_sel(4) = '1' ELSE '1'; |
|
|||
652 |
|
||||
653 | dma_data_2 <= dma_data; |
|
|||
654 |
|
||||
655 |
|
||||
656 | ----------------------------------------------------------------------------- |
|
|||
657 | -- DMA |
|
|||
658 | ----------------------------------------------------------------------------- |
|
|||
659 | lpp_dma_singleOrBurst_1 : lpp_dma_singleOrBurst |
|
|||
660 | GENERIC MAP ( |
|
|||
661 | tech => inferred, |
|
|||
662 | hindex => hindex) |
|
|||
663 | PORT MAP ( |
|
|||
664 | HCLK => clk, |
|
|||
665 | HRESETn => rstn, |
|
|||
666 | run => run, |
|
|||
667 | AHB_Master_In => OPEN, |
|
|||
668 | AHB_Master_Out => OPEN, |
|
|||
669 |
|
||||
670 | send => dma_send, |
|
|||
671 | valid_burst => dma_valid_burst, |
|
|||
672 | done => dma_done, |
|
|||
673 | ren => dma_ren, |
|
|||
674 | address => dma_address, |
|
|||
675 | data => dma_data_2); |
|
|||
676 |
|
465 | |||
677 | ----------------------------------------------------------------------------- |
|
466 | ----------------------------------------------------------------------------- | |
678 | -- Matrix Spectral |
|
467 | -- Matrix Spectral |
@@ -38,7 +38,7 USE techmap.gencomp.ALL; | |||||
38 | ENTITY lpp_lfr_apbreg IS |
|
38 | ENTITY lpp_lfr_apbreg IS | |
39 | GENERIC ( |
|
39 | GENERIC ( | |
40 | nb_data_by_buffer_size : INTEGER := 11; |
|
40 | nb_data_by_buffer_size : INTEGER := 11; | |
41 | nb_word_by_buffer_size : INTEGER := 11; |
|
41 | -- nb_word_by_buffer_size : INTEGER := 11; | |
42 | nb_snapshot_param_size : INTEGER := 11; |
|
42 | nb_snapshot_param_size : INTEGER := 11; | |
43 | delta_vector_size : INTEGER := 20; |
|
43 | delta_vector_size : INTEGER := 20; | |
44 | delta_vector_size_f0_2 : INTEGER := 3; |
|
44 | delta_vector_size_f0_2 : INTEGER := 3; | |
@@ -95,11 +95,11 ENTITY lpp_lfr_apbreg IS | |||||
95 | --------------------------------------------------------------------------- |
|
95 | --------------------------------------------------------------------------- | |
96 | --------------------------------------------------------------------------- |
|
96 | --------------------------------------------------------------------------- | |
97 | -- WaveForm picker Reg |
|
97 | -- WaveForm picker Reg | |
98 | status_full : IN STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
98 | --status_full : IN STD_LOGIC_VECTOR(3 DOWNTO 0); | |
99 | status_full_ack : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
99 | --status_full_ack : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); | |
100 | status_full_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
100 | --status_full_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0); | |
101 | status_new_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
101 | status_new_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0); | |
102 |
|
102 | |||
103 |
|
|
103 | -- OUT | |
104 | data_shaping_BW : OUT STD_LOGIC; |
|
104 | data_shaping_BW : OUT STD_LOGIC; | |
105 | data_shaping_SP0 : OUT STD_LOGIC; |
|
105 | data_shaping_SP0 : OUT STD_LOGIC; | |
@@ -114,7 +114,7 ENTITY lpp_lfr_apbreg IS | |||||
114 | delta_f1 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); |
|
114 | delta_f1 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); | |
115 | delta_f2 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); |
|
115 | delta_f2 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); | |
116 | nb_data_by_buffer : OUT STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0); |
|
116 | nb_data_by_buffer : OUT STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0); | |
117 | nb_word_by_buffer : OUT STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0); |
|
117 | --nb_word_by_buffer : OUT STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0); | |
118 | nb_snapshot_param : OUT STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0); |
|
118 | nb_snapshot_param : OUT STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0); | |
119 |
|
119 | |||
120 | enable_f0 : OUT STD_LOGIC; |
|
120 | enable_f0 : OUT STD_LOGIC; | |
@@ -128,14 +128,15 ENTITY lpp_lfr_apbreg IS | |||||
128 |
|
128 | |||
129 | run : OUT STD_LOGIC; |
|
129 | run : OUT STD_LOGIC; | |
130 |
|
130 | |||
131 | addr_data_f0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
|||
132 | addr_data_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
|||
133 | addr_data_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
|||
134 | addr_data_f3 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
|||
135 | start_date : OUT STD_LOGIC_VECTOR(30 DOWNTO 0); |
|
131 | start_date : OUT STD_LOGIC_VECTOR(30 DOWNTO 0); | |
136 | --------------------------------------------------------------------------- |
|
132 | ||
137 |
|
|
133 | wfp_status_buffer_ready : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); | |
138 | --------------------------------------------------------------------------- |
|
134 | wfp_addr_buffer : OUT STD_LOGIC_VECTOR(32*4 DOWNTO 0); | |
|
135 | wfp_length_buffer : OUT STD_LOGIC_VECTOR(25 DOWNTO 0); | |||
|
136 | wfp_ready_buffer : IN STD_LOGIC_VECTOR(3 DOWNTO 0); | |||
|
137 | wfp_buffer_time : IN STD_LOGIC_VECTOR(48*4-1 DOWNTO 0); | |||
|
138 | wfp_error_buffer_full : IN STD_LOGIC_VECTOR(3 DOWNTO 0) | |||
|
139 | ||||
139 |
|
|
140 | ); | |
140 |
|
141 | |||
141 | END lpp_lfr_apbreg; |
|
142 | END lpp_lfr_apbreg; | |
@@ -181,8 +182,8 ARCHITECTURE beh OF lpp_lfr_apbreg IS | |||||
181 | SIGNAL reg_sp : lpp_SpectralMatrix_regs; |
|
182 | SIGNAL reg_sp : lpp_SpectralMatrix_regs; | |
182 |
|
183 | |||
183 | TYPE lpp_WaveformPicker_regs IS RECORD |
|
184 | TYPE lpp_WaveformPicker_regs IS RECORD | |
184 | status_full : STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
185 | -- status_full : STD_LOGIC_VECTOR(3 DOWNTO 0); | |
185 | status_full_err : STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
186 | -- status_full_err : STD_LOGIC_VECTOR(3 DOWNTO 0); | |
186 | status_new_err : STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
187 | status_new_err : STD_LOGIC_VECTOR(3 DOWNTO 0); | |
187 | data_shaping_BW : STD_LOGIC; |
|
188 | data_shaping_BW : STD_LOGIC; | |
188 | data_shaping_SP0 : STD_LOGIC; |
|
189 | data_shaping_SP0 : STD_LOGIC; | |
@@ -196,7 +197,7 ARCHITECTURE beh OF lpp_lfr_apbreg IS | |||||
196 | delta_f1 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); |
|
197 | delta_f1 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); | |
197 | delta_f2 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); |
|
198 | delta_f2 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); | |
198 | nb_data_by_buffer : STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0); |
|
199 | nb_data_by_buffer : STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0); | |
199 | nb_word_by_buffer : STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0); |
|
200 | -- nb_word_by_buffer : STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0); | |
200 | nb_snapshot_param : STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0); |
|
201 | nb_snapshot_param : STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0); | |
201 | enable_f0 : STD_LOGIC; |
|
202 | enable_f0 : STD_LOGIC; | |
202 | enable_f1 : STD_LOGIC; |
|
203 | enable_f1 : STD_LOGIC; | |
@@ -206,10 +207,11 ARCHITECTURE beh OF lpp_lfr_apbreg IS | |||||
206 | burst_f1 : STD_LOGIC; |
|
207 | burst_f1 : STD_LOGIC; | |
207 | burst_f2 : STD_LOGIC; |
|
208 | burst_f2 : STD_LOGIC; | |
208 | run : STD_LOGIC; |
|
209 | run : STD_LOGIC; | |
209 |
|
|
210 | status_ready_buffer_f : STD_LOGIC_VECTOR(4*2-1 DOWNTO 0); | |
210 |
|
|
211 | addr_buffer_f : STD_LOGIC_VECTOR(4*2*32-1 DOWNTO 0); | |
211 |
|
|
212 | time_buffer_f : STD_LOGIC_VECTOR(4*2*48-1 DOWNTO 0); | |
212 |
|
|
213 | length_buffer : STD_LOGIC_VECTOR(25 DOWNTO 0); | |
|
214 | error_buffer_full : STD_LOGIC_VECTOR(3 DOWNTO 0); | |||
213 | start_date : STD_LOGIC_VECTOR(30 DOWNTO 0); |
|
215 | start_date : STD_LOGIC_VECTOR(30 DOWNTO 0); | |
214 | END RECORD; |
|
216 | END RECORD; | |
215 | SIGNAL reg_wp : lpp_WaveformPicker_regs; |
|
217 | SIGNAL reg_wp : lpp_WaveformPicker_regs; | |
@@ -254,6 +256,8 ARCHITECTURE beh OF lpp_lfr_apbreg IS | |||||
254 | SIGNAL reg1_matrix_time_f2 : STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
256 | SIGNAL reg1_matrix_time_f2 : STD_LOGIC_VECTOR(47 DOWNTO 0); | |
255 | SIGNAL apbo_irq_ms : STD_LOGIC; |
|
257 | SIGNAL apbo_irq_ms : STD_LOGIC; | |
256 | SIGNAL apbo_irq_wfp : STD_LOGIC; |
|
258 | SIGNAL apbo_irq_wfp : STD_LOGIC; | |
|
259 | ----------------------------------------------------------------------------- | |||
|
260 | SIGNAL reg_ready_buffer_f : STD_LOGIC_VECTOR( 2*4-1 DOWNTO 0); | |||
257 |
|
261 | |||
258 | BEGIN -- beh |
|
262 | BEGIN -- beh | |
259 |
|
263 | |||
@@ -283,7 +287,6 BEGIN -- beh | |||||
283 | delta_f1 <= reg_wp.delta_f1; |
|
287 | delta_f1 <= reg_wp.delta_f1; | |
284 | delta_f2 <= reg_wp.delta_f2; |
|
288 | delta_f2 <= reg_wp.delta_f2; | |
285 | nb_data_by_buffer <= reg_wp.nb_data_by_buffer; |
|
289 | nb_data_by_buffer <= reg_wp.nb_data_by_buffer; | |
286 | nb_word_by_buffer <= reg_wp.nb_word_by_buffer; |
|
|||
287 | nb_snapshot_param <= reg_wp.nb_snapshot_param; |
|
290 | nb_snapshot_param <= reg_wp.nb_snapshot_param; | |
288 |
|
291 | |||
289 | enable_f0 <= reg_wp.enable_f0; |
|
292 | enable_f0 <= reg_wp.enable_f0; | |
@@ -297,16 +300,16 BEGIN -- beh | |||||
297 |
|
300 | |||
298 | run <= reg_wp.run; |
|
301 | run <= reg_wp.run; | |
299 |
|
302 | |||
300 | addr_data_f0 <= reg_wp.addr_data_f0; |
|
303 | --addr_data_f0 <= reg_wp.addr_data_f0; | |
301 | addr_data_f1 <= reg_wp.addr_data_f1; |
|
304 | --addr_data_f1 <= reg_wp.addr_data_f1; | |
302 | addr_data_f2 <= reg_wp.addr_data_f2; |
|
305 | --addr_data_f2 <= reg_wp.addr_data_f2; | |
303 | addr_data_f3 <= reg_wp.addr_data_f3; |
|
306 | --addr_data_f3 <= reg_wp.addr_data_f3; | |
304 |
|
307 | |||
305 | start_date <= reg_wp.start_date; |
|
308 | start_date <= reg_wp.start_date; | |
306 |
|
309 | |||
307 | length_matrix_f0 <= reg_sp.length_matrix; |
|
310 | --length_matrix_f0 <= reg_sp.length_matrix; | |
308 | length_matrix_f1 <= reg_sp.length_matrix; |
|
311 | --length_matrix_f1 <= reg_sp.length_matrix; | |
309 | length_matrix_f2 <= reg_sp.length_matrix; |
|
312 | --length_matrix_f2 <= reg_sp.length_matrix; | |
310 |
|
313 | |||
311 |
|
314 | |||
312 | lpp_lfr_apbreg : PROCESS (HCLK, HRESETn) |
|
315 | lpp_lfr_apbreg : PROCESS (HCLK, HRESETn) | |
@@ -322,7 +325,6 BEGIN -- beh | |||||
322 | reg_sp.status_ready_matrix_f0_1 <= '0'; |
|
325 | reg_sp.status_ready_matrix_f0_1 <= '0'; | |
323 | reg_sp.status_ready_matrix_f1_1 <= '0'; |
|
326 | reg_sp.status_ready_matrix_f1_1 <= '0'; | |
324 | reg_sp.status_ready_matrix_f2_1 <= '0'; |
|
327 | reg_sp.status_ready_matrix_f2_1 <= '0'; | |
325 | -- reg_sp.status_error_bad_component_error <= '0'; |
|
|||
326 | reg_sp.status_error_buffer_full <= '0'; |
|
328 | reg_sp.status_error_buffer_full <= '0'; | |
327 | reg_sp.status_error_input_fifo_write <= (OTHERS => '0'); |
|
329 | reg_sp.status_error_input_fifo_write <= (OTHERS => '0'); | |
328 |
|
330 | |||
@@ -351,7 +353,7 BEGIN -- beh | |||||
351 | apbo_irq_wfp <= '0'; |
|
353 | apbo_irq_wfp <= '0'; | |
352 |
|
354 | |||
353 |
|
355 | |||
354 |
|
|
356 | -- status_full_ack <= (OTHERS => '0'); | |
355 |
|
357 | |||
356 | reg_wp.data_shaping_BW <= '0'; |
|
358 | reg_wp.data_shaping_BW <= '0'; | |
357 | reg_wp.data_shaping_SP0 <= '0'; |
|
359 | reg_wp.data_shaping_SP0 <= '0'; | |
@@ -367,13 +369,10 BEGIN -- beh | |||||
367 | reg_wp.burst_f1 <= '0'; |
|
369 | reg_wp.burst_f1 <= '0'; | |
368 | reg_wp.burst_f2 <= '0'; |
|
370 | reg_wp.burst_f2 <= '0'; | |
369 | reg_wp.run <= '0'; |
|
371 | reg_wp.run <= '0'; | |
370 |
reg_wp. |
|
372 | -- reg_wp.status_full <= (OTHERS => '0'); | |
371 |
reg_wp. |
|
373 | -- reg_wp.status_full_err <= (OTHERS => '0'); | |
372 | reg_wp.addr_data_f2 <= (OTHERS => '0'); |
|
|||
373 | reg_wp.addr_data_f3 <= (OTHERS => '0'); |
|
|||
374 | reg_wp.status_full <= (OTHERS => '0'); |
|
|||
375 | reg_wp.status_full_err <= (OTHERS => '0'); |
|
|||
376 | reg_wp.status_new_err <= (OTHERS => '0'); |
|
374 | reg_wp.status_new_err <= (OTHERS => '0'); | |
|
375 | reg_wp.error_buffer_full <= (OTHERS => '0'); | |||
377 | reg_wp.delta_snapshot <= (OTHERS => '0'); |
|
376 | reg_wp.delta_snapshot <= (OTHERS => '0'); | |
378 | reg_wp.delta_f0 <= (OTHERS => '0'); |
|
377 | reg_wp.delta_f0 <= (OTHERS => '0'); | |
379 | reg_wp.delta_f0_2 <= (OTHERS => '0'); |
|
378 | reg_wp.delta_f0_2 <= (OTHERS => '0'); | |
@@ -385,7 +384,7 BEGIN -- beh | |||||
385 |
|
384 | |||
386 | ELSIF HCLK'EVENT AND HCLK = '1' THEN -- rising clock edge |
|
385 | ELSIF HCLK'EVENT AND HCLK = '1' THEN -- rising clock edge | |
387 |
|
386 | |||
388 | status_full_ack <= (OTHERS => '0'); |
|
387 | -- status_full_ack <= (OTHERS => '0'); | |
389 |
|
388 | |||
390 | reg_sp.status_ready_matrix_f0_0 <= reg_sp.status_ready_matrix_f0_0 OR reg0_ready_matrix_f0; |
|
389 | reg_sp.status_ready_matrix_f0_0 <= reg_sp.status_ready_matrix_f0_0 OR reg0_ready_matrix_f0; | |
391 | reg_sp.status_ready_matrix_f1_0 <= reg_sp.status_ready_matrix_f1_0 OR reg0_ready_matrix_f1; |
|
390 | reg_sp.status_ready_matrix_f1_0 <= reg_sp.status_ready_matrix_f1_0 OR reg0_ready_matrix_f1; | |
@@ -395,7 +394,10 BEGIN -- beh | |||||
395 | reg_sp.status_ready_matrix_f1_1 <= reg_sp.status_ready_matrix_f1_1 OR reg1_ready_matrix_f1; |
|
394 | reg_sp.status_ready_matrix_f1_1 <= reg_sp.status_ready_matrix_f1_1 OR reg1_ready_matrix_f1; | |
396 | reg_sp.status_ready_matrix_f2_1 <= reg_sp.status_ready_matrix_f2_1 OR reg1_ready_matrix_f2; |
|
395 | reg_sp.status_ready_matrix_f2_1 <= reg_sp.status_ready_matrix_f2_1 OR reg1_ready_matrix_f2; | |
397 |
|
396 | |||
398 | -- reg_sp.status_error_bad_component_error <= reg_sp.status_error_bad_component_error OR error_bad_component_error; |
|
397 | all_status_ready_buffer_bit: FOR I IN 4*2-1 DOWNTO 0 LOOP | |
|
398 | reg_wp.status_ready_buffer_f(I) <= reg_wp.status_ready_buffer_f(I) OR reg_ready_buffer_f(I); | |||
|
399 | END LOOP all_status_ready_buffer_bit; | |||
|
400 | ||||
399 |
|
401 | |||
400 | reg_sp.status_error_buffer_full <= reg_sp.status_error_buffer_full OR error_buffer_full; |
|
402 | reg_sp.status_error_buffer_full <= reg_sp.status_error_buffer_full OR error_buffer_full; | |
401 | reg_sp.status_error_input_fifo_write(0) <= reg_sp.status_error_input_fifo_write(0) OR error_input_fifo_write(0); |
|
403 | reg_sp.status_error_input_fifo_write(0) <= reg_sp.status_error_input_fifo_write(0) OR error_input_fifo_write(0); | |
@@ -405,9 +407,8 BEGIN -- beh | |||||
405 |
|
407 | |||
406 |
|
408 | |||
407 | all_status : FOR I IN 3 DOWNTO 0 LOOP |
|
409 | all_status : FOR I IN 3 DOWNTO 0 LOOP | |
408 | reg_wp.status_full(I) <= status_full(I) AND reg_wp.run; |
|
410 | reg_wp.error_buffer_full(I) <= reg_wp.error_buffer_full(I) OR wfp_error_buffer_full(I); | |
409 |
reg_wp.status_ |
|
411 | reg_wp.status_new_err(I) <= reg_wp.status_new_err(I) OR status_new_err(I); | |
410 | reg_wp.status_new_err(I) <= status_new_err(I) AND reg_wp.run; |
|
|||
411 | END LOOP all_status; |
|
412 | END LOOP all_status; | |
412 |
|
413 | |||
413 | paddr := "000000"; |
|
414 | paddr := "000000"; | |
@@ -488,35 +489,58 BEGIN -- beh | |||||
488 | prdata(6) <= reg_wp.burst_f2; |
|
489 | prdata(6) <= reg_wp.burst_f2; | |
489 | prdata(7) <= reg_wp.run; |
|
490 | prdata(7) <= reg_wp.run; | |
490 | --22 |
|
491 | --22 | |
491 | WHEN "010111" => prdata <= reg_wp.addr_data_f0; |
|
492 | --ON GOING \/ | |
492 | --23 |
|
493 | WHEN "010111" => prdata <= reg_wp.addr_buffer_f(32*1-1 DOWNTO 32*0); | |
493 |
WHEN "011000" => prdata <= reg_wp.addr_ |
|
494 | WHEN "011000" => prdata <= reg_wp.addr_buffer_f(32*2-1 DOWNTO 32*1); | |
494 | --24 |
|
495 | WHEN "011001" => prdata <= reg_wp.addr_buffer_f(32*3-1 DOWNTO 32*2); | |
495 |
WHEN "0110 |
|
496 | WHEN "011010" => prdata <= reg_wp.addr_buffer_f(32*4-1 DOWNTO 32*3); | |
496 | --25 |
|
497 | WHEN "011011" => prdata <= reg_wp.addr_buffer_f(32*5-1 DOWNTO 32*4); | |
497 |
WHEN "011 |
|
498 | WHEN "011100" => prdata <= reg_wp.addr_buffer_f(32*6-1 DOWNTO 32*5); | |
498 | --26 |
|
499 | WHEN "011101" => prdata <= reg_wp.addr_buffer_f(32*7-1 DOWNTO 32*6); | |
499 |
WHEN "011 |
|
500 | WHEN "011110" => prdata <= reg_wp.addr_buffer_f(32*8-1 DOWNTO 32*7); | |
500 | prdata(7 DOWNTO 4) <= reg_wp.status_full_err; |
|
501 | --ON GOING /\ | |
501 |
|
|
502 | WHEN "011111" => prdata(7 DOWNTO 0) <= reg_wp.status_ready_buffer_f; | |
|
503 | prdata(11 DOWNTO 8) <= reg_wp.error_buffer_full; | |||
|
504 | prdata(15 DOWNTO 12) <= reg_wp.status_new_err; | |||
|
505 | --prdata(3 DOWNTO 0) <= reg_wp.status_full; | |||
|
506 | -- prdata(7 DOWNTO 4) <= reg_wp.status_full_err; | |||
502 | --27 |
|
507 | --27 | |
503 |
WHEN " |
|
508 | WHEN "100000" => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_snapshot; | |
504 | --28 |
|
509 | --28 | |
505 |
WHEN " |
|
510 | WHEN "100001" => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_f0; | |
506 | --29 |
|
511 | --29 | |
507 |
WHEN " |
|
512 | WHEN "100010" => prdata(delta_vector_size_f0_2-1 DOWNTO 0) <= reg_wp.delta_f0_2; | |
508 | --30 |
|
513 | --30 | |
509 |
WHEN " |
|
514 | WHEN "100011" => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_f1; | |
510 | --31 |
|
515 | --31 | |
511 |
WHEN "100 |
|
516 | WHEN "100100" => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_f2; | |
512 | --32 |
|
517 | --32 | |
513 |
WHEN "100 |
|
518 | WHEN "100101" => prdata(nb_data_by_buffer_size-1 DOWNTO 0) <= reg_wp.nb_data_by_buffer; | |
514 | --33 |
|
519 | --33 | |
515 |
WHEN "100 |
|
520 | WHEN "100110" => prdata(nb_snapshot_param_size-1 DOWNTO 0) <= reg_wp.nb_snapshot_param; | |
516 | --34 |
|
521 | --34 | |
517 |
WHEN "100 |
|
522 | WHEN "100111" => prdata(30 DOWNTO 0) <= reg_wp.start_date; | |
518 | --35 |
|
523 | --35 | |
519 |
WHEN "10 |
|
524 | WHEN "101000" => prdata(15 DOWNTO 0) <= reg_wp.time_buffer_f(48*0+15 DOWNTO 48*0); | |
|
525 | WHEN "101001" => prdata(31 DOWNTO 0) <= reg_wp.time_buffer_f(48*0+47 DOWNTO 48*0+16); | |||
|
526 | WHEN "101010" => prdata(15 DOWNTO 0) <= reg_wp.time_buffer_f(48*1+15 DOWNTO 48*1); | |||
|
527 | WHEN "101011" => prdata(31 DOWNTO 0) <= reg_wp.time_buffer_f(48*1+47 DOWNTO 48*1+16); | |||
|
528 | WHEN "101100" => prdata(15 DOWNTO 0) <= reg_wp.time_buffer_f(48*2+15 DOWNTO 48*2); | |||
|
529 | WHEN "101110" => prdata(31 DOWNTO 0) <= reg_wp.time_buffer_f(48*2+47 DOWNTO 48*2+16); | |||
|
530 | WHEN "101111" => prdata(15 DOWNTO 0) <= reg_wp.time_buffer_f(48*3+15 DOWNTO 48*3); | |||
|
531 | WHEN "110000" => prdata(31 DOWNTO 0) <= reg_wp.time_buffer_f(48*3+47 DOWNTO 48*3+16); | |||
|
532 | ||||
|
533 | WHEN "110001" => prdata(15 DOWNTO 0) <= reg_wp.time_buffer_f(48*4+15 DOWNTO 48*4); | |||
|
534 | WHEN "111010" => prdata(31 DOWNTO 0) <= reg_wp.time_buffer_f(48*4+47 DOWNTO 48*4+16); | |||
|
535 | WHEN "110011" => prdata(15 DOWNTO 0) <= reg_wp.time_buffer_f(48*5+15 DOWNTO 48*5); | |||
|
536 | WHEN "110100" => prdata(31 DOWNTO 0) <= reg_wp.time_buffer_f(48*5+47 DOWNTO 48*5+16); | |||
|
537 | WHEN "110101" => prdata(15 DOWNTO 0) <= reg_wp.time_buffer_f(48*6+15 DOWNTO 48*6); | |||
|
538 | WHEN "110110" => prdata(31 DOWNTO 0) <= reg_wp.time_buffer_f(48*6+47 DOWNTO 48*6+16); | |||
|
539 | WHEN "110111" => prdata(15 DOWNTO 0) <= reg_wp.time_buffer_f(48*7+15 DOWNTO 48*7); | |||
|
540 | WHEN "111000" => prdata(31 DOWNTO 0) <= reg_wp.time_buffer_f(48*7+47 DOWNTO 48*7+16); | |||
|
541 | WHEN "111001" => prdata(25 DOWNTO 0) <= reg_wp.length_buffer; | |||
|
542 | ||||
|
543 | -- WHEN "100100" => prdata(nb_word_by_buffer_size-1 DOWNTO 0) <= reg_wp.nb_word_by_buffer; | |||
520 | ---------------------------------------------------- |
|
544 | ---------------------------------------------------- | |
521 | WHEN "111100" => prdata(23 DOWNTO 0) <= top_lfr_version(23 DOWNTO 0); |
|
545 | WHEN "111100" => prdata(23 DOWNTO 0) <= top_lfr_version(23 DOWNTO 0); | |
522 | WHEN OTHERS => NULL; |
|
546 | WHEN OTHERS => NULL; | |
@@ -527,8 +551,8 BEGIN -- beh | |||||
527 | CASE paddr(7 DOWNTO 2) IS |
|
551 | CASE paddr(7 DOWNTO 2) IS | |
528 | -- |
|
552 | -- | |
529 | WHEN "000000" => reg_sp.config_active_interruption_onNewMatrix <= apbi.pwdata(0); |
|
553 | WHEN "000000" => reg_sp.config_active_interruption_onNewMatrix <= apbi.pwdata(0); | |
530 | reg_sp.config_active_interruption_onError <= apbi.pwdata(1); |
|
554 | reg_sp.config_active_interruption_onError <= apbi.pwdata(1); | |
531 | reg_sp.config_ms_run <= apbi.pwdata(2); |
|
555 | reg_sp.config_ms_run <= apbi.pwdata(2); | |
532 |
|
556 | |||
533 | WHEN "000001" => |
|
557 | WHEN "000001" => | |
534 | reg_sp.status_ready_matrix_f0_0 <= ((NOT apbi.pwdata(0) ) AND reg_sp.status_ready_matrix_f0_0 ) OR reg0_ready_matrix_f0; |
|
558 | reg_sp.status_ready_matrix_f0_0 <= ((NOT apbi.pwdata(0) ) AND reg_sp.status_ready_matrix_f0_0 ) OR reg0_ready_matrix_f0; | |
@@ -567,27 +591,39 BEGIN -- beh | |||||
567 | reg_wp.burst_f2 <= apbi.pwdata(6); |
|
591 | reg_wp.burst_f2 <= apbi.pwdata(6); | |
568 | reg_wp.run <= apbi.pwdata(7); |
|
592 | reg_wp.run <= apbi.pwdata(7); | |
569 | --22 |
|
593 | --22 | |
570 |
WHEN "010111" => reg_wp.addr_ |
|
594 | WHEN "010111" => reg_wp.addr_buffer_f(32*1-1 DOWNTO 32*0) <= apbi.pwdata; | |
571 |
WHEN "011000" => reg_wp.addr_ |
|
595 | WHEN "011000" => reg_wp.addr_buffer_f(32*2-1 DOWNTO 32*1) <= apbi.pwdata; | |
572 |
WHEN "011001" => reg_wp.addr_ |
|
596 | WHEN "011001" => reg_wp.addr_buffer_f(32*3-1 DOWNTO 32*2) <= apbi.pwdata; | |
573 |
WHEN "011010" => reg_wp.addr_ |
|
597 | WHEN "011010" => reg_wp.addr_buffer_f(32*4-1 DOWNTO 32*3) <= apbi.pwdata; | |
|
598 | WHEN "011011" => reg_wp.addr_buffer_f(32*5-1 DOWNTO 32*4) <= apbi.pwdata; | |||
|
599 | WHEN "011100" => reg_wp.addr_buffer_f(32*6-1 DOWNTO 32*5) <= apbi.pwdata; | |||
|
600 | WHEN "011101" => reg_wp.addr_buffer_f(32*7-1 DOWNTO 32*6) <= apbi.pwdata; | |||
|
601 | WHEN "011110" => reg_wp.addr_buffer_f(32*8-1 DOWNTO 32*7) <= apbi.pwdata; | |||
574 | --26 |
|
602 | --26 | |
575 | WHEN "011011" => reg_wp.status_full <= apbi.pwdata(3 DOWNTO 0); |
|
603 | WHEN "011111" => | |
576 | reg_wp.status_full_err <= apbi.pwdata(7 DOWNTO 4); |
|
604 | all_reg_wp_status_bit: FOR I IN 3 DOWNTO 0 LOOP | |
577 | reg_wp.status_new_err <= apbi.pwdata(11 DOWNTO 8); |
|
605 | reg_wp.status_ready_buffer_f(I) <= ((NOT apbi.pwdata(I) ) AND reg_wp.status_ready_buffer_f(I) ) OR reg_ready_buffer_f(I); | |
578 | status_full_ack(0) <= reg_wp.status_full(0) AND NOT apbi.pwdata(0); |
|
606 | reg_wp.status_ready_buffer_f(I*2+1) <= ((NOT apbi.pwdata(I*2+1)) AND reg_wp.status_ready_buffer_f(I*2+1)) OR reg_ready_buffer_f(I*2+1); | |
579 | status_full_ack(1) <= reg_wp.status_full(1) AND NOT apbi.pwdata(1); |
|
607 | reg_wp.error_buffer_full(I) <= ((NOT apbi.pwdata(I+8) ) AND reg_wp.error_buffer_full(I) ) OR wfp_error_buffer_full(I); | |
580 | status_full_ack(2) <= reg_wp.status_full(2) AND NOT apbi.pwdata(2); |
|
608 | reg_wp.status_new_err(I) <= ((NOT apbi.pwdata(I+12) ) AND reg_wp.status_new_err(I) ) OR status_new_err(I); | |
581 | status_full_ack(3) <= reg_wp.status_full(3) AND NOT apbi.pwdata(3); |
|
609 | END LOOP all_reg_wp_status_bit; | |
582 | WHEN "011100" => reg_wp.delta_snapshot <= apbi.pwdata(delta_vector_size-1 DOWNTO 0); |
|
610 | ||
583 |
WHEN " |
|
611 | WHEN "100000" => reg_wp.delta_snapshot <= apbi.pwdata(delta_vector_size-1 DOWNTO 0); | |
584 |
WHEN " |
|
612 | WHEN "100001" => reg_wp.delta_f0 <= apbi.pwdata(delta_vector_size-1 DOWNTO 0); | |
585 |
WHEN " |
|
613 | WHEN "100010" => reg_wp.delta_f0_2 <= apbi.pwdata(delta_vector_size_f0_2-1 DOWNTO 0); | |
586 |
WHEN "1000 |
|
614 | WHEN "100011" => reg_wp.delta_f1 <= apbi.pwdata(delta_vector_size-1 DOWNTO 0); | |
587 |
WHEN "10000 |
|
615 | WHEN "100100" => reg_wp.delta_f2 <= apbi.pwdata(delta_vector_size-1 DOWNTO 0); | |
588 |
WHEN "100 |
|
616 | WHEN "100101" => reg_wp.nb_data_by_buffer <= apbi.pwdata(nb_data_by_buffer_size-1 DOWNTO 0); | |
589 |
WHEN "100 |
|
617 | WHEN "100110" => reg_wp.nb_snapshot_param <= apbi.pwdata(nb_snapshot_param_size-1 DOWNTO 0); | |
590 |
WHEN "1001 |
|
618 | WHEN "100111" => reg_wp.start_date <= apbi.pwdata(30 DOWNTO 0); | |
|
619 | ||||
|
620 | WHEN "111001" => reg_wp.length_buffer <= apbi.pwdata(25 DOWNTO 0); | |||
|
621 | ||||
|
622 | ||||
|
623 | ||||
|
624 | ||||
|
625 | ||||
|
626 | -- WHEN "100100" => reg_wp.nb_word_by_buffer <= apbi.pwdata(nb_word_by_buffer_size-1 DOWNTO 0); | |||
591 | -- |
|
627 | -- | |
592 | WHEN OTHERS => NULL; |
|
628 | WHEN OTHERS => NULL; | |
593 | END CASE; |
|
629 | END CASE; | |
@@ -622,7 +658,7 BEGIN -- beh | |||||
622 | ----------------------------------------------------------------------------- |
|
658 | ----------------------------------------------------------------------------- | |
623 | -- IRQ |
|
659 | -- IRQ | |
624 | ----------------------------------------------------------------------------- |
|
660 | ----------------------------------------------------------------------------- | |
625 |
irq_wfp_reg_s <= status_ |
|
661 | irq_wfp_reg_s <= wfp_status_buffer_ready & wfp_error_buffer_full & status_new_err; | |
626 |
|
662 | |||
627 | PROCESS (HCLK, HRESETn) |
|
663 | PROCESS (HCLK, HRESETn) | |
628 | BEGIN -- PROCESS |
|
664 | BEGIN -- PROCESS | |
@@ -706,16 +742,29 BEGIN -- beh | |||||
706 | matrix_time => matrix_time_f2); |
|
742 | matrix_time => matrix_time_f2); | |
707 |
|
743 | |||
708 | ----------------------------------------------------------------------------- |
|
744 | ----------------------------------------------------------------------------- | |
709 | debug_signal(31 DOWNTO 12) <= (OTHERS => '0'); |
|
745 | all_wfp_pointer: FOR I IN 3 DOWNTO 0 GENERATE | |
710 | debug_signal(11 DOWNTO 0) <= apbo_irq_ms & --11 |
|
746 | lpp_apbreg_wfp_pointer_fi : lpp_apbreg_ms_pointer | |
711 | reg_sp.status_error_input_fifo_write(2) &--10 |
|
747 | PORT MAP ( | |
712 | reg_sp.status_error_input_fifo_write(1) &--9 |
|
748 | clk => HCLK, | |
713 | reg_sp.status_error_input_fifo_write(0) &--8 |
|
749 | rstn => HRESETn, | |
714 | reg_sp.status_error_buffer_full & |
|
750 | ||
715 | '0' & |
|
751 | reg0_status_ready_matrix => reg_wp.status_ready_buffer_f(2*I), | |
716 | -- reg_sp.status_error_bad_component_error & --7 6 |
|
752 | reg0_ready_matrix => reg_ready_buffer_f(2*I), | |
717 | reg_sp.status_ready_matrix_f2_1 & reg_sp.status_ready_matrix_f2_0 &--5 4 |
|
753 | reg0_addr_matrix => reg_wp.addr_buffer_f((2*I+1)*32-1 DOWNTO (2*I)*32), | |
718 | reg_sp.status_ready_matrix_f1_1 & reg_sp.status_ready_matrix_f1_0 &--3 2 |
|
754 | reg0_matrix_time => reg_wp.time_buffer_f((2*I+1)*48-1 DOWNTO (2*I)*48), | |
719 | reg_sp.status_ready_matrix_f0_1 & reg_sp.status_ready_matrix_f0_0; --1 0 |
|
755 | ||
|
756 | reg1_status_ready_matrix => reg_wp.status_ready_buffer_f(2*I+1), | |||
|
757 | reg1_ready_matrix => reg_ready_buffer_f(2*I+1), | |||
|
758 | reg1_addr_matrix => reg_wp.addr_buffer_f((2*I+2)*32-1 DOWNTO (2*I+1)*32), | |||
|
759 | reg1_matrix_time => reg_wp.time_buffer_f((2*I+2)*48-1 DOWNTO (2*I+1)*48), | |||
|
760 | ||||
|
761 | ready_matrix => wfp_ready_buffer(I), | |||
|
762 | status_ready_matrix => wfp_status_buffer_ready(I), | |||
|
763 | addr_matrix => wfp_addr_buffer((I+1)*32-1 DOWNTO I*32), | |||
|
764 | matrix_time => wfp_buffer_time((I+1)*48-1 DOWNTO I*48) | |||
|
765 | ); | |||
|
766 | ||||
|
767 | END GENERATE all_wfp_pointer; | |||
|
768 | ----------------------------------------------------------------------------- | |||
720 |
|
769 | |||
721 |
END beh; |
|
770 | END beh; No newline at end of file |
@@ -258,7 +258,6 PACKAGE lpp_lfr_pkg IS | |||||
258 | COMPONENT lpp_lfr_apbreg |
|
258 | COMPONENT lpp_lfr_apbreg | |
259 | GENERIC ( |
|
259 | GENERIC ( | |
260 | nb_data_by_buffer_size : INTEGER; |
|
260 | nb_data_by_buffer_size : INTEGER; | |
261 | nb_word_by_buffer_size : INTEGER; |
|
|||
262 | nb_snapshot_param_size : INTEGER; |
|
261 | nb_snapshot_param_size : INTEGER; | |
263 | delta_vector_size : INTEGER; |
|
262 | delta_vector_size : INTEGER; | |
264 | delta_vector_size_f0_2 : INTEGER; |
|
263 | delta_vector_size_f0_2 : INTEGER; | |
@@ -269,60 +268,57 PACKAGE lpp_lfr_pkg IS | |||||
269 | pirq_wfp : INTEGER; |
|
268 | pirq_wfp : INTEGER; | |
270 | top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0)); |
|
269 | top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0)); | |
271 | PORT ( |
|
270 | PORT ( | |
272 | HCLK : IN STD_ULOGIC; |
|
271 | HCLK : IN STD_ULOGIC; | |
273 | HRESETn : IN STD_ULOGIC; |
|
272 | HRESETn : IN STD_ULOGIC; | |
274 | apbi : IN apb_slv_in_type; |
|
273 | apbi : IN apb_slv_in_type; | |
275 | apbo : OUT apb_slv_out_type; |
|
274 | apbo : OUT apb_slv_out_type; | |
276 | run_ms : OUT STD_LOGIC; |
|
275 | run_ms : OUT STD_LOGIC; | |
277 | ready_matrix_f0 : IN STD_LOGIC; |
|
276 | ready_matrix_f0 : IN STD_LOGIC; | |
278 | ready_matrix_f1 : IN STD_LOGIC; |
|
277 | ready_matrix_f1 : IN STD_LOGIC; | |
279 | ready_matrix_f2 : IN STD_LOGIC; |
|
278 | ready_matrix_f2 : IN STD_LOGIC; | |
280 | error_buffer_full : IN STD_LOGIC; |
|
279 | error_buffer_full : IN STD_LOGIC; | |
281 | error_input_fifo_write : IN STD_LOGIC_VECTOR(2 DOWNTO 0); |
|
280 | error_input_fifo_write : IN STD_LOGIC_VECTOR(2 DOWNTO 0); | |
282 | status_ready_matrix_f0 : OUT STD_LOGIC; |
|
281 | status_ready_matrix_f0 : OUT STD_LOGIC; | |
283 | status_ready_matrix_f1 : OUT STD_LOGIC; |
|
282 | status_ready_matrix_f1 : OUT STD_LOGIC; | |
284 | status_ready_matrix_f2 : OUT STD_LOGIC; |
|
283 | status_ready_matrix_f2 : OUT STD_LOGIC; | |
285 | addr_matrix_f0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
284 | addr_matrix_f0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
286 | addr_matrix_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
285 | addr_matrix_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
287 | addr_matrix_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
286 | addr_matrix_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
288 | length_matrix_f0 : OUT STD_LOGIC_VECTOR(25 DOWNTO 0); |
|
287 | length_matrix_f0 : OUT STD_LOGIC_VECTOR(25 DOWNTO 0); | |
289 | length_matrix_f1 : OUT STD_LOGIC_VECTOR(25 DOWNTO 0); |
|
288 | length_matrix_f1 : OUT STD_LOGIC_VECTOR(25 DOWNTO 0); | |
290 | length_matrix_f2 : OUT STD_LOGIC_VECTOR(25 DOWNTO 0); |
|
289 | length_matrix_f2 : OUT STD_LOGIC_VECTOR(25 DOWNTO 0); | |
291 | matrix_time_f0 : IN STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
290 | matrix_time_f0 : IN STD_LOGIC_VECTOR(47 DOWNTO 0); | |
292 | matrix_time_f1 : IN STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
291 | matrix_time_f1 : IN STD_LOGIC_VECTOR(47 DOWNTO 0); | |
293 | matrix_time_f2 : IN STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
292 | matrix_time_f2 : IN STD_LOGIC_VECTOR(47 DOWNTO 0); | |
294 |
status_ |
|
293 | status_new_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0); | |
295 |
|
|
294 | data_shaping_BW : OUT STD_LOGIC; | |
296 | status_full_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
295 | data_shaping_SP0 : OUT STD_LOGIC; | |
297 | status_new_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
296 | data_shaping_SP1 : OUT STD_LOGIC; | |
298 |
data_shaping_ |
|
297 | data_shaping_R0 : OUT STD_LOGIC; | |
299 |
data_shaping_ |
|
298 | data_shaping_R1 : OUT STD_LOGIC; | |
300 |
data_shaping_ |
|
299 | data_shaping_R2 : OUT STD_LOGIC; | |
301 | data_shaping_R0 : OUT STD_LOGIC; |
|
300 | delta_snapshot : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); | |
302 | data_shaping_R1 : OUT STD_LOGIC; |
|
301 | delta_f0 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); | |
303 | data_shaping_R2 : OUT STD_LOGIC; |
|
302 | delta_f0_2 : OUT STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0); | |
304 |
delta_ |
|
303 | delta_f1 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); | |
305 |
delta_f |
|
304 | delta_f2 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); | |
306 |
|
|
305 | nb_data_by_buffer : OUT STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0); | |
307 |
|
|
306 | nb_snapshot_param : OUT STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0); | |
308 |
|
|
307 | enable_f0 : OUT STD_LOGIC; | |
309 | nb_data_by_buffer : OUT STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0); |
|
308 | enable_f1 : OUT STD_LOGIC; | |
310 | nb_word_by_buffer : OUT STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0); |
|
309 | enable_f2 : OUT STD_LOGIC; | |
311 | nb_snapshot_param : OUT STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0); |
|
310 | enable_f3 : OUT STD_LOGIC; | |
312 |
|
|
311 | burst_f0 : OUT STD_LOGIC; | |
313 |
|
|
312 | burst_f1 : OUT STD_LOGIC; | |
314 |
|
|
313 | burst_f2 : OUT STD_LOGIC; | |
315 |
|
|
314 | run : OUT STD_LOGIC; | |
316 |
|
|
315 | start_date : OUT STD_LOGIC_VECTOR(30 DOWNTO 0); | |
317 | burst_f1 : OUT STD_LOGIC; |
|
316 | wfp_status_buffer_ready : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); | |
318 |
bur |
|
317 | wfp_addr_buffer : OUT STD_LOGIC_VECTOR(32*4 DOWNTO 0); | |
319 | run : OUT STD_LOGIC; |
|
318 | wfp_length_buffer : OUT STD_LOGIC_VECTOR(25 DOWNTO 0); | |
320 |
|
|
319 | wfp_ready_buffer : IN STD_LOGIC_VECTOR(3 DOWNTO 0); | |
321 |
|
|
320 | wfp_buffer_time : IN STD_LOGIC_VECTOR(48*4-1 DOWNTO 0); | |
322 |
|
|
321 | wfp_error_buffer_full : IN STD_LOGIC_VECTOR(3 DOWNTO 0)); | |
323 | addr_data_f3 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
|||
324 | start_date : OUT STD_LOGIC_VECTOR(30 DOWNTO 0); |
|
|||
325 | debug_signal : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)); |
|
|||
326 | END COMPONENT; |
|
322 | END COMPONENT; | |
327 |
|
323 | |||
328 | COMPONENT lpp_top_ms |
|
324 | COMPONENT lpp_top_ms |
@@ -44,7 +44,7 ENTITY lpp_waveform IS | |||||
44 | tech : INTEGER := inferred; |
|
44 | tech : INTEGER := inferred; | |
45 | data_size : INTEGER := 96; --16*6 |
|
45 | data_size : INTEGER := 96; --16*6 | |
46 | nb_data_by_buffer_size : INTEGER := 11; |
|
46 | nb_data_by_buffer_size : INTEGER := 11; | |
47 | nb_word_by_buffer_size : INTEGER := 11; |
|
47 | -- nb_word_by_buffer_size : INTEGER := 11; | |
48 | nb_snapshot_param_size : INTEGER := 11; |
|
48 | nb_snapshot_param_size : INTEGER := 11; | |
49 | delta_vector_size : INTEGER := 20; |
|
49 | delta_vector_size : INTEGER := 20; | |
50 | delta_vector_size_f0_2 : INTEGER := 3); |
|
50 | delta_vector_size_f0_2 : INTEGER := 3); | |
@@ -76,31 +76,36 ENTITY lpp_waveform IS | |||||
76 | burst_f2 : IN STD_LOGIC; |
|
76 | burst_f2 : IN STD_LOGIC; | |
77 |
|
77 | |||
78 | nb_data_by_buffer : IN STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0); |
|
78 | nb_data_by_buffer : IN STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0); | |
79 | nb_word_by_buffer : IN STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0); |
|
79 | -- nb_word_by_buffer : IN STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0); | |
80 | nb_snapshot_param : IN STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0); |
|
80 | nb_snapshot_param : IN STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0); | |
81 | status_full : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
81 | ||
82 | status_full_ack : IN STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
|||
83 | status_full_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
|||
84 | status_new_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); -- New data f(i) before the current data is write by dma |
|
82 | status_new_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); -- New data f(i) before the current data is write by dma | |
|
83 | ||||
|
84 | ||||
|
85 | -- REG DMA | |||
|
86 | status_buffer_ready : IN STD_LOGIC_VECTOR(3 DOWNTO 0); | |||
|
87 | addr_buffer : IN STD_LOGIC_VECTOR(32*4 DOWNTO 0); | |||
|
88 | length_buffer : IN STD_LOGIC_VECTOR(25 DOWNTO 0); | |||
|
89 | ||||
|
90 | ready_buffer : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); | |||
|
91 | buffer_time : OUT STD_LOGIC_VECTOR(48*4-1 DOWNTO 0); | |||
|
92 | error_buffer_full : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); | |||
|
93 | ||||
85 |
|
|
94 | --------------------------------------------------------------------------- | |
86 | -- INPUT |
|
95 | -- INPUT | |
87 | coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
96 | coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
88 | fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); |
|
97 | fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); | |
89 |
|
98 | |||
90 | --f0 |
|
99 | --f0 | |
91 | addr_data_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
|||
92 | data_f0_in_valid : IN STD_LOGIC; |
|
100 | data_f0_in_valid : IN STD_LOGIC; | |
93 | data_f0_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); |
|
101 | data_f0_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); | |
94 | --f1 |
|
102 | --f1 | |
95 | addr_data_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
|||
96 | data_f1_in_valid : IN STD_LOGIC; |
|
103 | data_f1_in_valid : IN STD_LOGIC; | |
97 | data_f1_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); |
|
104 | data_f1_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); | |
98 | --f2 |
|
105 | --f2 | |
99 | addr_data_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
|||
100 | data_f2_in_valid : IN STD_LOGIC; |
|
106 | data_f2_in_valid : IN STD_LOGIC; | |
101 | data_f2_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); |
|
107 | data_f2_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); | |
102 | --f3 |
|
108 | --f3 | |
103 | addr_data_f3 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
|||
104 | data_f3_in_valid : IN STD_LOGIC; |
|
109 | data_f3_in_valid : IN STD_LOGIC; | |
105 | data_f3_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); |
|
110 | data_f3_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); | |
106 |
|
111 | |||
@@ -110,7 +115,7 ENTITY lpp_waveform IS | |||||
110 | dma_fifo_valid_burst : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
115 | dma_fifo_valid_burst : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); | |
111 | dma_fifo_data : OUT STD_LOGIC_VECTOR(32*4-1 DOWNTO 0); |
|
116 | dma_fifo_data : OUT STD_LOGIC_VECTOR(32*4-1 DOWNTO 0); | |
112 | dma_fifo_ren : IN STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
117 | dma_fifo_ren : IN STD_LOGIC_VECTOR(3 DOWNTO 0); | |
113 |
dma_buffer_new : |
|
118 | dma_buffer_new : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); | |
114 | dma_buffer_addr : OUT STD_LOGIC_VECTOR(32*4-1 DOWNTO 0); |
|
119 | dma_buffer_addr : OUT STD_LOGIC_VECTOR(32*4-1 DOWNTO 0); | |
115 | dma_buffer_length : OUT STD_LOGIC_VECTOR(26*4-1 DOWNTO 0); |
|
120 | dma_buffer_length : OUT STD_LOGIC_VECTOR(26*4-1 DOWNTO 0); | |
116 | dma_buffer_full : IN STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
121 | dma_buffer_full : IN STD_LOGIC_VECTOR(3 DOWNTO 0); | |
@@ -178,9 +183,10 ARCHITECTURE beh OF lpp_waveform IS | |||||
178 | SIGNAL s_rdata_v : STD_LOGIC_VECTOR(32*4-1 DOWNTO 0); |
|
183 | SIGNAL s_rdata_v : STD_LOGIC_VECTOR(32*4-1 DOWNTO 0); | |
179 |
|
184 | |||
180 | -- |
|
185 | -- | |
|
186 | SIGNAL arbiter_time_out : STD_LOGIC_VECTOR(47 DOWNTO 0); | |||
|
187 | SIGNAL arbiter_time_out_new : STD_LOGIC_VECTOR(3 DOWNTO 0); | |||
181 |
|
188 | |||
182 |
SIGNAL |
|
189 | SIGNAL fifo_buffer_time : STD_LOGIC_VECTOR(48*4-1 DOWNTO 0); | |
183 |
|
||||
184 |
|
190 | |||
185 | BEGIN -- beh |
|
191 | BEGIN -- beh | |
186 |
|
192 | |||
@@ -357,19 +363,6 BEGIN -- beh | |||||
357 | END GENERATE all_sample_of_time_out; |
|
363 | END GENERATE all_sample_of_time_out; | |
358 | END GENERATE all_bit_of_time_out; |
|
364 | END GENERATE all_bit_of_time_out; | |
359 |
|
365 | |||
360 | -- DEBUG -- |
|
|||
361 | --time_out_debug(0) <= x"0A0A" & x"0A0A0A0A"; |
|
|||
362 | --time_out_debug(1) <= x"1B1B" & x"1B1B1B1B"; |
|
|||
363 | --time_out_debug(2) <= x"2C2C" & x"2C2C2C2C"; |
|
|||
364 | --time_out_debug(3) <= x"3D3D" & x"3D3D3D3D"; |
|
|||
365 |
|
||||
366 | --all_bit_of_time_out : FOR I IN 47 DOWNTO 0 GENERATE |
|
|||
367 | -- all_sample_of_time_out : FOR J IN 3 DOWNTO 0 GENERATE |
|
|||
368 | -- time_out_2(J, I) <= time_out_debug(J)(I); |
|
|||
369 | -- END GENERATE all_sample_of_time_out; |
|
|||
370 | --END GENERATE all_bit_of_time_out; |
|
|||
371 | -- DEBUG -- |
|
|||
372 |
|
||||
373 | lpp_waveform_fifo_arbiter_1 : lpp_waveform_fifo_arbiter |
|
366 | lpp_waveform_fifo_arbiter_1 : lpp_waveform_fifo_arbiter | |
374 | GENERIC MAP (tech => tech, |
|
367 | GENERIC MAP (tech => tech, | |
375 | nb_data_by_buffer_size => nb_data_by_buffer_size) |
|
368 | nb_data_by_buffer_size => nb_data_by_buffer_size) | |
@@ -386,62 +379,16 BEGIN -- beh | |||||
386 | data_out => wdata, |
|
379 | data_out => wdata, | |
387 | data_out_wen => data_wen, |
|
380 | data_out_wen => data_wen, | |
388 | full_almost => full_almost, |
|
381 | full_almost => full_almost, | |
389 |
full => full |
|
382 | full => full, | |
|
383 | ||||
|
384 | time_out => arbiter_time_out, | |||
|
385 | time_out_new => arbiter_time_out_new | |||
|
386 | ||||
|
387 | ); | |||
390 |
|
388 | |||
391 | ----------------------------------------------------------------------------- |
|
389 | ----------------------------------------------------------------------------- | |
392 | -- DEBUG -- SNAPSHOT IN |
|
|||
393 | --debug_f0_data_fifo_in_valid <= NOT data_wen(0); |
|
|||
394 | --debug_f0_data_fifo_in <= wdata; |
|
|||
395 | --debug_f1_data_fifo_in_valid <= NOT data_wen(1); |
|
|||
396 | --debug_f1_data_fifo_in <= wdata; |
|
|||
397 | --debug_f2_data_fifo_in_valid <= NOT data_wen(2); |
|
|||
398 | --debug_f2_data_fifo_in <= wdata; |
|
|||
399 | --debug_f3_data_fifo_in_valid <= NOT data_wen(3); |
|
|||
400 | --debug_f3_data_fifo_in <= wdata;s |
|
|||
401 | ----------------------------------------------------------------------------- |
|
390 | ----------------------------------------------------------------------------- | |
402 |
|
391 | |||
403 |
|
||||
404 | -- lpp_fifo_4_shared_1: lpp_fifo_4_shared |
|
|||
405 | -- GENERIC MAP ( |
|
|||
406 | -- tech => tech, |
|
|||
407 | -- Mem_use => use_RAM, |
|
|||
408 | -- EMPTY_ALMOST_LIMIT => 16, |
|
|||
409 | -- FULL_ALMOST_LIMIT => 5, |
|
|||
410 | -- DataSz => 32, |
|
|||
411 | -- AddrSz => 7 |
|
|||
412 | -- ) |
|
|||
413 | -- PORT MAP ( |
|
|||
414 | -- clk => clk, |
|
|||
415 | -- rstn => rstn, |
|
|||
416 | -- run => run, |
|
|||
417 | -- empty_almost => s_empty_almost, |
|
|||
418 | -- empty => s_empty, |
|
|||
419 | -- r_en => s_data_ren, |
|
|||
420 | -- r_data => s_rdata, |
|
|||
421 | -- full_almost => full_almost, |
|
|||
422 | -- full => full, |
|
|||
423 | -- w_en => data_wen, |
|
|||
424 | -- w_data => wdata); |
|
|||
425 |
|
||||
426 | --lpp_waveform_fifo_headreg_1 : lpp_fifo_4_shared_headreg_latency_1 |
|
|||
427 | -- PORT MAP ( |
|
|||
428 | -- clk => clk, |
|
|||
429 | -- rstn => rstn, |
|
|||
430 | -- run => run, |
|
|||
431 | -- o_empty_almost => empty_almost, |
|
|||
432 | -- o_empty => empty, |
|
|||
433 |
|
||||
434 | -- o_data_ren => data_ren, |
|
|||
435 | -- o_rdata_0 => data_f0_data_out, |
|
|||
436 | -- o_rdata_1 => data_f1_data_out, |
|
|||
437 | -- o_rdata_2 => data_f2_data_out, |
|
|||
438 | -- o_rdata_3 => data_f3_data_out, |
|
|||
439 |
|
||||
440 | -- i_empty_almost => s_empty_almost, |
|
|||
441 | -- i_empty => s_empty, |
|
|||
442 | -- i_data_ren => s_data_ren, |
|
|||
443 | -- i_rdata => s_rdata); |
|
|||
444 |
|
||||
445 | generate_all_fifo: FOR I IN 0 TO 3 GENERATE |
|
392 | generate_all_fifo: FOR I IN 0 TO 3 GENERATE | |
446 | lpp_fifo_1: lpp_fifo |
|
393 | lpp_fifo_1: lpp_fifo | |
447 | GENERIC MAP ( |
|
394 | GENERIC MAP ( | |
@@ -468,86 +415,34 BEGIN -- beh | |||||
468 |
|
415 | |||
469 | END GENERATE generate_all_fifo; |
|
416 | END GENERATE generate_all_fifo; | |
470 |
|
417 | |||
471 |
|
||||
472 | ----empty <= s_empty; |
|
|||
473 | ----empty_almost <= s_empty_almost; |
|
|||
474 | ----s_data_ren <= data_ren; |
|
|||
475 |
|
||||
476 | --data_f0_data_out <= s_rdata_v(31 downto 0); |
|
|||
477 | --data_f1_data_out <= s_rdata_v(31+32 downto 0+32); |
|
|||
478 | --data_f2_data_out <= s_rdata_v(31+32*2 downto 32*2); |
|
|||
479 | --data_f3_data_out <= s_rdata_v(31+32*3 downto 32*3); |
|
|||
480 |
|
||||
481 | --data_ren <= data_f3_data_out_ren & |
|
|||
482 | -- data_f2_data_out_ren & |
|
|||
483 | -- data_f1_data_out_ren & |
|
|||
484 | -- data_f0_data_out_ren; |
|
|||
485 |
|
||||
486 | --lpp_waveform_gen_address_1 : lpp_waveform_genaddress |
|
|||
487 | -- GENERIC MAP ( |
|
|||
488 | -- nb_data_by_buffer_size => nb_word_by_buffer_size) |
|
|||
489 | -- PORT MAP ( |
|
|||
490 | -- clk => clk, |
|
|||
491 | -- rstn => rstn, |
|
|||
492 | -- run => run, |
|
|||
493 |
|
||||
494 | -- ------------------------------------------------------------------------- |
|
|||
495 | -- -- CONFIG |
|
|||
496 | -- ------------------------------------------------------------------------- |
|
|||
497 | -- nb_data_by_buffer => nb_word_by_buffer, |
|
|||
498 |
|
||||
499 | -- addr_data_f0 => addr_data_f0, |
|
|||
500 | -- addr_data_f1 => addr_data_f1, |
|
|||
501 | -- addr_data_f2 => addr_data_f2, |
|
|||
502 | -- addr_data_f3 => addr_data_f3, |
|
|||
503 | -- ------------------------------------------------------------------------- |
|
|||
504 | -- -- CTRL |
|
|||
505 | -- ------------------------------------------------------------------------- |
|
|||
506 | -- -- IN |
|
|||
507 | -- empty => empty, |
|
|||
508 | -- empty_almost => empty_almost, |
|
|||
509 | -- data_ren => data_ren, |
|
|||
510 |
|
||||
511 | -- ------------------------------------------------------------------------- |
|
|||
512 | -- -- STATUS |
|
|||
513 | -- ------------------------------------------------------------------------- |
|
|||
514 | -- status_full => status_full_s, |
|
|||
515 | -- status_full_ack => status_full_ack, |
|
|||
516 | -- status_full_err => status_full_err, |
|
|||
517 |
|
||||
518 | -- ------------------------------------------------------------------------- |
|
|||
519 | -- -- ADDR DATA OUT |
|
|||
520 | -- ------------------------------------------------------------------------- |
|
|||
521 | -- data_f0_data_out_valid_burst => data_f0_data_out_valid_burst, |
|
|||
522 | -- data_f1_data_out_valid_burst => data_f1_data_out_valid_burst, |
|
|||
523 | -- data_f2_data_out_valid_burst => data_f2_data_out_valid_burst, |
|
|||
524 | -- data_f3_data_out_valid_burst => data_f3_data_out_valid_burst, |
|
|||
525 |
|
||||
526 | -- data_f0_data_out_valid => data_f0_data_out_valid, |
|
|||
527 | -- data_f1_data_out_valid => data_f1_data_out_valid, |
|
|||
528 | -- data_f2_data_out_valid => data_f2_data_out_valid, |
|
|||
529 | -- data_f3_data_out_valid => data_f3_data_out_valid, |
|
|||
530 |
|
||||
531 | -- data_f0_addr_out => data_f0_addr_out, |
|
|||
532 | -- data_f1_addr_out => data_f1_addr_out, |
|
|||
533 | -- data_f2_addr_out => data_f2_addr_out, |
|
|||
534 | -- data_f3_addr_out => data_f3_addr_out |
|
|||
535 | -- ); |
|
|||
536 | --status_full <= status_full_s; |
|
|||
537 |
|
||||
538 |
|
||||
539 | ----------------------------------------------------------------------------- |
|
418 | ----------------------------------------------------------------------------- | |
540 | -- |
|
419 | -- | |
541 | ----------------------------------------------------------------------------- |
|
420 | ----------------------------------------------------------------------------- | |
542 |
|
421 | |||
543 | all_channel: FOR I IN 3 DOWNTO 0 GENERATE |
|
422 | all_channel: FOR I IN 3 DOWNTO 0 GENERATE | |
|
423 | ||||
|
424 | PROCESS (clk, rstn) | |||
|
425 | BEGIN | |||
|
426 | IF rstn = '0' THEN | |||
|
427 | fifo_buffer_time(48*(I+1)-1 DOWNTO 48*I) <= (OTHERS => '0'); | |||
|
428 | ELSIF clk'event AND clk = '1' THEN | |||
|
429 | IF run = '0' THEN | |||
|
430 | fifo_buffer_time(48*(I+1)-1 DOWNTO 48*I) <= (OTHERS => '0'); | |||
|
431 | ELSE | |||
|
432 | IF arbiter_time_out_new(I) = '0' THEN | |||
|
433 | fifo_buffer_time(48*(I+1)-1 DOWNTO 48*I) <= arbiter_time_out; | |||
|
434 | END IF; | |||
|
435 | END IF; | |||
|
436 | END IF; | |||
|
437 | END PROCESS; | |||
|
438 | ||||
544 |
|
|
439 | lpp_waveform_fsmdma_I: lpp_waveform_fsmdma | |
545 | PORT MAP ( |
|
440 | PORT MAP ( | |
546 | clk => clk, |
|
441 | clk => clk, | |
547 | rstn => rstn, |
|
442 | rstn => rstn, | |
548 | run => run, |
|
443 | run => run, | |
549 |
|
444 | |||
550 |
fifo_buffer_time => fifo_buffer_time(48*(I+1)-1 DOWNTO 48*I), |
|
445 | fifo_buffer_time => fifo_buffer_time(48*(I+1)-1 DOWNTO 48*I), | |
551 |
|
446 | |||
552 | fifo_data => s_rdata_v(32*(I+1)-1 DOWNTO 32*I), |
|
447 | fifo_data => s_rdata_v(32*(I+1)-1 DOWNTO 32*I), | |
553 | fifo_empty => empty(I), |
|
448 | fifo_empty => empty(I), | |
@@ -565,7 +460,7 BEGIN -- beh | |||||
565 |
|
460 | |||
566 | status_buffer_ready => status_buffer_ready(I), -- TODO |
|
461 | status_buffer_ready => status_buffer_ready(I), -- TODO | |
567 | addr_buffer => addr_buffer(32*(I+1)-1 DOWNTO 32*I), -- TODO |
|
462 | addr_buffer => addr_buffer(32*(I+1)-1 DOWNTO 32*I), -- TODO | |
568 |
length_buffer => length_buffer |
|
463 | length_buffer => length_buffer,--(26*(I+1)-1 DOWNTO 26*I), -- TODO | |
569 | ready_buffer => ready_buffer(I), -- TODO |
|
464 | ready_buffer => ready_buffer(I), -- TODO | |
570 | buffer_time => buffer_time(48*(I+1)-1 DOWNTO 48*I), -- TODO |
|
465 | buffer_time => buffer_time(48*(I+1)-1 DOWNTO 48*I), -- TODO | |
571 | error_buffer_full => error_buffer_full(I)); -- TODO |
|
466 | error_buffer_full => error_buffer_full(I)); -- TODO |
@@ -37,7 +37,7 ENTITY lpp_waveform_dma_genvalid IS | |||||
37 | valid_in : IN STD_LOGIC; |
|
37 | valid_in : IN STD_LOGIC; | |
38 | time_in : IN STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
38 | time_in : IN STD_LOGIC_VECTOR(47 DOWNTO 0); | |
39 |
|
39 | |||
40 | ack_in : IN STD_LOGIC; |
|
40 | ack_in : IN STD_LOGIC; | |
41 | valid_out : OUT STD_LOGIC; |
|
41 | valid_out : OUT STD_LOGIC; | |
42 | time_out : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
42 | time_out : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); | |
43 | error : OUT STD_LOGIC |
|
43 | error : OUT STD_LOGIC | |
@@ -55,25 +55,21 BEGIN | |||||
55 | state <= IDLE; |
|
55 | state <= IDLE; | |
56 | valid_out <= '0'; |
|
56 | valid_out <= '0'; | |
57 | error <= '0'; |
|
57 | error <= '0'; | |
58 | time_out <= (OTHERS => '0'); |
|
58 | time_out <= (OTHERS => '0'); | |
59 | ELSIF HCLK'EVENT AND HCLK = '1' THEN |
|
59 | ELSIF HCLK'EVENT AND HCLK = '1' THEN | |
60 | CASE state IS |
|
60 | IF run = '1' THEN | |
61 | WHEN IDLE => |
|
61 | CASE state IS | |
62 |
|
62 | WHEN IDLE => | ||
63 |
|
|
63 | ||
64 | error <= '0'; |
|
64 | valid_out <= valid_in; | |
65 | IF run = '1' AND valid_in = '1' THEN |
|
65 | error <= '0'; | |
66 | state <= VALID; |
|
|||
67 | valid_out <= '1'; |
|
|||
68 | time_out <= time_in; |
|
66 | time_out <= time_in; | |
69 | END IF; |
|
|||
70 |
|
67 | |||
71 | WHEN VALID => |
|
68 | IF valid_in = '1' THEN | |
72 | IF run = '0' THEN |
|
69 | state <= VALID; | |
73 |
|
|
70 | END IF; | |
74 | valid_out <= '0'; |
|
71 | ||
75 | error <= '0'; |
|
72 | WHEN VALID => | |
76 | ELSE |
|
|||
77 | IF valid_in = '1' THEN |
|
73 | IF valid_in = '1' THEN | |
78 | IF ack_in = '1' THEN |
|
74 | IF ack_in = '1' THEN | |
79 | state <= VALID; |
|
75 | state <= VALID; | |
@@ -88,10 +84,16 BEGIN | |||||
88 | state <= IDLE; |
|
84 | state <= IDLE; | |
89 | valid_out <= '0'; |
|
85 | valid_out <= '0'; | |
90 | END IF; |
|
86 | END IF; | |
91 |
|
|
87 | ||
92 |
|
88 | WHEN OTHERS => NULL; | ||
93 | WHEN OTHERS => NULL; |
|
89 | END CASE; | |
94 | END CASE; |
|
90 | ||
|
91 | ELSE | |||
|
92 | state <= IDLE; | |||
|
93 | valid_out <= '0'; | |||
|
94 | error <= '0'; | |||
|
95 | time_out <= (OTHERS => '0'); | |||
|
96 | END IF; | |||
95 | END IF; |
|
97 | END IF; | |
96 | END PROCESS FSM_SELECT_ADDRESS; |
|
98 | END PROCESS FSM_SELECT_ADDRESS; | |
97 |
|
99 |
@@ -44,6 +44,7 ENTITY lpp_waveform_fifo_arbiter IS | |||||
44 | data_in_valid : IN STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
44 | data_in_valid : IN STD_LOGIC_VECTOR(3 DOWNTO 0); | |
45 | data_in_ack : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
45 | data_in_ack : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); | |
46 | data_in : IN Data_Vector(3 DOWNTO 0, 95 DOWNTO 0); |
|
46 | data_in : IN Data_Vector(3 DOWNTO 0, 95 DOWNTO 0); | |
|
47 | ||||
47 |
|
|
48 | time_in : IN Data_Vector(3 DOWNTO 0, 47 DOWNTO 0); | |
48 |
|
49 | |||
49 | --------------------------------------------------------------------------- |
|
50 | --------------------------------------------------------------------------- | |
@@ -52,29 +53,31 ENTITY lpp_waveform_fifo_arbiter IS | |||||
52 | data_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
53 | data_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
53 | data_out_wen : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
54 | data_out_wen : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); | |
54 | full_almost : IN STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
55 | full_almost : IN STD_LOGIC_VECTOR(3 DOWNTO 0); | |
55 | full : IN STD_LOGIC_VECTOR(3 DOWNTO 0) |
|
56 | full : IN STD_LOGIC_VECTOR(3 DOWNTO 0); | |
|
57 | ||||
|
58 | --------------------------------------------------------------------------- | |||
|
59 | -- TIME INTERFACE (OUTPUT) | |||
|
60 | --------------------------------------------------------------------------- | |||
|
61 | time_out : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); | |||
|
62 | time_out_new : OUT STD_LOGIC_VECTOR(3 DOWNTO 0) | |||
56 |
|
|
63 | ||
57 |
|
|
64 | ); | |
58 | END ENTITY; |
|
65 | END ENTITY; | |
59 |
|
66 | |||
60 |
|
67 | |||
61 | ARCHITECTURE ar_lpp_waveform_fifo_arbiter OF lpp_waveform_fifo_arbiter IS |
|
68 | ARCHITECTURE ar_lpp_waveform_fifo_arbiter OF lpp_waveform_fifo_arbiter IS | |
62 |
TYPE state_type_fifo_arbiter IS (IDLE, |
|
69 | TYPE state_type_fifo_arbiter IS (IDLE,DATA1,DATA2,DATA3,LAST); | |
63 | SIGNAL state : state_type_fifo_arbiter; |
|
70 | SIGNAL state : state_type_fifo_arbiter; | |
64 |
|
71 | |||
65 | ----------------------------------------------------------------------------- |
|
72 | ----------------------------------------------------------------------------- | |
66 | -- DATA MUX |
|
73 | -- DATA MUX | |
67 | ----------------------------------------------------------------------------- |
|
74 | ----------------------------------------------------------------------------- | |
68 | SIGNAL data_0_v : STD_LOGIC_VECTOR(32*5-1 DOWNTO 0); |
|
|||
69 | SIGNAL data_1_v : STD_LOGIC_VECTOR(32*5-1 DOWNTO 0); |
|
|||
70 | SIGNAL data_2_v : STD_LOGIC_VECTOR(32*5-1 DOWNTO 0); |
|
|||
71 | SIGNAL data_3_v : STD_LOGIC_VECTOR(32*5-1 DOWNTO 0); |
|
|||
72 | TYPE WORD_VECTOR IS ARRAY (NATURAL RANGE <>) OF STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
75 | TYPE WORD_VECTOR IS ARRAY (NATURAL RANGE <>) OF STD_LOGIC_VECTOR(31 DOWNTO 0); | |
73 |
SIGNAL data_0 : WORD_VECTOR( |
|
76 | SIGNAL data_0 : WORD_VECTOR(3 DOWNTO 0); | |
74 |
SIGNAL data_1 : WORD_VECTOR( |
|
77 | SIGNAL data_1 : WORD_VECTOR(3 DOWNTO 0); | |
75 |
SIGNAL data_2 : WORD_VECTOR( |
|
78 | SIGNAL data_2 : WORD_VECTOR(3 DOWNTO 0); | |
76 |
SIGNAL data_3 : WORD_VECTOR( |
|
79 | SIGNAL data_3 : WORD_VECTOR(3 DOWNTO 0); | |
77 |
SIGNAL data_sel : WORD_VECTOR( |
|
80 | SIGNAL data_sel : WORD_VECTOR(3 DOWNTO 0); | |
78 |
|
81 | |||
79 | ----------------------------------------------------------------------------- |
|
82 | ----------------------------------------------------------------------------- | |
80 | -- RR and SELECTION |
|
83 | -- RR and SELECTION | |
@@ -92,14 +95,8 ARCHITECTURE ar_lpp_waveform_fifo_arbite | |||||
92 | SIGNAL count_enable : STD_LOGIC; |
|
95 | SIGNAL count_enable : STD_LOGIC; | |
93 | SIGNAL count : STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0); |
|
96 | SIGNAL count : STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0); | |
94 | SIGNAL count_s : STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0); |
|
97 | SIGNAL count_s : STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0); | |
95 |
|
98 | |||
96 | --SIGNAL shift_data_enable : STD_LOGIC; |
|
99 | SIGNAL time_sel : STD_LOGIC_VECTOR(47 DOWNTO 0); | |
97 | --SIGNAL shift_data : STD_LOGIC_VECTOR(1 DOWNTO 0); |
|
|||
98 | --SIGNAL shift_data_s : STD_LOGIC_VECTOR(1 DOWNTO 0); |
|
|||
99 |
|
||||
100 | --SIGNAL shift_time_enable : STD_LOGIC; |
|
|||
101 | --SIGNAL shift_time : STD_LOGIC_VECTOR(1 DOWNTO 0); |
|
|||
102 | --SIGNAL shift_time_s : STD_LOGIC_VECTOR(1 DOWNTO 0); |
|
|||
103 |
|
100 | |||
104 | BEGIN |
|
101 | BEGIN | |
105 |
|
102 | |||
@@ -113,44 +110,40 BEGIN | |||||
113 | data_in_ack <= (OTHERS => '0'); |
|
110 | data_in_ack <= (OTHERS => '0'); | |
114 | data_out_wen <= (OTHERS => '1'); |
|
111 | data_out_wen <= (OTHERS => '1'); | |
115 | sel_ack <= '0'; |
|
112 | sel_ack <= '0'; | |
116 | state <= IDLE; |
|
113 | state <= IDLE; | |
|
114 | time_out <= (OTHERS => '0'); | |||
|
115 | time_out_new <= (OTHERS => '0'); | |||
117 | ELSIF clk'event AND clk = '1' THEN -- rising clock edge |
|
116 | ELSIF clk'event AND clk = '1' THEN -- rising clock edge | |
118 | count_enable <= '0'; |
|
117 | count_enable <= '0'; | |
119 | data_in_ack <= (OTHERS => '0'); |
|
118 | data_in_ack <= (OTHERS => '0'); | |
120 | data_out_wen <= (OTHERS => '1'); |
|
119 | data_out_wen <= (OTHERS => '1'); | |
121 | sel_ack <= '0'; |
|
120 | sel_ack <= '0'; | |
|
121 | time_out_new <= (OTHERS => '0'); | |||
122 | IF run = '0' THEN |
|
122 | IF run = '0' THEN | |
123 | state <= IDLE; |
|
123 | state <= IDLE; | |
|
124 | time_out <= (OTHERS => '0'); | |||
124 | ELSE |
|
125 | ELSE | |
125 | CASE state IS |
|
126 | CASE state IS | |
126 | WHEN IDLE => |
|
127 | WHEN IDLE => | |
127 | IF no_sel = '0' THEN |
|
128 | IF no_sel = '0' THEN | |
128 |
state <= |
|
129 | state <= DATA1; | |
129 | END IF; |
|
130 | END IF; | |
130 |
WHEN |
|
131 | WHEN DATA1 => | |
131 | count_enable <= '1'; |
|
132 | count_enable <= '1'; | |
132 | IF UNSIGNED(count) = 0 THEN |
|
133 | IF UNSIGNED(count) = 0 THEN | |
133 |
|
|
134 | time_out <= time_sel; | |
134 |
|
|
135 | time_out_new <= sel; | |
135 | data_out <= data_sel(0); |
|
|||
136 | ELSE |
|
|||
137 | state <= DATA1; |
|
|||
138 | END IF; |
|
136 | END IF; | |
139 | WHEN TIME2 => |
|
|||
140 | data_out_wen <= NOT sel; |
|
137 | data_out_wen <= NOT sel; | |
141 |
data_out <= data_sel( |
|
138 | data_out <= data_sel(0); | |
142 | state <= DATA1; |
|
|||
143 | WHEN DATA1 => |
|
|||
144 | data_out_wen <= NOT sel; |
|
|||
145 | data_out <= data_sel(2); |
|
|||
146 | state <= DATA2; |
|
139 | state <= DATA2; | |
147 | WHEN DATA2 => |
|
140 | WHEN DATA2 => | |
148 | data_out_wen <= NOT sel; |
|
141 | data_out_wen <= NOT sel; | |
149 |
data_out <= data_sel( |
|
142 | data_out <= data_sel(1); | |
150 | state <= DATA3; |
|
143 | state <= DATA3; | |
151 | WHEN DATA3 => |
|
144 | WHEN DATA3 => | |
152 | data_out_wen <= NOT sel; |
|
145 | data_out_wen <= NOT sel; | |
153 |
data_out <= data_sel( |
|
146 | data_out <= data_sel(2); | |
154 | state <= LAST; |
|
147 | state <= LAST; | |
155 | data_in_ack <= sel; |
|
148 | data_in_ack <= sel; | |
156 | WHEN LAST => |
|
149 | WHEN LAST => | |
@@ -163,101 +156,17 BEGIN | |||||
163 | END IF; |
|
156 | END IF; | |
164 | END PROCESS; |
|
157 | END PROCESS; | |
165 | ----------------------------------------------------------------------------- |
|
158 | ----------------------------------------------------------------------------- | |
166 |
|
||||
167 |
|
||||
168 | --PROCESS (clk, rstn) |
|
|||
169 | --BEGIN -- PROCESS |
|
|||
170 | -- IF rstn = '0' THEN -- asynchronous reset (active low) |
|
|||
171 | -- count_enable <= '0'; |
|
|||
172 | -- shift_time_enable <= '0'; |
|
|||
173 | -- shift_data_enable <= '0'; |
|
|||
174 | -- data_in_ack <= (OTHERS => '0'); |
|
|||
175 | -- data_out_wen <= (OTHERS => '1'); |
|
|||
176 | -- sel_ack <= '0'; |
|
|||
177 | -- ELSIF clk'event AND clk = '1' THEN -- rising clock edge |
|
|||
178 | -- IF run = '0' OR no_sel = '1' THEN |
|
|||
179 | -- count_enable <= '0'; |
|
|||
180 | -- shift_time_enable <= '0'; |
|
|||
181 | -- shift_data_enable <= '0'; |
|
|||
182 | -- data_in_ack <= (OTHERS => '0'); |
|
|||
183 | -- data_out_wen <= (OTHERS => '1'); |
|
|||
184 | -- sel_ack <= '0'; |
|
|||
185 | -- ELSE |
|
|||
186 | -- --COUNT |
|
|||
187 | -- IF shift_data_s = "10" THEN |
|
|||
188 | -- count_enable <= '1'; |
|
|||
189 | -- ELSE |
|
|||
190 | -- count_enable <= '0'; |
|
|||
191 | -- END IF; |
|
|||
192 | -- --DATA |
|
|||
193 | -- IF shift_time_s = "10" THEN |
|
|||
194 | -- shift_data_enable <= '1'; |
|
|||
195 | -- ELSE |
|
|||
196 | -- shift_data_enable <= '0'; |
|
|||
197 | -- END IF; |
|
|||
198 |
|
||||
199 | -- --TIME |
|
|||
200 | -- IF ((shift_data_s = "10") AND (count = nb_data_by_buffer)) OR |
|
|||
201 | -- shift_time_s = "00" OR |
|
|||
202 | -- shift_time_s = "01" |
|
|||
203 | -- THEN |
|
|||
204 | -- shift_time_enable <= '1'; |
|
|||
205 | -- ELSE |
|
|||
206 | -- shift_time_enable <= '0'; |
|
|||
207 | -- END IF; |
|
|||
208 |
|
||||
209 | -- --ACK |
|
|||
210 | -- IF shift_data_s = "10" THEN |
|
|||
211 | -- data_in_ack <= sel; |
|
|||
212 | -- sel_ack <= '1'; |
|
|||
213 | -- ELSE |
|
|||
214 | -- data_in_ack <= (OTHERS => '0'); |
|
|||
215 | -- sel_ack <= '0'; |
|
|||
216 | -- END IF; |
|
|||
217 |
|
||||
218 | -- --VALID OUT |
|
|||
219 | -- all_wen: FOR I IN 3 DOWNTO 0 LOOP |
|
|||
220 | -- IF sel(I) = '1' AND count_enable = '0' THEN |
|
|||
221 | -- data_out_wen(I) <= '0'; |
|
|||
222 | -- ELSE |
|
|||
223 | -- data_out_wen(I) <= '1'; |
|
|||
224 | -- END IF; |
|
|||
225 | -- END LOOP all_wen; |
|
|||
226 |
|
||||
227 | -- END IF; |
|
|||
228 | -- END IF; |
|
|||
229 | --END PROCESS; |
|
|||
230 |
|
159 | |||
231 | ----------------------------------------------------------------------------- |
|
160 | ----------------------------------------------------------------------------- | |
232 | -- DATA MUX |
|
161 | -- DATA MUX | |
233 | ----------------------------------------------------------------------------- |
|
162 | ----------------------------------------------------------------------------- | |
234 | all_bit_data_in: FOR I IN 32*5-1 DOWNTO 0 GENERATE |
|
|||
235 | I_time_in: IF I < 48 GENERATE |
|
|||
236 | data_0_v(I) <= time_in(0,I); |
|
|||
237 | data_1_v(I) <= time_in(1,I); |
|
|||
238 | data_2_v(I) <= time_in(2,I); |
|
|||
239 | data_3_v(I) <= time_in(3,I); |
|
|||
240 | END GENERATE I_time_in; |
|
|||
241 | I_null: IF (I > 47) AND (I < 32*2) GENERATE |
|
|||
242 | data_0_v(I) <= '0'; |
|
|||
243 | data_1_v(I) <= '0'; |
|
|||
244 | data_2_v(I) <= '0'; |
|
|||
245 | data_3_v(I) <= '0'; |
|
|||
246 | END GENERATE I_null; |
|
|||
247 | I_data_in: IF I > 32*2-1 GENERATE |
|
|||
248 | data_0_v(I) <= data_in(0,I-32*2); |
|
|||
249 | data_1_v(I) <= data_in(1,I-32*2); |
|
|||
250 | data_2_v(I) <= data_in(2,I-32*2); |
|
|||
251 | data_3_v(I) <= data_in(3,I-32*2); |
|
|||
252 | END GENERATE I_data_in; |
|
|||
253 | END GENERATE all_bit_data_in; |
|
|||
254 |
|
163 | |||
255 |
all_word: FOR J IN |
|
164 | all_word: FOR J IN 2 DOWNTO 0 GENERATE | |
256 | all_data_bit: FOR I IN 31 DOWNTO 0 GENERATE |
|
165 | all_data_bit: FOR I IN 31 DOWNTO 0 GENERATE | |
257 |
data_0(J)(I) <= data_ |
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166 | data_0(J)(I) <= data_in(0,I+32*J); | |
258 |
data_1(J)(I) <= data_ |
|
167 | data_1(J)(I) <= data_in(1,I+32*J); | |
259 |
data_2(J)(I) <= data_ |
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168 | data_2(J)(I) <= data_in(2,I+32*J); | |
260 |
data_3(J)(I) <= data_ |
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169 | data_3(J)(I) <= data_in(3,I+32*J); | |
261 | END GENERATE all_data_bit; |
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170 | END GENERATE all_data_bit; | |
262 | END GENERATE all_word; |
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171 | END GENERATE all_word; | |
263 |
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172 | |||
@@ -266,18 +175,18 BEGIN | |||||
266 | data_2 WHEN sel(2) = '1' ELSE |
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175 | data_2 WHEN sel(2) = '1' ELSE | |
267 | data_3; |
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176 | data_3; | |
268 |
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177 | |||
269 | --data_out <= data_sel(0) WHEN shift_time = "00" ELSE |
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178 | all_time_bit: FOR I IN 3 DOWNTO 0 GENERATE | |
270 | -- data_sel(1) WHEN shift_time = "01" ELSE |
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179 | time_sel(I) <= time_in(0,I) WHEN sel(0) = '1' ELSE | |
271 | -- data_sel(2) WHEN shift_data = "00" ELSE |
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180 | time_in(1,I) WHEN sel(1) = '1' ELSE | |
272 | -- data_sel(3) WHEN shift_data = "01" ELSE |
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181 | time_in(2,I) WHEN sel(2) = '1' ELSE | |
273 | -- data_sel(4); |
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182 | time_in(3,I); | |
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183 | END GENERATE all_time_bit; | |||
274 |
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184 | |||
275 |
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185 | |||
276 | ----------------------------------------------------------------------------- |
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186 | ----------------------------------------------------------------------------- | |
277 | -- RR and SELECTION |
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187 | -- RR and SELECTION | |
278 | ----------------------------------------------------------------------------- |
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188 | ----------------------------------------------------------------------------- | |
279 | all_input_rr : FOR I IN 3 DOWNTO 0 GENERATE |
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189 | all_input_rr : FOR I IN 3 DOWNTO 0 GENERATE | |
280 | -- valid_in_rr(I) <= data_in_valid(I) AND NOT full(I); |
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281 | valid_in_rr(I) <= data_in_valid(I) AND NOT full_almost(I); |
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190 | valid_in_rr(I) <= data_in_valid(I) AND NOT full_almost(I); | |
282 | END GENERATE all_input_rr; |
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191 | END GENERATE all_input_rr; | |
283 |
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192 | |||
@@ -286,9 +195,7 BEGIN | |||||
286 | clk => clk, |
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195 | clk => clk, | |
287 | rstn => rstn, |
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196 | rstn => rstn, | |
288 | in_valid => valid_in_rr, |
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197 | in_valid => valid_in_rr, | |
289 |
out_grant => sel_s); |
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198 | out_grant => sel_s); | |
290 |
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||||
291 | -- sel <= sel_s; |
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292 |
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199 | |||
293 | PROCESS (clk, rstn) |
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200 | PROCESS (clk, rstn) | |
294 | BEGIN -- PROCESS |
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201 | BEGIN -- PROCESS | |
@@ -296,14 +203,7 BEGIN | |||||
296 | sel <= "0000"; |
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203 | sel <= "0000"; | |
297 | sel_reg <= '0'; |
|
204 | sel_reg <= '0'; | |
298 | ELSIF clk'event AND clk = '1' THEN -- rising clock edge |
|
205 | ELSIF clk'event AND clk = '1' THEN -- rising clock edge | |
299 | -- sel_reg |
|
206 | IF sel_reg = '0' OR sel_ack = '1' THEN | |
300 | -- sel_ack |
|
|||
301 | -- sel_s |
|
|||
302 | -- sel = "0000 " |
|
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303 | --sel <= sel_s; |
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304 | IF sel_reg = '0' OR sel_ack = '1' |
|
|||
305 | --OR shift_data_s = "10" |
|
|||
306 | THEN |
|
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307 | sel <= sel_s; |
|
207 | sel <= sel_s; | |
308 | IF sel_s = "0000" THEN |
|
208 | IF sel_s = "0000" THEN | |
309 | sel_reg <= '0'; |
|
209 | sel_reg <= '0'; | |
@@ -332,35 +232,6 BEGIN | |||||
332 | sel => sel, |
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232 | sel => sel, | |
333 | data => count, |
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233 | data => count, | |
334 | data_s => count_s); |
|
234 | data_s => count_s); | |
335 |
|
||||
336 | --reg_shift_data_i: lpp_waveform_fifo_arbiter_reg |
|
|||
337 | -- GENERIC MAP ( |
|
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338 | -- data_size => 2, |
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339 | -- data_nb => 4) |
|
|||
340 | -- PORT MAP ( |
|
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341 | -- clk => clk, |
|
|||
342 | -- rstn => rstn, |
|
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343 | -- run => run, |
|
|||
344 | -- max_count => "10", -- 2 |
|
|||
345 | -- enable => shift_data_enable, |
|
|||
346 | -- sel => sel, |
|
|||
347 | -- data => shift_data, |
|
|||
348 | -- data_s => shift_data_s); |
|
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349 |
|
||||
350 |
|
||||
351 | --reg_shift_time_i: lpp_waveform_fifo_arbiter_reg |
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|||
352 | -- GENERIC MAP ( |
|
|||
353 | -- data_size => 2, |
|
|||
354 | -- data_nb => 4) |
|
|||
355 | -- PORT MAP ( |
|
|||
356 | -- clk => clk, |
|
|||
357 | -- rstn => rstn, |
|
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358 | -- run => run, |
|
|||
359 | -- max_count => "10", -- 2 |
|
|||
360 | -- enable => shift_time_enable, |
|
|||
361 | -- sel => sel, |
|
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362 | -- data => shift_time, |
|
|||
363 | -- data_s => shift_time_s); |
|
|||
364 |
|
235 | |||
365 |
|
236 | |||
366 |
|
237 | |||
@@ -391,4 +262,3 END ARCHITECTURE; | |||||
391 |
|
262 | |||
392 |
|
263 | |||
393 |
|
264 | |||
394 |
|
@@ -105,7 +105,6 PACKAGE lpp_waveform_pkg IS | |||||
105 | tech : INTEGER; |
|
105 | tech : INTEGER; | |
106 | data_size : INTEGER; |
|
106 | data_size : INTEGER; | |
107 | nb_data_by_buffer_size : INTEGER; |
|
107 | nb_data_by_buffer_size : INTEGER; | |
108 | nb_word_by_buffer_size : INTEGER; |
|
|||
109 | nb_snapshot_param_size : INTEGER; |
|
108 | nb_snapshot_param_size : INTEGER; | |
110 | delta_vector_size : INTEGER; |
|
109 | delta_vector_size : INTEGER; | |
111 | delta_vector_size_f0_2 : INTEGER); |
|
110 | delta_vector_size_f0_2 : INTEGER); | |
@@ -127,24 +126,22 PACKAGE lpp_waveform_pkg IS | |||||
127 | burst_f1 : IN STD_LOGIC; |
|
126 | burst_f1 : IN STD_LOGIC; | |
128 | burst_f2 : IN STD_LOGIC; |
|
127 | burst_f2 : IN STD_LOGIC; | |
129 | nb_data_by_buffer : IN STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0); |
|
128 | nb_data_by_buffer : IN STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0); | |
130 | nb_word_by_buffer : IN STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0); |
|
|||
131 | nb_snapshot_param : IN STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0); |
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129 | nb_snapshot_param : IN STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0); | |
132 | status_full : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
|||
133 | status_full_ack : IN STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
|||
134 | status_full_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
|||
135 | status_new_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
130 | status_new_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); | |
|
131 | status_buffer_ready : IN STD_LOGIC_VECTOR(3 DOWNTO 0); | |||
|
132 | addr_buffer : IN STD_LOGIC_VECTOR(32*4 DOWNTO 0); | |||
|
133 | length_buffer : IN STD_LOGIC_VECTOR(25 DOWNTO 0); | |||
|
134 | ready_buffer : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); | |||
|
135 | buffer_time : OUT STD_LOGIC_VECTOR(48*4-1 DOWNTO 0); | |||
|
136 | error_buffer_full : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); | |||
136 | coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
137 | coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
137 | fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); |
|
138 | fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); | |
138 | addr_data_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
|||
139 | data_f0_in_valid : IN STD_LOGIC; |
|
139 | data_f0_in_valid : IN STD_LOGIC; | |
140 | data_f0_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); |
|
140 | data_f0_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); | |
141 | addr_data_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
|||
142 | data_f1_in_valid : IN STD_LOGIC; |
|
141 | data_f1_in_valid : IN STD_LOGIC; | |
143 | data_f1_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); |
|
142 | data_f1_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); | |
144 | addr_data_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
|||
145 | data_f2_in_valid : IN STD_LOGIC; |
|
143 | data_f2_in_valid : IN STD_LOGIC; | |
146 | data_f2_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); |
|
144 | data_f2_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); | |
147 | addr_data_f3 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
|||
148 | data_f3_in_valid : IN STD_LOGIC; |
|
145 | data_f3_in_valid : IN STD_LOGIC; | |
149 | data_f3_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); |
|
146 | data_f3_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); | |
150 | data_f0_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
147 | data_f0_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
@@ -167,27 +164,15 PACKAGE lpp_waveform_pkg IS | |||||
167 | data_f3_data_out_valid : OUT STD_LOGIC; |
|
164 | data_f3_data_out_valid : OUT STD_LOGIC; | |
168 | data_f3_data_out_valid_burst : OUT STD_LOGIC; |
|
165 | data_f3_data_out_valid_burst : OUT STD_LOGIC; | |
169 | data_f3_data_out_ren : IN STD_LOGIC; |
|
166 | data_f3_data_out_ren : IN STD_LOGIC; | |
170 |
|
167 | |||
171 | --debug |
|
168 | dma_fifo_valid_burst : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); | |
172 |
|
|
169 | dma_fifo_data : OUT STD_LOGIC_VECTOR(32*4-1 DOWNTO 0); | |
173 |
|
|
170 | dma_fifo_ren : IN STD_LOGIC_VECTOR(3 DOWNTO 0); | |
174 | --debug_f0_data_valid : OUT STD_LOGIC; |
|
171 | dma_buffer_new : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); | |
175 |
|
|
172 | dma_buffer_addr : OUT STD_LOGIC_VECTOR(32*4-1 DOWNTO 0); | |
176 | --debug_f1_data_valid : OUT STD_LOGIC; |
|
173 | dma_buffer_length : OUT STD_LOGIC_VECTOR(26*4-1 DOWNTO 0); | |
177 |
|
|
174 | dma_buffer_full : IN STD_LOGIC_VECTOR(3 DOWNTO 0); | |
178 | --debug_f2_data_valid : OUT STD_LOGIC; |
|
175 | dma_buffer_full_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0) | |
179 | --debug_f3_data : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); |
|
|||
180 | --debug_f3_data_valid : OUT STD_LOGIC; |
|
|||
181 |
|
||||
182 | ----debug FIFO IN |
|
|||
183 | --debug_f0_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
|||
184 | --debug_f0_data_fifo_in_valid : OUT STD_LOGIC; |
|
|||
185 | --debug_f1_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
|||
186 | --debug_f1_data_fifo_in_valid : OUT STD_LOGIC; |
|
|||
187 | --debug_f2_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
|||
188 | --debug_f2_data_fifo_in_valid : OUT STD_LOGIC; |
|
|||
189 | --debug_f3_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
|||
190 | --debug_f3_data_fifo_in_valid : OUT STD_LOGIC |
|
|||
191 | ); |
|
176 | ); | |
192 | END COMPONENT; |
|
177 | END COMPONENT; | |
193 |
|
178 | |||
@@ -243,7 +228,10 PACKAGE lpp_waveform_pkg IS | |||||
243 | data_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
228 | data_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
244 | data_out_wen : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
229 | data_out_wen : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); | |
245 | full_almost : IN STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
230 | full_almost : IN STD_LOGIC_VECTOR(3 DOWNTO 0); | |
246 |
full : IN STD_LOGIC_VECTOR(3 DOWNTO 0) |
|
231 | full : IN STD_LOGIC_VECTOR(3 DOWNTO 0); | |
|
232 | time_out : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); | |||
|
233 | time_out_new : OUT STD_LOGIC_VECTOR(3 DOWNTO 0) | |||
|
234 | ); | |||
247 | END COMPONENT; |
|
235 | END COMPONENT; | |
248 |
|
236 | |||
249 | COMPONENT lpp_waveform_fifo |
|
237 | COMPONENT lpp_waveform_fifo | |
@@ -370,7 +358,9 PACKAGE lpp_waveform_pkg IS | |||||
370 | enable : IN STD_LOGIC; |
|
358 | enable : IN STD_LOGIC; | |
371 | sel : IN STD_LOGIC_VECTOR(data_nb-1 DOWNTO 0); |
|
359 | sel : IN STD_LOGIC_VECTOR(data_nb-1 DOWNTO 0); | |
372 | data : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); |
|
360 | data : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); | |
373 |
data_s : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0) |
|
361 | data_s : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); | |
|
362 | time_out : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); | |||
|
363 | time_out_new : OUT STD_LOGIC_VECTOR(3 DOWNTO 0)); | |||
374 | END COMPONENT; |
|
364 | END COMPONENT; | |
375 |
|
365 | |||
376 | COMPONENT lpp_waveform_fsmdma |
|
366 | COMPONENT lpp_waveform_fsmdma |
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