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Added cross domain synchronisation blocks.
jeandet -
r223:006079fa8bed alexis
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1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2013, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 ------------------------------------------------------------------------------
19 -- Author : Alexis Jeandet
20 -- Mail : alexis.jeandet@member.fsf.org
21 ------------------------------------------------------------------------------
22 --
23 -- This module implements the SyncSignal generator explained in:
24 -- Data Transfer between Asynchronous Clock Domains without Pain
25 -- from Markus Schutti, Markus Pfaff, Richard Hagelauer
26 -- http://www-micrel.deis.unibo.it/~benini/files/SNUG/paper9_final.pdf
27 -- see page 4
28 --
29 --
30
31 library IEEE;
32 use IEEE.STD_LOGIC_1164.ALL;
33
34 entity CrossDomainSyncGen is
35 Port (
36 reset : in STD_LOGIC;
37 ClockS : in STD_LOGIC;
38 ClockF : in STD_LOGIC;
39 SyncSignal : out STD_LOGIC
40 );
41 end CrossDomainSyncGen;
42
43 architecture AR_CrossDomainSyncGen of CrossDomainSyncGen is
44
45 signal FFSYNC : std_logic_vector(2 downto 0);
46
47 begin
48
49 SyncSignal <= FFSYNC(2);
50
51 process(reset,ClockF)
52 begin
53 if reset = '0' then
54 FFSYNC <= (others => '0');
55 elsif ClockF'event and ClockF = '1' then
56 FFSYNC(0) <= ClockS;
57 FFSYNC(1) <= FFSYNC(0);
58 FFSYNC(2) <= FFSYNC(1);
59 end if;
60 end process;
61
62 end AR_CrossDomainSyncGen;
63
64
65
66
67
68
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1 library IEEE;
2 use IEEE.STD_LOGIC_1164.ALL;
3 use IEEE.NUMERIC_STD.ALL;
4 library lpp;
5 use lpp.lpp_ad_conv.all;
6 use lpp.lpp_amba.all;
7 use lpp.apb_devices_list.all;
8 use lpp.general_purpose.all;
9 use lpp.Rocket_PCM_Encoder.all;
10
11
12 entity DC_ACQ_TOP is
13 generic(
14 WordSize : integer := 8;
15 WordCnt : integer := 144;
16 MinFCount : integer := 64;
17 EnableSR : integer := 1;
18 FakeADC : integer := 0
19 );
20 port(
21
22 reset : in std_logic;
23 clk : in std_logic;
24 SyncSig : in STD_LOGIC;
25 minorF : in std_logic;
26 majorF : in std_logic;
27 sclk : in std_logic;
28 WordClk : in std_logic;
29
30 DC_ADC_Sclk : out std_logic;
31 DC_ADC_IN : in std_logic_vector(1 downto 0);
32 DC_ADC_ClkDiv : out std_logic;
33 DC_ADC_FSynch : out std_logic;
34 SET_RESET0 : out std_logic;
35 SET_RESET1 : out std_logic;
36
37 AMR1X : out std_logic_vector(23 downto 0);
38 AMR1Y : out std_logic_vector(23 downto 0);
39 AMR1Z : out std_logic_vector(23 downto 0);
40
41 AMR2X : out std_logic_vector(23 downto 0);
42 AMR2Y : out std_logic_vector(23 downto 0);
43 AMR2Z : out std_logic_vector(23 downto 0);
44
45 AMR3X : out std_logic_vector(23 downto 0);
46 AMR3Y : out std_logic_vector(23 downto 0);
47 AMR3Z : out std_logic_vector(23 downto 0);
48
49 AMR4X : out std_logic_vector(23 downto 0);
50 AMR4Y : out std_logic_vector(23 downto 0);
51 AMR4Z : out std_logic_vector(23 downto 0);
52
53 Temp1 : out std_logic_vector(23 downto 0);
54 Temp2 : out std_logic_vector(23 downto 0);
55 Temp3 : out std_logic_vector(23 downto 0);
56 Temp4 : out std_logic_vector(23 downto 0)
57 );
58 end DC_ACQ_TOP;
59
60 architecture Behavioral of DC_ACQ_TOP is
61
62 signal DC_ADC_SmplClk : std_logic;
63 signal LF_ADC_SmplClk : std_logic;
64 signal SET_RESET0_sig : std_logic;
65 signal SET_RESET1_sig : std_logic;
66 signal SET_RESET_counter : integer range 0 to 31:=0;
67
68 signal AMR1X_Sync : std_logic_vector(23 downto 0);
69 signal AMR1Y_Sync : std_logic_vector(23 downto 0);
70 signal AMR1Z_Sync : std_logic_vector(23 downto 0);
71
72 signal AMR2X_Sync : std_logic_vector(23 downto 0);
73 signal AMR2Y_Sync : std_logic_vector(23 downto 0);
74 signal AMR2Z_Sync : std_logic_vector(23 downto 0);
75
76 signal AMR3X_Sync : std_logic_vector(23 downto 0);
77 signal AMR3Y_Sync : std_logic_vector(23 downto 0);
78 signal AMR3Z_Sync : std_logic_vector(23 downto 0);
79
80 signal AMR4X_Sync : std_logic_vector(23 downto 0);
81 signal AMR4Y_Sync : std_logic_vector(23 downto 0);
82 signal AMR4Z_Sync : std_logic_vector(23 downto 0);
83
84 signal Temp1_Sync : std_logic_vector(23 downto 0);
85 signal Temp2_Sync : std_logic_vector(23 downto 0);
86 signal Temp3_Sync : std_logic_vector(23 downto 0);
87 signal Temp4_Sync : std_logic_vector(23 downto 0);
88
89 begin
90
91 ------------------------------------------------------------------
92 --
93 -- DC sampling clock generation
94 --
95 ------------------------------------------------------------------
96
97
98 DC_SMPL_CLK0 : entity work.LF_SMPL_CLK
99 --generic map(36)
100 generic map(288)
101 port map(
102 reset => reset,
103 wclk => WordClk,
104 SMPL_CLK => DC_ADC_SmplClk
105 );
106 ------------------------------------------------------------------
107
108
109
110
111 ------------------------------------------------------------------
112 --
113 -- DC ADC
114 --
115 ------------------------------------------------------------------
116 ADC : IF FakeADC /=1 GENERATE
117
118 DC_ADC0 : DUAL_ADS1278_DRIVER
119 port map(
120 Clk => clk,
121 reset => reset,
122 SpiClk => DC_ADC_Sclk,
123 DIN => DC_ADC_IN,
124 SmplClk => DC_ADC_SmplClk,
125 OUT00 => AMR1X_Sync,
126 OUT01 => AMR1Y_Sync,
127 OUT02 => AMR1Z_Sync,
128 OUT03 => AMR2X_Sync,
129 OUT04 => AMR2Y_Sync,
130 OUT05 => AMR2Z_Sync,
131 OUT06 => Temp1_Sync,
132 OUT07 => Temp2_Sync,
133 OUT10 => AMR3X_Sync,
134 OUT11 => AMR3Y_Sync,
135 OUT12 => AMR3Z_Sync,
136 OUT13 => AMR4X_Sync,
137 OUT14 => AMR4Y_Sync,
138 OUT15 => AMR4Z_Sync,
139 OUT16 => Temp3_Sync,
140 OUT17 => Temp4_Sync,
141 FSynch => DC_ADC_FSynch
142 );
143 END GENERATE;
144
145 NOADC: IF FakeADC=1 GENERATE
146
147 DC_ADC0 : entity work.FAKE_DUAL_ADS1278_DRIVER
148 port map(
149 Clk => clk,
150 reset => reset,
151 SpiClk => DC_ADC_Sclk,
152 DIN => DC_ADC_IN,
153 SmplClk => DC_ADC_SmplClk,
154 OUT00 => AMR1X_Sync,
155 OUT01 => AMR1Y_Sync,
156 OUT02 => AMR1Z_Sync,
157 OUT03 => AMR2X_Sync,
158 OUT04 => AMR2Y_Sync,
159 OUT05 => AMR2Z_Sync,
160 OUT06 => Temp1_Sync,
161 OUT07 => Temp2_Sync,
162 OUT10 => AMR3X_Sync,
163 OUT11 => AMR3Y_Sync,
164 OUT12 => AMR3Z_Sync,
165 OUT13 => AMR4X_Sync,
166 OUT14 => AMR4Y_Sync,
167 OUT15 => AMR4Z_Sync,
168 OUT16 => Temp3_Sync,
169 OUT17 => Temp4_Sync,
170 FSynch => DC_ADC_FSynch
171 );
172 END GENERATE;
173 ------------------------------------------------------------------
174
175
176
177
178 ------------------------------------------------------------------
179 --
180 -- SET/RESET GEN
181 --
182 ------------------------------------------------------------------
183
184 SR: IF EnableSR /=0 GENERATE
185 process(reset,DC_ADC_SmplClk)
186 begin
187 if reset = '0' then
188 SET_RESET0_sig <= '0';
189 elsif DC_ADC_SmplClk'event and DC_ADC_SmplClk = '0' then
190 if(SET_RESET_counter = 31) then
191 SET_RESET0_sig <= not SET_RESET0_sig;
192 SET_RESET_counter <= 0;
193 else
194 SET_RESET_counter <= SET_RESET_counter +1;
195 end if;
196 end if;
197 end process;
198
199 END GENERATE;
200 NOSR: IF EnableSR=0 GENERATE
201 SET_RESET0_sig <= '0';
202 END GENERATE;
203
204 SET_RESET1_sig <= SET_RESET0_sig;
205 SET_RESET0 <= SET_RESET0_sig;
206 SET_RESET1 <= SET_RESET1_sig;
207 ------------------------------------------------------------------
208 ------------------------------------------------------------------
209
210
211 ------------------------------------------------------------------
212 --
213 -- Cross domain clock synchronisation
214 --
215 ------------------------------------------------------------------
216
217
218
219 AMR1Xsync: entity work.Fast2SlowSync
220 generic map(N => 24)
221 port map( AMR1X_Sync,clk,sclk,SyncSig,AMR1X);
222 AMR1Ysync: entity work.Fast2SlowSync
223 generic map(N => 24)
224 port map( AMR1Y_Sync,clk,sclk,SyncSig,AMR1Y);
225 AMR1Zsync: entity work.Fast2SlowSync
226 generic map(N => 24)
227 port map( AMR1Z_Sync,clk,sclk,SyncSig,AMR1Z);
228
229 AMR2Xsync: entity work.Fast2SlowSync
230 generic map(N => 24)
231 port map( AMR2X_Sync,clk,sclk,SyncSig,AMR2X);
232 AMR2Ysync: entity work.Fast2SlowSync
233 generic map(N => 24)
234 port map( AMR2Y_Sync,clk,sclk,SyncSig,AMR2Y);
235 AMR2Zsync: entity work.Fast2SlowSync
236 generic map(N => 24)
237 port map( AMR2Z_Sync,clk,sclk,SyncSig,AMR2Z);
238
239 AMR3Xsync: entity work.Fast2SlowSync
240 generic map(N => 24)
241 port map( AMR3X_Sync,clk,sclk,SyncSig,AMR3X);
242 AMR3Ysync: entity work.Fast2SlowSync
243 generic map(N => 24)
244 port map( AMR3Y_Sync,clk,sclk,SyncSig,AMR3Y);
245 AMR3Zsync: entity work.Fast2SlowSync
246 generic map(N => 24)
247 port map( AMR3Z_Sync,clk,sclk,SyncSig,AMR3Z);
248
249
250 AMR4Xsync: entity work.Fast2SlowSync
251 generic map(N => 24)
252 port map( AMR4X_Sync,clk,sclk,SyncSig,AMR4X);
253 AMR4Ysync: entity work.Fast2SlowSync
254 generic map(N => 24)
255 port map( AMR4Y_Sync,clk,sclk,SyncSig,AMR4Y);
256 AMR4Zsync: entity work.Fast2SlowSync
257 generic map(N => 24)
258 port map( AMR4Z_Sync,clk,sclk,SyncSig,AMR4Z);
259
260
261 TEMP1sync: entity work.Fast2SlowSync
262 generic map(N => 24)
263 port map( TEMP1_Sync,clk,sclk,SyncSig,TEMP1);
264 TEMP2sync: entity work.Fast2SlowSync
265 generic map(N => 24)
266 port map( TEMP2_Sync,clk,sclk,SyncSig,TEMP2);
267 TEMP3sync: entity work.Fast2SlowSync
268 generic map(N => 24)
269 port map( TEMP3_Sync,clk,sclk,SyncSig,TEMP3);
270 TEMP4sync: entity work.Fast2SlowSync
271 generic map(N => 24)
272 port map( TEMP4_Sync,clk,sclk,SyncSig,TEMP4);
273
274 ------------------------------------------------------------------
275
276
277 end Behavioral;
278
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1 -- ADS1274_DRIVER.vhd
2 library IEEE;
3 use IEEE.std_logic_1164.all;
4 use IEEE.numeric_std.all;
5 library lpp;
6 use lpp.lpp_ad_conv.all;
7 use lpp.general_purpose.all;
8
9
10
11
12
13 entity FAKE_DUAL_ADS1278_DRIVER is
14 generic
15 (
16 SCLKDIV : integer range 2 to 256 :=16
17 );
18 port(
19 Clk : in std_logic;
20 reset : in std_logic;
21 SpiClk : out std_logic;
22 DIN : in std_logic_vector(1 downto 0);
23 SmplClk : in std_logic;
24 OUT00 : out std_logic_vector(23 downto 0);
25 OUT01 : out std_logic_vector(23 downto 0);
26 OUT02 : out std_logic_vector(23 downto 0);
27 OUT03 : out std_logic_vector(23 downto 0);
28 OUT04 : out std_logic_vector(23 downto 0);
29 OUT05 : out std_logic_vector(23 downto 0);
30 OUT06 : out std_logic_vector(23 downto 0);
31 OUT07 : out std_logic_vector(23 downto 0);
32 OUT10 : out std_logic_vector(23 downto 0);
33 OUT11 : out std_logic_vector(23 downto 0);
34 OUT12 : out std_logic_vector(23 downto 0);
35 OUT13 : out std_logic_vector(23 downto 0);
36 OUT14 : out std_logic_vector(23 downto 0);
37 OUT15 : out std_logic_vector(23 downto 0);
38 OUT16 : out std_logic_vector(23 downto 0);
39 OUT17 : out std_logic_vector(23 downto 0);
40 FSynch : out std_logic
41 );
42 end FAKE_DUAL_ADS1278_DRIVER;
43
44
45
46
47
48
49 architecture ar_FAKE_DUAL_ADS1278_DRIVER of FAKE_DUAL_ADS1278_DRIVER is
50 signal ShiftGeg0,ShiftGeg1 : std_logic_vector((8*24)-1 downto 0);
51 signal ShiftGeg20,ShiftGeg21 : std_logic_vector((8*24)-1 downto 0);
52 signal SmplClk_Reg : std_logic:= '0';
53 signal N : integer range 0 to (24*8) := 0;
54 signal SPI_CLk : std_logic;
55 signal SmplClk_clkd : std_logic:= '0';
56 signal OUT00_r : std_logic_vector(23 downto 0) := (others => '0');
57 signal OUT01_r : std_logic_vector(23 downto 0) := (others => '0');
58 signal OUT02_r : std_logic_vector(23 downto 0) := (others => '0');
59 signal OUT03_r : std_logic_vector(23 downto 0) := (others => '0');
60 signal OUT04_r : std_logic_vector(23 downto 0) := (others => '0');
61 signal OUT05_r : std_logic_vector(23 downto 0) := (others => '0');
62 signal OUT06_r : std_logic_vector(23 downto 0) := (others => '0');
63 signal OUT07_r : std_logic_vector(23 downto 0) := (others => '0');
64 signal OUT10_r : std_logic_vector(23 downto 0) := (others => '0');
65 signal OUT11_r : std_logic_vector(23 downto 0) := (others => '0');
66 signal OUT12_r : std_logic_vector(23 downto 0) := (others => '0');
67 signal OUT13_r : std_logic_vector(23 downto 0) := (others => '0');
68 signal OUT14_r : std_logic_vector(23 downto 0) := (others => '0');
69 signal OUT15_r : std_logic_vector(23 downto 0) := (others => '0');
70 signal OUT16_r : std_logic_vector(23 downto 0) := (others => '0');
71 signal OUT17_r : std_logic_vector(23 downto 0) := (others => '0');
72
73 begin
74
75
76 CLKDIV0 : Clk_Divider2
77 generic map(SCLKDIV)
78 port map(Clk,SPI_CLk);
79
80
81 FSynch <= SmplClk;
82 SpiClk <= SPI_CLk;
83
84 process(reset,SPI_CLk)
85 begin
86
87 if reset = '0' then
88 ShiftGeg0 <= (others => '0');
89 ShiftGeg1 <= (others => '0');
90 N <= 0;
91 OUT00_r <= (others => '0');
92 OUT01_r <= (others => '0');
93 OUT02_r <= (others => '0');
94 OUT03_r <= (others => '0');
95 OUT04_r <= (others => '0');
96 OUT05_r <= (others => '0');
97 OUT06_r <= (others => '0');
98 OUT07_r <= (others => '0');
99 OUT10_r <= (others => '0');
100 OUT11_r <= (others => '0');
101 OUT12_r <= (others => '0');
102 OUT13_r <= (others => '0');
103 OUT14_r <= (others => '0');
104 OUT15_r <= (others => '0');
105 OUT16_r <= (others => '0');
106 OUT17_r <= (others => '0');
107 ShiftGeg20 <= (others => '0');
108 ShiftGeg21 <= (others => '0');
109
110 elsif SPI_CLk'event and SPI_CLk = '1' then
111 if ((SmplClk_clkd = '1' and SmplClk_Reg = '0') or (N /= 0)) then
112 ShiftGeg20((8*24)-1 downto 0) <= ShiftGeg20((8*24)-2 downto 0) & '0';
113 ShiftGeg21((8*24)-1 downto 0) <= ShiftGeg21((8*24)-2 downto 0) & '0';
114 ShiftGeg0((8*24)-1 downto 0) <= ShiftGeg0((8*24)-2 downto 0) & ShiftGeg20((8*24)-1);
115 ShiftGeg1((8*24)-1 downto 0) <= ShiftGeg1((8*24)-2 downto 0) & ShiftGeg21((8*24)-1);
116 if N = ((24*8)-1) then
117 N <= 0;
118 OUT00_r <= std_logic_vector(UNSIGNED(OUT00_r) + 1);
119 OUT01_r <= std_logic_vector(UNSIGNED(OUT01_r) + 2);
120 OUT02_r <= std_logic_vector(UNSIGNED(OUT02_r) + 3);
121 OUT03_r <= std_logic_vector(UNSIGNED(OUT03_r) + 4);
122 OUT04_r <= std_logic_vector(UNSIGNED(OUT04_r) + 5);
123 OUT05_r <= std_logic_vector(UNSIGNED(OUT05_r) + 6);
124 OUT06_r <= std_logic_vector(UNSIGNED(OUT06_r) + 7);
125 OUT07_r <= std_logic_vector(UNSIGNED(OUT07_r) + 8);
126 OUT10_r <= std_logic_vector(UNSIGNED(OUT10_r) + 9);
127 OUT11_r <= std_logic_vector(UNSIGNED(OUT11_r) + 10);
128 OUT12_r <= std_logic_vector(UNSIGNED(OUT12_r) + 11);
129 OUT13_r <= std_logic_vector(UNSIGNED(OUT13_r) + 12);
130 OUT14_r <= std_logic_vector(UNSIGNED(OUT14_r) + 13);
131 OUT15_r <= std_logic_vector(UNSIGNED(OUT15_r) + 14);
132 OUT16_r <= std_logic_vector(UNSIGNED(OUT16_r) + 15);
133 OUT17_r <= std_logic_vector(UNSIGNED(OUT17_r) + 16);
134
135 ShiftGeg20((24*1)-1 downto (24*(1-1))) <= OUT00_r;
136 ShiftGeg20((24*2)-1 downto (24*(2-1))) <= OUT01_r;
137 ShiftGeg20((24*3)-1 downto (24*(3-1))) <= OUT02_r;
138 ShiftGeg20((24*4)-1 downto (24*(4-1))) <= OUT03_r;
139 ShiftGeg20((24*5)-1 downto (24*(5-1))) <= OUT04_r;
140 ShiftGeg20((24*6)-1 downto (24*(6-1))) <= OUT05_r;
141 ShiftGeg20((24*7)-1 downto (24*(7-1))) <= OUT06_r;
142 ShiftGeg20((24*8)-1 downto (24*(8-1))) <= OUT07_r;
143
144 ShiftGeg21((24*1)-1 downto (24*(1-1))) <= OUT10_r;
145 ShiftGeg21((24*2)-1 downto (24*(2-1))) <= OUT11_r;
146 ShiftGeg21((24*3)-1 downto (24*(3-1))) <= OUT12_r;
147 ShiftGeg21((24*4)-1 downto (24*(4-1))) <= OUT13_r;
148 ShiftGeg21((24*5)-1 downto (24*(5-1))) <= OUT14_r;
149 ShiftGeg21((24*6)-1 downto (24*(6-1))) <= OUT15_r;
150 ShiftGeg21((24*7)-1 downto (24*(7-1))) <= OUT16_r;
151 ShiftGeg21((24*8)-1 downto (24*(8-1))) <= OUT17_r;
152 else
153 N <= N+1;
154 end if;
155 end if;
156 end if;
157 end process;
158
159
160 process(SPI_CLk)
161 begin
162 if SPI_CLk'event and SPI_CLk ='0' then
163 SmplClk_clkd <= SmplClk;
164 SmplClk_Reg <= SmplClk_clkd;
165 end if;
166 end process;
167
168
169 process(clk,reset)
170 begin
171 if reset = '0' then
172 OUT00 <= (others => '0');
173 OUT01 <= (others => '0');
174 OUT02 <= (others => '0');
175 OUT03 <= (others => '0');
176 OUT04 <= (others => '0');
177 OUT05 <= (others => '0');
178 OUT06 <= (others => '0');
179 OUT07 <= (others => '0');
180
181 OUT10 <= (others => '0');
182 OUT11 <= (others => '0');
183 OUT12 <= (others => '0');
184 OUT13 <= (others => '0');
185 OUT14 <= (others => '0');
186 OUT15 <= (others => '0');
187 OUT16 <= (others => '0');
188 OUT17 <= (others => '0');
189 elsif clk'event and clk ='1' then
190 if N = 0 then
191 OUT00 <= ShiftGeg0((24*1)-1 downto (24*(1-1)));
192 OUT01 <= ShiftGeg0((24*2)-1 downto (24*(2-1)));
193 OUT02 <= ShiftGeg0((24*3)-1 downto (24*(3-1)));
194 OUT03 <= ShiftGeg0((24*4)-1 downto (24*(4-1)));
195 OUT04 <= ShiftGeg0((24*5)-1 downto (24*(5-1)));
196 OUT05 <= ShiftGeg0((24*6)-1 downto (24*(6-1)));
197 OUT06 <= ShiftGeg0((24*7)-1 downto (24*(7-1)));
198 OUT07 <= ShiftGeg0((24*8)-1 downto (24*(8-1)));
199
200 OUT10 <= ShiftGeg1((24*1)-1 downto (24*(1-1)));
201 OUT11 <= ShiftGeg1((24*2)-1 downto (24*(2-1)));
202 OUT12 <= ShiftGeg1((24*3)-1 downto (24*(3-1)));
203 OUT13 <= ShiftGeg1((24*4)-1 downto (24*(4-1)));
204 OUT14 <= ShiftGeg1((24*5)-1 downto (24*(5-1)));
205 OUT15 <= ShiftGeg1((24*6)-1 downto (24*(6-1)));
206 OUT16 <= ShiftGeg1((24*7)-1 downto (24*(7-1)));
207 OUT17 <= ShiftGeg1((24*8)-1 downto (24*(8-1)));
208
209 end if;
210 end if;
211 end process;
212
213 end ar_FAKE_DUAL_ADS1278_DRIVER;
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1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2013, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 ------------------------------------------------------------------------------
19 -- Author : Alexis Jeandet
20 -- Mail : alexis.jeandet@member.fsf.org
21 ------------------------------------------------------------------------------
22 --
23 -- This module implements the Fast to Slow clock transfer:
24 -- Data Transfer between Asynchronous Clock Domains without Pain
25 -- from Markus Schutti, Markus Pfaff, Richard Hagelauer
26 -- http://www-micrel.deis.unibo.it/~benini/files/SNUG/paper9_final.pdf
27 -- see page 6
28 --
29 --
30
31 library IEEE;
32 use IEEE.STD_LOGIC_1164.ALL;
33
34 entity Fast2SlowSync is
35 generic
36 (
37 N : integer range 0 to 256:=8
38 );
39 Port
40 (
41 Data : in STD_LOGIC_VECTOR (N-1 downto 0);
42 ClockF : in STD_LOGIC;
43 ClockS : in STD_LOGIC;
44 SyncSignal : in STD_LOGIC;
45 DataSinkF : out STD_LOGIC_VECTOR (N-1 downto 0)
46 );
47 end Fast2SlowSync;
48
49 architecture AR_Fast2SlowSync of Fast2SlowSync is
50
51 signal DataF : STD_LOGIC_VECTOR (N-1 downto 0);
52 signal DataFlocked : STD_LOGIC_VECTOR (N-1 downto 0);
53
54 signal MuxOut : STD_LOGIC_VECTOR (N-1 downto 0);
55
56 begin
57
58 MuxOut <= DataF when SyncSignal = '1' else
59 DataFlocked;
60
61 process(ClockF)
62 begin
63 if ClockF'event and ClockF = '1' then
64 DataF <= Data;
65 DataFlocked <= MuxOut;
66 end if;
67 end process;
68
69 process(ClockS)
70 begin
71 if ClockS'event and ClockS = '1' then
72 DataSinkF <= DataFlocked;
73 end if;
74 end process;
75
76 end AR_Fast2SlowSync;
77
78
79
80
81
82
83
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1 library ieee;
2 use ieee.std_logic_1164.all;
3 use IEEE.numeric_std.all;
4 library grlib, techmap;
5 use grlib.amba.all;
6 use grlib.amba.all;
7 use grlib.stdlib.all;
8 use techmap.gencomp.all;
9 use techmap.allclkgen.all;
10 library gaisler;
11 use gaisler.memctrl.all;
12 use gaisler.leon3.all;
13 use gaisler.uart.all;
14 use gaisler.misc.all;
15 --use gaisler.sim.all;
16 library lpp;
17 use lpp.lpp_ad_conv.all;
18 use lpp.lpp_amba.all;
19 use lpp.apb_devices_list.all;
20 use lpp.general_purpose.all;
21 use lpp.Rocket_PCM_Encoder.all;
22
23
24 use work.Convertisseur_config.all;
25
26
27 use work.config.all;
28 --==================================================================
29 --
30 --
31 -- FPGA FREQ = 48MHz
32 -- ADC Oscillator frequency = 4MHz
33 --
34 --
35 --==================================================================
36
37 entity ici4_OLD is
38 generic (
39 fabtech : integer := CFG_FABTECH;
40 memtech : integer := CFG_MEMTECH;
41 padtech : integer := CFG_PADTECH;
42 clktech : integer := CFG_CLKTECH;
43 WordSize : integer := 8; WordCnt : integer := 144;MinFCount : integer := 64
44 );
45 port (
46 reset : in std_ulogic;
47 clk : in std_ulogic;
48 sclk : in std_logic;
49 Gate : in std_logic;
50 MinF : in std_logic;
51 MajF : in std_logic;
52 Data : out std_logic;
53 DC_ADC_Sclk : out std_logic;
54 DC_ADC_IN : in std_logic_vector(1 downto 0);
55 DC_ADC_ClkDiv : out std_logic;
56 DC_ADC_FSynch : out std_logic;
57 SET_RESET0 : out std_logic;
58 SET_RESET1 : out std_logic;
59 LED : out std_logic
60 );
61 end;
62
63 architecture rtl of ici4_OLD is
64
65 signal clk_buf,reset_buf : std_logic;
66
67 Constant FramePlacerCount : integer := 2;
68
69 signal MinF_Inv : std_logic;
70 signal Gate_Inv : std_logic;
71 signal sclk_Inv : std_logic;
72 signal WordCount : integer range 0 to WordCnt-1;
73 signal WordClk : std_logic;
74
75 signal data_int : std_logic;
76
77 signal MuxOUT : std_logic_vector(WordSize-1 downto 0);
78 signal MuxIN : std_logic_vector((2*WordSize)-1 downto 0);
79 signal Sel : integer range 0 to 1;
80
81 signal AMR1X : std_logic_vector(23 downto 0);
82 signal AMR1Y : std_logic_vector(23 downto 0);
83 signal AMR1Z : std_logic_vector(23 downto 0);
84
85 signal AMR2X : std_logic_vector(23 downto 0);
86 signal AMR2Y : std_logic_vector(23 downto 0);
87 signal AMR2Z : std_logic_vector(23 downto 0);
88
89 signal AMR3X : std_logic_vector(23 downto 0);
90 signal AMR3Y : std_logic_vector(23 downto 0);
91 signal AMR3Z : std_logic_vector(23 downto 0);
92
93 signal AMR4X : std_logic_vector(23 downto 0);
94 signal AMR4Y : std_logic_vector(23 downto 0);
95 signal AMR4Z : std_logic_vector(23 downto 0);
96
97 signal AMR1X_ADC : std_logic_vector(23 downto 0);
98 signal AMR1Y_ADC : std_logic_vector(23 downto 0);
99 signal AMR1Z_ADC : std_logic_vector(23 downto 0);
100
101 signal AMR2X_ADC : std_logic_vector(23 downto 0);
102 signal AMR2Y_ADC : std_logic_vector(23 downto 0);
103 signal AMR2Z_ADC : std_logic_vector(23 downto 0);
104
105 signal AMR3X_ADC : std_logic_vector(23 downto 0);
106 signal AMR3Y_ADC : std_logic_vector(23 downto 0);
107 signal AMR3Z_ADC : std_logic_vector(23 downto 0);
108
109 signal AMR4X_ADC : std_logic_vector(23 downto 0);
110 signal AMR4Y_ADC : std_logic_vector(23 downto 0);
111 signal AMR4Z_ADC : std_logic_vector(23 downto 0);
112
113 signal AMR1X_R : std_logic_vector(23 downto 0);
114 signal AMR1Y_R : std_logic_vector(23 downto 0);
115 signal AMR1Z_R : std_logic_vector(23 downto 0);
116
117 signal AMR2X_R : std_logic_vector(23 downto 0);
118 signal AMR2Y_R : std_logic_vector(23 downto 0);
119 signal AMR2Z_R : std_logic_vector(23 downto 0);
120
121 signal AMR3X_R : std_logic_vector(23 downto 0);
122 signal AMR3Y_R : std_logic_vector(23 downto 0);
123 signal AMR3Z_R : std_logic_vector(23 downto 0);
124
125 signal AMR4X_R : std_logic_vector(23 downto 0);
126 signal AMR4Y_R : std_logic_vector(23 downto 0);
127 signal AMR4Z_R : std_logic_vector(23 downto 0);
128
129 signal AMR1X_S : std_logic_vector(23 downto 0);
130 signal AMR1Y_S : std_logic_vector(23 downto 0);
131 signal AMR1Z_S : std_logic_vector(23 downto 0);
132
133 signal AMR2X_S : std_logic_vector(23 downto 0);
134 signal AMR2Y_S : std_logic_vector(23 downto 0);
135 signal AMR2Z_S : std_logic_vector(23 downto 0);
136
137 signal AMR3X_S : std_logic_vector(23 downto 0);
138 signal AMR3Y_S : std_logic_vector(23 downto 0);
139 signal AMR3Z_S : std_logic_vector(23 downto 0);
140
141 signal AMR4X_S : std_logic_vector(23 downto 0);
142 signal AMR4Y_S : std_logic_vector(23 downto 0);
143 signal AMR4Z_s : std_logic_vector(23 downto 0);
144
145
146
147 signal Temp1 : std_logic_vector(23 downto 0);
148 signal Temp2 : std_logic_vector(23 downto 0);
149 signal Temp3 : std_logic_vector(23 downto 0);
150 signal Temp4 : std_logic_vector(23 downto 0);
151
152
153 signal LF1 : std_logic_vector(15 downto 0);
154 signal LF2 : std_logic_vector(15 downto 0);
155 signal LF3 : std_logic_vector(15 downto 0);
156
157
158 signal LF1_int : std_logic_vector(23 downto 0);
159 signal LF2_int : std_logic_vector(23 downto 0);
160 signal LF3_int : std_logic_vector(23 downto 0);
161
162 signal DC_ADC_SmplClk : std_logic;
163 signal LF_ADC_SmplClk : std_logic;
164 signal SET_RESET0_sig : std_logic;
165 signal SET_RESET1_sig : std_logic;
166 signal SET_RESET_counter : integer range 0 to 31:=0;
167
168 signal MinFCnt : integer range 0 to MinFCount-1;
169
170 signal FramePlacerFlags : std_logic_vector(FramePlacerCount-1 downto 0);
171
172 begin
173
174
175 clk_buf <= clk;
176 reset_buf <= reset;
177 --
178
179 Gate_Inv <= not Gate;
180 sclk_Inv <= not Sclk;
181 MinF_Inv <= not MinF;
182
183 LED <= not data_int;
184 data <= data_int;
185
186
187
188 SD0 : Serial_Driver
189 generic map(WordSize)
190 port map(sclk_Inv,MuxOUT,Gate_inv,data_int);
191
192 WC0 : Word_Cntr
193 generic map(WordSize,WordCnt)
194 port map(sclk_Inv,MinF,WordClk,WordCount);
195
196 MFC0 : MinF_Cntr
197 generic map(MinFCount)
198 port map(
199 clk => MinF_Inv,
200 reset => MajF,
201 Cnt_out => MinFCnt
202 );
203
204
205 MUX0 : Serial_Driver_Multiplexor
206 generic map(FramePlacerCount,WordSize)
207 port map(sclk_Inv,Sel,MuxIN,MuxOUT);
208
209
210 DCFP0 : entity work.DC_FRAME_PLACER
211 generic map(WordSize,WordCnt,MinFCount)
212 port map(
213 clk => Sclk,
214 Wcount => WordCount,
215 MinFCnt => MinFCnt,
216 Flag => FramePlacerFlags(0),
217 AMR1X => AMR1X,
218 AMR1Y => AMR1Y,
219 AMR1Z => AMR1Z,
220 AMR2X => AMR2X,
221 AMR2Y => AMR2Y,
222 AMR2Z => AMR2Z,
223 AMR3X => AMR3X,
224 AMR3Y => AMR3Y,
225 AMR3Z => AMR3Z,
226 AMR4X => AMR4X,
227 AMR4Y => AMR4Y,
228 AMR4Z => AMR4Z,
229 Temp1 => Temp1,
230 Temp2 => Temp2,
231 Temp3 => Temp3,
232 Temp4 => Temp4,
233 WordOut => MuxIN(7 downto 0));
234
235
236
237 LFP0 : entity work.LF_FRAME_PLACER
238 generic map(WordSize,WordCnt,MinFCount)
239 port map(
240 clk => Sclk,
241 Wcount => WordCount,
242 Flag => FramePlacerFlags(1),
243 LF1 => LF1,
244 LF2 => LF2,
245 LF3 => LF3,
246 WordOut => MuxIN(15 downto 8));
247
248
249
250 DC_SMPL_CLK0 : entity work.LF_SMPL_CLK
251 generic map(36)
252 port map(
253 reset => reset,
254 wclk => WordClk,
255 SMPL_CLK => DC_ADC_SmplClk);
256
257 process(reset,DC_ADC_SmplClk)
258 begin
259 if reset = '0' then
260 SET_RESET0_sig <= '0';
261 elsif DC_ADC_SmplClk'event and DC_ADC_SmplClk = '0' then
262 if(SET_RESET_counter = 31) then
263 SET_RESET0_sig <= not SET_RESET0_sig;
264 SET_RESET_counter <= 0;
265 else
266 SET_RESET_counter <= SET_RESET_counter +1;
267 end if;
268 end if;
269 end process;
270
271 SET_RESET1_sig <= SET_RESET0_sig;
272 SET_RESET0 <= SET_RESET0_sig;
273 SET_RESET1 <= SET_RESET1_sig;
274 --
275
276
277
278 send_ADC_DATA : IF SEND_CONSTANT_DATA = 0 GENERATE
279 DC_ADC0 : DUAL_ADS1278_DRIVER --With AMR down ! => 24bits DC TM -> SC high res on Spin
280 port map(
281 Clk => clk_buf,
282 reset => reset_buf,
283 SpiClk => DC_ADC_Sclk,
284 DIN => DC_ADC_IN,
285 SmplClk => DC_ADC_SmplClk,
286 OUT00 => AMR1X,
287 OUT01 => AMR1Y,
288 OUT02 => AMR1Z,
289 OUT03 => AMR2X,
290 OUT04 => AMR2Y,
291 OUT05 => AMR2Z,
292 OUT06 => Temp1,
293 OUT07 => Temp2,
294 OUT10 => AMR3X,
295 OUT11 => AMR3Y,
296 OUT12 => AMR3Z,
297 OUT13 => AMR4X,
298 OUT14 => AMR4Y,
299 OUT15 => AMR4Z,
300 OUT16 => Temp3,
301 OUT17 => Temp4,
302 FSynch => DC_ADC_FSynch
303 );
304 LF1 <= LF1cst;
305 LF2 <= LF2cst;
306 LF3 <= LF3cst;
307 END GENERATE;
308
309 send_CST_DATA : IF (SEND_CONSTANT_DATA = 1) and (SEND_MINF_VALUE = 0) GENERATE
310 AMR1X <= AMR1Xcst;
311 AMR1Y <= AMR1Ycst;
312 AMR1Z <= AMR1Zcst;
313 AMR2X <= AMR2Xcst;
314 AMR2Y <= AMR2Ycst;
315 AMR2Z <= AMR2Zcst;
316 Temp1 <= Temp1cst;
317 Temp2 <= Temp2cst;
318 AMR3X <= AMR3Xcst;
319 AMR3Y <= AMR3Ycst;
320 AMR3Z <= AMR3Zcst;
321 AMR4X <= AMR4Xcst;
322 AMR4Y <= AMR4Ycst;
323 AMR4Z <= AMR4Zcst;
324 Temp3 <= Temp3cst;
325 Temp4 <= Temp4cst;
326
327 LF1 <= LF1cst;
328 LF2 <= LF2cst;
329 LF3 <= LF3cst;
330 END GENERATE;
331
332
333
334
335 send_minF_valuelbl : IF (SEND_CONSTANT_DATA = 1) and (SEND_MINF_VALUE = 1) GENERATE
336 AMR1X <= X"000" & "000" & std_logic_vector(TO_UNSIGNED(MinFCnt,9));
337 AMR1Y <= X"000" & "000" & std_logic_vector(TO_UNSIGNED(MinFCnt,9));
338 AMR1Z <= X"000" & "000" & std_logic_vector(TO_UNSIGNED(MinFCnt,9));
339 AMR2X <= X"000" & "000" & std_logic_vector(TO_UNSIGNED(MinFCnt,9));
340 AMR2Y <= X"000" & "000" & std_logic_vector(TO_UNSIGNED(MinFCnt,9));
341 AMR2Z <= X"000" & "000" & std_logic_vector(TO_UNSIGNED(MinFCnt,9));
342 Temp1 <= X"000" & "000" & std_logic_vector(TO_UNSIGNED(MinFCnt,9));
343 Temp2 <= X"000" & "000" & std_logic_vector(TO_UNSIGNED(MinFCnt,9));
344 AMR3X <= X"000" & "000" & std_logic_vector(TO_UNSIGNED(MinFCnt,9));
345 AMR3Y <= X"000" & "000" & std_logic_vector(TO_UNSIGNED(MinFCnt,9));
346 AMR3Z <= X"000" & "000" & std_logic_vector(TO_UNSIGNED(MinFCnt,9));
347 AMR4X <= X"000" & "000" & std_logic_vector(TO_UNSIGNED(MinFCnt,9));
348 AMR4Y <= X"000" & "000" & std_logic_vector(TO_UNSIGNED(MinFCnt,9));
349 AMR4Z <= X"000" & "000" & std_logic_vector(TO_UNSIGNED(MinFCnt,9));
350 Temp3 <= X"000" & "000" & std_logic_vector(TO_UNSIGNED(MinFCnt,9));
351 Temp4 <= X"000" & "000" & std_logic_vector(TO_UNSIGNED(MinFCnt,9));
352
353 LF1 <= LF1cst;
354 LF2 <= LF2cst;
355 LF3 <= LF3cst;
356 END GENERATE;
357
358 LF_SMPL_CLK0 : entity work.LF_SMPL_CLK
359 port map(
360 reset => reset,
361 wclk => WordClk,
362 SMPL_CLK => LF_ADC_SmplClk
363 );
364
365
366 sr_hndl: IF SEND_CONSTANT_DATA = 0 GENERATE
367 process(clk)
368 begin
369 if clk'event and clk ='1' then
370 if SET_RESET0_sig = '1' then
371 AMR1X_S <= AMR1X_ADC;
372 AMR1Y_S <= AMR1Y_ADC;
373 AMR1Z_S <= AMR1Z_ADC;
374 AMR2X_S <= AMR2X_ADC;
375 AMR2Y_S <= AMR2Y_ADC;
376 AMR2Z_S <= AMR2Z_ADC;
377 AMR3X_S <= AMR3X_ADC;
378 AMR3Y_S <= AMR3Y_ADC;
379 AMR3Z_S <= AMR3Z_ADC;
380 AMR4X_S <= AMR4X_ADC;
381 AMR4Y_S <= AMR4Y_ADC;
382 AMR4Z_S <= AMR4Z_ADC;
383 else
384 AMR1X_R <= AMR1X_ADC;
385 AMR1Y_R <= AMR1Y_ADC;
386 AMR1Z_R <= AMR1Z_ADC;
387 AMR2X_R <= AMR2X_ADC;
388 AMR2Y_R <= AMR2Y_ADC;
389 AMR2Z_R <= AMR2Z_ADC;
390 AMR3X_R <= AMR3X_ADC;
391 AMR3Y_R <= AMR3Y_ADC;
392 AMR3Z_R <= AMR3Z_ADC;
393 AMR4X_R <= AMR4X_ADC;
394 AMR4Y_R <= AMR4Y_ADC;
395 AMR4Z_R <= AMR4Z_ADC;
396 end if;
397 -- AMR1X <= std_logic_vector((signed(AMR1X_S) - signed(AMR1X_R))/2);
398 -- AMR1Y <= std_logic_vector((signed(AMR1Y_S) - signed(AMR1Y_R))/2);
399 -- AMR1Z <= std_logic_vector((signed(AMR1Z_S) - signed(AMR1Z_R))/2);
400 -- AMR2X <= std_logic_vector((signed(AMR2X_S) - signed(AMR2X_R))/2);
401 -- AMR2Y <= std_logic_vector((signed(AMR2Y_S) - signed(AMR2Y_R))/2);
402 -- AMR2Z <= std_logic_vector((signed(AMR2Z_S) - signed(AMR2Z_R))/2);
403 -- AMR3X <= std_logic_vector((signed(AMR3X_S) - signed(AMR3X_R))/2);
404 -- AMR3Y <= std_logic_vector((signed(AMR3Y_S) - signed(AMR3Y_R))/2);
405 -- AMR3Z <= std_logic_vector((signed(AMR3Z_S) - signed(AMR3Z_R))/2);
406 -- AMR4X <= std_logic_vector((signed(AMR4X_S) - signed(AMR4X_R))/2);
407 -- AMR4Y <= std_logic_vector((signed(AMR4Y_S) - signed(AMR4Y_R))/2);
408 -- AMR4Z <= std_logic_vector((signed(AMR4Z_S) - signed(AMR4Z_R))/2);
409 -- AMR1X <= AMR1X_S;
410 -- AMR1Y <= AMR1Y_S;
411 -- AMR1Z <= AMR1Z_S;
412 -- AMR2X <= AMR2X_S;
413 -- AMR2Y <= AMR2Y_S;
414 -- AMR2Z <= AMR2Z_S;
415 -- AMR3X <= AMR3X_S;
416 -- AMR3Y <= AMR3Y_S;
417 -- AMR3Z <= AMR3Z_S;
418 -- AMR4X <= AMR4X_S;
419 -- AMR4Y <= AMR4Y_S;
420 -- AMR4Z <= AMR4Z_S;
421 end if;
422 end process;
423 end generate;
424
425
426 process(clk)
427 variable SelVar : integer range 0 to 1;
428 begin
429 if clk'event and clk ='1' then
430 Decoder: FOR i IN 0 to FramePlacerCount-1 loop
431 if FramePlacerFlags(i) = '1' then
432 SelVar := i;
433 end if;
434 END loop Decoder;
435 Sel <= SelVar;
436 end if;
437 end process;
438
439
440 end rtl;
441
442
443
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1 library IEEE;
2 use IEEE.STD_LOGIC_1164.ALL;
3 library lpp;
4 use lpp.lpp_ad_conv.all;
5 use lpp.lpp_amba.all;
6 use lpp.apb_devices_list.all;
7 use lpp.general_purpose.all;
8 use lpp.Rocket_PCM_Encoder.all;
9 use lpp.iir_filter.all;
10 use work.config.all;
11
12 entity LF_ACQ_TOP is
13 generic(
14 WordSize : integer := 8;
15 WordCnt : integer := 144;
16 MinFCount : integer := 64;
17 CstDATA : integer := 0;
18 IIRFilter : integer := 1
19 );
20 port(
21
22 reset : in std_logic;
23 clk : in std_logic;
24 SyncSig : in STD_LOGIC;
25 minorF : in std_logic;
26 majorF : in std_logic;
27 sclk : in std_logic;
28 WordClk : in std_logic;
29 LF_SCK : out std_logic;
30 LF_CNV : out std_logic;
31 LF_SDO1 : in std_logic;
32 LF_SDO2 : in std_logic;
33 LF_SDO3 : in std_logic;
34 LF1 : out std_logic_vector(15 downto 0);
35 LF2 : out std_logic_vector(15 downto 0);
36 LF3 : out std_logic_vector(15 downto 0)
37 );
38 end LF_ACQ_TOP;
39
40 architecture AR_LF_ACQ_TOP of LF_ACQ_TOP is
41
42 signal LF_ADC_SmplClk : std_logic;
43
44 signal LF_ADC_SpPulse : std_logic;
45 signal SDO : STD_LOGIC_VECTOR(2 DOWNTO 0);
46 signal sps : Samples(2 DOWNTO 0);
47
48 signal LFX : Samples(2 DOWNTO 0);
49 signal sample_val : std_logic;
50 signal AD_in : AD7688_in(2 DOWNTO 0);
51 signal AD_out : AD7688_out;
52 signal Filter_sp_in : samplT(2 DOWNTO 0, 15 DOWNTO 0);
53 signal Filter_sp_out : samplT(2 DOWNTO 0, 15 DOWNTO 0);
54 signal sample_out_val : std_logic;
55
56 begin
57
58
59 AD_in(0).sdi <= LF_SDO1;
60 AD_in(1).sdi <= LF_SDO2;
61 AD_in(2).sdi <= LF_SDO3;
62 LF_SCK <= AD_out.SCK;
63 LF_CNV <= AD_out.CNV;
64
65
66 LF_SMPL_CLK0 : entity work.LF_SMPL_CLK
67 generic map(6)
68 port map(
69 reset => reset,
70 wclk => WordClk,
71 SMPL_CLK => LF_ADC_SmplClk
72 );
73
74
75 ADC: IF CstDATA =0 GENERATE
76 ADCs: AD7688_drvr
77 GENERIC map
78 (
79 ChanelCount => 3,
80 clkkHz => 48000
81 )
82 PORT map
83 (
84 clk => clk,
85 rstn => reset,
86 enable => '1',
87 smplClk => LF_ADC_SmplClk,
88 DataReady => sample_val,
89 smpout => sps,
90 AD_in => AD_in,
91 AD_out => AD_out
92 );
93
94 smpPulse: entity work.OneShot
95 Port map(
96 reset => reset,
97 clk => clk,
98 input => LF_ADC_SmplClk,
99 output => LF_ADC_SpPulse
100 );
101
102
103
104 Filter: IIR_CEL_CTRLR_v2
105 GENERIC map(
106 tech => CFG_MEMTECH,
107 Mem_use => use_RAM,
108 Sample_SZ => Sample_SZ,
109 Coef_SZ => Coef_SZ,
110 Coef_Nb => 25,
111 Coef_sel_SZ => 5,
112 Cels_count => 5,
113 ChanelsCount => ChanelsCount
114 )
115 PORT map(
116 rstn => reset,
117 clk => clk,
118
119 virg_pos => virgPos,
120 coefs => CoefsInitValCst_v2,
121
122 sample_in_val => LF_ADC_SpPulse,
123 sample_in => Filter_sp_in,
124
125 sample_out_val => sample_out_val,
126 sample_out => Filter_sp_out
127 );
128
129 NOfilt: IF IIRFilter = 0 GENERATE
130 process(reset,clk)
131 begin
132 if reset ='0' then
133 LF1 <= (others => '0');
134 LF2 <= (others => '0');
135 LF3 <= (others => '0');
136 elsif clk'event and clk ='1' then
137 if sample_val = '1' then
138 LF1 <= sps(0);
139 LF2 <= sps(1);
140 LF3 <= sps(2);
141 end if;
142 end if;
143 end process;
144 END GENERATE;
145 filt: IF IIRFilter /= 0 GENERATE
146
147 LF1 <= LFX(0);
148 LF2 <= LFX(1);
149 LF3 <= LFX(2);
150
151 loop_all_sample : FOR J IN 15 DOWNTO 0 GENERATE
152
153 loop_all_chanel : FOR I IN 2 DOWNTO 0 GENERATE
154 process(reset,clk)
155 begin
156 if reset ='0' then
157 Filter_sp_in(I,J) <= '0';
158 -- LFX(I) <= (others => '0');
159 elsif clk'event and clk ='1' then
160 if sample_out_val = '1' then
161 LFX(I)(J) <= Filter_sp_out(I,J);
162 Filter_sp_in(I,J) <= sps(I)(J);
163 end if;
164 end if;
165 end process;
166 END GENERATE;
167 END GENERATE;
168 END GENERATE;
169
170
171
172
173 END GENERATE;
174
175 CST: IF CstDATA /=0 GENERATE
176
177 LF1 <= LF1cst;
178 LF2 <= LF2cst;
179 LF3 <= LF3cst;
180
181 END GENERATE;
182
183
184
185
186 --Filter: IIR_CEL_FILTER
187 -- GENERIC map(
188 -- tech => CFG_MEMTECH,
189 -- Sample_SZ => Sample_SZ,
190 -- ChanelsCount => ChanelsCount,
191 -- Coef_SZ => Coef_SZ,
192 -- CoefCntPerCel => CoefCntPerCel,
193 -- Cels_count => Cels_count,
194 -- Mem_use => use_RAM
195 -- )
196 -- PORT map(
197 -- reset => reset,
198 -- clk => clk,
199 -- sample_clk => LF_ADC_SmplClk,
200 -- regs_in : IN in_IIR_CEL_reg;
201 -- regs_out : IN out_IIR_CEL_reg;
202 -- sample_in : IN samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0);
203 -- sample_out : OUT samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0);
204 -- GOtest : OUT STD_LOGIC;
205 -- coefs : IN STD_LOGIC_VECTOR(Coef_SZ*CoefCntPerCel*Cels_count-1 DOWNTO 0)
206 --
207 -- );
208
209
210
211
212 end AR_LF_ACQ_TOP;
213
214
215
216
217
218
219
220
221
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@@ -0,0 +1,67
1 ----------------------------------------------------------------------------------
2 -- Company:
3 -- Engineer:
4 --
5 -- Create Date: 21:06:46 08/22/2013
6 -- Design Name:
7 -- Module Name: OneShot - AR_OneShot
8 -- Project Name:
9 -- Target Devices:
10 -- Tool versions:
11 -- Description:
12 --
13 -- Dependencies:
14 --
15 -- Revision:
16 -- Revision 0.01 - File Created
17 -- Additional Comments:
18 --
19 ----------------------------------------------------------------------------------
20 library IEEE;
21 use IEEE.STD_LOGIC_1164.ALL;
22
23 -- Uncomment the following library declaration if using
24 -- arithmetic functions with Signed or Unsigned values
25 --use IEEE.NUMERIC_STD.ALL;
26
27 -- Uncomment the following library declaration if instantiating
28 -- any Xilinx primitives in this code.
29 --library UNISIM;
30 --use UNISIM.VComponents.all;
31
32 entity OneShot is
33 Port ( reset : in STD_LOGIC;
34 clk : in STD_LOGIC;
35 input : in STD_LOGIC;
36 output : out STD_LOGIC);
37 end OneShot;
38
39 architecture AR_OneShot of OneShot is
40 signal inreg : std_logic;
41 begin
42
43 process(clk,reset)
44 begin
45 if reset = '0' then
46 output <= '0';
47 elsif clk'event and clk = '1' then
48 inreg <= input;
49 if inreg = '0' and input = '1' then
50 output <= '1';
51 else
52 output <= '0';
53 end if;
54 end if;
55 end process;
56
57 end AR_OneShot;
58
59
60
61
62
63
64
65
66
67
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@@ -0,0 +1,91
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2013, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 ------------------------------------------------------------------------------
19 -- Author : Alexis Jeandet
20 -- Mail : alexis.jeandet@member.fsf.org
21 ------------------------------------------------------------------------------
22 --
23 -- This module implements the Slow to Slow Fast transfer:
24 -- Data Transfer between Asynchronous Clock Domains without Pain
25 -- from Markus Schutti, Markus Pfaff, Richard Hagelauer
26 -- http://www-micrel.deis.unibo.it/~benini/files/SNUG/paper9_final.pdf
27 -- see page 5
28 --
29 --
30
31 library IEEE;
32 use IEEE.STD_LOGIC_1164.ALL;
33
34 entity Slow2FastSync is
35 generic
36 (
37 N : integer range 0 to 256:=8
38 );
39 Port
40 (
41 Data : in STD_LOGIC_VECTOR (N-1 downto 0);
42 ClockF : in STD_LOGIC;
43 ClockS : in STD_LOGIC;
44 SyncSignal : in STD_LOGIC;
45 DataSinkS : out STD_LOGIC_VECTOR (N-1 downto 0)
46 );
47 end Slow2FastSync;
48
49 architecture AR_Slow2FastSync of Slow2FastSync is
50
51 signal DataS : STD_LOGIC_VECTOR (N-1 downto 0);
52
53
54 begin
55
56
57
58 process(ClockF)
59 begin
60 if ClockF'event and ClockF = '1' and SyncSignal = '1' then
61 DataSinkS <= DataS;
62 end if;
63 end process;
64
65 process(ClockS)
66 begin
67 if ClockS'event and ClockS = '1' then
68 DataS <= Data;
69 end if;
70 end process;
71
72 end AR_Slow2FastSync;
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
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@@ -0,0 +1,177
1 ----------------------------------------------------------------------------------
2 -- Company:
3 -- Engineer:
4 --
5 -- Create Date: 10:03:54 08/21/2013
6 -- Design Name:
7 -- Module Name: TM_MODULE - AR_TM_MODULE
8 -- Project Name:
9 -- Target Devices:
10 -- Tool versions:
11 -- Description:
12 --
13 -- Dependencies:
14 --
15 -- Revision:
16 -- Revision 0.01 - File Created
17 -- Additional Comments:
18 --
19 ----------------------------------------------------------------------------------
20 library IEEE;
21 use IEEE.STD_LOGIC_1164.ALL;
22 library lpp;
23 use lpp.lpp_ad_conv.all;
24 use lpp.lpp_amba.all;
25 use lpp.apb_devices_list.all;
26 use lpp.general_purpose.all;
27 use lpp.Rocket_PCM_Encoder.all;
28
29 entity TM_MODULE is
30 generic(
31 WordSize : integer := 8; WordCnt : integer := 144;MinFCount : integer := 64
32 );
33 port(
34
35 reset : in std_logic;
36 clk : in std_logic;
37 MinF : in std_logic;
38 MajF : in std_logic;
39 sclk : in std_logic;
40 gate : in std_logic;
41 data : out std_logic;
42 WordClk : out std_logic;
43
44
45 LF1 : in std_logic_vector(15 downto 0);
46 LF2 : in std_logic_vector(15 downto 0);
47 LF3 : in std_logic_vector(15 downto 0);
48
49 AMR1X : in std_logic_vector(23 downto 0);
50 AMR1Y : in std_logic_vector(23 downto 0);
51 AMR1Z : in std_logic_vector(23 downto 0);
52
53 AMR2X : in std_logic_vector(23 downto 0);
54 AMR2Y : in std_logic_vector(23 downto 0);
55 AMR2Z : in std_logic_vector(23 downto 0);
56
57 AMR3X : in std_logic_vector(23 downto 0);
58 AMR3Y : in std_logic_vector(23 downto 0);
59 AMR3Z : in std_logic_vector(23 downto 0);
60
61 AMR4X : in std_logic_vector(23 downto 0);
62 AMR4Y : in std_logic_vector(23 downto 0);
63 AMR4Z : in std_logic_vector(23 downto 0);
64
65 Temp1 : in std_logic_vector(23 downto 0);
66 Temp2 : in std_logic_vector(23 downto 0);
67 Temp3 : in std_logic_vector(23 downto 0);
68 Temp4 : in std_logic_vector(23 downto 0)
69 );
70 end TM_MODULE;
71
72 architecture AR_TM_MODULE of TM_MODULE is
73
74 Constant FramePlacerCount : integer := 2;
75 signal MinFCnt : integer range 0 to MinFCount-1;
76 signal FramePlacerFlags : std_logic_vector(FramePlacerCount-1 downto 0);
77
78 signal WordCount : integer range 0 to WordCnt-1;
79
80 signal data_int : std_logic;
81
82 signal MuxOUT : std_logic_vector(WordSize-1 downto 0);
83 signal MuxIN : std_logic_vector((2*WordSize)-1 downto 0);
84 signal Sel : integer range 0 to 1;
85
86
87 signal MinF_Inv : std_logic;
88 signal Gate_Inv : std_logic;
89 signal sclk_Inv : std_logic;
90
91 begin
92
93
94 Gate_Inv <= not Gate;
95 sclk_Inv <= not Sclk;
96 MinF_Inv <= not MinF;
97 data <= data_int;
98
99 SD0 : Serial_Driver
100 generic map(WordSize)
101 port map(sclk_Inv,MuxOUT,Gate_inv,data_int);
102
103 WC0 : Word_Cntr
104 generic map(WordSize,WordCnt)
105 port map(sclk_Inv,MinF,WordClk,WordCount);
106
107 MFC0 : MinF_Cntr
108 generic map(MinFCount)
109 port map(
110 clk => MinF_Inv,
111 reset => MajF,
112 Cnt_out => MinFCnt
113 );
114
115
116 MUX0 : Serial_Driver_Multiplexor
117 generic map(FramePlacerCount,WordSize)
118 port map(sclk_Inv,Sel,MuxIN,MuxOUT);
119
120
121 DCFP0 : entity work.DC_FRAME_PLACER
122 generic map(WordSize,WordCnt,MinFCount)
123 port map(
124 clk => Sclk,
125 Wcount => WordCount,
126 MinFCnt => MinFCnt,
127 Flag => FramePlacerFlags(0),
128 AMR1X => AMR1X,
129 AMR1Y => AMR1Y,
130 AMR1Z => AMR1Z,
131 AMR2X => AMR2X,
132 AMR2Y => AMR2Y,
133 AMR2Z => AMR2Z,
134 AMR3X => AMR3X,
135 AMR3Y => AMR3Y,
136 AMR3Z => AMR3Z,
137 AMR4X => AMR4X,
138 AMR4Y => AMR4Y,
139 AMR4Z => AMR4Z,
140 Temp1 => Temp1,
141 Temp2 => Temp2,
142 Temp3 => Temp3,
143 Temp4 => Temp4,
144 WordOut => MuxIN(7 downto 0));
145
146
147
148 LFP0 : entity work.LF_FRAME_PLACER
149 generic map(WordSize,WordCnt,MinFCount)
150 port map(
151 clk => Sclk,
152 Wcount => WordCount,
153 Flag => FramePlacerFlags(1),
154 LF1 => LF1,
155 LF2 => LF2,
156 LF3 => LF3,
157 WordOut => MuxIN(15 downto 8));
158
159
160
161 process(clk)
162 variable SelVar : integer range 0 to 1;
163 begin
164 if clk'event and clk ='1' then
165 Decoder: FOR i IN 0 to FramePlacerCount-1 loop
166 if FramePlacerFlags(i) = '1' then
167 SelVar := i;
168 end if;
169 END loop Decoder;
170 Sel <= SelVar;
171 end if;
172 end process;
173
174
175
176 end AR_TM_MODULE;
177
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@@ -1,11 +1,31
1 NET "CLK" LOC = "B10";
1 NET "CLK" LOC = "B10" | IOSTANDARD = LVCMOS33;
2
3 NET "RESET" CLOCK_DEDICATED_ROUTE = FALSE;
2 4 NET "RESET" LOC = "A5" | IOSTANDARD = LVTTL;
5
6 NET "SCLK" CLOCK_DEDICATED_ROUTE = FALSE;
3 7 NET "SCLK" LOC = "V22" | IOSTANDARD = LVTTL;
8
4 9 NET "GATE" LOC = "T22" | IOSTANDARD = LVTTL;
10
11 NET "MINF" CLOCK_DEDICATED_ROUTE = FALSE;
5 12 NET "MINF" LOC = "T21" | IOSTANDARD = LVTTL;
13
6 14 NET "MAJF" LOC = "U22" | IOSTANDARD = LVTTL;
7 NET "DATA" LOC = "V21";
8 NET "DC_ADC_SCLK" LOC = "AB17";
15 NET "DATA" LOC = "V21" | IOSTANDARD = LVCMOS33;
16 NET "DC_ADC_SCLK" LOC = "AB17" | IOSTANDARD = LVCMOS33;
9 17 NET "DC_ADC_IN(0)" LOC = "AB19" | IOSTANDARD = LVTTL;
10 18 NET "DC_ADC_IN(1)" LOC = "AA18" | IOSTANDARD = LVTTL;
11 NET "DC_ADC_FSynch" LOC = "AB18";
19 NET "DC_ADC_FSynch" LOC = "AB18" | IOSTANDARD = LVCMOS33;
20 NET "LED" LOC = "A3" | IOSTANDARD = LVCMOS33;
21 NET "SET_RESET0" LOC = "AB21" | IOSTANDARD = LVCMOS33;
22 NET "SET_RESET1" LOC = "AB20" | IOSTANDARD = LVCMOS33;
23
24
25 NET "LF_SCK" LOC = "W20"| IOSTANDARD = LVCMOS33;
26 NET "LF_CNV" LOC = "Y18"| IOSTANDARD = LVCMOS33;
27 NET "LF_SDO1" LOC = "W17" | IOSTANDARD = LVTTL;
28 NET "LF_SDO2" LOC = "AA21" | IOSTANDARD = LVTTL;
29 NET "LF_SDO3" LOC = "AA16" | IOSTANDARD = LVTTL;
30
31
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@@ -4,10 +4,11 use IEEE.numeric_std.all;
4 4 use IEEE.std_logic_1164.all;
5 5
6 6
7 entity LF_SMPL_CLK is
7 entity LF_SMPL_CLK is
8 generic(N : integer range 0 to 4096 :=24);
8 9 port(
9 Wclck : in std_logic;
10 MinF : in std_logic;
10 reset : in std_logic;
11 wclk : in std_logic;
11 12 SMPL_CLK : out std_logic
12 13 );
13 14 end entity;
@@ -19,24 +20,25 end entity;
19 20
20 21 architecture ar_LF_SMPL_CLK of LF_SMPL_CLK is
21 22
22 signal cpt : integer range 0 to 23 := 0;
23 signal cpt : integer range 0 to N-1 := 0;
23 24 begin
24 25
25 26
26 27
27 process(Wclck,MinF)
28 process(reset,wclk)
28 29 begin
29 if MinF = '0' then
30 SMPL_CLK <= '1';
31 elsif Wclck'event and Wclck = '1' then
32 if cpt = 23 then
30 if reset = '0' then
31 SMPL_CLK <= '1';
32 cpt <= 0;
33 elsif wclk'event and wclk = '1' then
34 if cpt = (N-1) then
33 35 cpt <= 0;
34 36 else
35 37 cpt <= cpt+1;
36 38 end if;
37 39 if cpt = 0 then
38 40 SMPL_CLK <= '1';
39 elsif cpt = 10 then
41 elsif cpt = (N/2) then
40 42 SMPL_CLK <= '0';
41 43 end if;
42 44 end if;
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@@ -4,11 +4,11 include .config
4 4 TOP=ici4
5 5 BOARD=ICI4-main-BD
6 6 #BOARD=SP601
7 include $(GRLIB)/boards/$(BOARD)/Makefile.inc
7 include ../../boards/$(BOARD)/Makefile.inc
8 8 DEVICE=$(PART)-$(PACKAGE)$(SPEED)
9 9 #UCF=$(GRLIB)/boards/$(BOARD)/ICI3.ucf
10 UCF=$(GRLIB)/boards/$(BOARD)/ICI4-Main-BD.ucf
11 QSF=$(GRLIB)/boards/$(BOARD)/$(TOP).qsf
10 UCF=../../boards/$(BOARD)/ICI4-Main-BD.ucf
11 QSF=../../boards/$(BOARD)/$(TOP).qsf
12 12 EFFORT=high
13 13 ISEMAPOPT="-timing"
14 14 XSTOPT=""
@@ -19,7 +19,16 VHDLOPTSYNFILES= \
19 19 ICI4HDL/DC_FRAME_PLACER.vhd \
20 20 ICI4HDL/DC_SMPL_CLK.vhd \
21 21 ICI4HDL/LF_FRAME_PLACER.vhd \
22 ICI4HDL/LF_SMPL_CLK.vhd
22 ICI4HDL/LF_SMPL_CLK.vhd \
23 ICI4HDL/Fast2SlowSync.vhd \
24 ICI4HDL/Slow2FastSync.vhd \
25 ICI4HDL/CrossDomainSyncGen.vhd \
26 ICI4HDL/TM_MODULE.vhd \
27 ICI4HDL/DC_ACQ_TOP.vhd \
28 ICI4HDL/LF_ACQ_TOP.vhd \
29 ICI4HDL/FAKE_ADC.vhd \
30 ICI4HDL/OneShot.vhd
31
23 32
24 33 VHDLSYNFILES= \
25 34 config.vhd ici4.vhd
@@ -27,7 +36,7 VHDLSIMFILES=testbench.vhd
27 36 SIMTOP=testbench
28 37 #SDCFILE=$(GRLIB)/boards/$(BOARD)/default.sdc
29 38 SDCFILE=default.sdc
30 BITGEN=$(GRLIB)/boards/$(BOARD)/default.ut
39 BITGEN=../../boards/$(BOARD)/default.ut
31 40 CLEAN=soft-clean
32 41 VCOMOPT=-explicit
33 42 TECHLIBS = secureip unisim
@@ -47,4 +56,5 include $(GRLIB)/software/leon3/Makefile
47 56
48 57 ################## project specific targets ##########################
49 58
50
59 flash:
60 xc3sprog -c ftdi -p 1 ici4.bit
Show file before | Show file after | Hide comments
@@ -9,8 +9,10
9 9
10 10 library techmap;
11 11 use techmap.gencomp.all;
12 library ieee;
13 use ieee.std_logic_1164.all;
12 LIBRARY IEEE;
13 USE IEEE.numeric_std.ALL;
14 USE IEEE.std_logic_1164.ALL;
15
14 16
15 17 package config is
16 18 -- Technology and synthesis options
@@ -19,8 +21,8 package config is
19 21 constant CFG_PADTECH : integer := spartan6;
20 22 -- Clock generator
21 23 constant CFG_CLKTECH : integer := spartan6;
22 constant SEND_CONSTANT_DATA : integer := 1;
23 constant SEND_MINF_VALUE : integer := 1;
24 constant SEND_CONSTANT_DATA : integer := 0;
25 constant SEND_MINF_VALUE : integer := 0;
24 26
25 27
26 28
@@ -29,13 +31,13 constant LF2cst : std_logic_vector(15
29 31 constant LF3cst : std_logic_vector(15 downto 0) := X"3333";
30 32
31 33
32 constant AMR1Xcst : std_logic_vector(23 downto 0):= X"444444";
33 constant AMR1Ycst : std_logic_vector(23 downto 0):= X"555555";
34 constant AMR1Zcst : std_logic_vector(23 downto 0):= X"666666";
34 constant AMR1Xcst : std_logic_vector(23 downto 0):= X"000001";
35 constant AMR1Ycst : std_logic_vector(23 downto 0):= X"111111";
36 constant AMR1Zcst : std_logic_vector(23 downto 0):= X"7FFFFF";
35 37
36 constant AMR2Xcst : std_logic_vector(23 downto 0):= X"777777";
37 constant AMR2Ycst : std_logic_vector(23 downto 0):= X"888888";
38 constant AMR2Zcst : std_logic_vector(23 downto 0):= X"999999";
38 constant AMR2Xcst : std_logic_vector(23 downto 0):= X"800000";
39 constant AMR2Ycst : std_logic_vector(23 downto 0):= X"000002";
40 constant AMR2Zcst : std_logic_vector(23 downto 0):= X"800001";
39 41
40 42 constant AMR3Xcst : std_logic_vector(23 downto 0):= X"AAAAAA";
41 43 constant AMR3Ycst : std_logic_vector(23 downto 0):= X"BBBBBB";
@@ -49,4 +51,95 constant Temp1cst : std_logic_vec
49 51 constant Temp2cst : std_logic_vector(23 downto 0):= X"343434";
50 52 constant Temp3cst : std_logic_vector(23 downto 0):= X"565656";
51 53 constant Temp4cst : std_logic_vector(23 downto 0):= X"787878";
54
55
56
57 --===========================================================|
58 --========F I L T E R C O N F I G V A L U E S=============|
59 --===========================================================|
60 --____________________________
61 --Bus Width and chanels number|
62 --____________________________|
63 constant ChanelsCount : integer := 3;
64 constant Sample_SZ : integer := 16;
65 constant Coef_SZ : integer := 9;
66 constant CoefCntPerCel: integer := 6;
67 constant CoefPerCel: integer := 5;
68 constant Cels_count : integer := 5;
69 constant virgPos : integer := 7;
70 constant Mem_use : integer := 1;
71
72
73
74 --============================================================
75 -- create each initial values for each coefs ============
76 --!!!!!!!!!!It should be interfaced with a software !!!!!!!!!!
77 --============================================================
78 constant b0_0 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(58,Coef_SZ));
79 constant b0_1 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(-66,Coef_SZ));
80 constant b0_2 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(58,Coef_SZ));
81
82 constant b1_0 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(58,Coef_SZ));
83 constant b1_1 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(-57,Coef_SZ));
84 constant b1_2 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(58,Coef_SZ));
85
86 constant b2_0 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(29,Coef_SZ));
87 constant b2_1 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(-17,Coef_SZ));
88 constant b2_2 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(29,Coef_SZ));
89
90 constant b3_0 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(15,Coef_SZ));
91 constant b3_1 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(4,Coef_SZ));
92 constant b3_2 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(15,Coef_SZ));
93
94 constant b4_0 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(15,Coef_SZ));
95 constant b4_1 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(24,Coef_SZ));
96 constant b4_2 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(15,Coef_SZ));
97
98 --constant b5_0 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(-81,Coef_SZ));
99 --constant b5_1 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(-153,Coef_SZ));
100 --constant b5_2 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(-171,Coef_SZ));
101
102 --constant b6_0 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(-144,Coef_SZ));
103 --constant b6_1 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(-72,Coef_SZ));
104 --constant b6_2 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(-25,Coef_SZ));
105
106
107 constant a0_0 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(-128,Coef_SZ));
108 constant a0_1 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(189,Coef_SZ));
109 constant a0_2 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(-111,Coef_SZ));
110
111 constant a1_0 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(-128,Coef_SZ));
112 constant a1_1 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(162,Coef_SZ));
113 constant a1_2 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(-81,Coef_SZ));
114
115 constant a2_0 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(-128,Coef_SZ));
116 constant a2_1 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(136,Coef_SZ));
117 constant a2_2 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(-55,Coef_SZ));
118
119 constant a3_0 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(-128,Coef_SZ));
120 constant a3_1 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(114,Coef_SZ));
121 constant a3_2 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(-33,Coef_SZ));
122
123 constant a4_0 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(-128,Coef_SZ));
124 constant a4_1 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(100,Coef_SZ));
125 constant a4_2 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(-20,Coef_SZ));
126
127 --constant a5_0 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(60,Coef_SZ));
128 --constant a5_1 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(-128,Coef_SZ));
129 --constant a5_2 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(87,Coef_SZ));
130 --constant a6_0 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(60,Coef_SZ));
131 --constant a6_1 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(-128,Coef_SZ));
132 --constant a6_2 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(87,Coef_SZ));
133
134 constant CoefsInitValCst : std_logic_vector((Cels_count*CoefCntPerCel*Coef_SZ)-1 downto 0) := (a4_2 & a4_1 & a4_0 & b4_2 & b4_1 & b4_0 & a3_2 & a3_1 & a3_0 & b3_2 & b3_1 & b3_0 & a2_2 & a2_1 & a2_0 & b2_2 & b2_1 & b2_0 & a1_2 & a1_1 & a1_0 & b1_2 & b1_1 & b1_0 & a0_2 & a0_1 & a0_0 & b0_2 & b0_1 & b0_0);
135
136 constant CoefsInitValCst_v2 : std_logic_vector((Cels_count*CoefPerCel*Coef_SZ)-1 downto 0) :=
137 (a4_1 & a4_2 & b4_0 & b4_1 & b4_2 &
138 a3_1 & a3_2 & b3_0 & b3_1 & b3_2 &
139 a2_1 & a2_2 & b2_0 & b2_1 & b2_2 &
140 a1_1 & a1_2 & b1_0 & b1_1 & b1_2 &
141 a0_1 & a0_2 & b0_0 & b0_1 & b0_2 );
142
143
144
52 145 end;
Show file before | Show file after | Hide comments
@@ -1,5 +1,5
1 1 library ieee;
2 use ieee.std_logic_1164.all;
2 use ieee.std_logic_1164.all;
3 3 use IEEE.numeric_std.all;
4 4 library grlib, techmap;
5 5 use grlib.amba.all;
@@ -25,6 +25,14 use work.Convertisseur_config.all;
25 25
26 26
27 27 use work.config.all;
28 --==================================================================
29 --
30 --
31 -- FPGA FREQ = 48MHz
32 -- ADC Oscillator frequency = 12MHz
33 --
34 --
35 --==================================================================
28 36
29 37 entity ici4 is
30 38 generic (
@@ -35,20 +43,25 entity ici4 is
35 43 WordSize : integer := 8; WordCnt : integer := 144;MinFCount : integer := 64
36 44 );
37 45 port (
38 reset : in std_ulogic;
39 clk : in std_ulogic;
40 sclk : in std_logic;
41 Gate : in std_logic;
42 MinF : in std_logic;
43 MajF : in std_logic;
44 Data : out std_logic;
45 DC_ADC_Sclk : out std_logic;
46 DC_ADC_IN : in std_logic_vector(1 downto 0);
47 DC_ADC_ClkDiv : out std_logic;
48 DC_ADC_FSynch : out std_logic;
49 SET_RESET0 : out std_logic;
50 SET_RESET1 : out std_logic;
51 LED : out std_logic
46 reset : in std_ulogic;
47 clk : in std_ulogic;
48 sclk : in std_logic;
49 Gate : in std_logic;
50 MinF : in std_logic;
51 MajF : in std_logic;
52 Data : out std_logic;
53 LF_SCK : out std_logic;
54 LF_CNV : out std_logic;
55 LF_SDO1 : in std_logic;
56 LF_SDO2 : in std_logic;
57 LF_SDO3 : in std_logic;
58 DC_ADC_Sclk : out std_logic;
59 DC_ADC_IN : in std_logic_vector(1 downto 0);
60 DC_ADC_ClkDiv : out std_logic;
61 DC_ADC_FSynch : out std_logic;
62 SET_RESET0 : out std_logic;
63 SET_RESET1 : out std_logic;
64 LED : out std_logic
52 65 );
53 66 end;
54 67
@@ -58,17 +71,10 signal clk_buf,reset_buf : std_logi
58 71
59 72 Constant FramePlacerCount : integer := 2;
60 73
61 signal MinF_Inv : std_logic;
62 signal Gate_Inv : std_logic;
63 signal sclk_Inv : std_logic;
74
64 75 signal WordCount : integer range 0 to WordCnt-1;
65 76 signal WordClk : std_logic;
66 77
67 signal data_int : std_logic;
68
69 signal MuxOUT : std_logic_vector(WordSize-1 downto 0);
70 signal MuxIN : std_logic_vector((2*WordSize)-1 downto 0);
71 signal Sel : integer range 0 to 1;
72 78
73 79 signal AMR1X : std_logic_vector(23 downto 0);
74 80 signal AMR1Y : std_logic_vector(23 downto 0);
@@ -86,229 +92,153 signal AMR4X : std_logic_vector(2
86 92 signal AMR4Y : std_logic_vector(23 downto 0);
87 93 signal AMR4Z : std_logic_vector(23 downto 0);
88 94
89 signal Temp1 : std_logic_vector(23 downto 0);
90 signal Temp2 : std_logic_vector(23 downto 0);
91 signal Temp3 : std_logic_vector(23 downto 0);
92 signal Temp4 : std_logic_vector(23 downto 0);
93 95
96 signal TEMP1 : std_logic_vector(23 downto 0);
97 signal TEMP2 : std_logic_vector(23 downto 0);
98 signal TEMP3 : std_logic_vector(23 downto 0);
99 signal TEMP4 : std_logic_vector(23 downto 0);
94 100
95 101 signal LF1 : std_logic_vector(15 downto 0);
96 102 signal LF2 : std_logic_vector(15 downto 0);
97 103 signal LF3 : std_logic_vector(15 downto 0);
98 104
99
100 signal LF1_int : std_logic_vector(23 downto 0);
101 signal LF2_int : std_logic_vector(23 downto 0);
102 signal LF3_int : std_logic_vector(23 downto 0);
105 signal data_int : std_logic;
103 106
104 signal DC_ADC_SmplClk : std_logic;
105 signal LF_ADC_SmplClk : std_logic;
106 signal SET_RESET0_sig : std_logic;
107 signal SET_RESET1_sig : std_logic;
108
109 signal MinFCnt : integer range 0 to MinFCount-1;
110
111 signal FramePlacerFlags : std_logic_vector(FramePlacerCount-1 downto 0);
107 signal CrossDomainSync : std_logic;
112 108
113 109 begin
114 110
115 111
116 clk_buf <= clk;
117 reset_buf <= reset;
118 --
119
120 Gate_Inv <= not Gate;
121 sclk_Inv <= not Sclk;
122 MinF_Inv <= not MinF;
123
124 112 LED <= not data_int;
125 data <= data_int;
126
127
128
129 SD0 : Serial_Driver
130 generic map(WordSize)
131 port map(sclk_Inv,MuxOUT,Gate_inv,data_int);
132
133 WC0 : Word_Cntr
134 generic map(WordSize,WordCnt)
135 port map(sclk_Inv,MinF,WordClk,WordCount);
136
137 MFC0 : MinF_Cntr
138 generic map(MinFCount)
139 port map(
140 clk => MinF_Inv,
141 reset => MajF,
142 Cnt_out => MinFCnt
143 );
144
145
146 MUX0 : Serial_Driver_Multiplexor
147 generic map(FramePlacerCount,WordSize)
148 port map(sclk_Inv,Sel,MuxIN,MuxOUT);
149
150
151 DCFP0 : entity work.DC_FRAME_PLACER
152 generic map(WordSize,WordCnt,MinFCount)
153 port map(
154 clk => Sclk,
155 Wcount => WordCount,
156 MinFCnt => MinFCnt,
157 Flag => FramePlacerFlags(0),
158 AMR1X => AMR1X,
159 AMR1Y => AMR1Y,
160 AMR1Z => AMR1Z,
161 AMR2X => AMR2X,
162 AMR2Y => AMR2Y,
163 AMR2Z => AMR2Z,
164 AMR3X => AMR3X,
165 AMR3Y => AMR3Y,
166 AMR3Z => AMR3Z,
167 AMR4X => AMR4X,
168 AMR4Y => AMR4Y,
169 AMR4Z => AMR4Z,
170 Temp1 => Temp1,
171 Temp2 => Temp2,
172 Temp3 => Temp3,
173 Temp4 => Temp4,
174 WordOut => MuxIN(7 downto 0));
175
176
177
178 LFP0 : entity work.LF_FRAME_PLACER
179 generic map(WordSize,WordCnt,MinFCount)
180 port map(
181 clk => Sclk,
182 Wcount => WordCount,
183 Flag => FramePlacerFlags(1),
184 LF1 => LF1,
185 LF2 => LF2,
186 LF3 => LF3,
187 WordOut => MuxIN(15 downto 8));
188
189
190
191 DC_SMPL_CLK0 : entity work.DC_SMPL_CLK
192 port map(MinF_Inv,DC_ADC_SmplClk);
193
194 process(reset,DC_ADC_SmplClk)
195 begin
196 if reset = '0' then
197 SET_RESET0_sig <= '0';
198 elsif DC_ADC_SmplClk'event and DC_ADC_SmplClk = '1' then
199 SET_RESET0_sig <= not SET_RESET0_sig;
200 end if;
201 end process;
202
203 SET_RESET1_sig <= SET_RESET0_sig;
204 SET_RESET0 <= SET_RESET0_sig;
205 SET_RESET1 <= SET_RESET1_sig;
206 --
113 data <= data_int;
207 114
208 115
209 116
210 send_ADC_DATA : IF SEND_CONSTANT_DATA = 0 GENERATE
211 DC_ADC0 : DUAL_ADS1278_DRIVER --With AMR down ! => 24bits DC TM -> SC high res on Spin
212 port map(
213 Clk => clk_buf,
214 reset => reset_buf,
215 SpiClk => DC_ADC_Sclk,
216 DIN => DC_ADC_IN,
217 SmplClk => DC_ADC_SmplClk,
218 OUT00 => AMR1X,
219 OUT01 => AMR1Y,
220 OUT02 => AMR1Z,
221 OUT03 => AMR2X,
222 OUT04 => AMR2Y,
223 OUT05 => AMR2Z,
224 OUT06 => Temp1,
225 OUT07 => Temp2,
226 OUT10 => AMR3X,
227 OUT11 => AMR3Y,
228 OUT12 => AMR3Z,
229 OUT13 => AMR4X,
230 OUT14 => AMR4Y,
231 OUT15 => AMR4Z,
232 OUT16 => Temp3,
233 OUT17 => Temp4,
234 FSynch => DC_ADC_FSynch
235 );
236 LF1 <= LF1cst;
237 LF2 <= LF2cst;
238 LF3 <= LF3cst;
239 END GENERATE;
117 CDS0 : entity work.CrossDomainSyncGen
118 Port map(
119 reset => reset,
120 ClockS => sclk,
121 ClockF => clk,
122 SyncSignal => CrossDomainSync
123 );
240 124
241 send_CST_DATA : IF (SEND_CONSTANT_DATA = 1) and (SEND_MINF_VALUE = 0) GENERATE
242 AMR1X <= AMR1Xcst;
243 AMR1Y <= AMR1Ycst;
244 AMR1Z <= AMR1Zcst;
245 AMR2X <= AMR2Xcst;
246 AMR2Y <= AMR2Ycst;
247 AMR2Z <= AMR2Zcst;
248 Temp1 <= Temp1cst;
249 Temp2 <= Temp2cst;
250 AMR3X <= AMR3Xcst;
251 AMR3Y <= AMR3Ycst;
252 AMR3Z <= AMR3Zcst;
253 AMR4X <= AMR4Xcst;
254 AMR4Y <= AMR4Ycst;
255 AMR4Z <= AMR4Zcst;
256 Temp3 <= Temp3cst;
257 Temp4 <= Temp4cst;
258
259 LF1 <= LF1cst;
260 LF2 <= LF2cst;
261 LF3 <= LF3cst;
262 END GENERATE;
263
264
125 TM : entity work.TM_MODULE
126 generic map(
127 WordSize => WordSize,
128 WordCnt => WordCnt,
129 MinFCount => MinFCount
130 )
131 port map(
132
133 reset =>reset,
134 clk =>clk,
135 MinF =>MinF,
136 MajF =>MajF,
137 sclk =>sclk,
138 gate =>gate,
139 data =>data_int,
140 WordClk =>WordClk,
265 141
266 142
267 send_minF_valuelbl : IF (SEND_CONSTANT_DATA = 1) and (SEND_MINF_VALUE = 1) GENERATE
268 AMR1X <= X"000" & "000" & std_logic_vector(TO_UNSIGNED(MinFCnt,9));
269 AMR1Y <= X"000" & "000" & std_logic_vector(TO_UNSIGNED(MinFCnt,9));
270 AMR1Z <= X"000" & "000" & std_logic_vector(TO_UNSIGNED(MinFCnt,9));
271 AMR2X <= X"000" & "000" & std_logic_vector(TO_UNSIGNED(MinFCnt,9));
272 AMR2Y <= X"000" & "000" & std_logic_vector(TO_UNSIGNED(MinFCnt,9));
273 AMR2Z <= X"000" & "000" & std_logic_vector(TO_UNSIGNED(MinFCnt,9));
274 Temp1 <= X"000" & "000" & std_logic_vector(TO_UNSIGNED(MinFCnt,9));
275 Temp2 <= X"000" & "000" & std_logic_vector(TO_UNSIGNED(MinFCnt,9));
276 AMR3X <= X"000" & "000" & std_logic_vector(TO_UNSIGNED(MinFCnt,9));
277 AMR3Y <= X"000" & "000" & std_logic_vector(TO_UNSIGNED(MinFCnt,9));
278 AMR3Z <= X"000" & "000" & std_logic_vector(TO_UNSIGNED(MinFCnt,9));
279 AMR4X <= X"000" & "000" & std_logic_vector(TO_UNSIGNED(MinFCnt,9));
280 AMR4Y <= X"000" & "000" & std_logic_vector(TO_UNSIGNED(MinFCnt,9));
281 AMR4Z <= X"000" & "000" & std_logic_vector(TO_UNSIGNED(MinFCnt,9));
282 Temp3 <= X"000" & "000" & std_logic_vector(TO_UNSIGNED(MinFCnt,9));
283 Temp4 <= X"000" & "000" & std_logic_vector(TO_UNSIGNED(MinFCnt,9));
284
285 LF1 <= LF1cst;
286 LF2 <= LF2cst;
287 LF3 <= LF3cst;
288 END GENERATE;
143 LF1 => LF1,
144 LF2 => LF2,
145 LF3 => LF3,
146
147 AMR1X => AMR1X,
148 AMR1Y => AMR1Y,
149 AMR1Z => AMR1Z,
150
151 AMR2X => AMR2X,
152 AMR2Y => AMR2Y,
153 AMR2Z => AMR2Z,
154
155 AMR3X => AMR3X,
156 AMR3Y => AMR3Y,
157 AMR3Z => AMR3Z,
158
159 AMR4X => AMR4X,
160 AMR4Y => AMR4Y,
161 AMR4Z => AMR4Z,
162
163 Temp1 => Temp1,
164 Temp2 => Temp2,
165 Temp3 => Temp3,
166 Temp4 => Temp4
167 );
168
169 DC_ADC0:entity work.DC_ACQ_TOP
170 generic map (
171 WordSize => WordSize,
172 WordCnt => WordCnt,
173 MinFCount => MinFCount,
174 EnableSR => 0,
175 FakeADC => 1
176 )
177 port map(
289 178
290 LF_SMPL_CLK0 : entity work.LF_SMPL_CLK
291 port map(
292 Wclck => WordClk,
293 MinF => MinF,
294 SMPL_CLK => LF_ADC_SmplClk
179 reset => reset,
180 clk => clk,
181 SyncSig => CrossDomainSync,
182 minorF => minF,
183 majorF => majF,
184 sclk => sclk,
185 WordClk => WordClk,
186
187 DC_ADC_Sclk => DC_ADC_Sclk,
188 DC_ADC_IN => DC_ADC_IN,
189 DC_ADC_ClkDiv => DC_ADC_ClkDiv,
190 DC_ADC_FSynch => DC_ADC_FSynch,
191 SET_RESET0 => SET_RESET0,
192 SET_RESET1 => SET_RESET1,
193
194 AMR1X => AMR1X,
195 AMR1Y => AMR1Y,
196 AMR1Z => AMR1Z,
197
198 AMR2X => AMR2X,
199 AMR2Y => AMR2Y,
200 AMR2Z => AMR2Z,
201
202 AMR3X => AMR3X,
203 AMR3Y => AMR3Y,
204 AMR3Z => AMR3Z,
205
206 AMR4X => AMR4X,
207 AMR4Y => AMR4Y,
208 AMR4Z => AMR4Z,
209
210 Temp1 => Temp1,
211 Temp2 => Temp2,
212 Temp3 => Temp3,
213 Temp4 => Temp4
295 214 );
296 215
297 216
217 LF: entity work.LF_ACQ_TOP
218 generic map(
219 WordSize => WordSize,
220 WordCnt => WordCnt,
221 MinFCount => MinFCount,
222 CstDATA => 0
223 )
224 port map(
298 225
299 process(clk)
300 variable SelVar : integer range 0 to 1;
301 begin
302 if clk'event and clk ='1' then
303 Decoder: FOR i IN 0 to FramePlacerCount-1 loop
304 if FramePlacerFlags(i) = '1' then
305 SelVar := i;
306 end if;
307 END loop Decoder;
308 Sel <= SelVar;
309 end if;
310 end process;
311
226 reset => reset,
227 clk => clk,
228 SyncSig => CrossDomainSync,
229 minorF => minF,
230 majorF => majF,
231 sclk => sclk,
232 WordClk => WordClk,
233 LF_SCK => LF_SCK,
234 LF_CNV => LF_CNV,
235 LF_SDO1 => LF_SDO1,
236 LF_SDO2 => LF_SDO2,
237 LF_SDO3 => LF_SDO3,
238 LF1 => LF1,
239 LF2 => LF2,
240 LF3 => LF3
241 );
312 242
313 243 end rtl;
314 244
Show file before | Show file after | Hide comments
@@ -40,7 +40,7 Port(
40 40 enable : in std_logic; --! Negative enable
41 41 smplClk : in STD_LOGIC; --! Sampling clock
42 42 DataReady : out std_logic; --! New sample available
43 smpout : out Samples_out(ChanelCount-1 downto 0); --! Samples
43 smpout : out Samples(ChanelCount-1 downto 0); --! Samples
44 44 AD_in : in AD7688_in(ChanelCount-1 downto 0); --! Input signals for ADC see lpp.lpp_ad_conv
45 45 AD_out : out AD7688_out --! Output signals for ADC see lpp.lpp_ad_conv
46 46 );
Show file before | Show file after | Hide comments
@@ -32,13 +32,13 entity AD7688_spi_if is
32 32 cnv : in STD_LOGIC;
33 33 DataReady : out std_logic;
34 34 sdi : in AD7688_in(ChanelCount-1 downto 0);
35 smpout : out Samples_out(ChanelCount-1 downto 0)
35 smpout : out Samples(ChanelCount-1 downto 0)
36 36 );
37 37 end AD7688_spi_if;
38 38
39 39 architecture ar_AD7688_spi_if of AD7688_spi_if is
40 40
41 signal shift_reg : Samples_out(ChanelCount-1 downto 0);
41 signal shift_reg : Samples(ChanelCount-1 downto 0);
42 42 signal i : integer range 0 to 16 :=0;
43 43 signal cnv_reg : std_logic := '0';
44 44
Show file before | Show file after | Hide comments
@@ -10,13 +10,17 use lpp.general_purpose.all;
10 10
11 11
12 12
13 entity DUAL_ADS1278_DRIVER is
13 entity DUAL_ADS1278_DRIVER is
14 generic
15 (
16 SCLKDIV : integer range 2 to 256 :=16
17 );
14 18 port(
15 Clk : in std_logic;
16 reset : in std_logic;
17 SpiClk : out std_logic;
18 DIN : in std_logic_vector(1 downto 0);
19 SmplClk : in std_logic;
19 Clk : in std_logic;
20 reset : in std_logic;
21 SpiClk : out std_logic;
22 DIN : in std_logic_vector(1 downto 0);
23 SmplClk : in std_logic;
20 24 OUT00 : out std_logic_vector(23 downto 0);
21 25 OUT01 : out std_logic_vector(23 downto 0);
22 26 OUT02 : out std_logic_vector(23 downto 0);
@@ -33,7 +37,7 port(
33 37 OUT15 : out std_logic_vector(23 downto 0);
34 38 OUT16 : out std_logic_vector(23 downto 0);
35 39 OUT17 : out std_logic_vector(23 downto 0);
36 FSynch : out std_logic
40 FSynch : out std_logic
37 41 );
38 42 end DUAL_ADS1278_DRIVER;
39 43
@@ -43,10 +47,9 end DUAL_ADS1278_DRIVER;
43 47
44 48
45 49 architecture ar_DUAL_ADS1278_DRIVER of DUAL_ADS1278_DRIVER is
46
47 signal Vec00,Vec01,Vec02,Vec03,Vec04,Vec05,Vec06,Vec07,Vec10,Vec11,Vec12,Vec13,Vec14,Vec15,Vec16,Vec17 : std_logic_vector(23 downto 0);
50 signal ShiftGeg0,ShiftGeg1 : std_logic_vector((8*24)-1 downto 0);
48 51 signal SmplClk_Reg : std_logic:= '0';
49 signal N : integer range 0 to 23*8 := 0;
52 signal N : integer range 0 to (24*8) := 0;
50 53 signal SPI_CLk : std_logic;
51 54 signal SmplClk_clkd : std_logic:= '0';
52 55
@@ -54,97 +57,24 begin
54 57
55 58
56 59 CLKDIV0 : Clk_Divider2
57 generic map(16)
60 generic map(SCLKDIV)
58 61 port map(Clk,SPI_CLk);
59 62
60
61 FSynch <= SmplClk_clkd;
62 SpiClk <= SPI_CLk;
63 SpiClk <= not SPI_CLk;
63 64
64 65 process(reset,SPI_CLk)
65 66 begin
66 67
67 68 if reset = '0' then
68 Vec00 <= (others => '0');
69 Vec01 <= (others => '0');
70 Vec02 <= (others => '0');
71 Vec03 <= (others => '0');
72 Vec04 <= (others => '0');
73 Vec05 <= (others => '0');
74 Vec06 <= (others => '0');
75 Vec07 <= (others => '0');
76
77 Vec10 <= (others => '0');
78 Vec11 <= (others => '0');
79 Vec12 <= (others => '0');
80 Vec13 <= (others => '0');
81 Vec14 <= (others => '0');
82 Vec15 <= (others => '0');
83 Vec16 <= (others => '0');
84 Vec17 <= (others => '0');
85 N <= 0;
69 ShiftGeg0 <= (others => '0');
70 ShiftGeg1 <= (others => '0');
71 N <= 0;
86 72 elsif SPI_CLk'event and SPI_CLk = '1' then
87 -- SmplClk_clkd <= SmplClk;
88 -- SmplClk_Reg <= SmplClk_clkd;
89 --if ((SmplClk_clkd = '1' and SmplClk_Reg = '0') or (N /= 0)) then
90 if ((SmplClk_clkd = '1' and SmplClk_Reg = '0') or (N /= 0)) then
91 --Vec0(0) <= DIN(0);
92 --Vec1(0) <= DIN(1);
93 --Vec2(0) <= DIN(2);
94 --Vec3(0) <= DIN(3);
95 --Vec0(23 downto 1) <= Vec0(22 downto 0);
96 --Vec1(23 downto 1) <= Vec1(22 downto 0);
97 --Vec2(23 downto 1) <= Vec2(22 downto 0);
98 --Vec3(23 downto 1) <= Vec3(22 downto 0);
99 Vec00(0) <= DIN(0);
100 Vec00(23 downto 1) <= Vec00(22 downto 0);
101 Vec01(0) <= Vec00(23);
102
103 Vec01(23 downto 1) <= Vec01(22 downto 0);
104 Vec02(0) <= Vec01(23);
105
106 Vec02(23 downto 1) <= Vec02(22 downto 0);
107 Vec03(0) <= Vec02(23);
108
109 Vec03(23 downto 1) <= Vec03(22 downto 0);
110 Vec04(0) <= Vec03(23);
111
112 Vec04(23 downto 1) <= Vec04(22 downto 0);
113 Vec05(0) <= Vec04(23);
114
115 Vec05(23 downto 1) <= Vec05(22 downto 0);
116 Vec06(0) <= Vec05(23);
117
118 Vec06(23 downto 1) <= Vec06(22 downto 0);
119 Vec07(0) <= Vec06(23);
120
121 Vec07(23 downto 1) <= Vec07(22 downto 0);
122
123
124 Vec10(0) <= DIN(1);
125 Vec10(23 downto 1) <= Vec10(22 downto 0);
126 Vec11(0) <= Vec10(23);
127
128 Vec11(23 downto 1) <= Vec11(22 downto 0);
129 Vec12(0) <= Vec11(23);
130
131 Vec12(23 downto 1) <= Vec12(22 downto 0);
132 Vec13(0) <= Vec12(23);
133
134 Vec13(23 downto 1) <= Vec13(22 downto 0);
135 Vec14(0) <= Vec13(23);
136
137 Vec14(23 downto 1) <= Vec14(22 downto 0);
138 Vec15(0) <= Vec14(23);
139
140 Vec15(23 downto 1) <= Vec15(22 downto 0);
141 Vec16(0) <= Vec15(23);
142
143 Vec16(23 downto 1) <= Vec16(22 downto 0);
144 Vec17(0) <= Vec16(23);
145
146 Vec17(23 downto 1) <= Vec17(22 downto 0);
147 if N = (23*8) then
73 FSynch <= SmplClk;
74 if ((SmplClk_clkd = '1' and SmplClk_Reg = '0') or (N /= 0)) then
75 ShiftGeg0((8*24)-1 downto 0) <= ShiftGeg0((8*24)-2 downto 0) & DIN(0);
76 ShiftGeg1((8*24)-1 downto 0) <= ShiftGeg1((8*24)-2 downto 0) & DIN(1);
77 if N = ((24*8)-1) then
148 78 N <= 0;
149 79 else
150 80 N <= N+1;
@@ -163,27 +93,45 begin
163 93 end process;
164 94
165 95
166 process(SPI_CLk)
167 begin
168 if SPI_CLk'event and SPI_CLk ='1' then
96 process(clk,reset)
97 begin
98 if reset = '0' then
99 OUT00 <= (others => '0');
100 OUT01 <= (others => '0');
101 OUT02 <= (others => '0');
102 OUT03 <= (others => '0');
103 OUT04 <= (others => '0');
104 OUT05 <= (others => '0');
105 OUT06 <= (others => '0');
106 OUT07 <= (others => '0');
107
108 OUT10 <= (others => '0');
109 OUT11 <= (others => '0');
110 OUT12 <= (others => '0');
111 OUT13 <= (others => '0');
112 OUT14 <= (others => '0');
113 OUT15 <= (others => '0');
114 OUT16 <= (others => '0');
115 OUT17 <= (others => '0');
116 elsif clk'event and clk ='1' then
169 117 if N = 0 then
170 OUT00 <= Vec00;
171 OUT01 <= Vec01;
172 OUT02 <= Vec02;
173 OUT03 <= Vec03;
174 OUT04 <= Vec04;
175 OUT05 <= Vec05;
176 OUT06 <= Vec06;
177 OUT07 <= Vec07;
118 OUT00 <= ShiftGeg0((24*1)-1 downto (24*(1-1)));
119 OUT01 <= ShiftGeg0((24*2)-1 downto (24*(2-1)));
120 OUT02 <= ShiftGeg0((24*3)-1 downto (24*(3-1)));
121 OUT03 <= ShiftGeg0((24*4)-1 downto (24*(4-1)));
122 OUT04 <= ShiftGeg0((24*5)-1 downto (24*(5-1)));
123 OUT05 <= ShiftGeg0((24*6)-1 downto (24*(6-1)));
124 OUT06 <= ShiftGeg0((24*7)-1 downto (24*(7-1)));
125 OUT07 <= ShiftGeg0((24*8)-1 downto (24*(8-1)));
178 126
179 OUT10 <= Vec10;
180 OUT11 <= Vec11;
181 OUT12 <= Vec12;
182 OUT13 <= Vec13;
183 OUT14 <= Vec14;
184 OUT15 <= Vec15;
185 OUT16 <= Vec16;
186 OUT17 <= Vec17;
127 OUT10 <= ShiftGeg1((24*1)-1 downto (24*(1-1)));
128 OUT11 <= ShiftGeg1((24*2)-1 downto (24*(2-1)));
129 OUT12 <= ShiftGeg1((24*3)-1 downto (24*(3-1)));
130 OUT13 <= ShiftGeg1((24*4)-1 downto (24*(4-1)));
131 OUT14 <= ShiftGeg1((24*5)-1 downto (24*(5-1)));
132 OUT15 <= ShiftGeg1((24*6)-1 downto (24*(6-1)));
133 OUT16 <= ShiftGeg1((24*7)-1 downto (24*(7-1)));
134 OUT17 <= ShiftGeg1((24*8)-1 downto (24*(8-1)));
187 135 end if;
188 136 end if;
189 137 end process;
Show file before | Show file after | Hide comments
@@ -35,18 +35,18 PACKAGE lpp_ad_conv IS
35 35 --CONSTANT ADS7886 : INTEGER := 1;
36 36
37 37
38 --TYPE AD7688_out IS
39 --RECORD
40 -- CNV : STD_LOGIC;
41 -- SCK : STD_LOGIC;
42 --END RECORD;
38 TYPE AD7688_out IS
39 RECORD
40 CNV : STD_LOGIC;
41 SCK : STD_LOGIC;
42 END RECORD;
43 43
44 --TYPE AD7688_in_element IS
45 --RECORD
46 -- SDI : STD_LOGIC;
47 --END RECORD;
44 TYPE AD7688_in_element IS
45 RECORD
46 SDI : STD_LOGIC;
47 END RECORD;
48 48
49 --TYPE AD7688_in IS ARRAY(NATURAL RANGE <>) OF AD7688_in_element;
49 TYPE AD7688_in IS ARRAY(NATURAL RANGE <>) OF AD7688_in_element;
50 50
51 51 TYPE Samples IS ARRAY(NATURAL RANGE <>) OF STD_LOGIC_VECTOR(15 DOWNTO 0);
52 52
@@ -68,30 +68,30 PACKAGE lpp_ad_conv IS
68 68 sample_val : OUT STD_LOGIC);
69 69 END COMPONENT;
70 70
71 --COMPONENT AD7688_drvr IS
72 -- GENERIC(ChanelCount : INTEGER;
73 -- clkkHz : INTEGER);
74 -- PORT (clk : IN STD_LOGIC;
75 -- rstn : IN STD_LOGIC;
76 -- enable : IN STD_LOGIC;
77 -- smplClk : IN STD_LOGIC;
78 -- DataReady : OUT STD_LOGIC;
79 -- smpout : OUT Samples_out(ChanelCount-1 DOWNTO 0);
80 -- AD_in : IN AD7688_in(ChanelCount-1 DOWNTO 0);
81 -- AD_out : OUT AD7688_out);
82 --END COMPONENT;
71 COMPONENT AD7688_drvr IS
72 GENERIC(ChanelCount : INTEGER;
73 clkkHz : INTEGER);
74 PORT (clk : IN STD_LOGIC;
75 rstn : IN STD_LOGIC;
76 enable : IN STD_LOGIC;
77 smplClk : IN STD_LOGIC;
78 DataReady : OUT STD_LOGIC;
79 smpout : OUT Samples(ChanelCount-1 DOWNTO 0);
80 AD_in : IN AD7688_in(ChanelCount-1 DOWNTO 0);
81 AD_out : OUT AD7688_out);
82 END COMPONENT;
83 83
84 84
85 --COMPONENT AD7688_spi_if IS
86 -- GENERIC(ChanelCount : INTEGER);
87 -- PORT(clk : IN STD_LOGIC;
88 -- reset : IN STD_LOGIC;
89 -- cnv : IN STD_LOGIC;
90 -- DataReady : OUT STD_LOGIC;
91 -- sdi : IN AD7688_in(ChanelCount-1 DOWNTO 0);
92 -- smpout : OUT Samples_out(ChanelCount-1 DOWNTO 0)
93 -- );
94 --END COMPONENT;
85 COMPONENT AD7688_spi_if IS
86 GENERIC(ChanelCount : INTEGER);
87 PORT(clk : IN STD_LOGIC;
88 reset : IN STD_LOGIC;
89 cnv : IN STD_LOGIC;
90 DataReady : OUT STD_LOGIC;
91 sdi : IN AD7688_in(ChanelCount-1 DOWNTO 0);
92 smpout : OUT Samples(ChanelCount-1 DOWNTO 0)
93 );
94 END COMPONENT;
95 95
96 96
97 97 --COMPONENT lpp_apb_ad_conv
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