# HG changeset patch # User jeandet # Date 2013-08-22 23:55:11 # Node ID 006079fa8bede8da423ef3b7a20a409b08b977ba # Parent 0b190be76d60148f150af6bbf9d100cc17211193 Added cross domain synchronisation blocks. diff --git a/boards/ICI4-main-BD/ICI4-Main-BD.ucf b/boards/ICI4-main-BD/ICI4-Main-BD.ucf --- a/boards/ICI4-main-BD/ICI4-Main-BD.ucf +++ b/boards/ICI4-main-BD/ICI4-Main-BD.ucf @@ -1,11 +1,31 @@ -NET "CLK" LOC = "B10"; +NET "CLK" LOC = "B10" | IOSTANDARD = LVCMOS33; + +NET "RESET" CLOCK_DEDICATED_ROUTE = FALSE; NET "RESET" LOC = "A5" | IOSTANDARD = LVTTL; + +NET "SCLK" CLOCK_DEDICATED_ROUTE = FALSE; NET "SCLK" LOC = "V22" | IOSTANDARD = LVTTL; + NET "GATE" LOC = "T22" | IOSTANDARD = LVTTL; + +NET "MINF" CLOCK_DEDICATED_ROUTE = FALSE; NET "MINF" LOC = "T21" | IOSTANDARD = LVTTL; + NET "MAJF" LOC = "U22" | IOSTANDARD = LVTTL; -NET "DATA" LOC = "V21"; -NET "DC_ADC_SCLK" LOC = "AB17"; +NET "DATA" LOC = "V21" | IOSTANDARD = LVCMOS33; +NET "DC_ADC_SCLK" LOC = "AB17" | IOSTANDARD = LVCMOS33; NET "DC_ADC_IN(0)" LOC = "AB19" | IOSTANDARD = LVTTL; NET "DC_ADC_IN(1)" LOC = "AA18" | IOSTANDARD = LVTTL; -NET "DC_ADC_FSynch" LOC = "AB18"; +NET "DC_ADC_FSynch" LOC = "AB18" | IOSTANDARD = LVCMOS33; +NET "LED" LOC = "A3" | IOSTANDARD = LVCMOS33; +NET "SET_RESET0" LOC = "AB21" | IOSTANDARD = LVCMOS33; +NET "SET_RESET1" LOC = "AB20" | IOSTANDARD = LVCMOS33; + + +NET "LF_SCK" LOC = "W20"| IOSTANDARD = LVCMOS33; +NET "LF_CNV" LOC = "Y18"| IOSTANDARD = LVCMOS33; +NET "LF_SDO1" LOC = "W17" | IOSTANDARD = LVTTL; +NET "LF_SDO2" LOC = "AA21" | IOSTANDARD = LVTTL; +NET "LF_SDO3" LOC = "AA16" | IOSTANDARD = LVTTL; + + diff --git a/designs/ICI4-Integ1/ICI4HDL/CrossDomainSyncGen.vhd b/designs/ICI4-Integ1/ICI4HDL/CrossDomainSyncGen.vhd new file mode 100644 --- /dev/null +++ b/designs/ICI4-Integ1/ICI4HDL/CrossDomainSyncGen.vhd @@ -0,0 +1,68 @@ +------------------------------------------------------------------------------ +-- This file is a part of the LPP VHDL IP LIBRARY +-- Copyright (C) 2009 - 2013, Laboratory of Plasmas Physic - CNRS +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 3 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +------------------------------------------------------------------------------ +-- Author : Alexis Jeandet +-- Mail : alexis.jeandet@member.fsf.org +------------------------------------------------------------------------------ +-- +-- This module implements the SyncSignal generator explained in: +-- Data Transfer between Asynchronous Clock Domains without Pain +-- from Markus Schutti, Markus Pfaff, Richard Hagelauer +-- http://www-micrel.deis.unibo.it/~benini/files/SNUG/paper9_final.pdf +-- see page 4 +-- +-- + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +entity CrossDomainSyncGen is +Port ( + reset : in STD_LOGIC; + ClockS : in STD_LOGIC; + ClockF : in STD_LOGIC; + SyncSignal : out STD_LOGIC +); +end CrossDomainSyncGen; + +architecture AR_CrossDomainSyncGen of CrossDomainSyncGen is + +signal FFSYNC : std_logic_vector(2 downto 0); + +begin + +SyncSignal <= FFSYNC(2); + +process(reset,ClockF) +begin +if reset = '0' then + FFSYNC <= (others => '0'); +elsif ClockF'event and ClockF = '1' then + FFSYNC(0) <= ClockS; + FFSYNC(1) <= FFSYNC(0); + FFSYNC(2) <= FFSYNC(1); +end if; +end process; + +end AR_CrossDomainSyncGen; + + + + + + diff --git a/designs/ICI4-Integ1/ICI4HDL/DC_ACQ_TOP.vhd b/designs/ICI4-Integ1/ICI4HDL/DC_ACQ_TOP.vhd new file mode 100644 --- /dev/null +++ b/designs/ICI4-Integ1/ICI4HDL/DC_ACQ_TOP.vhd @@ -0,0 +1,288 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.NUMERIC_STD.ALL; +library lpp; +use lpp.lpp_ad_conv.all; +use lpp.lpp_amba.all; +use lpp.apb_devices_list.all; +use lpp.general_purpose.all; +use lpp.Rocket_PCM_Encoder.all; + + +entity DC_ACQ_TOP is +generic( + WordSize : integer := 8; + WordCnt : integer := 144; + MinFCount : integer := 64; + EnableSR : integer := 1; + FakeADC : integer := 0 +); +port( + + reset : in std_logic; + clk : in std_logic; + SyncSig : in STD_LOGIC; + minorF : in std_logic; + majorF : in std_logic; + sclk : in std_logic; + WordClk : in std_logic; + + DC_ADC_Sclk : out std_logic; + DC_ADC_IN : in std_logic_vector(1 downto 0); + DC_ADC_ClkDiv : out std_logic; + DC_ADC_FSynch : out std_logic; + SET_RESET0 : out std_logic; + SET_RESET1 : out std_logic; + + AMR1X : out std_logic_vector(23 downto 0); + AMR1Y : out std_logic_vector(23 downto 0); + AMR1Z : out std_logic_vector(23 downto 0); + + AMR2X : out std_logic_vector(23 downto 0); + AMR2Y : out std_logic_vector(23 downto 0); + AMR2Z : out std_logic_vector(23 downto 0); + + AMR3X : out std_logic_vector(23 downto 0); + AMR3Y : out std_logic_vector(23 downto 0); + AMR3Z : out std_logic_vector(23 downto 0); + + AMR4X : out std_logic_vector(23 downto 0); + AMR4Y : out std_logic_vector(23 downto 0); + AMR4Z : out std_logic_vector(23 downto 0); + + Temp1 : out std_logic_vector(23 downto 0); + Temp2 : out std_logic_vector(23 downto 0); + Temp3 : out std_logic_vector(23 downto 0); + Temp4 : out std_logic_vector(23 downto 0) +); +end DC_ACQ_TOP; + +architecture Behavioral of DC_ACQ_TOP is + +signal DC_ADC_SmplClk : std_logic; +signal LF_ADC_SmplClk : std_logic; +signal SET_RESET0_sig : std_logic; +signal SET_RESET1_sig : std_logic; +signal SET_RESET_counter : integer range 0 to 31:=0; + +signal AMR1X_Sync : std_logic_vector(23 downto 0); +signal AMR1Y_Sync : std_logic_vector(23 downto 0); +signal AMR1Z_Sync : std_logic_vector(23 downto 0); + +signal AMR2X_Sync : std_logic_vector(23 downto 0); +signal AMR2Y_Sync : std_logic_vector(23 downto 0); +signal AMR2Z_Sync : std_logic_vector(23 downto 0); + +signal AMR3X_Sync : std_logic_vector(23 downto 0); +signal AMR3Y_Sync : std_logic_vector(23 downto 0); +signal AMR3Z_Sync : std_logic_vector(23 downto 0); + +signal AMR4X_Sync : std_logic_vector(23 downto 0); +signal AMR4Y_Sync : std_logic_vector(23 downto 0); +signal AMR4Z_Sync : std_logic_vector(23 downto 0); + +signal Temp1_Sync : std_logic_vector(23 downto 0); +signal Temp2_Sync : std_logic_vector(23 downto 0); +signal Temp3_Sync : std_logic_vector(23 downto 0); +signal Temp4_Sync : std_logic_vector(23 downto 0); + +begin + +------------------------------------------------------------------ +-- +-- DC sampling clock generation +-- +------------------------------------------------------------------ + + +DC_SMPL_CLK0 : entity work.LF_SMPL_CLK +--generic map(36) +generic map(288) +port map( + reset => reset, + wclk => WordClk, + SMPL_CLK => DC_ADC_SmplClk +); +------------------------------------------------------------------ + + + + +------------------------------------------------------------------ +-- +-- DC ADC +-- +------------------------------------------------------------------ +ADC : IF FakeADC /=1 GENERATE + +DC_ADC0 : DUAL_ADS1278_DRIVER +port map( + Clk => clk, + reset => reset, + SpiClk => DC_ADC_Sclk, + DIN => DC_ADC_IN, + SmplClk => DC_ADC_SmplClk, + OUT00 => AMR1X_Sync, + OUT01 => AMR1Y_Sync, + OUT02 => AMR1Z_Sync, + OUT03 => AMR2X_Sync, + OUT04 => AMR2Y_Sync, + OUT05 => AMR2Z_Sync, + OUT06 => Temp1_Sync, + OUT07 => Temp2_Sync, + OUT10 => AMR3X_Sync, + OUT11 => AMR3Y_Sync, + OUT12 => AMR3Z_Sync, + OUT13 => AMR4X_Sync, + OUT14 => AMR4Y_Sync, + OUT15 => AMR4Z_Sync, + OUT16 => Temp3_Sync, + OUT17 => Temp4_Sync, + FSynch => DC_ADC_FSynch +); +END GENERATE; + +NOADC: IF FakeADC=1 GENERATE + +DC_ADC0 : entity work.FAKE_DUAL_ADS1278_DRIVER +port map( + Clk => clk, + reset => reset, + SpiClk => DC_ADC_Sclk, + DIN => DC_ADC_IN, + SmplClk => DC_ADC_SmplClk, + OUT00 => AMR1X_Sync, + OUT01 => AMR1Y_Sync, + OUT02 => AMR1Z_Sync, + OUT03 => AMR2X_Sync, + OUT04 => AMR2Y_Sync, + OUT05 => AMR2Z_Sync, + OUT06 => Temp1_Sync, + OUT07 => Temp2_Sync, + OUT10 => AMR3X_Sync, + OUT11 => AMR3Y_Sync, + OUT12 => AMR3Z_Sync, + OUT13 => AMR4X_Sync, + OUT14 => AMR4Y_Sync, + OUT15 => AMR4Z_Sync, + OUT16 => Temp3_Sync, + OUT17 => Temp4_Sync, + FSynch => DC_ADC_FSynch +); +END GENERATE; +------------------------------------------------------------------ + + + + +------------------------------------------------------------------ +-- +-- SET/RESET GEN +-- +------------------------------------------------------------------ + +SR: IF EnableSR /=0 GENERATE +process(reset,DC_ADC_SmplClk) +begin + if reset = '0' then + SET_RESET0_sig <= '0'; + elsif DC_ADC_SmplClk'event and DC_ADC_SmplClk = '0' then + if(SET_RESET_counter = 31) then + SET_RESET0_sig <= not SET_RESET0_sig; + SET_RESET_counter <= 0; + else + SET_RESET_counter <= SET_RESET_counter +1; + end if; + end if; +end process; + +END GENERATE; +NOSR: IF EnableSR=0 GENERATE + SET_RESET0_sig <= '0'; +END GENERATE; + +SET_RESET1_sig <= SET_RESET0_sig; +SET_RESET0 <= SET_RESET0_sig; +SET_RESET1 <= SET_RESET1_sig; +------------------------------------------------------------------ +------------------------------------------------------------------ + + +------------------------------------------------------------------ +-- +-- Cross domain clock synchronisation +-- +------------------------------------------------------------------ + + + +AMR1Xsync: entity work.Fast2SlowSync +generic map(N => 24) +port map( AMR1X_Sync,clk,sclk,SyncSig,AMR1X); +AMR1Ysync: entity work.Fast2SlowSync +generic map(N => 24) +port map( AMR1Y_Sync,clk,sclk,SyncSig,AMR1Y); +AMR1Zsync: entity work.Fast2SlowSync +generic map(N => 24) +port map( AMR1Z_Sync,clk,sclk,SyncSig,AMR1Z); + +AMR2Xsync: entity work.Fast2SlowSync +generic map(N => 24) +port map( AMR2X_Sync,clk,sclk,SyncSig,AMR2X); +AMR2Ysync: entity work.Fast2SlowSync +generic map(N => 24) +port map( AMR2Y_Sync,clk,sclk,SyncSig,AMR2Y); +AMR2Zsync: entity work.Fast2SlowSync +generic map(N => 24) +port map( AMR2Z_Sync,clk,sclk,SyncSig,AMR2Z); + +AMR3Xsync: entity work.Fast2SlowSync +generic map(N => 24) +port map( AMR3X_Sync,clk,sclk,SyncSig,AMR3X); +AMR3Ysync: entity work.Fast2SlowSync +generic map(N => 24) +port map( AMR3Y_Sync,clk,sclk,SyncSig,AMR3Y); +AMR3Zsync: entity work.Fast2SlowSync +generic map(N => 24) +port map( AMR3Z_Sync,clk,sclk,SyncSig,AMR3Z); + + +AMR4Xsync: entity work.Fast2SlowSync +generic map(N => 24) +port map( AMR4X_Sync,clk,sclk,SyncSig,AMR4X); +AMR4Ysync: entity work.Fast2SlowSync +generic map(N => 24) +port map( AMR4Y_Sync,clk,sclk,SyncSig,AMR4Y); +AMR4Zsync: entity work.Fast2SlowSync +generic map(N => 24) +port map( AMR4Z_Sync,clk,sclk,SyncSig,AMR4Z); + + +TEMP1sync: entity work.Fast2SlowSync +generic map(N => 24) +port map( TEMP1_Sync,clk,sclk,SyncSig,TEMP1); +TEMP2sync: entity work.Fast2SlowSync +generic map(N => 24) +port map( TEMP2_Sync,clk,sclk,SyncSig,TEMP2); +TEMP3sync: entity work.Fast2SlowSync +generic map(N => 24) +port map( TEMP3_Sync,clk,sclk,SyncSig,TEMP3); +TEMP4sync: entity work.Fast2SlowSync +generic map(N => 24) +port map( TEMP4_Sync,clk,sclk,SyncSig,TEMP4); + +------------------------------------------------------------------ + + +end Behavioral; + + + + + + + + + + + diff --git a/designs/ICI4-Integ1/ICI4HDL/FAKE_ADC.vhd b/designs/ICI4-Integ1/ICI4HDL/FAKE_ADC.vhd new file mode 100644 --- /dev/null +++ b/designs/ICI4-Integ1/ICI4HDL/FAKE_ADC.vhd @@ -0,0 +1,243 @@ +-- ADS1274_DRIVER.vhd +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; +library lpp; +use lpp.lpp_ad_conv.all; +use lpp.general_purpose.all; + + + + + +entity FAKE_DUAL_ADS1278_DRIVER is +generic +( + SCLKDIV : integer range 2 to 256 :=16 +); +port( + Clk : in std_logic; + reset : in std_logic; + SpiClk : out std_logic; + DIN : in std_logic_vector(1 downto 0); + SmplClk : in std_logic; + OUT00 : out std_logic_vector(23 downto 0); + OUT01 : out std_logic_vector(23 downto 0); + OUT02 : out std_logic_vector(23 downto 0); + OUT03 : out std_logic_vector(23 downto 0); + OUT04 : out std_logic_vector(23 downto 0); + OUT05 : out std_logic_vector(23 downto 0); + OUT06 : out std_logic_vector(23 downto 0); + OUT07 : out std_logic_vector(23 downto 0); + OUT10 : out std_logic_vector(23 downto 0); + OUT11 : out std_logic_vector(23 downto 0); + OUT12 : out std_logic_vector(23 downto 0); + OUT13 : out std_logic_vector(23 downto 0); + OUT14 : out std_logic_vector(23 downto 0); + OUT15 : out std_logic_vector(23 downto 0); + OUT16 : out std_logic_vector(23 downto 0); + OUT17 : out std_logic_vector(23 downto 0); + FSynch : out std_logic +); +end FAKE_DUAL_ADS1278_DRIVER; + + + + + + +architecture ar_FAKE_DUAL_ADS1278_DRIVER of FAKE_DUAL_ADS1278_DRIVER is +signal ShiftGeg0,ShiftGeg1 : std_logic_vector((8*24)-1 downto 0); +signal ShiftGeg20,ShiftGeg21 : std_logic_vector((8*24)-1 downto 0); +signal SmplClk_Reg : std_logic:= '0'; +signal N : integer range 0 to (24*8) := 0; +signal SPI_CLk : std_logic; +signal SmplClk_clkd : std_logic:= '0'; +signal OUT00_r : std_logic_vector(23 downto 0) := (others => '0'); +signal OUT01_r : std_logic_vector(23 downto 0) := (others => '0'); +signal OUT02_r : std_logic_vector(23 downto 0) := (others => '0'); +signal OUT03_r : std_logic_vector(23 downto 0) := (others => '0'); +signal OUT04_r : std_logic_vector(23 downto 0) := (others => '0'); +signal OUT05_r : std_logic_vector(23 downto 0) := (others => '0'); +signal OUT06_r : std_logic_vector(23 downto 0) := (others => '0'); +signal OUT07_r : std_logic_vector(23 downto 0) := (others => '0'); +signal OUT10_r : std_logic_vector(23 downto 0) := (others => '0'); +signal OUT11_r : std_logic_vector(23 downto 0) := (others => '0'); +signal OUT12_r : std_logic_vector(23 downto 0) := (others => '0'); +signal OUT13_r : std_logic_vector(23 downto 0) := (others => '0'); +signal OUT14_r : std_logic_vector(23 downto 0) := (others => '0'); +signal OUT15_r : std_logic_vector(23 downto 0) := (others => '0'); +signal OUT16_r : std_logic_vector(23 downto 0) := (others => '0'); +signal OUT17_r : std_logic_vector(23 downto 0) := (others => '0'); + +begin + + +CLKDIV0 : Clk_Divider2 +generic map(SCLKDIV) +port map(Clk,SPI_CLk); + + +FSynch <= SmplClk; +SpiClk <= SPI_CLk; + +process(reset,SPI_CLk) +begin + + if reset = '0' then + ShiftGeg0 <= (others => '0'); + ShiftGeg1 <= (others => '0'); + N <= 0; + OUT00_r <= (others => '0'); + OUT01_r <= (others => '0'); + OUT02_r <= (others => '0'); + OUT03_r <= (others => '0'); + OUT04_r <= (others => '0'); + OUT05_r <= (others => '0'); + OUT06_r <= (others => '0'); + OUT07_r <= (others => '0'); + OUT10_r <= (others => '0'); + OUT11_r <= (others => '0'); + OUT12_r <= (others => '0'); + OUT13_r <= (others => '0'); + OUT14_r <= (others => '0'); + OUT15_r <= (others => '0'); + OUT16_r <= (others => '0'); + OUT17_r <= (others => '0'); + ShiftGeg20 <= (others => '0'); + ShiftGeg21 <= (others => '0'); + + elsif SPI_CLk'event and SPI_CLk = '1' then + if ((SmplClk_clkd = '1' and SmplClk_Reg = '0') or (N /= 0)) then + ShiftGeg20((8*24)-1 downto 0) <= ShiftGeg20((8*24)-2 downto 0) & '0'; + ShiftGeg21((8*24)-1 downto 0) <= ShiftGeg21((8*24)-2 downto 0) & '0'; + ShiftGeg0((8*24)-1 downto 0) <= ShiftGeg0((8*24)-2 downto 0) & ShiftGeg20((8*24)-1); + ShiftGeg1((8*24)-1 downto 0) <= ShiftGeg1((8*24)-2 downto 0) & ShiftGeg21((8*24)-1); + if N = ((24*8)-1) then + N <= 0; + OUT00_r <= std_logic_vector(UNSIGNED(OUT00_r) + 1); + OUT01_r <= std_logic_vector(UNSIGNED(OUT01_r) + 2); + OUT02_r <= std_logic_vector(UNSIGNED(OUT02_r) + 3); + OUT03_r <= std_logic_vector(UNSIGNED(OUT03_r) + 4); + OUT04_r <= std_logic_vector(UNSIGNED(OUT04_r) + 5); + OUT05_r <= std_logic_vector(UNSIGNED(OUT05_r) + 6); + OUT06_r <= std_logic_vector(UNSIGNED(OUT06_r) + 7); + OUT07_r <= std_logic_vector(UNSIGNED(OUT07_r) + 8); + OUT10_r <= std_logic_vector(UNSIGNED(OUT10_r) + 9); + OUT11_r <= std_logic_vector(UNSIGNED(OUT11_r) + 10); + OUT12_r <= std_logic_vector(UNSIGNED(OUT12_r) + 11); + OUT13_r <= std_logic_vector(UNSIGNED(OUT13_r) + 12); + OUT14_r <= std_logic_vector(UNSIGNED(OUT14_r) + 13); + OUT15_r <= std_logic_vector(UNSIGNED(OUT15_r) + 14); + OUT16_r <= std_logic_vector(UNSIGNED(OUT16_r) + 15); + OUT17_r <= std_logic_vector(UNSIGNED(OUT17_r) + 16); + + ShiftGeg20((24*1)-1 downto (24*(1-1))) <= OUT00_r; + ShiftGeg20((24*2)-1 downto (24*(2-1))) <= OUT01_r; + ShiftGeg20((24*3)-1 downto (24*(3-1))) <= OUT02_r; + ShiftGeg20((24*4)-1 downto (24*(4-1))) <= OUT03_r; + ShiftGeg20((24*5)-1 downto (24*(5-1))) <= OUT04_r; + ShiftGeg20((24*6)-1 downto (24*(6-1))) <= OUT05_r; + ShiftGeg20((24*7)-1 downto (24*(7-1))) <= OUT06_r; + ShiftGeg20((24*8)-1 downto (24*(8-1))) <= OUT07_r; + + ShiftGeg21((24*1)-1 downto (24*(1-1))) <= OUT10_r; + ShiftGeg21((24*2)-1 downto (24*(2-1))) <= OUT11_r; + ShiftGeg21((24*3)-1 downto (24*(3-1))) <= OUT12_r; + ShiftGeg21((24*4)-1 downto (24*(4-1))) <= OUT13_r; + ShiftGeg21((24*5)-1 downto (24*(5-1))) <= OUT14_r; + ShiftGeg21((24*6)-1 downto (24*(6-1))) <= OUT15_r; + ShiftGeg21((24*7)-1 downto (24*(7-1))) <= OUT16_r; + ShiftGeg21((24*8)-1 downto (24*(8-1))) <= OUT17_r; + else + N <= N+1; + end if; + end if; + end if; +end process; + + +process(SPI_CLk) +begin + if SPI_CLk'event and SPI_CLk ='0' then + SmplClk_clkd <= SmplClk; + SmplClk_Reg <= SmplClk_clkd; + end if; +end process; + + +process(clk,reset) +begin + if reset = '0' then + OUT00 <= (others => '0'); + OUT01 <= (others => '0'); + OUT02 <= (others => '0'); + OUT03 <= (others => '0'); + OUT04 <= (others => '0'); + OUT05 <= (others => '0'); + OUT06 <= (others => '0'); + OUT07 <= (others => '0'); + + OUT10 <= (others => '0'); + OUT11 <= (others => '0'); + OUT12 <= (others => '0'); + OUT13 <= (others => '0'); + OUT14 <= (others => '0'); + OUT15 <= (others => '0'); + OUT16 <= (others => '0'); + OUT17 <= (others => '0'); + elsif clk'event and clk ='1' then + if N = 0 then + OUT00 <= ShiftGeg0((24*1)-1 downto (24*(1-1))); + OUT01 <= ShiftGeg0((24*2)-1 downto (24*(2-1))); + OUT02 <= ShiftGeg0((24*3)-1 downto (24*(3-1))); + OUT03 <= ShiftGeg0((24*4)-1 downto (24*(4-1))); + OUT04 <= ShiftGeg0((24*5)-1 downto (24*(5-1))); + OUT05 <= ShiftGeg0((24*6)-1 downto (24*(6-1))); + OUT06 <= ShiftGeg0((24*7)-1 downto (24*(7-1))); + OUT07 <= ShiftGeg0((24*8)-1 downto (24*(8-1))); + + OUT10 <= ShiftGeg1((24*1)-1 downto (24*(1-1))); + OUT11 <= ShiftGeg1((24*2)-1 downto (24*(2-1))); + OUT12 <= ShiftGeg1((24*3)-1 downto (24*(3-1))); + OUT13 <= ShiftGeg1((24*4)-1 downto (24*(4-1))); + OUT14 <= ShiftGeg1((24*5)-1 downto (24*(5-1))); + OUT15 <= ShiftGeg1((24*6)-1 downto (24*(6-1))); + OUT16 <= ShiftGeg1((24*7)-1 downto (24*(7-1))); + OUT17 <= ShiftGeg1((24*8)-1 downto (24*(8-1))); + + end if; + end if; +end process; + +end ar_FAKE_DUAL_ADS1278_DRIVER; + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/designs/ICI4-Integ1/ICI4HDL/Fast2SlowSync.vhd b/designs/ICI4-Integ1/ICI4HDL/Fast2SlowSync.vhd new file mode 100644 --- /dev/null +++ b/designs/ICI4-Integ1/ICI4HDL/Fast2SlowSync.vhd @@ -0,0 +1,95 @@ +------------------------------------------------------------------------------ +-- This file is a part of the LPP VHDL IP LIBRARY +-- Copyright (C) 2009 - 2013, Laboratory of Plasmas Physic - CNRS +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 3 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +------------------------------------------------------------------------------ +-- Author : Alexis Jeandet +-- Mail : alexis.jeandet@member.fsf.org +------------------------------------------------------------------------------ +-- +-- This module implements the Fast to Slow clock transfer: +-- Data Transfer between Asynchronous Clock Domains without Pain +-- from Markus Schutti, Markus Pfaff, Richard Hagelauer +-- http://www-micrel.deis.unibo.it/~benini/files/SNUG/paper9_final.pdf +-- see page 6 +-- +-- + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +entity Fast2SlowSync is +generic +( + N : integer range 0 to 256:=8 +); +Port +( + Data : in STD_LOGIC_VECTOR (N-1 downto 0); + ClockF : in STD_LOGIC; + ClockS : in STD_LOGIC; + SyncSignal : in STD_LOGIC; + DataSinkF : out STD_LOGIC_VECTOR (N-1 downto 0) +); +end Fast2SlowSync; + +architecture AR_Fast2SlowSync of Fast2SlowSync is + +signal DataF : STD_LOGIC_VECTOR (N-1 downto 0); +signal DataFlocked : STD_LOGIC_VECTOR (N-1 downto 0); + +signal MuxOut : STD_LOGIC_VECTOR (N-1 downto 0); + +begin + +MuxOut <= DataF when SyncSignal = '1' else + DataFlocked; + +process(ClockF) +begin + if ClockF'event and ClockF = '1' then + DataF <= Data; + DataFlocked <= MuxOut; + end if; +end process; + +process(ClockS) +begin + if ClockS'event and ClockS = '1' then + DataSinkF <= DataFlocked; + end if; +end process; + +end AR_Fast2SlowSync; + + + + + + + + + + + + + + + + + + + diff --git a/designs/ICI4-Integ1/ICI4HDL/IC4_OLD_TOP.vhd b/designs/ICI4-Integ1/ICI4HDL/IC4_OLD_TOP.vhd new file mode 100644 --- /dev/null +++ b/designs/ICI4-Integ1/ICI4HDL/IC4_OLD_TOP.vhd @@ -0,0 +1,443 @@ +library ieee; +use ieee.std_logic_1164.all; +use IEEE.numeric_std.all; +library grlib, techmap; +use grlib.amba.all; +use grlib.amba.all; +use grlib.stdlib.all; +use techmap.gencomp.all; +use techmap.allclkgen.all; +library gaisler; +use gaisler.memctrl.all; +use gaisler.leon3.all; +use gaisler.uart.all; +use gaisler.misc.all; +--use gaisler.sim.all; +library lpp; +use lpp.lpp_ad_conv.all; +use lpp.lpp_amba.all; +use lpp.apb_devices_list.all; +use lpp.general_purpose.all; +use lpp.Rocket_PCM_Encoder.all; + + +use work.Convertisseur_config.all; + + +use work.config.all; +--================================================================== +-- +-- +-- FPGA FREQ = 48MHz +-- ADC Oscillator frequency = 4MHz +-- +-- +--================================================================== + +entity ici4_OLD is + generic ( + fabtech : integer := CFG_FABTECH; + memtech : integer := CFG_MEMTECH; + padtech : integer := CFG_PADTECH; + clktech : integer := CFG_CLKTECH; +WordSize : integer := 8; WordCnt : integer := 144;MinFCount : integer := 64 + ); + port ( + reset : in std_ulogic; + clk : in std_ulogic; + sclk : in std_logic; + Gate : in std_logic; + MinF : in std_logic; + MajF : in std_logic; + Data : out std_logic; + DC_ADC_Sclk : out std_logic; + DC_ADC_IN : in std_logic_vector(1 downto 0); + DC_ADC_ClkDiv : out std_logic; + DC_ADC_FSynch : out std_logic; + SET_RESET0 : out std_logic; + SET_RESET1 : out std_logic; + LED : out std_logic + ); +end; + +architecture rtl of ici4_OLD is + +signal clk_buf,reset_buf : std_logic; + +Constant FramePlacerCount : integer := 2; + +signal MinF_Inv : std_logic; +signal Gate_Inv : std_logic; +signal sclk_Inv : std_logic; +signal WordCount : integer range 0 to WordCnt-1; +signal WordClk : std_logic; + +signal data_int : std_logic; + +signal MuxOUT : std_logic_vector(WordSize-1 downto 0); +signal MuxIN : std_logic_vector((2*WordSize)-1 downto 0); +signal Sel : integer range 0 to 1; + +signal AMR1X : std_logic_vector(23 downto 0); +signal AMR1Y : std_logic_vector(23 downto 0); +signal AMR1Z : std_logic_vector(23 downto 0); + +signal AMR2X : std_logic_vector(23 downto 0); +signal AMR2Y : std_logic_vector(23 downto 0); +signal AMR2Z : std_logic_vector(23 downto 0); + +signal AMR3X : std_logic_vector(23 downto 0); +signal AMR3Y : std_logic_vector(23 downto 0); +signal AMR3Z : std_logic_vector(23 downto 0); + +signal AMR4X : std_logic_vector(23 downto 0); +signal AMR4Y : std_logic_vector(23 downto 0); +signal AMR4Z : std_logic_vector(23 downto 0); + +signal AMR1X_ADC : std_logic_vector(23 downto 0); +signal AMR1Y_ADC : std_logic_vector(23 downto 0); +signal AMR1Z_ADC : std_logic_vector(23 downto 0); + +signal AMR2X_ADC : std_logic_vector(23 downto 0); +signal AMR2Y_ADC : std_logic_vector(23 downto 0); +signal AMR2Z_ADC : std_logic_vector(23 downto 0); + +signal AMR3X_ADC : std_logic_vector(23 downto 0); +signal AMR3Y_ADC : std_logic_vector(23 downto 0); +signal AMR3Z_ADC : std_logic_vector(23 downto 0); + +signal AMR4X_ADC : std_logic_vector(23 downto 0); +signal AMR4Y_ADC : std_logic_vector(23 downto 0); +signal AMR4Z_ADC : std_logic_vector(23 downto 0); + +signal AMR1X_R : std_logic_vector(23 downto 0); +signal AMR1Y_R : std_logic_vector(23 downto 0); +signal AMR1Z_R : std_logic_vector(23 downto 0); + +signal AMR2X_R : std_logic_vector(23 downto 0); +signal AMR2Y_R : std_logic_vector(23 downto 0); +signal AMR2Z_R : std_logic_vector(23 downto 0); + +signal AMR3X_R : std_logic_vector(23 downto 0); +signal AMR3Y_R : std_logic_vector(23 downto 0); +signal AMR3Z_R : std_logic_vector(23 downto 0); + +signal AMR4X_R : std_logic_vector(23 downto 0); +signal AMR4Y_R : std_logic_vector(23 downto 0); +signal AMR4Z_R : std_logic_vector(23 downto 0); + +signal AMR1X_S : std_logic_vector(23 downto 0); +signal AMR1Y_S : std_logic_vector(23 downto 0); +signal AMR1Z_S : std_logic_vector(23 downto 0); + +signal AMR2X_S : std_logic_vector(23 downto 0); +signal AMR2Y_S : std_logic_vector(23 downto 0); +signal AMR2Z_S : std_logic_vector(23 downto 0); + +signal AMR3X_S : std_logic_vector(23 downto 0); +signal AMR3Y_S : std_logic_vector(23 downto 0); +signal AMR3Z_S : std_logic_vector(23 downto 0); + +signal AMR4X_S : std_logic_vector(23 downto 0); +signal AMR4Y_S : std_logic_vector(23 downto 0); +signal AMR4Z_s : std_logic_vector(23 downto 0); + + + +signal Temp1 : std_logic_vector(23 downto 0); +signal Temp2 : std_logic_vector(23 downto 0); +signal Temp3 : std_logic_vector(23 downto 0); +signal Temp4 : std_logic_vector(23 downto 0); + + +signal LF1 : std_logic_vector(15 downto 0); +signal LF2 : std_logic_vector(15 downto 0); +signal LF3 : std_logic_vector(15 downto 0); + + +signal LF1_int : std_logic_vector(23 downto 0); +signal LF2_int : std_logic_vector(23 downto 0); +signal LF3_int : std_logic_vector(23 downto 0); + +signal DC_ADC_SmplClk : std_logic; +signal LF_ADC_SmplClk : std_logic; +signal SET_RESET0_sig : std_logic; +signal SET_RESET1_sig : std_logic; +signal SET_RESET_counter : integer range 0 to 31:=0; + +signal MinFCnt : integer range 0 to MinFCount-1; + +signal FramePlacerFlags : std_logic_vector(FramePlacerCount-1 downto 0); + +begin + + +clk_buf <= clk; +reset_buf <= reset; +-- + +Gate_Inv <= not Gate; +sclk_Inv <= not Sclk; +MinF_Inv <= not MinF; + +LED <= not data_int; +data <= data_int; + + + +SD0 : Serial_Driver +generic map(WordSize) +port map(sclk_Inv,MuxOUT,Gate_inv,data_int); + +WC0 : Word_Cntr +generic map(WordSize,WordCnt) +port map(sclk_Inv,MinF,WordClk,WordCount); + +MFC0 : MinF_Cntr +generic map(MinFCount) +port map( + clk => MinF_Inv, + reset => MajF, + Cnt_out => MinFCnt +); + + +MUX0 : Serial_Driver_Multiplexor +generic map(FramePlacerCount,WordSize) +port map(sclk_Inv,Sel,MuxIN,MuxOUT); + + +DCFP0 : entity work.DC_FRAME_PLACER +generic map(WordSize,WordCnt,MinFCount) +port map( + clk => Sclk, + Wcount => WordCount, + MinFCnt => MinFCnt, + Flag => FramePlacerFlags(0), + AMR1X => AMR1X, + AMR1Y => AMR1Y, + AMR1Z => AMR1Z, + AMR2X => AMR2X, + AMR2Y => AMR2Y, + AMR2Z => AMR2Z, + AMR3X => AMR3X, + AMR3Y => AMR3Y, + AMR3Z => AMR3Z, + AMR4X => AMR4X, + AMR4Y => AMR4Y, + AMR4Z => AMR4Z, + Temp1 => Temp1, + Temp2 => Temp2, + Temp3 => Temp3, + Temp4 => Temp4, + WordOut => MuxIN(7 downto 0)); + + + +LFP0 : entity work.LF_FRAME_PLACER +generic map(WordSize,WordCnt,MinFCount) +port map( + clk => Sclk, + Wcount => WordCount, + Flag => FramePlacerFlags(1), + LF1 => LF1, + LF2 => LF2, + LF3 => LF3, + WordOut => MuxIN(15 downto 8)); + + + +DC_SMPL_CLK0 : entity work.LF_SMPL_CLK +generic map(36) +port map( + reset => reset, + wclk => WordClk, + SMPL_CLK => DC_ADC_SmplClk); + +process(reset,DC_ADC_SmplClk) +begin +if reset = '0' then + SET_RESET0_sig <= '0'; +elsif DC_ADC_SmplClk'event and DC_ADC_SmplClk = '0' then + if(SET_RESET_counter = 31) then + SET_RESET0_sig <= not SET_RESET0_sig; + SET_RESET_counter <= 0; + else + SET_RESET_counter <= SET_RESET_counter +1; + end if; +end if; +end process; + +SET_RESET1_sig <= SET_RESET0_sig; +SET_RESET0 <= SET_RESET0_sig; +SET_RESET1 <= SET_RESET1_sig; +-- + + + +send_ADC_DATA : IF SEND_CONSTANT_DATA = 0 GENERATE + DC_ADC0 : DUAL_ADS1278_DRIVER --With AMR down ! => 24bits DC TM -> SC high res on Spin + port map( + Clk => clk_buf, + reset => reset_buf, + SpiClk => DC_ADC_Sclk, + DIN => DC_ADC_IN, + SmplClk => DC_ADC_SmplClk, + OUT00 => AMR1X, + OUT01 => AMR1Y, + OUT02 => AMR1Z, + OUT03 => AMR2X, + OUT04 => AMR2Y, + OUT05 => AMR2Z, + OUT06 => Temp1, + OUT07 => Temp2, + OUT10 => AMR3X, + OUT11 => AMR3Y, + OUT12 => AMR3Z, + OUT13 => AMR4X, + OUT14 => AMR4Y, + OUT15 => AMR4Z, + OUT16 => Temp3, + OUT17 => Temp4, + FSynch => DC_ADC_FSynch + ); + LF1 <= LF1cst; + LF2 <= LF2cst; + LF3 <= LF3cst; + END GENERATE; + +send_CST_DATA : IF (SEND_CONSTANT_DATA = 1) and (SEND_MINF_VALUE = 0) GENERATE + AMR1X <= AMR1Xcst; + AMR1Y <= AMR1Ycst; + AMR1Z <= AMR1Zcst; + AMR2X <= AMR2Xcst; + AMR2Y <= AMR2Ycst; + AMR2Z <= AMR2Zcst; + Temp1 <= Temp1cst; + Temp2 <= Temp2cst; + AMR3X <= AMR3Xcst; + AMR3Y <= AMR3Ycst; + AMR3Z <= AMR3Zcst; + AMR4X <= AMR4Xcst; + AMR4Y <= AMR4Ycst; + AMR4Z <= AMR4Zcst; + Temp3 <= Temp3cst; + Temp4 <= Temp4cst; + + LF1 <= LF1cst; + LF2 <= LF2cst; + LF3 <= LF3cst; + END GENERATE; + + + + +send_minF_valuelbl : IF (SEND_CONSTANT_DATA = 1) and (SEND_MINF_VALUE = 1) GENERATE + AMR1X <= X"000" & "000" & std_logic_vector(TO_UNSIGNED(MinFCnt,9)); + AMR1Y <= X"000" & "000" & std_logic_vector(TO_UNSIGNED(MinFCnt,9)); + AMR1Z <= X"000" & "000" & std_logic_vector(TO_UNSIGNED(MinFCnt,9)); + AMR2X <= X"000" & "000" & std_logic_vector(TO_UNSIGNED(MinFCnt,9)); + AMR2Y <= X"000" & "000" & std_logic_vector(TO_UNSIGNED(MinFCnt,9)); + AMR2Z <= X"000" & "000" & std_logic_vector(TO_UNSIGNED(MinFCnt,9)); + Temp1 <= X"000" & "000" & std_logic_vector(TO_UNSIGNED(MinFCnt,9)); + Temp2 <= X"000" & "000" & std_logic_vector(TO_UNSIGNED(MinFCnt,9)); + AMR3X <= X"000" & "000" & std_logic_vector(TO_UNSIGNED(MinFCnt,9)); + AMR3Y <= X"000" & "000" & std_logic_vector(TO_UNSIGNED(MinFCnt,9)); + AMR3Z <= X"000" & "000" & std_logic_vector(TO_UNSIGNED(MinFCnt,9)); + AMR4X <= X"000" & "000" & std_logic_vector(TO_UNSIGNED(MinFCnt,9)); + AMR4Y <= X"000" & "000" & std_logic_vector(TO_UNSIGNED(MinFCnt,9)); + AMR4Z <= X"000" & "000" & std_logic_vector(TO_UNSIGNED(MinFCnt,9)); + Temp3 <= X"000" & "000" & std_logic_vector(TO_UNSIGNED(MinFCnt,9)); + Temp4 <= X"000" & "000" & std_logic_vector(TO_UNSIGNED(MinFCnt,9)); + + LF1 <= LF1cst; + LF2 <= LF2cst; + LF3 <= LF3cst; + END GENERATE; + +LF_SMPL_CLK0 : entity work.LF_SMPL_CLK +port map( + reset => reset, + wclk => WordClk, + SMPL_CLK => LF_ADC_SmplClk +); + + +sr_hndl: IF SEND_CONSTANT_DATA = 0 GENERATE +process(clk) +begin + if clk'event and clk ='1' then + if SET_RESET0_sig = '1' then + AMR1X_S <= AMR1X_ADC; + AMR1Y_S <= AMR1Y_ADC; + AMR1Z_S <= AMR1Z_ADC; + AMR2X_S <= AMR2X_ADC; + AMR2Y_S <= AMR2Y_ADC; + AMR2Z_S <= AMR2Z_ADC; + AMR3X_S <= AMR3X_ADC; + AMR3Y_S <= AMR3Y_ADC; + AMR3Z_S <= AMR3Z_ADC; + AMR4X_S <= AMR4X_ADC; + AMR4Y_S <= AMR4Y_ADC; + AMR4Z_S <= AMR4Z_ADC; + else + AMR1X_R <= AMR1X_ADC; + AMR1Y_R <= AMR1Y_ADC; + AMR1Z_R <= AMR1Z_ADC; + AMR2X_R <= AMR2X_ADC; + AMR2Y_R <= AMR2Y_ADC; + AMR2Z_R <= AMR2Z_ADC; + AMR3X_R <= AMR3X_ADC; + AMR3Y_R <= AMR3Y_ADC; + AMR3Z_R <= AMR3Z_ADC; + AMR4X_R <= AMR4X_ADC; + AMR4Y_R <= AMR4Y_ADC; + AMR4Z_R <= AMR4Z_ADC; + end if; +-- AMR1X <= std_logic_vector((signed(AMR1X_S) - signed(AMR1X_R))/2); +-- AMR1Y <= std_logic_vector((signed(AMR1Y_S) - signed(AMR1Y_R))/2); +-- AMR1Z <= std_logic_vector((signed(AMR1Z_S) - signed(AMR1Z_R))/2); +-- AMR2X <= std_logic_vector((signed(AMR2X_S) - signed(AMR2X_R))/2); +-- AMR2Y <= std_logic_vector((signed(AMR2Y_S) - signed(AMR2Y_R))/2); +-- AMR2Z <= std_logic_vector((signed(AMR2Z_S) - signed(AMR2Z_R))/2); +-- AMR3X <= std_logic_vector((signed(AMR3X_S) - signed(AMR3X_R))/2); +-- AMR3Y <= std_logic_vector((signed(AMR3Y_S) - signed(AMR3Y_R))/2); +-- AMR3Z <= std_logic_vector((signed(AMR3Z_S) - signed(AMR3Z_R))/2); +-- AMR4X <= std_logic_vector((signed(AMR4X_S) - signed(AMR4X_R))/2); +-- AMR4Y <= std_logic_vector((signed(AMR4Y_S) - signed(AMR4Y_R))/2); +-- AMR4Z <= std_logic_vector((signed(AMR4Z_S) - signed(AMR4Z_R))/2); +-- AMR1X <= AMR1X_S; +-- AMR1Y <= AMR1Y_S; +-- AMR1Z <= AMR1Z_S; +-- AMR2X <= AMR2X_S; +-- AMR2Y <= AMR2Y_S; +-- AMR2Z <= AMR2Z_S; +-- AMR3X <= AMR3X_S; +-- AMR3Y <= AMR3Y_S; +-- AMR3Z <= AMR3Z_S; +-- AMR4X <= AMR4X_S; +-- AMR4Y <= AMR4Y_S; +-- AMR4Z <= AMR4Z_S; + end if; +end process; +end generate; + + +process(clk) +variable SelVar : integer range 0 to 1; +begin + if clk'event and clk ='1' then + Decoder: FOR i IN 0 to FramePlacerCount-1 loop + if FramePlacerFlags(i) = '1' then + SelVar := i; + end if; + END loop Decoder; + Sel <= SelVar; + end if; +end process; + + +end rtl; + + + diff --git a/designs/ICI4-Integ1/ICI4HDL/LF_ACQ_TOP.vhd b/designs/ICI4-Integ1/ICI4HDL/LF_ACQ_TOP.vhd new file mode 100644 --- /dev/null +++ b/designs/ICI4-Integ1/ICI4HDL/LF_ACQ_TOP.vhd @@ -0,0 +1,221 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library lpp; +use lpp.lpp_ad_conv.all; +use lpp.lpp_amba.all; +use lpp.apb_devices_list.all; +use lpp.general_purpose.all; +use lpp.Rocket_PCM_Encoder.all; +use lpp.iir_filter.all; +use work.config.all; + +entity LF_ACQ_TOP is +generic( + WordSize : integer := 8; + WordCnt : integer := 144; + MinFCount : integer := 64; + CstDATA : integer := 0; + IIRFilter : integer := 1 +); +port( + + reset : in std_logic; + clk : in std_logic; + SyncSig : in STD_LOGIC; + minorF : in std_logic; + majorF : in std_logic; + sclk : in std_logic; + WordClk : in std_logic; + LF_SCK : out std_logic; + LF_CNV : out std_logic; + LF_SDO1 : in std_logic; + LF_SDO2 : in std_logic; + LF_SDO3 : in std_logic; + LF1 : out std_logic_vector(15 downto 0); + LF2 : out std_logic_vector(15 downto 0); + LF3 : out std_logic_vector(15 downto 0) +); +end LF_ACQ_TOP; + +architecture AR_LF_ACQ_TOP of LF_ACQ_TOP is + +signal LF_ADC_SmplClk : std_logic; + +signal LF_ADC_SpPulse : std_logic; +signal SDO : STD_LOGIC_VECTOR(2 DOWNTO 0); +signal sps : Samples(2 DOWNTO 0); + +signal LFX : Samples(2 DOWNTO 0); +signal sample_val : std_logic; +signal AD_in : AD7688_in(2 DOWNTO 0); +signal AD_out : AD7688_out; +signal Filter_sp_in : samplT(2 DOWNTO 0, 15 DOWNTO 0); +signal Filter_sp_out : samplT(2 DOWNTO 0, 15 DOWNTO 0); +signal sample_out_val : std_logic; + +begin + + +AD_in(0).sdi <= LF_SDO1; +AD_in(1).sdi <= LF_SDO2; +AD_in(2).sdi <= LF_SDO3; +LF_SCK <= AD_out.SCK; +LF_CNV <= AD_out.CNV; + + +LF_SMPL_CLK0 : entity work.LF_SMPL_CLK +generic map(6) +port map( + reset => reset, + wclk => WordClk, + SMPL_CLK => LF_ADC_SmplClk +); + + +ADC: IF CstDATA =0 GENERATE +ADCs: AD7688_drvr +GENERIC map +( + ChanelCount => 3, + clkkHz => 48000 +) +PORT map +( + clk => clk, + rstn => reset, + enable => '1', + smplClk => LF_ADC_SmplClk, + DataReady => sample_val, + smpout => sps, + AD_in => AD_in, + AD_out => AD_out +); + +smpPulse: entity work.OneShot + Port map( + reset => reset, + clk => clk, + input => LF_ADC_SmplClk, + output => LF_ADC_SpPulse +); + + + +Filter: IIR_CEL_CTRLR_v2 + GENERIC map( + tech => CFG_MEMTECH, + Mem_use => use_RAM, + Sample_SZ => Sample_SZ, + Coef_SZ => Coef_SZ, + Coef_Nb => 25, + Coef_sel_SZ => 5, + Cels_count => 5, + ChanelsCount => ChanelsCount + ) + PORT map( + rstn => reset, + clk => clk, + + virg_pos => virgPos, + coefs => CoefsInitValCst_v2, + + sample_in_val => LF_ADC_SpPulse, + sample_in => Filter_sp_in, + + sample_out_val => sample_out_val, + sample_out => Filter_sp_out +); + +NOfilt: IF IIRFilter = 0 GENERATE + process(reset,clk) + begin + if reset ='0' then + LF1 <= (others => '0'); + LF2 <= (others => '0'); + LF3 <= (others => '0'); + elsif clk'event and clk ='1' then + if sample_val = '1' then + LF1 <= sps(0); + LF2 <= sps(1); + LF3 <= sps(2); + end if; + end if; + end process; + END GENERATE; +filt: IF IIRFilter /= 0 GENERATE + + LF1 <= LFX(0); + LF2 <= LFX(1); + LF3 <= LFX(2); + + loop_all_sample : FOR J IN 15 DOWNTO 0 GENERATE + + loop_all_chanel : FOR I IN 2 DOWNTO 0 GENERATE + process(reset,clk) + begin + if reset ='0' then + Filter_sp_in(I,J) <= '0'; +-- LFX(I) <= (others => '0'); + elsif clk'event and clk ='1' then + if sample_out_val = '1' then + LFX(I)(J) <= Filter_sp_out(I,J); + Filter_sp_in(I,J) <= sps(I)(J); + end if; + end if; + end process; + END GENERATE; + END GENERATE; +END GENERATE; + + + + +END GENERATE; + +CST: IF CstDATA /=0 GENERATE + + LF1 <= LF1cst; + LF2 <= LF2cst; + LF3 <= LF3cst; + +END GENERATE; + + + + +--Filter: IIR_CEL_FILTER +-- GENERIC map( +-- tech => CFG_MEMTECH, +-- Sample_SZ => Sample_SZ, +-- ChanelsCount => ChanelsCount, +-- Coef_SZ => Coef_SZ, +-- CoefCntPerCel => CoefCntPerCel, +-- Cels_count => Cels_count, +-- Mem_use => use_RAM +-- ) +-- PORT map( +-- reset => reset, +-- clk => clk, +-- sample_clk => LF_ADC_SmplClk, +-- regs_in : IN in_IIR_CEL_reg; +-- regs_out : IN out_IIR_CEL_reg; +-- sample_in : IN samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0); +-- sample_out : OUT samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0); +-- GOtest : OUT STD_LOGIC; +-- coefs : IN STD_LOGIC_VECTOR(Coef_SZ*CoefCntPerCel*Cels_count-1 DOWNTO 0) +-- +-- ); + + + + +end AR_LF_ACQ_TOP; + + + + + + + + + diff --git a/designs/ICI4-Integ1/ICI4HDL/LF_SMPL_CLK.vhd b/designs/ICI4-Integ1/ICI4HDL/LF_SMPL_CLK.vhd --- a/designs/ICI4-Integ1/ICI4HDL/LF_SMPL_CLK.vhd +++ b/designs/ICI4-Integ1/ICI4HDL/LF_SMPL_CLK.vhd @@ -4,10 +4,11 @@ use IEEE.numeric_std.all; use IEEE.std_logic_1164.all; -entity LF_SMPL_CLK is +entity LF_SMPL_CLK is +generic(N : integer range 0 to 4096 :=24); port( - Wclck : in std_logic; - MinF : in std_logic; + reset : in std_logic; + wclk : in std_logic; SMPL_CLK : out std_logic ); end entity; @@ -19,24 +20,25 @@ end entity; architecture ar_LF_SMPL_CLK of LF_SMPL_CLK is -signal cpt : integer range 0 to 23 := 0; +signal cpt : integer range 0 to N-1 := 0; begin -process(Wclck,MinF) +process(reset,wclk) begin -if MinF = '0' then - SMPL_CLK <= '1'; -elsif Wclck'event and Wclck = '1' then - if cpt = 23 then +if reset = '0' then + SMPL_CLK <= '1'; + cpt <= 0; +elsif wclk'event and wclk = '1' then + if cpt = (N-1) then cpt <= 0; else cpt <= cpt+1; end if; if cpt = 0 then SMPL_CLK <= '1'; - elsif cpt = 10 then + elsif cpt = (N/2) then SMPL_CLK <= '0'; end if; end if; diff --git a/designs/ICI4-Integ1/ICI4HDL/OneShot.vhd b/designs/ICI4-Integ1/ICI4HDL/OneShot.vhd new file mode 100644 --- /dev/null +++ b/designs/ICI4-Integ1/ICI4HDL/OneShot.vhd @@ -0,0 +1,67 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 21:06:46 08/22/2013 +-- Design Name: +-- Module Name: OneShot - AR_OneShot +-- Project Name: +-- Target Devices: +-- Tool versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +--use IEEE.NUMERIC_STD.ALL; + +-- Uncomment the following library declaration if instantiating +-- any Xilinx primitives in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity OneShot is + Port ( reset : in STD_LOGIC; + clk : in STD_LOGIC; + input : in STD_LOGIC; + output : out STD_LOGIC); +end OneShot; + +architecture AR_OneShot of OneShot is +signal inreg : std_logic; +begin + +process(clk,reset) +begin +if reset = '0' then + output <= '0'; +elsif clk'event and clk = '1' then + inreg <= input; + if inreg = '0' and input = '1' then + output <= '1'; + else + output <= '0'; + end if; +end if; +end process; + +end AR_OneShot; + + + + + + + + + + diff --git a/designs/ICI4-Integ1/ICI4HDL/Slow2FastSync.vhd b/designs/ICI4-Integ1/ICI4HDL/Slow2FastSync.vhd new file mode 100644 --- /dev/null +++ b/designs/ICI4-Integ1/ICI4HDL/Slow2FastSync.vhd @@ -0,0 +1,91 @@ +------------------------------------------------------------------------------ +-- This file is a part of the LPP VHDL IP LIBRARY +-- Copyright (C) 2009 - 2013, Laboratory of Plasmas Physic - CNRS +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 3 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +------------------------------------------------------------------------------ +-- Author : Alexis Jeandet +-- Mail : alexis.jeandet@member.fsf.org +------------------------------------------------------------------------------ +-- +-- This module implements the Slow to Slow Fast transfer: +-- Data Transfer between Asynchronous Clock Domains without Pain +-- from Markus Schutti, Markus Pfaff, Richard Hagelauer +-- http://www-micrel.deis.unibo.it/~benini/files/SNUG/paper9_final.pdf +-- see page 5 +-- +-- + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +entity Slow2FastSync is +generic +( + N : integer range 0 to 256:=8 +); +Port +( + Data : in STD_LOGIC_VECTOR (N-1 downto 0); + ClockF : in STD_LOGIC; + ClockS : in STD_LOGIC; + SyncSignal : in STD_LOGIC; + DataSinkS : out STD_LOGIC_VECTOR (N-1 downto 0) +); +end Slow2FastSync; + +architecture AR_Slow2FastSync of Slow2FastSync is + +signal DataS : STD_LOGIC_VECTOR (N-1 downto 0); + + +begin + + + +process(ClockF) +begin + if ClockF'event and ClockF = '1' and SyncSignal = '1' then + DataSinkS <= DataS; + end if; +end process; + +process(ClockS) +begin + if ClockS'event and ClockS = '1' then + DataS <= Data; + end if; +end process; + +end AR_Slow2FastSync; + + + + + + + + + + + + + + + + + + + diff --git a/designs/ICI4-Integ1/ICI4HDL/TM_MODULE.vhd b/designs/ICI4-Integ1/ICI4HDL/TM_MODULE.vhd new file mode 100644 --- /dev/null +++ b/designs/ICI4-Integ1/ICI4HDL/TM_MODULE.vhd @@ -0,0 +1,177 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 10:03:54 08/21/2013 +-- Design Name: +-- Module Name: TM_MODULE - AR_TM_MODULE +-- Project Name: +-- Target Devices: +-- Tool versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library lpp; +use lpp.lpp_ad_conv.all; +use lpp.lpp_amba.all; +use lpp.apb_devices_list.all; +use lpp.general_purpose.all; +use lpp.Rocket_PCM_Encoder.all; + +entity TM_MODULE is +generic( + WordSize : integer := 8; WordCnt : integer := 144;MinFCount : integer := 64 +); +port( + + reset : in std_logic; + clk : in std_logic; + MinF : in std_logic; + MajF : in std_logic; + sclk : in std_logic; + gate : in std_logic; + data : out std_logic; + WordClk : out std_logic; + + + LF1 : in std_logic_vector(15 downto 0); + LF2 : in std_logic_vector(15 downto 0); + LF3 : in std_logic_vector(15 downto 0); + + AMR1X : in std_logic_vector(23 downto 0); + AMR1Y : in std_logic_vector(23 downto 0); + AMR1Z : in std_logic_vector(23 downto 0); + + AMR2X : in std_logic_vector(23 downto 0); + AMR2Y : in std_logic_vector(23 downto 0); + AMR2Z : in std_logic_vector(23 downto 0); + + AMR3X : in std_logic_vector(23 downto 0); + AMR3Y : in std_logic_vector(23 downto 0); + AMR3Z : in std_logic_vector(23 downto 0); + + AMR4X : in std_logic_vector(23 downto 0); + AMR4Y : in std_logic_vector(23 downto 0); + AMR4Z : in std_logic_vector(23 downto 0); + + Temp1 : in std_logic_vector(23 downto 0); + Temp2 : in std_logic_vector(23 downto 0); + Temp3 : in std_logic_vector(23 downto 0); + Temp4 : in std_logic_vector(23 downto 0) +); +end TM_MODULE; + +architecture AR_TM_MODULE of TM_MODULE is + +Constant FramePlacerCount : integer := 2; +signal MinFCnt : integer range 0 to MinFCount-1; +signal FramePlacerFlags : std_logic_vector(FramePlacerCount-1 downto 0); + +signal WordCount : integer range 0 to WordCnt-1; + +signal data_int : std_logic; + +signal MuxOUT : std_logic_vector(WordSize-1 downto 0); +signal MuxIN : std_logic_vector((2*WordSize)-1 downto 0); +signal Sel : integer range 0 to 1; + + +signal MinF_Inv : std_logic; +signal Gate_Inv : std_logic; +signal sclk_Inv : std_logic; + +begin + + +Gate_Inv <= not Gate; +sclk_Inv <= not Sclk; +MinF_Inv <= not MinF; +data <= data_int; + +SD0 : Serial_Driver +generic map(WordSize) +port map(sclk_Inv,MuxOUT,Gate_inv,data_int); + +WC0 : Word_Cntr +generic map(WordSize,WordCnt) +port map(sclk_Inv,MinF,WordClk,WordCount); + +MFC0 : MinF_Cntr +generic map(MinFCount) +port map( + clk => MinF_Inv, + reset => MajF, + Cnt_out => MinFCnt +); + + +MUX0 : Serial_Driver_Multiplexor +generic map(FramePlacerCount,WordSize) +port map(sclk_Inv,Sel,MuxIN,MuxOUT); + + +DCFP0 : entity work.DC_FRAME_PLACER +generic map(WordSize,WordCnt,MinFCount) +port map( + clk => Sclk, + Wcount => WordCount, + MinFCnt => MinFCnt, + Flag => FramePlacerFlags(0), + AMR1X => AMR1X, + AMR1Y => AMR1Y, + AMR1Z => AMR1Z, + AMR2X => AMR2X, + AMR2Y => AMR2Y, + AMR2Z => AMR2Z, + AMR3X => AMR3X, + AMR3Y => AMR3Y, + AMR3Z => AMR3Z, + AMR4X => AMR4X, + AMR4Y => AMR4Y, + AMR4Z => AMR4Z, + Temp1 => Temp1, + Temp2 => Temp2, + Temp3 => Temp3, + Temp4 => Temp4, + WordOut => MuxIN(7 downto 0)); + + + +LFP0 : entity work.LF_FRAME_PLACER +generic map(WordSize,WordCnt,MinFCount) +port map( + clk => Sclk, + Wcount => WordCount, + Flag => FramePlacerFlags(1), + LF1 => LF1, + LF2 => LF2, + LF3 => LF3, + WordOut => MuxIN(15 downto 8)); + + + +process(clk) +variable SelVar : integer range 0 to 1; +begin + if clk'event and clk ='1' then + Decoder: FOR i IN 0 to FramePlacerCount-1 loop + if FramePlacerFlags(i) = '1' then + SelVar := i; + end if; + END loop Decoder; + Sel <= SelVar; + end if; +end process; + + + +end AR_TM_MODULE; + diff --git a/designs/ICI4-Integ1/Makefile b/designs/ICI4-Integ1/Makefile --- a/designs/ICI4-Integ1/Makefile +++ b/designs/ICI4-Integ1/Makefile @@ -4,11 +4,11 @@ include .config TOP=ici4 BOARD=ICI4-main-BD #BOARD=SP601 -include $(GRLIB)/boards/$(BOARD)/Makefile.inc +include ../../boards/$(BOARD)/Makefile.inc DEVICE=$(PART)-$(PACKAGE)$(SPEED) #UCF=$(GRLIB)/boards/$(BOARD)/ICI3.ucf -UCF=$(GRLIB)/boards/$(BOARD)/ICI4-Main-BD.ucf -QSF=$(GRLIB)/boards/$(BOARD)/$(TOP).qsf +UCF=../../boards/$(BOARD)/ICI4-Main-BD.ucf +QSF=../../boards/$(BOARD)/$(TOP).qsf EFFORT=high ISEMAPOPT="-timing" XSTOPT="" @@ -19,7 +19,16 @@ VHDLOPTSYNFILES= \ ICI4HDL/DC_FRAME_PLACER.vhd \ ICI4HDL/DC_SMPL_CLK.vhd \ ICI4HDL/LF_FRAME_PLACER.vhd \ - ICI4HDL/LF_SMPL_CLK.vhd + ICI4HDL/LF_SMPL_CLK.vhd \ + ICI4HDL/Fast2SlowSync.vhd \ + ICI4HDL/Slow2FastSync.vhd \ + ICI4HDL/CrossDomainSyncGen.vhd \ + ICI4HDL/TM_MODULE.vhd \ + ICI4HDL/DC_ACQ_TOP.vhd \ + ICI4HDL/LF_ACQ_TOP.vhd \ + ICI4HDL/FAKE_ADC.vhd \ + ICI4HDL/OneShot.vhd + VHDLSYNFILES= \ config.vhd ici4.vhd @@ -27,7 +36,7 @@ VHDLSIMFILES=testbench.vhd SIMTOP=testbench #SDCFILE=$(GRLIB)/boards/$(BOARD)/default.sdc SDCFILE=default.sdc -BITGEN=$(GRLIB)/boards/$(BOARD)/default.ut +BITGEN=../../boards/$(BOARD)/default.ut CLEAN=soft-clean VCOMOPT=-explicit TECHLIBS = secureip unisim @@ -47,4 +56,5 @@ include $(GRLIB)/software/leon3/Makefile ################## project specific targets ########################## - +flash: + xc3sprog -c ftdi -p 1 ici4.bit diff --git a/designs/ICI4-Integ1/config.vhd b/designs/ICI4-Integ1/config.vhd --- a/designs/ICI4-Integ1/config.vhd +++ b/designs/ICI4-Integ1/config.vhd @@ -9,8 +9,10 @@ library techmap; use techmap.gencomp.all; -library ieee; -use ieee.std_logic_1164.all; +LIBRARY IEEE; +USE IEEE.numeric_std.ALL; +USE IEEE.std_logic_1164.ALL; + package config is -- Technology and synthesis options @@ -19,8 +21,8 @@ package config is constant CFG_PADTECH : integer := spartan6; -- Clock generator constant CFG_CLKTECH : integer := spartan6; - constant SEND_CONSTANT_DATA : integer := 1; - constant SEND_MINF_VALUE : integer := 1; + constant SEND_CONSTANT_DATA : integer := 0; + constant SEND_MINF_VALUE : integer := 0; @@ -29,13 +31,13 @@ constant LF2cst : std_logic_vector(15 constant LF3cst : std_logic_vector(15 downto 0) := X"3333"; -constant AMR1Xcst : std_logic_vector(23 downto 0):= X"444444"; -constant AMR1Ycst : std_logic_vector(23 downto 0):= X"555555"; -constant AMR1Zcst : std_logic_vector(23 downto 0):= X"666666"; +constant AMR1Xcst : std_logic_vector(23 downto 0):= X"000001"; +constant AMR1Ycst : std_logic_vector(23 downto 0):= X"111111"; +constant AMR1Zcst : std_logic_vector(23 downto 0):= X"7FFFFF"; -constant AMR2Xcst : std_logic_vector(23 downto 0):= X"777777"; -constant AMR2Ycst : std_logic_vector(23 downto 0):= X"888888"; -constant AMR2Zcst : std_logic_vector(23 downto 0):= X"999999"; +constant AMR2Xcst : std_logic_vector(23 downto 0):= X"800000"; +constant AMR2Ycst : std_logic_vector(23 downto 0):= X"000002"; +constant AMR2Zcst : std_logic_vector(23 downto 0):= X"800001"; constant AMR3Xcst : std_logic_vector(23 downto 0):= X"AAAAAA"; constant AMR3Ycst : std_logic_vector(23 downto 0):= X"BBBBBB"; @@ -49,4 +51,95 @@ constant Temp1cst : std_logic_vec constant Temp2cst : std_logic_vector(23 downto 0):= X"343434"; constant Temp3cst : std_logic_vector(23 downto 0):= X"565656"; constant Temp4cst : std_logic_vector(23 downto 0):= X"787878"; + + + +--===========================================================| +--========F I L T E R C O N F I G V A L U E S=============| +--===========================================================| +--____________________________ +--Bus Width and chanels number| +--____________________________| +constant ChanelsCount : integer := 3; +constant Sample_SZ : integer := 16; +constant Coef_SZ : integer := 9; +constant CoefCntPerCel: integer := 6; +constant CoefPerCel: integer := 5; +constant Cels_count : integer := 5; +constant virgPos : integer := 7; +constant Mem_use : integer := 1; + + + +--============================================================ +-- create each initial values for each coefs ============ +--!!!!!!!!!!It should be interfaced with a software !!!!!!!!!! +--============================================================ +constant b0_0 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(58,Coef_SZ)); +constant b0_1 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(-66,Coef_SZ)); +constant b0_2 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(58,Coef_SZ)); + +constant b1_0 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(58,Coef_SZ)); +constant b1_1 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(-57,Coef_SZ)); +constant b1_2 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(58,Coef_SZ)); + +constant b2_0 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(29,Coef_SZ)); +constant b2_1 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(-17,Coef_SZ)); +constant b2_2 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(29,Coef_SZ)); + +constant b3_0 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(15,Coef_SZ)); +constant b3_1 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(4,Coef_SZ)); +constant b3_2 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(15,Coef_SZ)); + +constant b4_0 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(15,Coef_SZ)); +constant b4_1 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(24,Coef_SZ)); +constant b4_2 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(15,Coef_SZ)); + +--constant b5_0 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(-81,Coef_SZ)); +--constant b5_1 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(-153,Coef_SZ)); +--constant b5_2 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(-171,Coef_SZ)); + +--constant b6_0 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(-144,Coef_SZ)); +--constant b6_1 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(-72,Coef_SZ)); +--constant b6_2 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(-25,Coef_SZ)); + + +constant a0_0 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(-128,Coef_SZ)); +constant a0_1 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(189,Coef_SZ)); +constant a0_2 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(-111,Coef_SZ)); + +constant a1_0 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(-128,Coef_SZ)); +constant a1_1 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(162,Coef_SZ)); +constant a1_2 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(-81,Coef_SZ)); + +constant a2_0 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(-128,Coef_SZ)); +constant a2_1 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(136,Coef_SZ)); +constant a2_2 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(-55,Coef_SZ)); + +constant a3_0 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(-128,Coef_SZ)); +constant a3_1 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(114,Coef_SZ)); +constant a3_2 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(-33,Coef_SZ)); + +constant a4_0 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(-128,Coef_SZ)); +constant a4_1 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(100,Coef_SZ)); +constant a4_2 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(-20,Coef_SZ)); + +--constant a5_0 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(60,Coef_SZ)); +--constant a5_1 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(-128,Coef_SZ)); +--constant a5_2 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(87,Coef_SZ)); +--constant a6_0 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(60,Coef_SZ)); +--constant a6_1 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(-128,Coef_SZ)); +--constant a6_2 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(87,Coef_SZ)); + +constant CoefsInitValCst : std_logic_vector((Cels_count*CoefCntPerCel*Coef_SZ)-1 downto 0) := (a4_2 & a4_1 & a4_0 & b4_2 & b4_1 & b4_0 & a3_2 & a3_1 & a3_0 & b3_2 & b3_1 & b3_0 & a2_2 & a2_1 & a2_0 & b2_2 & b2_1 & b2_0 & a1_2 & a1_1 & a1_0 & b1_2 & b1_1 & b1_0 & a0_2 & a0_1 & a0_0 & b0_2 & b0_1 & b0_0); + +constant CoefsInitValCst_v2 : std_logic_vector((Cels_count*CoefPerCel*Coef_SZ)-1 downto 0) := + (a4_1 & a4_2 & b4_0 & b4_1 & b4_2 & + a3_1 & a3_2 & b3_0 & b3_1 & b3_2 & + a2_1 & a2_2 & b2_0 & b2_1 & b2_2 & + a1_1 & a1_2 & b1_0 & b1_1 & b1_2 & + a0_1 & a0_2 & b0_0 & b0_1 & b0_2 ); + + + end; diff --git a/designs/ICI4-Integ1/ici4.vhd b/designs/ICI4-Integ1/ici4.vhd --- a/designs/ICI4-Integ1/ici4.vhd +++ b/designs/ICI4-Integ1/ici4.vhd @@ -1,5 +1,5 @@ library ieee; -use ieee.std_logic_1164.all; +use ieee.std_logic_1164.all; use IEEE.numeric_std.all; library grlib, techmap; use grlib.amba.all; @@ -25,6 +25,14 @@ use work.Convertisseur_config.all; use work.config.all; +--================================================================== +-- +-- +-- FPGA FREQ = 48MHz +-- ADC Oscillator frequency = 12MHz +-- +-- +--================================================================== entity ici4 is generic ( @@ -35,20 +43,25 @@ entity ici4 is WordSize : integer := 8; WordCnt : integer := 144;MinFCount : integer := 64 ); port ( - reset : in std_ulogic; - clk : in std_ulogic; - sclk : in std_logic; - Gate : in std_logic; - MinF : in std_logic; - MajF : in std_logic; - Data : out std_logic; - DC_ADC_Sclk : out std_logic; - DC_ADC_IN : in std_logic_vector(1 downto 0); - DC_ADC_ClkDiv : out std_logic; - DC_ADC_FSynch : out std_logic; - SET_RESET0 : out std_logic; - SET_RESET1 : out std_logic; - LED : out std_logic + reset : in std_ulogic; + clk : in std_ulogic; + sclk : in std_logic; + Gate : in std_logic; + MinF : in std_logic; + MajF : in std_logic; + Data : out std_logic; + LF_SCK : out std_logic; + LF_CNV : out std_logic; + LF_SDO1 : in std_logic; + LF_SDO2 : in std_logic; + LF_SDO3 : in std_logic; + DC_ADC_Sclk : out std_logic; + DC_ADC_IN : in std_logic_vector(1 downto 0); + DC_ADC_ClkDiv : out std_logic; + DC_ADC_FSynch : out std_logic; + SET_RESET0 : out std_logic; + SET_RESET1 : out std_logic; + LED : out std_logic ); end; @@ -58,17 +71,10 @@ signal clk_buf,reset_buf : std_logi Constant FramePlacerCount : integer := 2; -signal MinF_Inv : std_logic; -signal Gate_Inv : std_logic; -signal sclk_Inv : std_logic; + signal WordCount : integer range 0 to WordCnt-1; signal WordClk : std_logic; -signal data_int : std_logic; - -signal MuxOUT : std_logic_vector(WordSize-1 downto 0); -signal MuxIN : std_logic_vector((2*WordSize)-1 downto 0); -signal Sel : integer range 0 to 1; signal AMR1X : std_logic_vector(23 downto 0); signal AMR1Y : std_logic_vector(23 downto 0); @@ -86,229 +92,153 @@ signal AMR4X : std_logic_vector(2 signal AMR4Y : std_logic_vector(23 downto 0); signal AMR4Z : std_logic_vector(23 downto 0); -signal Temp1 : std_logic_vector(23 downto 0); -signal Temp2 : std_logic_vector(23 downto 0); -signal Temp3 : std_logic_vector(23 downto 0); -signal Temp4 : std_logic_vector(23 downto 0); +signal TEMP1 : std_logic_vector(23 downto 0); +signal TEMP2 : std_logic_vector(23 downto 0); +signal TEMP3 : std_logic_vector(23 downto 0); +signal TEMP4 : std_logic_vector(23 downto 0); signal LF1 : std_logic_vector(15 downto 0); signal LF2 : std_logic_vector(15 downto 0); signal LF3 : std_logic_vector(15 downto 0); - -signal LF1_int : std_logic_vector(23 downto 0); -signal LF2_int : std_logic_vector(23 downto 0); -signal LF3_int : std_logic_vector(23 downto 0); +signal data_int : std_logic; -signal DC_ADC_SmplClk : std_logic; -signal LF_ADC_SmplClk : std_logic; -signal SET_RESET0_sig : std_logic; -signal SET_RESET1_sig : std_logic; - -signal MinFCnt : integer range 0 to MinFCount-1; - -signal FramePlacerFlags : std_logic_vector(FramePlacerCount-1 downto 0); +signal CrossDomainSync : std_logic; begin -clk_buf <= clk; -reset_buf <= reset; --- - -Gate_Inv <= not Gate; -sclk_Inv <= not Sclk; -MinF_Inv <= not MinF; - LED <= not data_int; -data <= data_int; - - - -SD0 : Serial_Driver -generic map(WordSize) -port map(sclk_Inv,MuxOUT,Gate_inv,data_int); - -WC0 : Word_Cntr -generic map(WordSize,WordCnt) -port map(sclk_Inv,MinF,WordClk,WordCount); - -MFC0 : MinF_Cntr -generic map(MinFCount) -port map( - clk => MinF_Inv, - reset => MajF, - Cnt_out => MinFCnt -); - - -MUX0 : Serial_Driver_Multiplexor -generic map(FramePlacerCount,WordSize) -port map(sclk_Inv,Sel,MuxIN,MuxOUT); - - -DCFP0 : entity work.DC_FRAME_PLACER -generic map(WordSize,WordCnt,MinFCount) -port map( - clk => Sclk, - Wcount => WordCount, - MinFCnt => MinFCnt, - Flag => FramePlacerFlags(0), - AMR1X => AMR1X, - AMR1Y => AMR1Y, - AMR1Z => AMR1Z, - AMR2X => AMR2X, - AMR2Y => AMR2Y, - AMR2Z => AMR2Z, - AMR3X => AMR3X, - AMR3Y => AMR3Y, - AMR3Z => AMR3Z, - AMR4X => AMR4X, - AMR4Y => AMR4Y, - AMR4Z => AMR4Z, - Temp1 => Temp1, - Temp2 => Temp2, - Temp3 => Temp3, - Temp4 => Temp4, - WordOut => MuxIN(7 downto 0)); - - - -LFP0 : entity work.LF_FRAME_PLACER -generic map(WordSize,WordCnt,MinFCount) -port map( - clk => Sclk, - Wcount => WordCount, - Flag => FramePlacerFlags(1), - LF1 => LF1, - LF2 => LF2, - LF3 => LF3, - WordOut => MuxIN(15 downto 8)); - - - -DC_SMPL_CLK0 : entity work.DC_SMPL_CLK -port map(MinF_Inv,DC_ADC_SmplClk); - -process(reset,DC_ADC_SmplClk) -begin -if reset = '0' then - SET_RESET0_sig <= '0'; -elsif DC_ADC_SmplClk'event and DC_ADC_SmplClk = '1' then - SET_RESET0_sig <= not SET_RESET0_sig; -end if; -end process; - -SET_RESET1_sig <= SET_RESET0_sig; -SET_RESET0 <= SET_RESET0_sig; -SET_RESET1 <= SET_RESET1_sig; --- +data <= data_int; -send_ADC_DATA : IF SEND_CONSTANT_DATA = 0 GENERATE - DC_ADC0 : DUAL_ADS1278_DRIVER --With AMR down ! => 24bits DC TM -> SC high res on Spin - port map( - Clk => clk_buf, - reset => reset_buf, - SpiClk => DC_ADC_Sclk, - DIN => DC_ADC_IN, - SmplClk => DC_ADC_SmplClk, - OUT00 => AMR1X, - OUT01 => AMR1Y, - OUT02 => AMR1Z, - OUT03 => AMR2X, - OUT04 => AMR2Y, - OUT05 => AMR2Z, - OUT06 => Temp1, - OUT07 => Temp2, - OUT10 => AMR3X, - OUT11 => AMR3Y, - OUT12 => AMR3Z, - OUT13 => AMR4X, - OUT14 => AMR4Y, - OUT15 => AMR4Z, - OUT16 => Temp3, - OUT17 => Temp4, - FSynch => DC_ADC_FSynch - ); - LF1 <= LF1cst; - LF2 <= LF2cst; - LF3 <= LF3cst; - END GENERATE; +CDS0 : entity work.CrossDomainSyncGen +Port map( + reset => reset, + ClockS => sclk, + ClockF => clk, + SyncSignal => CrossDomainSync +); -send_CST_DATA : IF (SEND_CONSTANT_DATA = 1) and (SEND_MINF_VALUE = 0) GENERATE - AMR1X <= AMR1Xcst; - AMR1Y <= AMR1Ycst; - AMR1Z <= AMR1Zcst; - AMR2X <= AMR2Xcst; - AMR2Y <= AMR2Ycst; - AMR2Z <= AMR2Zcst; - Temp1 <= Temp1cst; - Temp2 <= Temp2cst; - AMR3X <= AMR3Xcst; - AMR3Y <= AMR3Ycst; - AMR3Z <= AMR3Zcst; - AMR4X <= AMR4Xcst; - AMR4Y <= AMR4Ycst; - AMR4Z <= AMR4Zcst; - Temp3 <= Temp3cst; - Temp4 <= Temp4cst; - - LF1 <= LF1cst; - LF2 <= LF2cst; - LF3 <= LF3cst; - END GENERATE; - - +TM : entity work.TM_MODULE +generic map( + WordSize => WordSize, + WordCnt => WordCnt, + MinFCount => MinFCount +) +port map( + + reset =>reset, + clk =>clk, + MinF =>MinF, + MajF =>MajF, + sclk =>sclk, + gate =>gate, + data =>data_int, + WordClk =>WordClk, -send_minF_valuelbl : IF (SEND_CONSTANT_DATA = 1) and (SEND_MINF_VALUE = 1) GENERATE - AMR1X <= X"000" & "000" & std_logic_vector(TO_UNSIGNED(MinFCnt,9)); - AMR1Y <= X"000" & "000" & std_logic_vector(TO_UNSIGNED(MinFCnt,9)); - AMR1Z <= X"000" & "000" & std_logic_vector(TO_UNSIGNED(MinFCnt,9)); - AMR2X <= X"000" & "000" & std_logic_vector(TO_UNSIGNED(MinFCnt,9)); - AMR2Y <= X"000" & "000" & std_logic_vector(TO_UNSIGNED(MinFCnt,9)); - AMR2Z <= X"000" & "000" & std_logic_vector(TO_UNSIGNED(MinFCnt,9)); - Temp1 <= X"000" & "000" & std_logic_vector(TO_UNSIGNED(MinFCnt,9)); - Temp2 <= X"000" & "000" & std_logic_vector(TO_UNSIGNED(MinFCnt,9)); - AMR3X <= X"000" & "000" & std_logic_vector(TO_UNSIGNED(MinFCnt,9)); - AMR3Y <= X"000" & "000" & std_logic_vector(TO_UNSIGNED(MinFCnt,9)); - AMR3Z <= X"000" & "000" & std_logic_vector(TO_UNSIGNED(MinFCnt,9)); - AMR4X <= X"000" & "000" & std_logic_vector(TO_UNSIGNED(MinFCnt,9)); - AMR4Y <= X"000" & "000" & std_logic_vector(TO_UNSIGNED(MinFCnt,9)); - AMR4Z <= X"000" & "000" & std_logic_vector(TO_UNSIGNED(MinFCnt,9)); - Temp3 <= X"000" & "000" & std_logic_vector(TO_UNSIGNED(MinFCnt,9)); - Temp4 <= X"000" & "000" & std_logic_vector(TO_UNSIGNED(MinFCnt,9)); - - LF1 <= LF1cst; - LF2 <= LF2cst; - LF3 <= LF3cst; - END GENERATE; + LF1 => LF1, + LF2 => LF2, + LF3 => LF3, + + AMR1X => AMR1X, + AMR1Y => AMR1Y, + AMR1Z => AMR1Z, + + AMR2X => AMR2X, + AMR2Y => AMR2Y, + AMR2Z => AMR2Z, + + AMR3X => AMR3X, + AMR3Y => AMR3Y, + AMR3Z => AMR3Z, + + AMR4X => AMR4X, + AMR4Y => AMR4Y, + AMR4Z => AMR4Z, + + Temp1 => Temp1, + Temp2 => Temp2, + Temp3 => Temp3, + Temp4 => Temp4 +); + +DC_ADC0:entity work.DC_ACQ_TOP +generic map ( + WordSize => WordSize, + WordCnt => WordCnt, + MinFCount => MinFCount, + EnableSR => 0, + FakeADC => 1 +) +port map( -LF_SMPL_CLK0 : entity work.LF_SMPL_CLK -port map( - Wclck => WordClk, - MinF => MinF, - SMPL_CLK => LF_ADC_SmplClk + reset => reset, + clk => clk, + SyncSig => CrossDomainSync, + minorF => minF, + majorF => majF, + sclk => sclk, + WordClk => WordClk, + + DC_ADC_Sclk => DC_ADC_Sclk, + DC_ADC_IN => DC_ADC_IN, + DC_ADC_ClkDiv => DC_ADC_ClkDiv, + DC_ADC_FSynch => DC_ADC_FSynch, + SET_RESET0 => SET_RESET0, + SET_RESET1 => SET_RESET1, + + AMR1X => AMR1X, + AMR1Y => AMR1Y, + AMR1Z => AMR1Z, + + AMR2X => AMR2X, + AMR2Y => AMR2Y, + AMR2Z => AMR2Z, + + AMR3X => AMR3X, + AMR3Y => AMR3Y, + AMR3Z => AMR3Z, + + AMR4X => AMR4X, + AMR4Y => AMR4Y, + AMR4Z => AMR4Z, + + Temp1 => Temp1, + Temp2 => Temp2, + Temp3 => Temp3, + Temp4 => Temp4 ); +LF: entity work.LF_ACQ_TOP +generic map( + WordSize => WordSize, + WordCnt => WordCnt, + MinFCount => MinFCount, + CstDATA => 0 +) +port map( -process(clk) -variable SelVar : integer range 0 to 1; -begin - if clk'event and clk ='1' then - Decoder: FOR i IN 0 to FramePlacerCount-1 loop - if FramePlacerFlags(i) = '1' then - SelVar := i; - end if; - END loop Decoder; - Sel <= SelVar; - end if; -end process; - + reset => reset, + clk => clk, + SyncSig => CrossDomainSync, + minorF => minF, + majorF => majF, + sclk => sclk, + WordClk => WordClk, + LF_SCK => LF_SCK, + LF_CNV => LF_CNV, + LF_SDO1 => LF_SDO1, + LF_SDO2 => LF_SDO2, + LF_SDO3 => LF_SDO3, + LF1 => LF1, + LF2 => LF2, + LF3 => LF3 +); end rtl; diff --git a/lib/lpp/lpp_ad_Conv/AD7688_drvr.vhd b/lib/lpp/lpp_ad_Conv/AD7688_drvr.vhd --- a/lib/lpp/lpp_ad_Conv/AD7688_drvr.vhd +++ b/lib/lpp/lpp_ad_Conv/AD7688_drvr.vhd @@ -40,7 +40,7 @@ Port( enable : in std_logic; --! Negative enable smplClk : in STD_LOGIC; --! Sampling clock DataReady : out std_logic; --! New sample available - smpout : out Samples_out(ChanelCount-1 downto 0); --! Samples + smpout : out Samples(ChanelCount-1 downto 0); --! Samples AD_in : in AD7688_in(ChanelCount-1 downto 0); --! Input signals for ADC see lpp.lpp_ad_conv AD_out : out AD7688_out --! Output signals for ADC see lpp.lpp_ad_conv ); diff --git a/lib/lpp/lpp_ad_Conv/AD7688_spi_if.vhd b/lib/lpp/lpp_ad_Conv/AD7688_spi_if.vhd --- a/lib/lpp/lpp_ad_Conv/AD7688_spi_if.vhd +++ b/lib/lpp/lpp_ad_Conv/AD7688_spi_if.vhd @@ -32,13 +32,13 @@ entity AD7688_spi_if is cnv : in STD_LOGIC; DataReady : out std_logic; sdi : in AD7688_in(ChanelCount-1 downto 0); - smpout : out Samples_out(ChanelCount-1 downto 0) + smpout : out Samples(ChanelCount-1 downto 0) ); end AD7688_spi_if; architecture ar_AD7688_spi_if of AD7688_spi_if is -signal shift_reg : Samples_out(ChanelCount-1 downto 0); +signal shift_reg : Samples(ChanelCount-1 downto 0); signal i : integer range 0 to 16 :=0; signal cnv_reg : std_logic := '0'; diff --git a/lib/lpp/lpp_ad_Conv/dual_ADS1278_drvr.vhd b/lib/lpp/lpp_ad_Conv/dual_ADS1278_drvr.vhd --- a/lib/lpp/lpp_ad_Conv/dual_ADS1278_drvr.vhd +++ b/lib/lpp/lpp_ad_Conv/dual_ADS1278_drvr.vhd @@ -10,13 +10,17 @@ use lpp.general_purpose.all; -entity DUAL_ADS1278_DRIVER is +entity DUAL_ADS1278_DRIVER is +generic +( + SCLKDIV : integer range 2 to 256 :=16 +); port( - Clk : in std_logic; - reset : in std_logic; - SpiClk : out std_logic; - DIN : in std_logic_vector(1 downto 0); - SmplClk : in std_logic; + Clk : in std_logic; + reset : in std_logic; + SpiClk : out std_logic; + DIN : in std_logic_vector(1 downto 0); + SmplClk : in std_logic; OUT00 : out std_logic_vector(23 downto 0); OUT01 : out std_logic_vector(23 downto 0); OUT02 : out std_logic_vector(23 downto 0); @@ -33,7 +37,7 @@ port( OUT15 : out std_logic_vector(23 downto 0); OUT16 : out std_logic_vector(23 downto 0); OUT17 : out std_logic_vector(23 downto 0); - FSynch : out std_logic + FSynch : out std_logic ); end DUAL_ADS1278_DRIVER; @@ -43,10 +47,9 @@ end DUAL_ADS1278_DRIVER; architecture ar_DUAL_ADS1278_DRIVER of DUAL_ADS1278_DRIVER is - -signal Vec00,Vec01,Vec02,Vec03,Vec04,Vec05,Vec06,Vec07,Vec10,Vec11,Vec12,Vec13,Vec14,Vec15,Vec16,Vec17 : std_logic_vector(23 downto 0); +signal ShiftGeg0,ShiftGeg1 : std_logic_vector((8*24)-1 downto 0); signal SmplClk_Reg : std_logic:= '0'; -signal N : integer range 0 to 23*8 := 0; +signal N : integer range 0 to (24*8) := 0; signal SPI_CLk : std_logic; signal SmplClk_clkd : std_logic:= '0'; @@ -54,97 +57,24 @@ begin CLKDIV0 : Clk_Divider2 -generic map(16) +generic map(SCLKDIV) port map(Clk,SPI_CLk); - -FSynch <= SmplClk_clkd; -SpiClk <= SPI_CLk; +SpiClk <= not SPI_CLk; process(reset,SPI_CLk) begin if reset = '0' then - Vec00 <= (others => '0'); - Vec01 <= (others => '0'); - Vec02 <= (others => '0'); - Vec03 <= (others => '0'); - Vec04 <= (others => '0'); - Vec05 <= (others => '0'); - Vec06 <= (others => '0'); - Vec07 <= (others => '0'); - - Vec10 <= (others => '0'); - Vec11 <= (others => '0'); - Vec12 <= (others => '0'); - Vec13 <= (others => '0'); - Vec14 <= (others => '0'); - Vec15 <= (others => '0'); - Vec16 <= (others => '0'); - Vec17 <= (others => '0'); - N <= 0; + ShiftGeg0 <= (others => '0'); + ShiftGeg1 <= (others => '0'); + N <= 0; elsif SPI_CLk'event and SPI_CLk = '1' then --- SmplClk_clkd <= SmplClk; --- SmplClk_Reg <= SmplClk_clkd; - --if ((SmplClk_clkd = '1' and SmplClk_Reg = '0') or (N /= 0)) then - if ((SmplClk_clkd = '1' and SmplClk_Reg = '0') or (N /= 0)) then - --Vec0(0) <= DIN(0); - --Vec1(0) <= DIN(1); - --Vec2(0) <= DIN(2); - --Vec3(0) <= DIN(3); - --Vec0(23 downto 1) <= Vec0(22 downto 0); - --Vec1(23 downto 1) <= Vec1(22 downto 0); - --Vec2(23 downto 1) <= Vec2(22 downto 0); - --Vec3(23 downto 1) <= Vec3(22 downto 0); - Vec00(0) <= DIN(0); - Vec00(23 downto 1) <= Vec00(22 downto 0); - Vec01(0) <= Vec00(23); - - Vec01(23 downto 1) <= Vec01(22 downto 0); - Vec02(0) <= Vec01(23); - - Vec02(23 downto 1) <= Vec02(22 downto 0); - Vec03(0) <= Vec02(23); - - Vec03(23 downto 1) <= Vec03(22 downto 0); - Vec04(0) <= Vec03(23); - - Vec04(23 downto 1) <= Vec04(22 downto 0); - Vec05(0) <= Vec04(23); - - Vec05(23 downto 1) <= Vec05(22 downto 0); - Vec06(0) <= Vec05(23); - - Vec06(23 downto 1) <= Vec06(22 downto 0); - Vec07(0) <= Vec06(23); - - Vec07(23 downto 1) <= Vec07(22 downto 0); - - - Vec10(0) <= DIN(1); - Vec10(23 downto 1) <= Vec10(22 downto 0); - Vec11(0) <= Vec10(23); - - Vec11(23 downto 1) <= Vec11(22 downto 0); - Vec12(0) <= Vec11(23); - - Vec12(23 downto 1) <= Vec12(22 downto 0); - Vec13(0) <= Vec12(23); - - Vec13(23 downto 1) <= Vec13(22 downto 0); - Vec14(0) <= Vec13(23); - - Vec14(23 downto 1) <= Vec14(22 downto 0); - Vec15(0) <= Vec14(23); - - Vec15(23 downto 1) <= Vec15(22 downto 0); - Vec16(0) <= Vec15(23); - - Vec16(23 downto 1) <= Vec16(22 downto 0); - Vec17(0) <= Vec16(23); - - Vec17(23 downto 1) <= Vec17(22 downto 0); - if N = (23*8) then + FSynch <= SmplClk; + if ((SmplClk_clkd = '1' and SmplClk_Reg = '0') or (N /= 0)) then + ShiftGeg0((8*24)-1 downto 0) <= ShiftGeg0((8*24)-2 downto 0) & DIN(0); + ShiftGeg1((8*24)-1 downto 0) <= ShiftGeg1((8*24)-2 downto 0) & DIN(1); + if N = ((24*8)-1) then N <= 0; else N <= N+1; @@ -163,27 +93,45 @@ begin end process; -process(SPI_CLk) -begin - if SPI_CLk'event and SPI_CLk ='1' then +process(clk,reset) +begin + if reset = '0' then + OUT00 <= (others => '0'); + OUT01 <= (others => '0'); + OUT02 <= (others => '0'); + OUT03 <= (others => '0'); + OUT04 <= (others => '0'); + OUT05 <= (others => '0'); + OUT06 <= (others => '0'); + OUT07 <= (others => '0'); + + OUT10 <= (others => '0'); + OUT11 <= (others => '0'); + OUT12 <= (others => '0'); + OUT13 <= (others => '0'); + OUT14 <= (others => '0'); + OUT15 <= (others => '0'); + OUT16 <= (others => '0'); + OUT17 <= (others => '0'); + elsif clk'event and clk ='1' then if N = 0 then - OUT00 <= Vec00; - OUT01 <= Vec01; - OUT02 <= Vec02; - OUT03 <= Vec03; - OUT04 <= Vec04; - OUT05 <= Vec05; - OUT06 <= Vec06; - OUT07 <= Vec07; + OUT00 <= ShiftGeg0((24*1)-1 downto (24*(1-1))); + OUT01 <= ShiftGeg0((24*2)-1 downto (24*(2-1))); + OUT02 <= ShiftGeg0((24*3)-1 downto (24*(3-1))); + OUT03 <= ShiftGeg0((24*4)-1 downto (24*(4-1))); + OUT04 <= ShiftGeg0((24*5)-1 downto (24*(5-1))); + OUT05 <= ShiftGeg0((24*6)-1 downto (24*(6-1))); + OUT06 <= ShiftGeg0((24*7)-1 downto (24*(7-1))); + OUT07 <= ShiftGeg0((24*8)-1 downto (24*(8-1))); - OUT10 <= Vec10; - OUT11 <= Vec11; - OUT12 <= Vec12; - OUT13 <= Vec13; - OUT14 <= Vec14; - OUT15 <= Vec15; - OUT16 <= Vec16; - OUT17 <= Vec17; + OUT10 <= ShiftGeg1((24*1)-1 downto (24*(1-1))); + OUT11 <= ShiftGeg1((24*2)-1 downto (24*(2-1))); + OUT12 <= ShiftGeg1((24*3)-1 downto (24*(3-1))); + OUT13 <= ShiftGeg1((24*4)-1 downto (24*(4-1))); + OUT14 <= ShiftGeg1((24*5)-1 downto (24*(5-1))); + OUT15 <= ShiftGeg1((24*6)-1 downto (24*(6-1))); + OUT16 <= ShiftGeg1((24*7)-1 downto (24*(7-1))); + OUT17 <= ShiftGeg1((24*8)-1 downto (24*(8-1))); end if; end if; end process; diff --git a/lib/lpp/lpp_ad_Conv/lpp_ad_Conv.vhd b/lib/lpp/lpp_ad_Conv/lpp_ad_Conv.vhd --- a/lib/lpp/lpp_ad_Conv/lpp_ad_Conv.vhd +++ b/lib/lpp/lpp_ad_Conv/lpp_ad_Conv.vhd @@ -35,18 +35,18 @@ PACKAGE lpp_ad_conv IS --CONSTANT ADS7886 : INTEGER := 1; - --TYPE AD7688_out IS - --RECORD - -- CNV : STD_LOGIC; - -- SCK : STD_LOGIC; - --END RECORD; + TYPE AD7688_out IS + RECORD + CNV : STD_LOGIC; + SCK : STD_LOGIC; + END RECORD; - --TYPE AD7688_in_element IS - --RECORD - -- SDI : STD_LOGIC; - --END RECORD; + TYPE AD7688_in_element IS + RECORD + SDI : STD_LOGIC; + END RECORD; - --TYPE AD7688_in IS ARRAY(NATURAL RANGE <>) OF AD7688_in_element; + TYPE AD7688_in IS ARRAY(NATURAL RANGE <>) OF AD7688_in_element; TYPE Samples IS ARRAY(NATURAL RANGE <>) OF STD_LOGIC_VECTOR(15 DOWNTO 0); @@ -68,30 +68,30 @@ PACKAGE lpp_ad_conv IS sample_val : OUT STD_LOGIC); END COMPONENT; - --COMPONENT AD7688_drvr IS - -- GENERIC(ChanelCount : INTEGER; - -- clkkHz : INTEGER); - -- PORT (clk : IN STD_LOGIC; - -- rstn : IN STD_LOGIC; - -- enable : IN STD_LOGIC; - -- smplClk : IN STD_LOGIC; - -- DataReady : OUT STD_LOGIC; - -- smpout : OUT Samples_out(ChanelCount-1 DOWNTO 0); - -- AD_in : IN AD7688_in(ChanelCount-1 DOWNTO 0); - -- AD_out : OUT AD7688_out); - --END COMPONENT; + COMPONENT AD7688_drvr IS + GENERIC(ChanelCount : INTEGER; + clkkHz : INTEGER); + PORT (clk : IN STD_LOGIC; + rstn : IN STD_LOGIC; + enable : IN STD_LOGIC; + smplClk : IN STD_LOGIC; + DataReady : OUT STD_LOGIC; + smpout : OUT Samples(ChanelCount-1 DOWNTO 0); + AD_in : IN AD7688_in(ChanelCount-1 DOWNTO 0); + AD_out : OUT AD7688_out); + END COMPONENT; - --COMPONENT AD7688_spi_if IS - -- GENERIC(ChanelCount : INTEGER); - -- PORT(clk : IN STD_LOGIC; - -- reset : IN STD_LOGIC; - -- cnv : IN STD_LOGIC; - -- DataReady : OUT STD_LOGIC; - -- sdi : IN AD7688_in(ChanelCount-1 DOWNTO 0); - -- smpout : OUT Samples_out(ChanelCount-1 DOWNTO 0) - -- ); - --END COMPONENT; + COMPONENT AD7688_spi_if IS + GENERIC(ChanelCount : INTEGER); + PORT(clk : IN STD_LOGIC; + reset : IN STD_LOGIC; + cnv : IN STD_LOGIC; + DataReady : OUT STD_LOGIC; + sdi : IN AD7688_in(ChanelCount-1 DOWNTO 0); + smpout : OUT Samples(ChanelCount-1 DOWNTO 0) + ); + END COMPONENT; --COMPONENT lpp_apb_ad_conv