lpp_memory.vhd
278 lines
| 8.9 KiB
| text/x-vhdl
|
VhdlLexer
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r53 | ------------------------------------------------------------------------------ | ||
-- This file is a part of the LPP VHDL IP LIBRARY | ||||
-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS | ||||
-- | ||||
-- This program is free software; you can redistribute it and/or modify | ||||
-- it under the terms of the GNU General Public License as published by | ||||
-- the Free Software Foundation; either version 3 of the License, or | ||||
-- (at your option) any later version. | ||||
-- | ||||
-- This program is distributed in the hope that it will be useful, | ||||
-- but WITHOUT ANY WARRANTY; without even the implied warranty of | ||||
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||||
-- GNU General Public License for more details. | ||||
-- | ||||
-- You should have received a copy of the GNU General Public License | ||||
-- along with this program; if not, write to the Free Software | ||||
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | ||||
------------------------------------------------------------------------------ | ||||
-- Author : Martin Morlot | ||||
-- Mail : martin.morlot@lpp.polytechnique.fr | ||||
------------------------------------------------------------------------------ | ||||
library ieee; | ||||
use ieee.std_logic_1164.all; | ||||
library grlib; | ||||
use grlib.amba.all; | ||||
use std.textio.all; | ||||
library lpp; | ||||
use lpp.lpp_amba.all; | ||||
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r85 | library gaisler; | ||
use gaisler.misc.all; | ||||
use gaisler.memctrl.all; | ||||
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r53 | |||
--! Package contenant tous les programmes qui forment le composant int�gr� dans le l�on | ||||
package lpp_memory is | ||||
--===========================================================| | ||||
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r65 | --=================== FIFO Compl�te =========================| | ||
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r53 | --===========================================================| | ||
component APB_FIFO is | ||||
generic ( | ||||
pindex : integer := 0; | ||||
paddr : integer := 0; | ||||
pmask : integer := 16#fff#; | ||||
pirq : integer := 0; | ||||
abits : integer := 8; | ||||
Data_sz : integer := 16; | ||||
Addr_sz : integer := 8; | ||||
addr_max_int : integer := 256); | ||||
port ( | ||||
clk : in std_logic; | ||||
rst : in std_logic; | ||||
apbi : in apb_slv_in_type; | ||||
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r79 | Full : out std_logic; | ||
Empty : out std_logic; | ||||
WR : out std_logic; | ||||
RE : out std_logic; | ||||
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r53 | apbo : out apb_slv_out_type | ||
); | ||||
end component; | ||||
component ApbDriver is | ||||
generic ( | ||||
pindex : integer := 0; | ||||
paddr : integer := 0; | ||||
pmask : integer := 16#fff#; | ||||
pirq : integer := 0; | ||||
abits : integer := 8; | ||||
LPP_DEVICE : integer; | ||||
Data_sz : integer := 16; | ||||
Addr_sz : integer := 8; | ||||
addr_max_int : integer := 256); | ||||
port ( | ||||
clk : in std_logic; | ||||
rst : in std_logic; | ||||
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r79 | ReadEnable : out std_logic; | ||
WriteEnable : out std_logic; | ||||
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r53 | FlagEmpty : in std_logic; | ||
FlagFull : in std_logic; | ||||
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r75 | ReUse : out std_logic; | ||
Lock : out std_logic; | ||||
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r53 | DataIn : out std_logic_vector(Data_sz-1 downto 0); | ||
DataOut : in std_logic_vector(Data_sz-1 downto 0); | ||||
AddrIn : in std_logic_vector(Addr_sz-1 downto 0); | ||||
AddrOut : in std_logic_vector(Addr_sz-1 downto 0); | ||||
apbi : in apb_slv_in_type; | ||||
apbo : out apb_slv_out_type | ||||
); | ||||
end component; | ||||
component Top_FIFO is | ||||
generic( | ||||
Data_sz : integer := 16; | ||||
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r62 | Addr_sz : integer := 8; | ||
addr_max_int : integer := 256 | ||||
); | ||||
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r53 | port( | ||
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r65 | clk,raz : in std_logic; | ||
flag_RE : in std_logic; | ||||
flag_WR : in std_logic; | ||||
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r70 | ReUse : in std_logic; | ||
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r75 | Lock : in std_logic; | ||
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r65 | Data_in : in std_logic_vector(Data_sz-1 downto 0); | ||
Addr_RE : out std_logic_vector(addr_sz-1 downto 0); | ||||
Addr_WR : out std_logic_vector(addr_sz-1 downto 0); | ||||
full : out std_logic; | ||||
empty : out std_logic; | ||||
Data_out : out std_logic_vector(Data_sz-1 downto 0) | ||||
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r53 | ); | ||
end component; | ||||
component Fifo_Read is | ||||
generic( | ||||
Addr_sz : integer := 8; | ||||
addr_max_int : integer := 256); | ||||
port( | ||||
clk : in std_logic; | ||||
raz : in std_logic; | ||||
flag_RE : in std_logic; | ||||
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r70 | ReUse : in std_logic; | ||
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r53 | Waddr : in std_logic_vector(addr_sz-1 downto 0); | ||
empty : out std_logic; | ||||
Raddr : out std_logic_vector(addr_sz-1 downto 0) | ||||
); | ||||
end component; | ||||
component Fifo_Write is | ||||
generic( | ||||
Addr_sz : integer := 8; | ||||
addr_max_int : integer := 256); | ||||
port( | ||||
clk : in std_logic; | ||||
raz : in std_logic; | ||||
flag_WR : in std_logic; | ||||
Raddr : in std_logic_vector(addr_sz-1 downto 0); | ||||
full : out std_logic; | ||||
Waddr : out std_logic_vector(addr_sz-1 downto 0) | ||||
); | ||||
end component; | ||||
component Link_Reg is | ||||
generic(Data_sz : integer := 16); | ||||
port( | ||||
clk,raz : in std_logic; | ||||
Data_one : in std_logic_vector(Data_sz-1 downto 0); | ||||
Data_two : in std_logic_vector(Data_sz-1 downto 0); | ||||
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r70 | ReUse : in std_logic; | ||
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r53 | flag_RE : in std_logic; | ||
flag_WR : in std_logic; | ||||
empty : in std_logic; | ||||
Data_out : out std_logic_vector(Data_sz-1 downto 0) | ||||
); | ||||
end component; | ||||
--===========================================================| | ||||
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r65 | --================= Demi FIFO Ecriture ======================| | ||
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r53 | --===========================================================| | ||
component APB_FifoWrite is | ||||
generic ( | ||||
pindex : integer := 0; | ||||
paddr : integer := 0; | ||||
pmask : integer := 16#fff#; | ||||
pirq : integer := 0; | ||||
abits : integer := 8; | ||||
Data_sz : integer := 16; | ||||
Addr_sz : integer := 8; | ||||
addr_max_int : integer := 256); | ||||
port ( | ||||
clk : in std_logic; | ||||
rst : in std_logic; | ||||
apbi : in apb_slv_in_type; | ||||
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r75 | ReadEnable : in std_logic; | ||
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r77 | Empty : out std_logic; | ||
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r79 | Full : out std_logic; | ||
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r75 | DATA : out std_logic_vector(Data_sz-1 downto 0); | ||
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r53 | apbo : out apb_slv_out_type | ||
); | ||||
end component; | ||||
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r75 | --component Top_FifoWrite is | ||
-- generic( | ||||
-- Data_sz : integer := 16; | ||||
-- Addr_sz : integer := 8; | ||||
-- addr_max_int : integer := 256); | ||||
-- port( | ||||
-- clk : in std_logic; | ||||
-- raz : in std_logic; | ||||
-- flag_RE : in std_logic; | ||||
-- flag_WR : in std_logic; | ||||
-- Data_in : in std_logic_vector(Data_sz-1 downto 0); | ||||
-- Raddr : in std_logic_vector(addr_sz-1 downto 0); | ||||
-- full : out std_logic; | ||||
-- empty : out std_logic; | ||||
-- Waddr : out std_logic_vector(addr_sz-1 downto 0); | ||||
-- Data_out : out std_logic_vector(Data_sz-1 downto 0) | ||||
-- ); | ||||
--end component; | ||||
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r53 | |||
--===========================================================| | ||||
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r65 | --================== Demi FIFO Lecture ======================| | ||
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r53 | --===========================================================| | ||
component APB_FifoRead is | ||||
generic ( | ||||
pindex : integer := 0; | ||||
paddr : integer := 0; | ||||
pmask : integer := 16#fff#; | ||||
pirq : integer := 0; | ||||
abits : integer := 8; | ||||
Data_sz : integer := 16; | ||||
Addr_sz : integer := 8; | ||||
addr_max_int : integer := 256); | ||||
port ( | ||||
clk : in std_logic; | ||||
rst : in std_logic; | ||||
apbi : in apb_slv_in_type; | ||||
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r77 | WriteEnable : in std_logic; | ||
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r79 | Full : out std_logic; | ||
Empty : out std_logic; | ||||
DATA : in std_logic_vector(Data_sz-1 downto 0); | ||||
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r53 | apbo : out apb_slv_out_type | ||
); | ||||
end component; | ||||
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r75 | --component Top_FifoRead is | ||
-- generic( | ||||
-- Data_sz : integer := 16; | ||||
-- Addr_sz : integer := 8; | ||||
-- addr_max_int : integer := 256); | ||||
-- port( | ||||
-- clk : in std_logic; | ||||
-- raz : in std_logic; | ||||
-- flag_RE : in std_logic; | ||||
-- flag_WR : in std_logic; | ||||
-- Data_in : in std_logic_vector(Data_sz-1 downto 0); | ||||
-- Waddr : in std_logic_vector(addr_sz-1 downto 0); | ||||
-- full : out std_logic; | ||||
-- empty : out std_logic; | ||||
-- Raddr : out std_logic_vector(addr_sz-1 downto 0); | ||||
-- Data_out : out std_logic_vector(Data_sz-1 downto 0) | ||||
-- ); | ||||
--end component; | ||||
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r53 | |||
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r84 | component ssram_plugin is | ||
generic (tech : integer := 0); | ||||
port | ||||
( | ||||
clk : in std_logic; | ||||
mem_ctrlr_o : in memory_out_type; | ||||
SSRAM_CLK : out std_logic; | ||||
nBWa : out std_logic; | ||||
nBWb : out std_logic; | ||||
nBWc : out std_logic; | ||||
nBWd : out std_logic; | ||||
nBWE : out std_logic; | ||||
nADSC : out std_logic; | ||||
nADSP : out std_logic; | ||||
nADV : out std_logic; | ||||
nGW : out std_logic; | ||||
nCE1 : out std_logic; | ||||
CE2 : out std_logic; | ||||
nCE3 : out std_logic; | ||||
nOE : out std_logic; | ||||
MODE : out std_logic; | ||||
ZZ : out std_logic | ||||
); | ||||
end component; | ||||
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r53 | end; | ||