HG_REPOSITORIES/LPP/INSTRUMENTATION/USERS/PELLION/VHD_Lib Files · lib/lpp/lpp_top_lfr/lpp_lfr_ms_reg_head.vhd

LFR EQM2

pellion - - Load All Authors

File last commit:

r478:656868b63e61 (MINI-LFR) WFP_MS-0-1-38 JC


                r620:c6d218df80ba

simu_with_Leon3

Download file

             lpp_lfr_ms_reg_head.vhd
        
                    106 lines
            
             | 2.9 KiB
            
                | text/x-vhdl
            
             |
                VhdlLexer
            
             / lib / lpp / lpp_top_lfr / lpp_lfr_ms_reg_head.vhd
          
                    History
                
                 |
                  Source
                 | Raw
                 |Copy content
                 |Copy permalink

        pellion
    
Add HeadReg for input fifo channel f1 (lpp_lfr_ms)

              r388
            
      LIBRARY ieee;

      USE ieee.std_logic_1164.ALL;

      ENTITY lpp_lfr_ms_reg_head IS

        PORT (

          clk  : IN STD_LOGIC;

          rstn : IN STD_LOGIC;

          in_wen   : IN STD_LOGIC;

          in_data  : IN STD_LOGIC_VECTOR(5*16-1 DOWNTO 0);

          in_full  : IN STD_LOGIC;

          in_empty : IN STD_LOGIC;

        pellion
    
modif ms_reg_head : add error signal

              r470
            
          out_write_error : OUT STD_LOGIC;

        pellion
    
Add HeadReg for input fifo channel f1 (lpp_lfr_ms)

              r388
            
          out_wen  : OUT STD_LOGIC;

          out_data : OUT STD_LOGIC_VECTOR(5*16-1 DOWNTO 0);

          out_full : OUT STD_LOGIC

          );

      END lpp_lfr_ms_reg_head;

      ARCHITECTURE Beh OF lpp_lfr_ms_reg_head IS

        pellion
    
modif ms_reg_head : un 2ème registre de tête

              r471
            
        TYPE fsm_state_reg_head IS (REG_EMPTY, REG_ONE_DATA, REG_FULL, REG_FULL_2);

        pellion
    
Add HeadReg for input fifo channel f1 (lpp_lfr_ms)

              r388
            
        SIGNAL fsm_state : fsm_state_reg_head;

        pellion
    
modif ms_reg_head : un 2ème registre de tête

              r471
            
        SIGNAL reg_data2 : STD_LOGIC_VECTOR(5*16-1 DOWNTO 0);

        SIGNAL reg_data  : STD_LOGIC_VECTOR(5*16-1 DOWNTO 0);

        pellion
    
Add HeadReg for input fifo channel f1 (lpp_lfr_ms)

              r388
            
        SIGNAL out_wen_s : STD_LOGIC;

        pellion
    
MINI-LFR 0.1.38 :...

              r478
            
        SIGNAL in_full_s : STD_LOGIC;

        pellion
    
Add HeadReg for input fifo channel f1 (lpp_lfr_ms)

              r388
            
      BEGIN  -- Beh

        PROCESS (clk, rstn)

        BEGIN

          IF rstn = '0' THEN

        pellion
    
modif ms_reg_head : un 2ème registre de tête

              r471
            
            fsm_state       <= REG_EMPTY;

            reg_data        <= (OTHERS => '0');

            reg_data2       <= (OTHERS => '0');

            out_wen_s       <= '1';

        pellion
    
modif ms_reg_head : add error signal

              r470
            
            out_write_error <= '0';

        pellion
    
MINI-LFR 0.1.38 :...

              r478
            
            in_full_s <= '0';

        pellion
    
Add HeadReg for input fifo channel f1 (lpp_lfr_ms)

              r388
            
          ELSIF clk'event AND clk = '1' THEN

        pellion
    
MINI-LFR 0.1.38 :...

              r478
            
            in_full_s <= in_full;

        pellion
    
Add HeadReg for input fifo channel f1 (lpp_lfr_ms)

              r388
            
            out_wen_s <= '1';

        pellion
    
modif ms_reg_head : add error signal

              r470
            
            out_write_error <= '0';      

        pellion
    
Add HeadReg for input fifo channel f1 (lpp_lfr_ms)

              r388
            
            CASE fsm_state IS

              WHEN REG_EMPTY =>

                reg_data <= in_data;

        pellion
    
MINI-LFR 0.1.38 :...

              r478
            
                IF in_wen = '0' AND in_full_s = '1' THEN

        pellion
    
modif ms_reg_head : un 2ème registre de tête

              r471
            
                  fsm_state <= REG_ONE_DATA;

                END IF;

              WHEN REG_ONE_DATA =>

                reg_data2 <= in_data;

        pellion
    
MINI-LFR 0.1.38 :...

              r478
            
                IF in_wen = '0' AND in_full_s = '1' THEN

        pellion
    
Add HeadReg for input fifo channel f1 (lpp_lfr_ms)

              r388
            
                  fsm_state <= REG_FULL;

        pellion
    
modif ms_reg_head : un 2ème registre de tête

              r471
            
                ELSIF in_empty = '1' THEN

                  out_wen_s <= '0';

                  IF in_wen = '0' THEN

                    reg_data <= in_data;

                  ELSE

                    fsm_state <= REG_EMPTY;               

                  END IF;            

        pellion
    
Add HeadReg for input fifo channel f1 (lpp_lfr_ms)

              r388
            
                END IF;

        pellion
    
modif ms_reg_head : un 2ème registre de tête

              r471
            
        pellion
    
Add HeadReg for input fifo channel f1 (lpp_lfr_ms)

              r388
            
              WHEN REG_FULL =>

                IF in_empty = '1' THEN

                  out_wen_s <= '0';

                  IF in_wen = '0' THEN

        pellion
    
modif ms_reg_head : un 2ème registre de tête

              r471
            
                    reg_data2 <= in_data;

        pellion
    
Add HeadReg for input fifo channel f1 (lpp_lfr_ms)

              r388
            
                  ELSE

        pellion
    
modif ms_reg_head : un 2ème registre de tête

              r471
            
                    fsm_state <= REG_FULL_2;              

        pellion
    
Add HeadReg for input fifo channel f1 (lpp_lfr_ms)

              r388
            
                  END IF;

        pellion
    
modif ms_reg_head : add error signal

              r470
            
                ELSE

                  IF in_wen = '0' THEN

                    out_write_error <= '1';

                  END IF;

        pellion
    
Add HeadReg for input fifo channel f1 (lpp_lfr_ms)

              r388
            
                END IF;

        pellion
    
modif ms_reg_head : un 2ème registre de tête

              r471
            
              WHEN REG_FULL_2 =>

                out_wen_s <= '0';

                fsm_state <= REG_EMPTY;          

        pellion
    
Add HeadReg for input fifo channel f1 (lpp_lfr_ms)

              r388
            
              WHEN OTHERS => NULL;

            END CASE;

          END IF;

        END PROCESS;

        pellion
    
MINI-LFR 0.1.38 :...

              r478
            
        out_full <= '1' WHEN fsm_state = REG_FULL ELSE in_full_s;

        pellion
    
Add HeadReg for input fifo channel f1 (lpp_lfr_ms)

              r388
            
        pellion
    
modif ms_reg_head : un 2ème registre de tête

              r471
            
        out_data <= reg_data2 WHEN fsm_state = REG_FULL     ELSE

                    reg_data  WHEN fsm_state = REG_ONE_DATA ELSE

                    reg_data  WHEN fsm_state = REG_FULL_2 ELSE

                    in_data;

        pellion
    
Add HeadReg for input fifo channel f1 (lpp_lfr_ms)

              r388
            
        pellion
    
modif ms_reg_head : un 2ème registre de tête

              r471
            
        out_wen  <= '0' WHEN out_wen_s = '0'          ELSE

                    '1' WHEN fsm_state = REG_ONE_DATA ELSE

                    '1' WHEN fsm_state = REG_FULL     ELSE

        pellion
    
MINI-LFR 0.1.38 :...

              r478
            
                    '1' WHEN in_full_s = '1'          ELSE

                    in_wen;

        pellion
    
Add HeadReg for input fifo channel f1 (lpp_lfr_ms)

              r388
            
      END Beh;

	Site-wide shortcuts
/	Use quick search box
g h	Goto home page
g g	Goto my private gists page
g G	Goto my public gists page
g 0-9	Goto bookmarked items from 0-9
n r	New repository page
n g	New gist page

	Repositories
g s	Goto summary page
g c	Goto changelog page
g f	Goto files page
g F	Goto files page with file search activated
g p	Goto pull requests page
g o	Goto repository settings
g O	Goto repository access permissions settings
t s	Toggle sidebar on some pages

pellion Add HeadReg for input fifo channel f1 (lpp_lfr_ms)	r388	LIBRARY ieee;
		USE ieee.std_logic_1164.ALL;

		ENTITY lpp_lfr_ms_reg_head IS

		PORT (
		clk : IN STD_LOGIC;
		rstn : IN STD_LOGIC;

		in_wen : IN STD_LOGIC;
		in_data : IN STD_LOGIC_VECTOR(5*16-1 DOWNTO 0);
		in_full : IN STD_LOGIC;
		in_empty : IN STD_LOGIC;
pellion modif ms_reg_head : add error signal	r470
		out_write_error : OUT STD_LOGIC;
pellion Add HeadReg for input fifo channel f1 (lpp_lfr_ms)	r388
		out_wen : OUT STD_LOGIC;
		out_data : OUT STD_LOGIC_VECTOR(5*16-1 DOWNTO 0);
		out_full : OUT STD_LOGIC
		);

		END lpp_lfr_ms_reg_head;

		ARCHITECTURE Beh OF lpp_lfr_ms_reg_head IS
pellion modif ms_reg_head : un 2ème registre de tête	r471	TYPE fsm_state_reg_head IS (REG_EMPTY, REG_ONE_DATA, REG_FULL, REG_FULL_2);
pellion Add HeadReg for input fifo channel f1 (lpp_lfr_ms)	r388	SIGNAL fsm_state : fsm_state_reg_head;

pellion modif ms_reg_head : un 2ème registre de tête	r471	SIGNAL reg_data2 : STD_LOGIC_VECTOR(5*16-1 DOWNTO 0);
		SIGNAL reg_data : STD_LOGIC_VECTOR(5*16-1 DOWNTO 0);
pellion Add HeadReg for input fifo channel f1 (lpp_lfr_ms)	r388	SIGNAL out_wen_s : STD_LOGIC;
pellion MINI-LFR 0.1.38 :...	r478
		SIGNAL in_full_s : STD_LOGIC;
pellion Add HeadReg for input fifo channel f1 (lpp_lfr_ms)	r388	BEGIN -- Beh

		PROCESS (clk, rstn)
		BEGIN
		IF rstn = '0' THEN
pellion modif ms_reg_head : un 2ème registre de tête	r471	fsm_state <= REG_EMPTY;
		reg_data <= (OTHERS => '0');
		reg_data2 <= (OTHERS => '0');
		out_wen_s <= '1';
pellion modif ms_reg_head : add error signal	r470	out_write_error <= '0';
pellion MINI-LFR 0.1.38 :...	r478	in_full_s <= '0';
pellion Add HeadReg for input fifo channel f1 (lpp_lfr_ms)	r388	ELSIF clk'event AND clk = '1' THEN
pellion MINI-LFR 0.1.38 :...	r478	in_full_s <= in_full;

pellion Add HeadReg for input fifo channel f1 (lpp_lfr_ms)	r388	out_wen_s <= '1';
pellion modif ms_reg_head : add error signal	r470	out_write_error <= '0';
pellion Add HeadReg for input fifo channel f1 (lpp_lfr_ms)	r388	CASE fsm_state IS
		WHEN REG_EMPTY =>
		reg_data <= in_data;
pellion MINI-LFR 0.1.38 :...	r478	IF in_wen = '0' AND in_full_s = '1' THEN
pellion modif ms_reg_head : un 2ème registre de tête	r471	fsm_state <= REG_ONE_DATA;
		END IF;

		WHEN REG_ONE_DATA =>
		reg_data2 <= in_data;
pellion MINI-LFR 0.1.38 :...	r478	IF in_wen = '0' AND in_full_s = '1' THEN
pellion Add HeadReg for input fifo channel f1 (lpp_lfr_ms)	r388	fsm_state <= REG_FULL;
pellion modif ms_reg_head : un 2ème registre de tête	r471	ELSIF in_empty = '1' THEN
		out_wen_s <= '0';
		IF in_wen = '0' THEN
		reg_data <= in_data;
		ELSE
		fsm_state <= REG_EMPTY;
		END IF;
pellion Add HeadReg for input fifo channel f1 (lpp_lfr_ms)	r388	END IF;
pellion modif ms_reg_head : un 2ème registre de tête	r471
pellion Add HeadReg for input fifo channel f1 (lpp_lfr_ms)	r388	WHEN REG_FULL =>
		IF in_empty = '1' THEN
		out_wen_s <= '0';
		IF in_wen = '0' THEN
pellion modif ms_reg_head : un 2ème registre de tête	r471	reg_data2 <= in_data;
pellion Add HeadReg for input fifo channel f1 (lpp_lfr_ms)	r388	ELSE
pellion modif ms_reg_head : un 2ème registre de tête	r471	fsm_state <= REG_FULL_2;
pellion Add HeadReg for input fifo channel f1 (lpp_lfr_ms)	r388	END IF;
pellion modif ms_reg_head : add error signal	r470	ELSE
		IF in_wen = '0' THEN
		out_write_error <= '1';
		END IF;
pellion Add HeadReg for input fifo channel f1 (lpp_lfr_ms)	r388	END IF;
pellion modif ms_reg_head : un 2ème registre de tête	r471
		WHEN REG_FULL_2 =>
		out_wen_s <= '0';
		fsm_state <= REG_EMPTY;

pellion Add HeadReg for input fifo channel f1 (lpp_lfr_ms)	r388	WHEN OTHERS => NULL;
		END CASE;

		END IF;
		END PROCESS;

pellion MINI-LFR 0.1.38 :...	r478	out_full <= '1' WHEN fsm_state = REG_FULL ELSE in_full_s;
pellion Add HeadReg for input fifo channel f1 (lpp_lfr_ms)	r388
pellion modif ms_reg_head : un 2ème registre de tête	r471	out_data <= reg_data2 WHEN fsm_state = REG_FULL ELSE
		reg_data WHEN fsm_state = REG_ONE_DATA ELSE
		reg_data WHEN fsm_state = REG_FULL_2 ELSE
		in_data;
pellion Add HeadReg for input fifo channel f1 (lpp_lfr_ms)	r388
pellion modif ms_reg_head : un 2ème registre de tête	r471	out_wen <= '0' WHEN out_wen_s = '0' ELSE
		'1' WHEN fsm_state = REG_ONE_DATA ELSE
		'1' WHEN fsm_state = REG_FULL ELSE
pellion MINI-LFR 0.1.38 :...	r478	'1' WHEN in_full_s = '1' ELSE
		in_wen;
pellion Add HeadReg for input fifo channel f1 (lpp_lfr_ms)	r388
		END Beh;