##// END OF EJS Templates
HG_REPOSITORIES » LPP » INSTRUMENTATION » USERS » PELLION » VHD_Lib
RSS

Clone from http://pc-instru.lpp.polytechnique.fr:5000/VHD_Lib

modif ms_reg_head : un 2ème registre de tête
pellion -
r471:091d074c8108 JC
parent child
Show More
Show file before | Show file after | Hide comments
@@ -22,19 +22,21 ENTITY lpp_lfr_ms_reg_head IS
22 END lpp_lfr_ms_reg_head;
22 END lpp_lfr_ms_reg_head;
23
23
24 ARCHITECTURE Beh OF lpp_lfr_ms_reg_head IS
24 ARCHITECTURE Beh OF lpp_lfr_ms_reg_head IS
25 TYPE fsm_state_reg_head IS (REG_EMPTY, REG_FULL);
25 TYPE fsm_state_reg_head IS (REG_EMPTY, REG_ONE_DATA, REG_FULL, REG_FULL_2);
26 SIGNAL fsm_state : fsm_state_reg_head;
26 SIGNAL fsm_state : fsm_state_reg_head;
27
27
28 SIGNAL reg_data : STD_LOGIC_VECTOR(5*16-1 DOWNTO 0);
28 SIGNAL reg_data2 : STD_LOGIC_VECTOR(5*16-1 DOWNTO 0);
29 SIGNAL reg_data : STD_LOGIC_VECTOR(5*16-1 DOWNTO 0);
29 SIGNAL out_wen_s : STD_LOGIC;
30 SIGNAL out_wen_s : STD_LOGIC;
30 BEGIN -- Beh
31 BEGIN -- Beh
31
32
32 PROCESS (clk, rstn)
33 PROCESS (clk, rstn)
33 BEGIN
34 BEGIN
34 IF rstn = '0' THEN
35 IF rstn = '0' THEN
35 fsm_state <= REG_EMPTY;
36 fsm_state <= REG_EMPTY;
36 reg_data <= (OTHERS => '0');
37 reg_data <= (OTHERS => '0');
37 out_wen_s <= '1';
38 reg_data2 <= (OTHERS => '0');
39 out_wen_s <= '1';
38 out_write_error <= '0';
40 out_write_error <= '0';
39 ELSIF clk'event AND clk = '1' THEN
41 ELSIF clk'event AND clk = '1' THEN
40 out_wen_s <= '1';
42 out_wen_s <= '1';
@@ -43,21 +45,40 BEGIN -- Beh
43 WHEN REG_EMPTY =>
45 WHEN REG_EMPTY =>
44 reg_data <= in_data;
46 reg_data <= in_data;
45 IF in_wen = '0' AND in_full = '1' THEN
47 IF in_wen = '0' AND in_full = '1' THEN
48 fsm_state <= REG_ONE_DATA;
49 END IF;
50
51 WHEN REG_ONE_DATA =>
52 reg_data2 <= in_data;
53 IF in_wen = '0' AND in_full = '1' THEN
46 fsm_state <= REG_FULL;
54 fsm_state <= REG_FULL;
55 ELSIF in_empty = '1' THEN
56 out_wen_s <= '0';
57 IF in_wen = '0' THEN
58 reg_data <= in_data;
59 ELSE
60 fsm_state <= REG_EMPTY;
61 END IF;
47 END IF;
62 END IF;
63
48 WHEN REG_FULL =>
64 WHEN REG_FULL =>
49 IF in_empty = '1' THEN
65 IF in_empty = '1' THEN
50 out_wen_s <= '0';
66 out_wen_s <= '0';
51 IF in_wen = '0' THEN
67 IF in_wen = '0' THEN
52 reg_data <= in_data;
68 reg_data2 <= in_data;
53 ELSE
69 ELSE
54 fsm_state <= REG_EMPTY;
70 fsm_state <= REG_FULL_2;
55 END IF;
71 END IF;
56 ELSE
72 ELSE
57 IF in_wen = '0' THEN
73 IF in_wen = '0' THEN
58 out_write_error <= '1';
74 out_write_error <= '1';
59 END IF;
75 END IF;
60 END IF;
76 END IF;
77
78 WHEN REG_FULL_2 =>
79 out_wen_s <= '0';
80 fsm_state <= REG_EMPTY;
81
61 WHEN OTHERS => NULL;
82 WHEN OTHERS => NULL;
62 END CASE;
83 END CASE;
63
84
@@ -66,10 +87,14 BEGIN -- Beh
66
87
67 out_full <= '1' WHEN fsm_state = REG_FULL ELSE in_full;
88 out_full <= '1' WHEN fsm_state = REG_FULL ELSE in_full;
68
89
69 out_data <= reg_data WHEN fsm_state = REG_FULL ELSE in_data;
90 out_data <= reg_data2 WHEN fsm_state = REG_FULL ELSE
91 reg_data WHEN fsm_state = REG_ONE_DATA ELSE
92 reg_data WHEN fsm_state = REG_FULL_2 ELSE
93 in_data;
70
94
71 out_wen <= '0' WHEN out_wen_s = '0' ELSE
95 out_wen <= '0' WHEN out_wen_s = '0' ELSE
72 '1' WHEN fsm_state = REG_FULL ELSE
96 '1' WHEN fsm_state = REG_ONE_DATA ELSE
97 '1' WHEN fsm_state = REG_FULL ELSE
73 in_wen;
98 in_wen;
74
99
75 END Beh;
100 END Beh;
General Comments 0
You need to be logged in to leave comments. Login now