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modif ms_reg_head : un 2ème registre de tête
pellion -
r471:091d074c8108 JC
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@@ -22,9 +22,10 ENTITY lpp_lfr_ms_reg_head IS
22 22 END lpp_lfr_ms_reg_head;
23 23
24 24 ARCHITECTURE Beh OF lpp_lfr_ms_reg_head IS
25 TYPE fsm_state_reg_head IS (REG_EMPTY, REG_FULL);
25 TYPE fsm_state_reg_head IS (REG_EMPTY, REG_ONE_DATA, REG_FULL, REG_FULL_2);
26 26 SIGNAL fsm_state : fsm_state_reg_head;
27 27
28 SIGNAL reg_data2 : STD_LOGIC_VECTOR(5*16-1 DOWNTO 0);
28 29 SIGNAL reg_data : STD_LOGIC_VECTOR(5*16-1 DOWNTO 0);
29 30 SIGNAL out_wen_s : STD_LOGIC;
30 31 BEGIN -- Beh
@@ -34,6 +35,7 BEGIN -- Beh
34 35 IF rstn = '0' THEN
35 36 fsm_state <= REG_EMPTY;
36 37 reg_data <= (OTHERS => '0');
38 reg_data2 <= (OTHERS => '0');
37 39 out_wen_s <= '1';
38 40 out_write_error <= '0';
39 41 ELSIF clk'event AND clk = '1' THEN
@@ -43,21 +45,40 BEGIN -- Beh
43 45 WHEN REG_EMPTY =>
44 46 reg_data <= in_data;
45 47 IF in_wen = '0' AND in_full = '1' THEN
46 fsm_state <= REG_FULL;
48 fsm_state <= REG_ONE_DATA;
47 49 END IF;
48 WHEN REG_FULL =>
49 IF in_empty = '1' THEN
50
51 WHEN REG_ONE_DATA =>
52 reg_data2 <= in_data;
53 IF in_wen = '0' AND in_full = '1' THEN
54 fsm_state <= REG_FULL;
55 ELSIF in_empty = '1' THEN
50 56 out_wen_s <= '0';
51 57 IF in_wen = '0' THEN
52 58 reg_data <= in_data;
53 59 ELSE
54 60 fsm_state <= REG_EMPTY;
55 61 END IF;
62 END IF;
63
64 WHEN REG_FULL =>
65 IF in_empty = '1' THEN
66 out_wen_s <= '0';
67 IF in_wen = '0' THEN
68 reg_data2 <= in_data;
69 ELSE
70 fsm_state <= REG_FULL_2;
71 END IF;
56 72 ELSE
57 73 IF in_wen = '0' THEN
58 74 out_write_error <= '1';
59 75 END IF;
60 76 END IF;
77
78 WHEN REG_FULL_2 =>
79 out_wen_s <= '0';
80 fsm_state <= REG_EMPTY;
81
61 82 WHEN OTHERS => NULL;
62 83 END CASE;
63 84
@@ -66,9 +87,13 BEGIN -- Beh
66 87
67 88 out_full <= '1' WHEN fsm_state = REG_FULL ELSE in_full;
68 89
69 out_data <= reg_data WHEN fsm_state = REG_FULL ELSE in_data;
90 out_data <= reg_data2 WHEN fsm_state = REG_FULL ELSE
91 reg_data WHEN fsm_state = REG_ONE_DATA ELSE
92 reg_data WHEN fsm_state = REG_FULL_2 ELSE
93 in_data;
70 94
71 95 out_wen <= '0' WHEN out_wen_s = '0' ELSE
96 '1' WHEN fsm_state = REG_ONE_DATA ELSE
72 97 '1' WHEN fsm_state = REG_FULL ELSE
73 98 in_wen;
74 99
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