HG_REPOSITORIES/LPP/INSTRUMENTATION/USERS/PELLION/VHD_Lib Commit - r470:8e762460b97c

modif ms_reg_head : add error signal

pellion -

r470:8e762460b97c JC

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Context file:

r470:8e762460b97c

designs/MINI-LFR_WFP_MS/run.do +1 -1

lib/lpp/lpp_top_lfr/lpp_lfr_ms.vhd +4 -3

                   in_data  => sample_f1_wdata,
                   in_full  => sample_f1_full_head_in,
                   in_empty => sample_f1_empty_head_in,
+                  out_write_error => error_wen_f1,
                   out_wen  => sample_f1_wen_head_out,
                   out_data => sample_f1_wdata_head,
                   out_full => sample_f1_full_head_out);
                   almost_full => sample_f1_almost_full);
-              one_sample_f1_wen <= '0' WHEN sample_f1_wen_s = "11111" ELSE '1';
+              one_sample_f1_wen <= '0' WHEN sample_f1_wen_head = "11111" ELSE '1';
               PROCESS (clk, rstn)
               BEGIN  -- PROCESS
                 IF rstn = '0' THEN                  -- asynchronous reset (active low)
                   one_sample_f1_full <= '0';
-                  error_wen_f1       <= '0';
+                  --error_wen_f1       <= '0';
                 ELSIF clk'EVENT AND clk = '1' THEN  -- rising clock edge
                   IF sample_f1_full_head_out = '0' THEN
                     one_sample_f1_full <= '0';
                   ELSE
                     one_sample_f1_full <= '1';
                   END IF;
-                  error_wen_f1 <= one_sample_f1_wen AND one_sample_f1_full;
+                  --error_wen_f1 <= one_sample_f1_wen AND one_sample_f1_full;
                 END IF;
               END PROCESS;

lib/lpp/lpp_top_lfr/lpp_lfr_ms_reg_head.vhd +8 -1

                 in_data  : IN STD_LOGIC_VECTOR(5*16-1 DOWNTO 0);
                 in_full  : IN STD_LOGIC;
                 in_empty : IN STD_LOGIC;
+                out_write_error : OUT STD_LOGIC;
                 out_wen  : OUT STD_LOGIC;
                 out_data : OUT STD_LOGIC_VECTOR(5*16-1 DOWNTO 0);
                   fsm_state <= REG_EMPTY;
                   reg_data  <= (OTHERS => '0');
                   out_wen_s <= '1';
+                  out_write_error <= '0';
                 ELSIF clk'event AND clk = '1' THEN
                   out_wen_s <= '1';
+                  out_write_error <= '0';
                   CASE fsm_state IS
                     WHEN REG_EMPTY =>
                       reg_data <= in_data;
                         ELSE
                           fsm_state <= REG_EMPTY;
                         END IF;
+                      ELSE
+                        IF in_wen = '0' THEN
+                          out_write_error <= '1';
+                        END IF;
                       END IF;
                     WHEN OTHERS => NULL;
                   END CASE;

lib/lpp/lpp_top_lfr/lpp_lfr_pkg.vhd +1 0

                   in_data  : IN  STD_LOGIC_VECTOR(5*16-1 DOWNTO 0);
                   in_full  : IN  STD_LOGIC;
                   in_empty : IN  STD_LOGIC;
+                  out_write_error : OUT STD_LOGIC;
                   out_wen  : OUT STD_LOGIC;
                   out_data : OUT STD_LOGIC_VECTOR(5*16-1 DOWNTO 0);
                   out_full : OUT STD_LOGIC);

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