HG_REPOSITORIES/LPP/INSTRUMENTATION/USERS/PELLION/VHD_Lib Files · lib/lpp/lpp_memory/vhdlsyn.txt

MiniSpartan6:...

MiniSpartan6: added ftdi chip config to switch between UART and Async FIFO. added few WIP designs with either spwlight core, FIFO_deom IP... Libs: added SpaceWire Light IP (Works really well!) started design of ahb_ftdi_fifo -> same protocol than AHBUART but over FTDI's Async FIFO interface. This might lead to much faster transfers UP to 12MB/s.

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pellion Synthesis File Updated	r229	lpp_memory.vhd
		lpp_FIFO.vhd
pellion temp	r416	lpp_FIFO_4_Shared.vhd
		lpp_FIFO_control.vhd
		lpp_FIFO_4_Shared_headreg_latency_0.vhd
		lpp_FIFO_4_Shared_headreg_latency_1.vhd
Alexis Jeandet Added simple FX2LP driver to write in endpoint 6 in 8 bit mode.	r217	lppFIFOxN.vhd
pellion Fusion avec martin	r296
pellion temp	r416

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