##// END OF EJS Templates
HG_REPOSITORIES » LPP » INSTRUMENTATION » USERS » PELLION » VHD_Lib
RSS

Clone from http://pc-instru.lpp.polytechnique.fr:5000/VHD_Lib

Synthesis File Updated
pellion -
r229:8ff242376ddf JC
parent child
Show More
Show file before | Show file after | Hide comments
1 NO CONTENT: new file 100644, binary diff hidden
NO CONTENT: new file 100644, binary diff hidden
Show file before | Show file after | Hide comments
@@ -1,23 +1,23
1 ./amba_lcd_16x2_ctrlr
1 ./amba_lcd_16x2_ctrlr
2 ./dsp/iir_filter
3 ./dsp/lpp_downsampling
4 ./dsp/lpp_fft
5 ./general_purpose
2 ./general_purpose
6 ./general_purpose/lpp_AMR
3 ./general_purpose/lpp_AMR
7 ./general_purpose/lpp_balise
4 ./general_purpose/lpp_balise
8 ./general_purpose/lpp_delay
5 ./general_purpose/lpp_delay
6 ./lpp_amba
7 ./dsp/iir_filter
8 ./dsp/lpp_downsampling
9 ./dsp/lpp_fft
9 ./lfr_time_management
10 ./lfr_time_management
10 ./lpp_ad_Conv
11 ./lpp_ad_Conv
11 ./lpp_amba
12 ./lpp_bootloader
12 ./lpp_bootloader
13 ./lpp_cna
13 ./lpp_cna
14 ./lpp_demux
14 ./lpp_demux
15 ./lpp_dma
16 ./lpp_Header
15 ./lpp_Header
17 ./lpp_matrix
16 ./lpp_matrix
18 ./lpp_memory
17 ./lpp_memory
19 ./lpp_top_lfr
18 ./lpp_dma
20 ./lpp_uart
19 ./lpp_uart
21 ./lpp_usb
20 ./lpp_usb
22 ./lpp_waveform
21 ./lpp_waveform
23 ./Rocket_PCM_Encoder
22 ./lpp_top_lfr
23 ./lpp_Header
Show file before | Show file after | Hide comments
@@ -1,19 +1,8
1 APB_IIR_CEL.vhd
1 iir_filter.vhd
2 APB_IIR_Filter.vhd
3 FILTERcfg.vhd
2 FILTERcfg.vhd
4 FilterCTRLR.vhd
3 RAM.vhd
5 FILTER_RAM_CTRLR.vhd
4 RAM_CEL.vhd
6 FILTER.vhd
5 RAM_CTRLR_v2.vhd
7 IIR_CEL_CTRLR_v2_CONTROL.vhd
6 IIR_CEL_CTRLR_v2_CONTROL.vhd
8 IIR_CEL_CTRLR_v2_DATAFLOW.vhd
7 IIR_CEL_CTRLR_v2_DATAFLOW.vhd
9 IIR_CEL_CTRLR_v2.vhd
8 IIR_CEL_CTRLR_v2.vhd
10 IIR_CEL_CTRLR.vhd
11 IIR_CEL_FILTER.vhd
12 iir_filter.vhd
13 RAM_CEL_N.vhd
14 RAM_CEL.vhd
15 RAM_CTRLR2.vhd
16 RAM_CTRLR_v2.vhd
17 RAM.vhd
18 Top_Filtre_IIR.vhd
19 Top_IIR.vhd
Show file before | Show file after | Hide comments
@@ -1,11 +1,16
1 APB_FFT_half.vhd
1 lpp_fft.vhd
2 APB_FFT.vhd
2 actar.vhd
3 Driver_FFT.vhd
3 actram.vhd
4 FFTamont.vhd
4 CoreFFT.vhd
5 FFTaval.vhd
5 fft_components.vhd
6 FFT.vhd
6 fftDp.vhd
7 FFT.vhd.bak
7 fftSm.vhd
8 Flag_Extremum.vhd
8 primitives.vhd
9 Flag_Extremum.vhd.bak
9 twiddle.vhd
10 Linker_FFT.vhd
10 APB_FFT.vhd
11 lpp_fft.vhd
11 Driver_FFT.vhd
12 FFT.vhd
13 FFTamont.vhd
14 FFTaval.vhd
15 Flag_Extremum.vhd
16 Linker_FFT.vhd
Show file before | Show file after | Hide comments
@@ -1,28 +1,21
1 Adder_V0.vhd
1 general_purpose.vhd
2 Adder.vhd
3 ADDRcntr.vhd
2 ADDRcntr.vhd
4 ALU_V0.vhd
5 ALU_V0.vhd~
6 ALU.vhd
3 ALU.vhd
4 Adder.vhd
7 Clk_Divider2.vhd
5 Clk_Divider2.vhd
8 Clk_Divider2.vhd~
9 Clk_divider.vhd
6 Clk_divider.vhd
10 general_purpose.vhd
7 MAC.vhd
11 general_purpose.vhd~
12 MAC_CONTROLER.vhd
8 MAC_CONTROLER.vhd
13 MAC_MUX2.vhd
14 MAC_MUX.vhd
9 MAC_MUX.vhd
10 MAC_MUX2.vhd
15 MAC_REG.vhd
11 MAC_REG.vhd
16 MAC_V0.vhd
17 MAC.vhd
18 Multiplier.vhd
19 MUX2.vhd
12 MUX2.vhd
20 MUXN.vhd
13 MUXN.vhd
14 Multiplier.vhd
21 REG.vhd
15 REG.vhd
16 SYNC_FF.vhd
22 Shifter.vhd
17 Shifter.vhd
23 SYNC_FF.vhd
24 TwoComplementer.vhd
18 TwoComplementer.vhd
25 lpp_front_to_level.vhd
19 lpp_front_to_level.vhd
26 lpp_front_detection.vhd
20 lpp_front_detection.vhd
27 SYNC_VALID_BIT.vhd
21 SYNC_VALID_BIT.vhd
28
Show file before | Show file after | Hide comments
@@ -1,4 +1,4
1 apb_lfr_time_management.vhd
1 lpp_counter.vhd
2 lpp_counter.vhd
2 apb_lfr_time_management.vhd
3 lfr_time_management.vhd
3 lfr_time_management.vhd
4 lpp_lfr_time_management.vhd
4 lpp_lfr_time_management.vhd
Show file before | Show file after | Hide comments
@@ -50,6 +50,78 PACKAGE lpp_ad_conv IS
50
50
51 TYPE Samples IS ARRAY(NATURAL RANGE <>) OF STD_LOGIC_VECTOR(15 DOWNTO 0);
51 TYPE Samples IS ARRAY(NATURAL RANGE <>) OF STD_LOGIC_VECTOR(15 DOWNTO 0);
52
52
53 -----------------------------------------------------------------------------
54 -----------------------------------------------------------------------------
55 SUBTYPE Samples24 IS STD_LOGIC_VECTOR(23 DOWNTO 0);
56
57 SUBTYPE Samples16 IS STD_LOGIC_VECTOR(15 DOWNTO 0);
58
59 SUBTYPE Samples14 IS STD_LOGIC_VECTOR(13 DOWNTO 0);
60
61 SUBTYPE Samples12 IS STD_LOGIC_VECTOR(11 DOWNTO 0);
62
63 SUBTYPE Samples10 IS STD_LOGIC_VECTOR(9 DOWNTO 0);
64
65 SUBTYPE Samples8 IS STD_LOGIC_VECTOR(7 DOWNTO 0);
66
67 TYPE Samples24v IS ARRAY(NATURAL RANGE <>) OF Samples24;
68
69 TYPE Samples16v IS ARRAY(NATURAL RANGE <>) OF Samples16;
70
71 TYPE Samples14v IS ARRAY(NATURAL RANGE <>) OF Samples14;
72
73 TYPE Samples12v IS ARRAY(NATURAL RANGE <>) OF Samples12;
74
75 TYPE Samples10v IS ARRAY(NATURAL RANGE <>) OF Samples10;
76
77 TYPE Samples8v IS ARRAY(NATURAL RANGE <>) OF Samples8;
78
79 COMPONENT RHF1401_drvr IS
80 GENERIC(
81 ChanelCount : INTEGER := 8);
82 PORT (
83 cnv_clk : IN STD_LOGIC;
84 clk : IN STD_LOGIC;
85 rstn : IN STD_LOGIC;
86 ADC_data : IN Samples14;
87 --ADC_smpclk : OUT STD_LOGIC;
88 ADC_nOE : OUT STD_LOGIC_VECTOR(ChanelCount-1 DOWNTO 0);
89 sample : OUT Samples14v(ChanelCount-1 DOWNTO 0);
90 sample_val : OUT STD_LOGIC
91 );
92 END COMPONENT;
93
94 COMPONENT top_ad_conv_RHF1401
95 GENERIC (
96 ChanelCount : INTEGER;
97 ncycle_cnv_high : INTEGER := 79;
98 ncycle_cnv : INTEGER := 500);
99 PORT (
100 cnv_clk : IN STD_LOGIC;
101 cnv_rstn : IN STD_LOGIC;
102 cnv : OUT STD_LOGIC;
103 clk : IN STD_LOGIC;
104 rstn : IN STD_LOGIC;
105 ADC_data : IN Samples14;
106 ADC_nOE : OUT STD_LOGIC_VECTOR(ChanelCount-1 DOWNTO 0);
107 sample : OUT Samples14v(ChanelCount-1 DOWNTO 0);
108 sample_val : OUT STD_LOGIC);
109 END COMPONENT;
110
111 COMPONENT TestModule_RHF1401
112 GENERIC (
113 freq : INTEGER;
114 amplitude : INTEGER;
115 impulsion : INTEGER);
116 PORT (
117 ADC_smpclk : IN STD_LOGIC;
118 ADC_OEB_bar : IN STD_LOGIC;
119 ADC_data : OUT STD_LOGIC_VECTOR(13 DOWNTO 0));
120 END COMPONENT;
121
122 -----------------------------------------------------------------------------
123 -----------------------------------------------------------------------------
124
53 COMPONENT ADS7886_drvr
125 COMPONENT ADS7886_drvr
54 GENERIC (
126 GENERIC (
55 ChanelCount : INTEGER;
127 ChanelCount : INTEGER;
Show file before | Show file after | Hide comments
@@ -1,19 +1,4
1 AD7688_drvr_sync.vhd
2 AD7688_drvr.vhd
3 AD7688_drvr.vhd.orig
4 AD7688_spi_if.vhd
5 ADS1274_drvr.vhd
6 ADS1274_drvr.vhd~
7 ADS1278_drvr.vhd
8 ADS1278_drvr.vhd~
9 ADS7886_drvr.vhd
10 dual_ADS1278_drvr.vhd
11 dual_ADS1278_drvr.vhd~
12 lpp_ad_Conv.vhd
1 lpp_ad_Conv.vhd
13 lpp_ad_Conv.vhd~
14 lpp_ad_Conv.vhd.orig
15 lpp_apb_ad_conv.vhd
16 RHF1401.vhd
2 RHF1401.vhd
17 top_ad_conv_RHF1401.vhd
3 top_ad_conv_RHF1401.vhd
18 top_ad_conv.vhd
4 TestModule_RHF1401.vhd
19 WriteGen_ADC.vhd
Show file before | Show file after | Hide comments
@@ -6,34 +6,36
6 --=================================================================================
6 --=================================================================================
7
7
8
8
9 library ieee;
9 LIBRARY ieee;
10 use ieee.std_logic_1164.all;
10 USE ieee.std_logic_1164.ALL;
11 library grlib;
11 LIBRARY grlib;
12 use grlib.amba.all;
12 USE grlib.amba.ALL;
13 use std.textio.all;
13 USE std.textio.ALL;
14
14
15
15
16 package apb_devices_list is
16 PACKAGE apb_devices_list IS
17
17
18
18
19 constant VENDOR_LPP : amba_vendor_type := 16#19#;
19 CONSTANT VENDOR_LPP : amba_vendor_type := 16#19#;
20
21 constant ROCKET_TM : amba_device_type := 16#1#;
22 constant otherCore : amba_device_type := 16#2#;
23 constant LPP_SIMPLE_DIODE : amba_device_type := 16#3#;
24 constant LPP_MULTI_DIODE : amba_device_type := 16#4#;
25 constant LPP_LCD_CTRLR : amba_device_type := 16#5#;
26 constant LPP_UART : amba_device_type := 16#6#;
27 constant LPP_CNA : amba_device_type := 16#7#;
28 constant LPP_APB_ADC : amba_device_type := 16#8#;
29 constant LPP_CHENILLARD : amba_device_type := 16#9#;
30 constant LPP_IIR_CEL_FILTER : amba_device_type := 16#10#;
31 constant LPP_FIFO_PID : amba_device_type := 16#11#;
32 constant LPP_FFT : amba_device_type := 16#12#;
33 constant LPP_MATRIX : amba_device_type := 16#13#;
34 constant LPP_DELAY : amba_device_type := 16#14#;
35 constant LPP_USB : amba_device_type := 16#15#;
36 constant LPP_BALISE : amba_device_type := 16#16#;
37
20
21 CONSTANT ROCKET_TM : amba_device_type := 16#1#;
22 CONSTANT otherCore : amba_device_type := 16#2#;
23 CONSTANT LPP_SIMPLE_DIODE : amba_device_type := 16#3#;
24 CONSTANT LPP_MULTI_DIODE : amba_device_type := 16#4#;
25 CONSTANT LPP_LCD_CTRLR : amba_device_type := 16#5#;
26 CONSTANT LPP_UART : amba_device_type := 16#6#;
27 CONSTANT LPP_CNA : amba_device_type := 16#7#;
28 CONSTANT LPP_APB_ADC : amba_device_type := 16#8#;
29 CONSTANT LPP_CHENILLARD : amba_device_type := 16#9#;
30 CONSTANT LPP_IIR_CEL_FILTER : amba_device_type := 16#10#;
31 CONSTANT LPP_FIFO_PID : amba_device_type := 16#11#;
32 CONSTANT LPP_FFT : amba_device_type := 16#12#;
33 CONSTANT LPP_MATRIX : amba_device_type := 16#13#;
34 CONSTANT LPP_DELAY : amba_device_type := 16#14#;
35 CONSTANT LPP_USB : amba_device_type := 16#15#;
36 CONSTANT LPP_BALISE : amba_device_type := 16#16#;
37 CONSTANT LPP_DMA_TYPE : amba_device_type := 16#17#;
38 CONSTANT LPP_BOOTLOADER_TYPE : amba_device_type := 16#18#;
39 CONSTANT LPP_LFR : amba_device_type := 16#19#;
38
40
39 end;
41 END;
Show file before | Show file after | Hide comments
@@ -1,4 +1,2
1 apb_devices_list.vhd
1 apb_devices_list.vhd
2 APB_MULTI_DIODE.vhd
3 APB_SIMPLE_DIODE.vhd
4 lpp_amba.vhd
2 lpp_amba.vhd
Show file before | Show file after | Hide comments
@@ -48,6 +48,7 ENTITY lpp_dma_send_1word IS
48 --
48 --
49 send : IN STD_LOGIC;
49 send : IN STD_LOGIC;
50 address : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
50 address : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
51
51 data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
52 data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
52 --
53 --
53 send_ok : OUT STD_LOGIC;
54 send_ok : OUT STD_LOGIC;
Show file before | Show file after | Hide comments
@@ -1,8 +1,6
1 lpp_dma_pkg.vhd
1 fifo_latency_correction.vhd
2 fifo_latency_correction.vhd
2 lpp_dma_apbreg.vhd
3 lpp_dma.vhd
3 lpp_dma_fsm.vhd
4 lpp_dma_ip.vhd
4 lpp_dma_ip.vhd
5 lpp_dma_pkg.vhd
6 lpp_dma_send_16word.vhd
5 lpp_dma_send_16word.vhd
7 lpp_dma_send_1word.vhd
6 lpp_dma_send_1word.vhd
8 lpp_dma.vhd
Show file before | Show file after | Hide comments
@@ -1,17 +1,14
1 ALU_Driver.vhd
1 ALU_Driver.vhd
2 ALU_Driver.vhd.bak
3 APB_Matrix.vhd
2 APB_Matrix.vhd
3 ReUse_CTRLR.vhd
4 Dispatch.vhd
4 Dispatch.vhd
5 DriveInputs.vhd
5 DriveInputs.vhd
6 GetResult.vhd
6 GetResult.vhd
7 lpp_matrix.vhd
8 MatriceSpectrale.vhd
7 MatriceSpectrale.vhd
9 MatriceSpectrale.vhd.bak
10 Matrix.vhd
8 Matrix.vhd
11 ReUse_CTRLR.vhd
12 SpectralMatrix.vhd
9 SpectralMatrix.vhd
13 SpectralMatrix.vhd.bak
14 Starter.vhd
10 Starter.vhd
15 TopMatrix_PDR.vhd
11 TopMatrix_PDR.vhd
12 TopSpecMatrix.vhd
16 Top_MatrixSpec.vhd
13 Top_MatrixSpec.vhd
17 TopSpecMatrix.vhd
14 lpp_matrix.vhd
Show file before | Show file after | Hide comments
@@ -1,11 +1,8
1 lpp_memory.vhd
2 lpp_FIFO.vhd
3 FillFifo.vhd
1 APB_FIFO.vhd
4 APB_FIFO.vhd
2 APB_FIFO.vhd.bak
5 Bridge.vhd
3 FIFO_pipeline.vhd
6 SSRAM_plugin.vhd
4 FillFifo.vhd
7 lppFIFOx5.vhd
5 lpp_FIFO.vhd
6 lppFIFOxN.vhd
8 lppFIFOxN.vhd
7 lppFIFOxN.vhd.bak
8 lpp_memory.vhd
9 lpp_memory.vhd.bak
10 SSRAM_plugin.vhd
11 SSRAM_plugin_vsim.vhd
Show file before | Show file after | Hide comments
@@ -139,6 +139,7 ARCHITECTURE beh OF lpp_lfr IS
139 SIGNAL data_f2_wfp : STD_LOGIC_VECTOR(159 DOWNTO 0) ;
139 SIGNAL data_f2_wfp : STD_LOGIC_VECTOR(159 DOWNTO 0) ;
140 SIGNAL data_f3_wfp : STD_LOGIC_VECTOR(159 DOWNTO 0) ;
140 SIGNAL data_f3_wfp : STD_LOGIC_VECTOR(159 DOWNTO 0) ;
141
141
142 SIGNAL run : STD_LOGIC;
142 -- SIGNAL val_f0_wfp : STD_LOGIC;
143 -- SIGNAL val_f0_wfp : STD_LOGIC;
143 -- SIGNAL val_f1_wfp : STD_LOGIC;
144 -- SIGNAL val_f1_wfp : STD_LOGIC;
144 -- SIGNAL val_f2_wfp : STD_LOGIC;
145 -- SIGNAL val_f2_wfp : STD_LOGIC;
@@ -234,6 +235,7 BEGIN
234 burst_f0 => burst_f0,
235 burst_f0 => burst_f0,
235 burst_f1 => burst_f1,
236 burst_f1 => burst_f1,
236 burst_f2 => burst_f2,
237 burst_f2 => burst_f2,
238 run => run,
237 addr_data_f0 => addr_data_f0,
239 addr_data_f0 => addr_data_f0,
238 addr_data_f1 => addr_data_f1,
240 addr_data_f1 => addr_data_f1,
239 addr_data_f2 => addr_data_f2,
241 addr_data_f2 => addr_data_f2,
@@ -267,6 +269,9 BEGIN
267 burst_f0 => burst_f0,
269 burst_f0 => burst_f0,
268 burst_f1 => burst_f1,
270 burst_f1 => burst_f1,
269 burst_f2 => burst_f2,
271 burst_f2 => burst_f2,
272
273 run => run,
274
270 nb_burst_available => nb_burst_available,
275 nb_burst_available => nb_burst_available,
271 nb_snapshot_param => nb_snapshot_param,
276 nb_snapshot_param => nb_snapshot_param,
272 status_full => status_full,
277 status_full => status_full,
Show file before | Show file after | Hide comments
This diff has been collapsed as it changes many lines, (822 lines changed) Show them Hide them
@@ -1,407 +1,415
1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
18 -------------------------------------------------------------------------------
19 -- Author : Jean-christophe Pellion
19 -- Author : Jean-christophe Pellion
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 -- jean-christophe.pellion@easii-ic.com
21 -- jean-christophe.pellion@easii-ic.com
22 ----------------------------------------------------------------------------
22 ----------------------------------------------------------------------------
23 LIBRARY ieee;
23 LIBRARY ieee;
24 USE ieee.std_logic_1164.ALL;
24 USE ieee.std_logic_1164.ALL;
25 USE ieee.numeric_std.ALL;
25 USE ieee.numeric_std.ALL;
26 LIBRARY grlib;
26 LIBRARY grlib;
27 USE grlib.amba.ALL;
27 USE grlib.amba.ALL;
28 USE grlib.stdlib.ALL;
28 USE grlib.stdlib.ALL;
29 USE grlib.devices.ALL;
29 USE grlib.devices.ALL;
30 LIBRARY lpp;
30 LIBRARY lpp;
31 USE lpp.lpp_amba.ALL;
31 USE lpp.lpp_amba.ALL;
32 USE lpp.apb_devices_list.ALL;
32 USE lpp.apb_devices_list.ALL;
33 USE lpp.lpp_memory.ALL;
33 USE lpp.lpp_memory.ALL;
34 LIBRARY techmap;
34 LIBRARY techmap;
35 USE techmap.gencomp.ALL;
35 USE techmap.gencomp.ALL;
36
36
37 ENTITY lpp_lfr_apbreg IS
37 ENTITY lpp_lfr_apbreg IS
38 GENERIC (
38 GENERIC (
39 nb_burst_available_size : INTEGER := 11;
39 nb_burst_available_size : INTEGER := 11;
40 nb_snapshot_param_size : INTEGER := 11;
40 nb_snapshot_param_size : INTEGER := 11;
41 delta_snapshot_size : INTEGER := 16;
41 delta_snapshot_size : INTEGER := 16;
42 delta_f2_f0_size : INTEGER := 10;
42 delta_f2_f0_size : INTEGER := 10;
43 delta_f2_f1_size : INTEGER := 10;
43 delta_f2_f1_size : INTEGER := 10;
44
44
45 pindex : INTEGER := 4;
45 pindex : INTEGER := 4;
46 paddr : INTEGER := 4;
46 paddr : INTEGER := 4;
47 pmask : INTEGER := 16#fff#;
47 pmask : INTEGER := 16#fff#;
48 pirq_ms : INTEGER := 0;
48 pirq_ms : INTEGER := 0;
49 pirq_wfp : INTEGER := 1);
49 pirq_wfp : INTEGER := 1);
50 PORT (
50 PORT (
51 -- AMBA AHB system signals
51 -- AMBA AHB system signals
52 HCLK : IN STD_ULOGIC;
52 HCLK : IN STD_ULOGIC;
53 HRESETn : IN STD_ULOGIC;
53 HRESETn : IN STD_ULOGIC;
54
54
55 -- AMBA APB Slave Interface
55 -- AMBA APB Slave Interface
56 apbi : IN apb_slv_in_type;
56 apbi : IN apb_slv_in_type;
57 apbo : OUT apb_slv_out_type;
57 apbo : OUT apb_slv_out_type;
58
58
59 ---------------------------------------------------------------------------
59 ---------------------------------------------------------------------------
60 -- Spectral Matrix Reg
60 -- Spectral Matrix Reg
61 -- IN
61 -- IN
62 ready_matrix_f0_0 : IN STD_LOGIC;
62 ready_matrix_f0_0 : IN STD_LOGIC;
63 ready_matrix_f0_1 : IN STD_LOGIC;
63 ready_matrix_f0_1 : IN STD_LOGIC;
64 ready_matrix_f1 : IN STD_LOGIC;
64 ready_matrix_f1 : IN STD_LOGIC;
65 ready_matrix_f2 : IN STD_LOGIC;
65 ready_matrix_f2 : IN STD_LOGIC;
66 error_anticipating_empty_fifo : IN STD_LOGIC;
66 error_anticipating_empty_fifo : IN STD_LOGIC;
67 error_bad_component_error : IN STD_LOGIC;
67 error_bad_component_error : IN STD_LOGIC;
68 debug_reg : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
68 debug_reg : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
69
69
70 -- OUT
70 -- OUT
71 status_ready_matrix_f0_0 : OUT STD_LOGIC;
71 status_ready_matrix_f0_0 : OUT STD_LOGIC;
72 status_ready_matrix_f0_1 : OUT STD_LOGIC;
72 status_ready_matrix_f0_1 : OUT STD_LOGIC;
73 status_ready_matrix_f1 : OUT STD_LOGIC;
73 status_ready_matrix_f1 : OUT STD_LOGIC;
74 status_ready_matrix_f2 : OUT STD_LOGIC;
74 status_ready_matrix_f2 : OUT STD_LOGIC;
75 status_error_anticipating_empty_fifo : OUT STD_LOGIC;
75 status_error_anticipating_empty_fifo : OUT STD_LOGIC;
76 status_error_bad_component_error : OUT STD_LOGIC;
76 status_error_bad_component_error : OUT STD_LOGIC;
77
77
78 config_active_interruption_onNewMatrix : OUT STD_LOGIC;
78 config_active_interruption_onNewMatrix : OUT STD_LOGIC;
79 config_active_interruption_onError : OUT STD_LOGIC;
79 config_active_interruption_onError : OUT STD_LOGIC;
80 addr_matrix_f0_0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
80 addr_matrix_f0_0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
81 addr_matrix_f0_1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
81 addr_matrix_f0_1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
82 addr_matrix_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
82 addr_matrix_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
83 addr_matrix_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
83 addr_matrix_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
84 ---------------------------------------------------------------------------
84 ---------------------------------------------------------------------------
85 ---------------------------------------------------------------------------
85 ---------------------------------------------------------------------------
86 -- WaveForm picker Reg
86 -- WaveForm picker Reg
87 status_full : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
87 status_full : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
88 status_full_ack : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
88 status_full_ack : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
89 status_full_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
89 status_full_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
90 status_new_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
90 status_new_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
91
91
92 -- OUT
92 -- OUT
93 data_shaping_BW : OUT STD_LOGIC;
93 data_shaping_BW : OUT STD_LOGIC;
94 data_shaping_SP0 : OUT STD_LOGIC;
94 data_shaping_SP0 : OUT STD_LOGIC;
95 data_shaping_SP1 : OUT STD_LOGIC;
95 data_shaping_SP1 : OUT STD_LOGIC;
96 data_shaping_R0 : OUT STD_LOGIC;
96 data_shaping_R0 : OUT STD_LOGIC;
97 data_shaping_R1 : OUT STD_LOGIC;
97 data_shaping_R1 : OUT STD_LOGIC;
98
98
99 delta_snapshot : OUT STD_LOGIC_VECTOR(delta_snapshot_size-1 DOWNTO 0);
99 delta_snapshot : OUT STD_LOGIC_VECTOR(delta_snapshot_size-1 DOWNTO 0);
100 delta_f2_f1 : OUT STD_LOGIC_VECTOR(delta_f2_f1_size-1 DOWNTO 0);
100 delta_f2_f1 : OUT STD_LOGIC_VECTOR(delta_f2_f1_size-1 DOWNTO 0);
101 delta_f2_f0 : OUT STD_LOGIC_VECTOR(delta_f2_f0_size-1 DOWNTO 0);
101 delta_f2_f0 : OUT STD_LOGIC_VECTOR(delta_f2_f0_size-1 DOWNTO 0);
102 nb_burst_available : OUT STD_LOGIC_VECTOR(nb_burst_available_size-1 DOWNTO 0);
102 nb_burst_available : OUT STD_LOGIC_VECTOR(nb_burst_available_size-1 DOWNTO 0);
103 nb_snapshot_param : OUT STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
103 nb_snapshot_param : OUT STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
104
104
105 enable_f0 : OUT STD_LOGIC;
105 enable_f0 : OUT STD_LOGIC;
106 enable_f1 : OUT STD_LOGIC;
106 enable_f1 : OUT STD_LOGIC;
107 enable_f2 : OUT STD_LOGIC;
107 enable_f2 : OUT STD_LOGIC;
108 enable_f3 : OUT STD_LOGIC;
108 enable_f3 : OUT STD_LOGIC;
109
109
110 burst_f0 : OUT STD_LOGIC;
110 burst_f0 : OUT STD_LOGIC;
111 burst_f1 : OUT STD_LOGIC;
111 burst_f1 : OUT STD_LOGIC;
112 burst_f2 : OUT STD_LOGIC;
112 burst_f2 : OUT STD_LOGIC;
113
113
114 addr_data_f0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
114 run : OUT STD_LOGIC;
115 addr_data_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
115
116 addr_data_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
116 addr_data_f0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
117 addr_data_f3 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
117 addr_data_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
118
118 addr_data_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
119 ---------------------------------------------------------------------------
119 addr_data_f3 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
120 );
120
121
121 ---------------------------------------------------------------------------
122 END lpp_lfr_apbreg;
122 );
123
123
124 ARCHITECTURE beh OF lpp_lfr_apbreg IS
124 END lpp_lfr_apbreg;
125
125
126 CONSTANT REVISION : INTEGER := 1;
126 ARCHITECTURE beh OF lpp_lfr_apbreg IS
127
127
128 CONSTANT pconfig : apb_config_type := (
128 CONSTANT REVISION : INTEGER := 1;
129 0 => ahb_device_reg (VENDOR_LPP, LPP_DMA_TYPE, 2, REVISION, pirq_wfp),
129
130 1 => apb_iobar(paddr, pmask));
130 CONSTANT pconfig : apb_config_type := (
131
131 0 => ahb_device_reg (VENDOR_LPP, LPP_LFR, 2, REVISION, pirq_wfp),
132 TYPE lpp_SpectralMatrix_regs IS RECORD
132 1 => apb_iobar(paddr, pmask));
133 config_active_interruption_onNewMatrix : STD_LOGIC;
133
134 config_active_interruption_onError : STD_LOGIC;
134 TYPE lpp_SpectralMatrix_regs IS RECORD
135 status_ready_matrix_f0_0 : STD_LOGIC;
135 config_active_interruption_onNewMatrix : STD_LOGIC;
136 status_ready_matrix_f0_1 : STD_LOGIC;
136 config_active_interruption_onError : STD_LOGIC;
137 status_ready_matrix_f1 : STD_LOGIC;
137 status_ready_matrix_f0_0 : STD_LOGIC;
138 status_ready_matrix_f2 : STD_LOGIC;
138 status_ready_matrix_f0_1 : STD_LOGIC;
139 status_error_anticipating_empty_fifo : STD_LOGIC;
139 status_ready_matrix_f1 : STD_LOGIC;
140 status_error_bad_component_error : STD_LOGIC;
140 status_ready_matrix_f2 : STD_LOGIC;
141 addr_matrix_f0_0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
141 status_error_anticipating_empty_fifo : STD_LOGIC;
142 addr_matrix_f0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
142 status_error_bad_component_error : STD_LOGIC;
143 addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
143 addr_matrix_f0_0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
144 addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
144 addr_matrix_f0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
145 END RECORD;
145 addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
146 SIGNAL reg_sp : lpp_SpectralMatrix_regs;
146 addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
147
147 END RECORD;
148 TYPE lpp_WaveformPicker_regs IS RECORD
148 SIGNAL reg_sp : lpp_SpectralMatrix_regs;
149 status_full : STD_LOGIC_VECTOR(3 DOWNTO 0);
149
150 status_full_err : STD_LOGIC_VECTOR(3 DOWNTO 0);
150 TYPE lpp_WaveformPicker_regs IS RECORD
151 status_new_err : STD_LOGIC_VECTOR(3 DOWNTO 0);
151 status_full : STD_LOGIC_VECTOR(3 DOWNTO 0);
152 data_shaping_BW : STD_LOGIC;
152 status_full_err : STD_LOGIC_VECTOR(3 DOWNTO 0);
153 data_shaping_SP0 : STD_LOGIC;
153 status_new_err : STD_LOGIC_VECTOR(3 DOWNTO 0);
154 data_shaping_SP1 : STD_LOGIC;
154 data_shaping_BW : STD_LOGIC;
155 data_shaping_R0 : STD_LOGIC;
155 data_shaping_SP0 : STD_LOGIC;
156 data_shaping_R1 : STD_LOGIC;
156 data_shaping_SP1 : STD_LOGIC;
157 delta_snapshot : STD_LOGIC_VECTOR(delta_snapshot_size-1 DOWNTO 0);
157 data_shaping_R0 : STD_LOGIC;
158 delta_f2_f1 : STD_LOGIC_VECTOR(delta_f2_f1_size-1 DOWNTO 0);
158 data_shaping_R1 : STD_LOGIC;
159 delta_f2_f0 : STD_LOGIC_VECTOR(delta_f2_f0_size-1 DOWNTO 0);
159 delta_snapshot : STD_LOGIC_VECTOR(delta_snapshot_size-1 DOWNTO 0);
160 nb_burst_available : STD_LOGIC_VECTOR(nb_burst_available_size-1 DOWNTO 0);
160 delta_f2_f1 : STD_LOGIC_VECTOR(delta_f2_f1_size-1 DOWNTO 0);
161 nb_snapshot_param : STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
161 delta_f2_f0 : STD_LOGIC_VECTOR(delta_f2_f0_size-1 DOWNTO 0);
162 enable_f0 : STD_LOGIC;
162 nb_burst_available : STD_LOGIC_VECTOR(nb_burst_available_size-1 DOWNTO 0);
163 enable_f1 : STD_LOGIC;
163 nb_snapshot_param : STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
164 enable_f2 : STD_LOGIC;
164 enable_f0 : STD_LOGIC;
165 enable_f3 : STD_LOGIC;
165 enable_f1 : STD_LOGIC;
166 burst_f0 : STD_LOGIC;
166 enable_f2 : STD_LOGIC;
167 burst_f1 : STD_LOGIC;
167 enable_f3 : STD_LOGIC;
168 burst_f2 : STD_LOGIC;
168 burst_f0 : STD_LOGIC;
169 addr_data_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
169 burst_f1 : STD_LOGIC;
170 addr_data_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
170 burst_f2 : STD_LOGIC;
171 addr_data_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
171 run : STD_LOGIC;
172 addr_data_f3 : STD_LOGIC_VECTOR(31 DOWNTO 0);
172 addr_data_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
173 END RECORD;
173 addr_data_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
174 SIGNAL reg_wp : lpp_WaveformPicker_regs;
174 addr_data_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
175
175 addr_data_f3 : STD_LOGIC_VECTOR(31 DOWNTO 0);
176 SIGNAL prdata : STD_LOGIC_VECTOR(31 DOWNTO 0);
176 END RECORD;
177
177 SIGNAL reg_wp : lpp_WaveformPicker_regs;
178 BEGIN -- beh
178
179
179 SIGNAL prdata : STD_LOGIC_VECTOR(31 DOWNTO 0);
180 status_ready_matrix_f0_0 <= reg_sp.status_ready_matrix_f0_0;
180
181 status_ready_matrix_f0_1 <= reg_sp.status_ready_matrix_f0_1;
181 BEGIN -- beh
182 status_ready_matrix_f1 <= reg_sp.status_ready_matrix_f1;
182
183 status_ready_matrix_f2 <= reg_sp.status_ready_matrix_f2;
183 status_ready_matrix_f0_0 <= reg_sp.status_ready_matrix_f0_0;
184 status_error_anticipating_empty_fifo <= reg_sp.status_error_anticipating_empty_fifo;
184 status_ready_matrix_f0_1 <= reg_sp.status_ready_matrix_f0_1;
185 status_error_bad_component_error <= reg_sp.status_error_bad_component_error;
185 status_ready_matrix_f1 <= reg_sp.status_ready_matrix_f1;
186
186 status_ready_matrix_f2 <= reg_sp.status_ready_matrix_f2;
187 config_active_interruption_onNewMatrix <= reg_sp.config_active_interruption_onNewMatrix;
187 status_error_anticipating_empty_fifo <= reg_sp.status_error_anticipating_empty_fifo;
188 config_active_interruption_onError <= reg_sp.config_active_interruption_onError;
188 status_error_bad_component_error <= reg_sp.status_error_bad_component_error;
189 addr_matrix_f0_0 <= reg_sp.addr_matrix_f0_0;
189
190 addr_matrix_f0_1 <= reg_sp.addr_matrix_f0_1;
190 config_active_interruption_onNewMatrix <= reg_sp.config_active_interruption_onNewMatrix;
191 addr_matrix_f1 <= reg_sp.addr_matrix_f1;
191 config_active_interruption_onError <= reg_sp.config_active_interruption_onError;
192 addr_matrix_f2 <= reg_sp.addr_matrix_f2;
192 addr_matrix_f0_0 <= reg_sp.addr_matrix_f0_0;
193
193 addr_matrix_f0_1 <= reg_sp.addr_matrix_f0_1;
194
194 addr_matrix_f1 <= reg_sp.addr_matrix_f1;
195 data_shaping_BW <= NOT reg_wp.data_shaping_BW;
195 addr_matrix_f2 <= reg_sp.addr_matrix_f2;
196 data_shaping_SP0 <= reg_wp.data_shaping_SP0;
196
197 data_shaping_SP1 <= reg_wp.data_shaping_SP1;
197
198 data_shaping_R0 <= reg_wp.data_shaping_R0;
198 data_shaping_BW <= NOT reg_wp.data_shaping_BW;
199 data_shaping_R1 <= reg_wp.data_shaping_R1;
199 data_shaping_SP0 <= reg_wp.data_shaping_SP0;
200
200 data_shaping_SP1 <= reg_wp.data_shaping_SP1;
201 delta_snapshot <= reg_wp.delta_snapshot;
201 data_shaping_R0 <= reg_wp.data_shaping_R0;
202 delta_f2_f1 <= reg_wp.delta_f2_f1;
202 data_shaping_R1 <= reg_wp.data_shaping_R1;
203 delta_f2_f0 <= reg_wp.delta_f2_f0;
203
204 nb_burst_available <= reg_wp.nb_burst_available;
204 delta_snapshot <= reg_wp.delta_snapshot;
205 nb_snapshot_param <= reg_wp.nb_snapshot_param;
205 delta_f2_f1 <= reg_wp.delta_f2_f1;
206
206 delta_f2_f0 <= reg_wp.delta_f2_f0;
207 enable_f0 <= reg_wp.enable_f0;
207 nb_burst_available <= reg_wp.nb_burst_available;
208 enable_f1 <= reg_wp.enable_f1;
208 nb_snapshot_param <= reg_wp.nb_snapshot_param;
209 enable_f2 <= reg_wp.enable_f2;
209
210 enable_f3 <= reg_wp.enable_f3;
210 enable_f0 <= reg_wp.enable_f0;
211
211 enable_f1 <= reg_wp.enable_f1;
212 burst_f0 <= reg_wp.burst_f0;
212 enable_f2 <= reg_wp.enable_f2;
213 burst_f1 <= reg_wp.burst_f1;
213 enable_f3 <= reg_wp.enable_f3;
214 burst_f2 <= reg_wp.burst_f2;
214
215
215 burst_f0 <= reg_wp.burst_f0;
216 addr_data_f0 <= reg_wp.addr_data_f0;
216 burst_f1 <= reg_wp.burst_f1;
217 addr_data_f1 <= reg_wp.addr_data_f1;
217 burst_f2 <= reg_wp.burst_f2;
218 addr_data_f2 <= reg_wp.addr_data_f2;
218
219 addr_data_f3 <= reg_wp.addr_data_f3;
219 run <= reg_wp.run;
220
220
221 lpp_lfr_apbreg : PROCESS (HCLK, HRESETn)
221 addr_data_f0 <= reg_wp.addr_data_f0;
222 VARIABLE paddr : STD_LOGIC_VECTOR(7 DOWNTO 2);
222 addr_data_f1 <= reg_wp.addr_data_f1;
223 BEGIN -- PROCESS lpp_dma_top
223 addr_data_f2 <= reg_wp.addr_data_f2;
224 IF HRESETn = '0' THEN -- asynchronous reset (active low)
224 addr_data_f3 <= reg_wp.addr_data_f3;
225 reg_sp.config_active_interruption_onNewMatrix <= '0';
225
226 reg_sp.config_active_interruption_onError <= '0';
226 lpp_lfr_apbreg : PROCESS (HCLK, HRESETn)
227 reg_sp.status_ready_matrix_f0_0 <= '0';
227 VARIABLE paddr : STD_LOGIC_VECTOR(7 DOWNTO 2);
228 reg_sp.status_ready_matrix_f0_1 <= '0';
228 BEGIN -- PROCESS lpp_dma_top
229 reg_sp.status_ready_matrix_f1 <= '0';
229 IF HRESETn = '0' THEN -- asynchronous reset (active low)
230 reg_sp.status_ready_matrix_f2 <= '0';
230 reg_sp.config_active_interruption_onNewMatrix <= '0';
231 reg_sp.status_error_anticipating_empty_fifo <= '0';
231 reg_sp.config_active_interruption_onError <= '0';
232 reg_sp.status_error_bad_component_error <= '0';
232 reg_sp.status_ready_matrix_f0_0 <= '0';
233 reg_sp.addr_matrix_f0_0 <= (OTHERS => '0');
233 reg_sp.status_ready_matrix_f0_1 <= '0';
234 reg_sp.addr_matrix_f0_1 <= (OTHERS => '0');
234 reg_sp.status_ready_matrix_f1 <= '0';
235 reg_sp.addr_matrix_f1 <= (OTHERS => '0');
235 reg_sp.status_ready_matrix_f2 <= '0';
236 reg_sp.addr_matrix_f2 <= (OTHERS => '0');
236 reg_sp.status_error_anticipating_empty_fifo <= '0';
237 prdata <= (OTHERS => '0');
237 reg_sp.status_error_bad_component_error <= '0';
238
238 reg_sp.addr_matrix_f0_0 <= (OTHERS => '0');
239 apbo.pirq <= (OTHERS => '0');
239 reg_sp.addr_matrix_f0_1 <= (OTHERS => '0');
240
240 reg_sp.addr_matrix_f1 <= (OTHERS => '0');
241 status_full_ack <= (OTHERS => '0');
241 reg_sp.addr_matrix_f2 <= (OTHERS => '0');
242
242 prdata <= (OTHERS => '0');
243 reg_wp.data_shaping_BW <= '0';
243
244 reg_wp.data_shaping_SP0 <= '0';
244 apbo.pirq <= (OTHERS => '0');
245 reg_wp.data_shaping_SP1 <= '0';
245
246 reg_wp.data_shaping_R0 <= '0';
246 status_full_ack <= (OTHERS => '0');
247 reg_wp.data_shaping_R1 <= '0';
247
248 reg_wp.enable_f0 <= '0';
248 reg_wp.data_shaping_BW <= '0';
249 reg_wp.enable_f1 <= '0';
249 reg_wp.data_shaping_SP0 <= '0';
250 reg_wp.enable_f2 <= '0';
250 reg_wp.data_shaping_SP1 <= '0';
251 reg_wp.enable_f3 <= '0';
251 reg_wp.data_shaping_R0 <= '0';
252 reg_wp.burst_f0 <= '0';
252 reg_wp.data_shaping_R1 <= '0';
253 reg_wp.burst_f1 <= '0';
253 reg_wp.enable_f0 <= '0';
254 reg_wp.burst_f2 <= '0';
254 reg_wp.enable_f1 <= '0';
255 reg_wp.addr_data_f0 <= (OTHERS => '0');
255 reg_wp.enable_f2 <= '0';
256 reg_wp.addr_data_f1 <= (OTHERS => '0');
256 reg_wp.enable_f3 <= '0';
257 reg_wp.addr_data_f2 <= (OTHERS => '0');
257 reg_wp.burst_f0 <= '0';
258 reg_wp.addr_data_f3 <= (OTHERS => '0');
258 reg_wp.burst_f1 <= '0';
259 reg_wp.status_full <= (OTHERS => '0');
259 reg_wp.burst_f2 <= '0';
260 reg_wp.status_full_err <= (OTHERS => '0');
260 reg_wp.run <= '0';
261 reg_wp.status_new_err <= (OTHERS => '0');
261 reg_wp.addr_data_f0 <= (OTHERS => '0');
262 reg_wp.delta_snapshot <= (OTHERS => '0');
262 reg_wp.addr_data_f1 <= (OTHERS => '0');
263 reg_wp.delta_f2_f1 <= (OTHERS => '0');
263 reg_wp.addr_data_f2 <= (OTHERS => '0');
264 reg_wp.delta_f2_f0 <= (OTHERS => '0');
264 reg_wp.addr_data_f3 <= (OTHERS => '0');
265 reg_wp.nb_burst_available <= (OTHERS => '0');
265 reg_wp.status_full <= (OTHERS => '0');
266 reg_wp.nb_snapshot_param <= (OTHERS => '0');
266 reg_wp.status_full_err <= (OTHERS => '0');
267
267 reg_wp.status_new_err <= (OTHERS => '0');
268 ELSIF HCLK'EVENT AND HCLK = '1' THEN -- rising clock edge
268 reg_wp.delta_snapshot <= (OTHERS => '0');
269 status_full_ack <= (OTHERS => '0');
269 reg_wp.delta_f2_f1 <= (OTHERS => '0');
270
270 reg_wp.delta_f2_f0 <= (OTHERS => '0');
271 reg_sp.status_ready_matrix_f0_0 <= reg_sp.status_ready_matrix_f0_0 OR ready_matrix_f0_0;
271 reg_wp.nb_burst_available <= (OTHERS => '0');
272 reg_sp.status_ready_matrix_f0_1 <= reg_sp.status_ready_matrix_f0_1 OR ready_matrix_f0_1;
272 reg_wp.nb_snapshot_param <= (OTHERS => '0');
273 reg_sp.status_ready_matrix_f1 <= reg_sp.status_ready_matrix_f1 OR ready_matrix_f1;
273
274 reg_sp.status_ready_matrix_f2 <= reg_sp.status_ready_matrix_f2 OR ready_matrix_f2;
274 ELSIF HCLK'EVENT AND HCLK = '1' THEN -- rising clock edge
275
275 status_full_ack <= (OTHERS => '0');
276 reg_sp.status_error_anticipating_empty_fifo <= reg_sp.status_error_anticipating_empty_fifo OR error_anticipating_empty_fifo;
276
277 reg_sp.status_error_bad_component_error <= reg_sp.status_error_bad_component_error OR error_bad_component_error;
277 reg_sp.status_ready_matrix_f0_0 <= reg_sp.status_ready_matrix_f0_0 OR ready_matrix_f0_0;
278
278 reg_sp.status_ready_matrix_f0_1 <= reg_sp.status_ready_matrix_f0_1 OR ready_matrix_f0_1;
279 reg_wp.status_full <= reg_wp.status_full OR status_full;
279 reg_sp.status_ready_matrix_f1 <= reg_sp.status_ready_matrix_f1 OR ready_matrix_f1;
280 reg_wp.status_full_err <= reg_wp.status_full_err OR status_full_err;
280 reg_sp.status_ready_matrix_f2 <= reg_sp.status_ready_matrix_f2 OR ready_matrix_f2;
281 reg_wp.status_new_err <= reg_wp.status_new_err OR status_new_err;
281
282
282 reg_sp.status_error_anticipating_empty_fifo <= reg_sp.status_error_anticipating_empty_fifo OR error_anticipating_empty_fifo;
283 paddr := "000000";
283 reg_sp.status_error_bad_component_error <= reg_sp.status_error_bad_component_error OR error_bad_component_error;
284 paddr(7 DOWNTO 2) := apbi.paddr(7 DOWNTO 2);
284
285 prdata <= (OTHERS => '0');
285 reg_wp.status_full <= reg_wp.status_full OR status_full;
286 IF apbi.psel(pindex) = '1' THEN
286 reg_wp.status_full_err <= reg_wp.status_full_err OR status_full_err;
287 -- APB DMA READ --
287 reg_wp.status_new_err <= reg_wp.status_new_err OR status_new_err;
288 CASE paddr(7 DOWNTO 2) IS
288
289 --
289 paddr := "000000";
290 WHEN "000000" => prdata(0) <= reg_sp.config_active_interruption_onNewMatrix;
290 paddr(7 DOWNTO 2) := apbi.paddr(7 DOWNTO 2);
291 prdata(1) <= reg_sp.config_active_interruption_onError;
291 prdata <= (OTHERS => '0');
292 WHEN "000001" => prdata(0) <= reg_sp.status_ready_matrix_f0_0;
292 IF apbi.psel(pindex) = '1' THEN
293 prdata(1) <= reg_sp.status_ready_matrix_f0_1;
293 -- APB DMA READ --
294 prdata(2) <= reg_sp.status_ready_matrix_f1;
294 CASE paddr(7 DOWNTO 2) IS
295 prdata(3) <= reg_sp.status_ready_matrix_f2;
295 --
296 prdata(4) <= reg_sp.status_error_anticipating_empty_fifo;
296 WHEN "000000" => prdata(0) <= reg_sp.config_active_interruption_onNewMatrix;
297 prdata(5) <= reg_sp.status_error_bad_component_error;
297 prdata(1) <= reg_sp.config_active_interruption_onError;
298 WHEN "000010" => prdata <= reg_sp.addr_matrix_f0_0;
298 WHEN "000001" => prdata(0) <= reg_sp.status_ready_matrix_f0_0;
299 WHEN "000011" => prdata <= reg_sp.addr_matrix_f0_1;
299 prdata(1) <= reg_sp.status_ready_matrix_f0_1;
300 WHEN "000100" => prdata <= reg_sp.addr_matrix_f1;
300 prdata(2) <= reg_sp.status_ready_matrix_f1;
301 WHEN "000101" => prdata <= reg_sp.addr_matrix_f2;
301 prdata(3) <= reg_sp.status_ready_matrix_f2;
302 WHEN "000110" => prdata <= debug_reg;
302 prdata(4) <= reg_sp.status_error_anticipating_empty_fifo;
303 --
303 prdata(5) <= reg_sp.status_error_bad_component_error;
304 WHEN "001000" => prdata(0) <= reg_wp.data_shaping_BW;
304 WHEN "000010" => prdata <= reg_sp.addr_matrix_f0_0;
305 prdata(1) <= reg_wp.data_shaping_SP0;
305 WHEN "000011" => prdata <= reg_sp.addr_matrix_f0_1;
306 prdata(2) <= reg_wp.data_shaping_SP1;
306 WHEN "000100" => prdata <= reg_sp.addr_matrix_f1;
307 prdata(3) <= reg_wp.data_shaping_R0;
307 WHEN "000101" => prdata <= reg_sp.addr_matrix_f2;
308 prdata(4) <= reg_wp.data_shaping_R1;
308 WHEN "000110" => prdata <= debug_reg;
309 WHEN "001001" => prdata(0) <= reg_wp.enable_f0;
309 --
310 prdata(1) <= reg_wp.enable_f1;
310 WHEN "001000" => prdata(0) <= reg_wp.data_shaping_BW;
311 prdata(2) <= reg_wp.enable_f2;
311 prdata(1) <= reg_wp.data_shaping_SP0;
312 prdata(3) <= reg_wp.enable_f3;
312 prdata(2) <= reg_wp.data_shaping_SP1;
313 prdata(4) <= reg_wp.burst_f0;
313 prdata(3) <= reg_wp.data_shaping_R0;
314 prdata(5) <= reg_wp.burst_f1;
314 prdata(4) <= reg_wp.data_shaping_R1;
315 prdata(6) <= reg_wp.burst_f2;
315 WHEN "001001" => prdata(0) <= reg_wp.enable_f0;
316 WHEN "001010" => prdata <= reg_wp.addr_data_f0;
316 prdata(1) <= reg_wp.enable_f1;
317 WHEN "001011" => prdata <= reg_wp.addr_data_f1;
317 prdata(2) <= reg_wp.enable_f2;
318 WHEN "001100" => prdata <= reg_wp.addr_data_f2;
318 prdata(3) <= reg_wp.enable_f3;
319 WHEN "001101" => prdata <= reg_wp.addr_data_f3;
319 prdata(4) <= reg_wp.burst_f0;
320 WHEN "001110" => prdata(3 DOWNTO 0) <= reg_wp.status_full;
320 prdata(5) <= reg_wp.burst_f1;
321 prdata(7 DOWNTO 4) <= reg_wp.status_full_err;
321 prdata(6) <= reg_wp.burst_f2;
322 prdata(11 DOWNTO 8) <= reg_wp.status_new_err;
322 prdata(7) <= reg_wp.run;
323 WHEN "001111" => prdata(delta_snapshot_size-1 DOWNTO 0) <= reg_wp.delta_snapshot;
323 WHEN "001010" => prdata <= reg_wp.addr_data_f0;
324 WHEN "010000" => prdata(delta_f2_f1_size-1 DOWNTO 0) <= reg_wp.delta_f2_f1;
324 WHEN "001011" => prdata <= reg_wp.addr_data_f1;
325 WHEN "010001" => prdata(delta_f2_f0_size-1 DOWNTO 0) <= reg_wp.delta_f2_f0;
325 WHEN "001100" => prdata <= reg_wp.addr_data_f2;
326 WHEN "010010" => prdata(nb_burst_available_size-1 DOWNTO 0) <= reg_wp.nb_burst_available;
326 WHEN "001101" => prdata <= reg_wp.addr_data_f3;
327 WHEN "010011" => prdata(nb_snapshot_param_size-1 DOWNTO 0) <= reg_wp.nb_snapshot_param;
327 WHEN "001110" => prdata(3 DOWNTO 0) <= reg_wp.status_full;
328 --
328 prdata(7 DOWNTO 4) <= reg_wp.status_full_err;
329 WHEN OTHERS => NULL;
329 prdata(11 DOWNTO 8) <= reg_wp.status_new_err;
330 END CASE;
330 WHEN "001111" => prdata(delta_snapshot_size-1 DOWNTO 0) <= reg_wp.delta_snapshot;
331 IF (apbi.pwrite AND apbi.penable) = '1' THEN
331 WHEN "010000" => prdata(delta_f2_f1_size-1 DOWNTO 0) <= reg_wp.delta_f2_f1;
332 -- APB DMA WRITE --
332 WHEN "010001" => prdata(delta_f2_f0_size-1 DOWNTO 0) <= reg_wp.delta_f2_f0;
333 CASE paddr(7 DOWNTO 2) IS
333 WHEN "010010" => prdata(nb_burst_available_size-1 DOWNTO 0) <= reg_wp.nb_burst_available;
334 --
334 WHEN "010011" => prdata(nb_snapshot_param_size-1 DOWNTO 0) <= reg_wp.nb_snapshot_param;
335 WHEN "000000" => reg_sp.config_active_interruption_onNewMatrix <= apbi.pwdata(0);
335 --
336 reg_sp.config_active_interruption_onError <= apbi.pwdata(1);
336 WHEN OTHERS => NULL;
337 WHEN "000001" => reg_sp.status_ready_matrix_f0_0 <= apbi.pwdata(0);
337 END CASE;
338 reg_sp.status_ready_matrix_f0_1 <= apbi.pwdata(1);
338 IF (apbi.pwrite AND apbi.penable) = '1' THEN
339 reg_sp.status_ready_matrix_f1 <= apbi.pwdata(2);
339 -- APB DMA WRITE --
340 reg_sp.status_ready_matrix_f2 <= apbi.pwdata(3);
340 CASE paddr(7 DOWNTO 2) IS
341 reg_sp.status_error_anticipating_empty_fifo <= apbi.pwdata(4);
341 --
342 reg_sp.status_error_bad_component_error <= apbi.pwdata(5);
342 WHEN "000000" => reg_sp.config_active_interruption_onNewMatrix <= apbi.pwdata(0);
343 WHEN "000010" => reg_sp.addr_matrix_f0_0 <= apbi.pwdata;
343 reg_sp.config_active_interruption_onError <= apbi.pwdata(1);
344 WHEN "000011" => reg_sp.addr_matrix_f0_1 <= apbi.pwdata;
344 WHEN "000001" => reg_sp.status_ready_matrix_f0_0 <= apbi.pwdata(0);
345 WHEN "000100" => reg_sp.addr_matrix_f1 <= apbi.pwdata;
345 reg_sp.status_ready_matrix_f0_1 <= apbi.pwdata(1);
346 WHEN "000101" => reg_sp.addr_matrix_f2 <= apbi.pwdata;
346 reg_sp.status_ready_matrix_f1 <= apbi.pwdata(2);
347 --
347 reg_sp.status_ready_matrix_f2 <= apbi.pwdata(3);
348 WHEN "001000" => reg_wp.data_shaping_BW <= apbi.pwdata(0);
348 reg_sp.status_error_anticipating_empty_fifo <= apbi.pwdata(4);
349 reg_wp.data_shaping_SP0 <= apbi.pwdata(1);
349 reg_sp.status_error_bad_component_error <= apbi.pwdata(5);
350 reg_wp.data_shaping_SP1 <= apbi.pwdata(2);
350 WHEN "000010" => reg_sp.addr_matrix_f0_0 <= apbi.pwdata;
351 reg_wp.data_shaping_R0 <= apbi.pwdata(3);
351 WHEN "000011" => reg_sp.addr_matrix_f0_1 <= apbi.pwdata;
352 reg_wp.data_shaping_R1 <= apbi.pwdata(4);
352 WHEN "000100" => reg_sp.addr_matrix_f1 <= apbi.pwdata;
353 WHEN "001001" => reg_wp.enable_f0 <= apbi.pwdata(0);
353 WHEN "000101" => reg_sp.addr_matrix_f2 <= apbi.pwdata;
354 reg_wp.enable_f1 <= apbi.pwdata(1);
354 --
355 reg_wp.enable_f2 <= apbi.pwdata(2);
355 WHEN "001000" => reg_wp.data_shaping_BW <= apbi.pwdata(0);
356 reg_wp.enable_f3 <= apbi.pwdata(3);
356 reg_wp.data_shaping_SP0 <= apbi.pwdata(1);
357 reg_wp.burst_f0 <= apbi.pwdata(4);
357 reg_wp.data_shaping_SP1 <= apbi.pwdata(2);
358 reg_wp.burst_f1 <= apbi.pwdata(5);
358 reg_wp.data_shaping_R0 <= apbi.pwdata(3);
359 reg_wp.burst_f2 <= apbi.pwdata(6);
359 reg_wp.data_shaping_R1 <= apbi.pwdata(4);
360 WHEN "001010" => reg_wp.addr_data_f0 <= apbi.pwdata;
360 WHEN "001001" => reg_wp.enable_f0 <= apbi.pwdata(0);
361 WHEN "001011" => reg_wp.addr_data_f1 <= apbi.pwdata;
361 reg_wp.enable_f1 <= apbi.pwdata(1);
362 WHEN "001100" => reg_wp.addr_data_f2 <= apbi.pwdata;
362 reg_wp.enable_f2 <= apbi.pwdata(2);
363 WHEN "001101" => reg_wp.addr_data_f3 <= apbi.pwdata;
363 reg_wp.enable_f3 <= apbi.pwdata(3);
364 WHEN "001110" => reg_wp.status_full <= apbi.pwdata(3 DOWNTO 0);
364 reg_wp.burst_f0 <= apbi.pwdata(4);
365 reg_wp.status_full_err <= apbi.pwdata(7 DOWNTO 4);
365 reg_wp.burst_f1 <= apbi.pwdata(5);
366 reg_wp.status_new_err <= apbi.pwdata(11 DOWNTO 8);
366 reg_wp.burst_f2 <= apbi.pwdata(6);
367 status_full_ack(0) <= reg_wp.status_full(0) AND NOT apbi.pwdata(0);
367 reg_wp.run <= apbi.pwdata(7);
368 status_full_ack(1) <= reg_wp.status_full(1) AND NOT apbi.pwdata(1);
368 WHEN "001010" => reg_wp.addr_data_f0 <= apbi.pwdata;
369 status_full_ack(2) <= reg_wp.status_full(2) AND NOT apbi.pwdata(2);
369 WHEN "001011" => reg_wp.addr_data_f1 <= apbi.pwdata;
370 status_full_ack(3) <= reg_wp.status_full(3) AND NOT apbi.pwdata(3);
370 WHEN "001100" => reg_wp.addr_data_f2 <= apbi.pwdata;
371 WHEN "001111" => reg_wp.delta_snapshot <= apbi.pwdata(delta_snapshot_size-1 DOWNTO 0);
371 WHEN "001101" => reg_wp.addr_data_f3 <= apbi.pwdata;
372 WHEN "010000" => reg_wp.delta_f2_f1 <= apbi.pwdata(delta_f2_f1_size-1 DOWNTO 0);
372 WHEN "001110" => reg_wp.status_full <= apbi.pwdata(3 DOWNTO 0);
373 WHEN "010001" => reg_wp.delta_f2_f0 <= apbi.pwdata(delta_f2_f0_size-1 DOWNTO 0);
373 reg_wp.status_full_err <= apbi.pwdata(7 DOWNTO 4);
374 WHEN "010010" => reg_wp.nb_burst_available <= apbi.pwdata(nb_burst_available_size-1 DOWNTO 0);
374 reg_wp.status_new_err <= apbi.pwdata(11 DOWNTO 8);
375 WHEN "010011" => reg_wp.nb_snapshot_param <= apbi.pwdata(nb_snapshot_param_size-1 DOWNTO 0);
375 status_full_ack(0) <= reg_wp.status_full(0) AND NOT apbi.pwdata(0);
376 --
376 status_full_ack(1) <= reg_wp.status_full(1) AND NOT apbi.pwdata(1);
377 WHEN OTHERS => NULL;
377 status_full_ack(2) <= reg_wp.status_full(2) AND NOT apbi.pwdata(2);
378 END CASE;
378 status_full_ack(3) <= reg_wp.status_full(3) AND NOT apbi.pwdata(3);
379 END IF;
379 WHEN "001111" => reg_wp.delta_snapshot <= apbi.pwdata(delta_snapshot_size-1 DOWNTO 0);
380 END IF;
380 WHEN "010000" => reg_wp.delta_f2_f1 <= apbi.pwdata(delta_f2_f1_size-1 DOWNTO 0);
381
381 WHEN "010001" => reg_wp.delta_f2_f0 <= apbi.pwdata(delta_f2_f0_size-1 DOWNTO 0);
382 apbo.pirq(pirq_ms) <= (reg_sp.config_active_interruption_onNewMatrix AND (ready_matrix_f0_0 OR
382 WHEN "010010" => reg_wp.nb_burst_available <= apbi.pwdata(nb_burst_available_size-1 DOWNTO 0);
383 ready_matrix_f0_1 OR
383 WHEN "010011" => reg_wp.nb_snapshot_param <= apbi.pwdata(nb_snapshot_param_size-1 DOWNTO 0);
384 ready_matrix_f1 OR
384 --
385 ready_matrix_f2)
385 WHEN OTHERS => NULL;
386 )
386 END CASE;
387 OR
387 END IF;
388 (reg_sp.config_active_interruption_onError AND (error_anticipating_empty_fifo OR
388 END IF;
389 error_bad_component_error)
389
390 );
390 apbo.pirq(pirq_ms) <= (reg_sp.config_active_interruption_onNewMatrix AND (ready_matrix_f0_0 OR
391
391 ready_matrix_f0_1 OR
392 apbo.pirq(pirq_wfp) <= (status_full(0) OR status_full_err(0) OR status_new_err(0) OR
392 ready_matrix_f1 OR
393 status_full(1) OR status_full_err(1) OR status_new_err(1) OR
393 ready_matrix_f2)
394 status_full(2) OR status_full_err(2) OR status_new_err(2) OR
394 )
395 status_full(3) OR status_full_err(3) OR status_new_err(3)
395 OR
396 );
396 (reg_sp.config_active_interruption_onError AND (error_anticipating_empty_fifo OR
397
397 error_bad_component_error)
398
398 );
399 END IF;
399
400 END PROCESS lpp_lfr_apbreg;
400 apbo.pirq(pirq_wfp) <= (status_full(0) OR status_full_err(0) OR status_new_err(0) OR
401
401 status_full(1) OR status_full_err(1) OR status_new_err(1) OR
402 apbo.pindex <= pindex;
402 status_full(2) OR status_full_err(2) OR status_new_err(2) OR
403 apbo.pconfig <= pconfig;
403 status_full(3) OR status_full_err(3) OR status_new_err(3)
404 apbo.prdata <= prdata;
404 );
405
405
406
406
407 END beh;
407 END IF;
408 END PROCESS lpp_lfr_apbreg;
409
410 apbo.pindex <= pindex;
411 apbo.pconfig <= pconfig;
412 apbo.prdata <= prdata;
413
414
415 END beh; No newline at end of file
Show file before | Show file after | Hide comments
@@ -159,6 +159,7 PACKAGE lpp_lfr_pkg IS
159 burst_f0 : OUT STD_LOGIC;
159 burst_f0 : OUT STD_LOGIC;
160 burst_f1 : OUT STD_LOGIC;
160 burst_f1 : OUT STD_LOGIC;
161 burst_f2 : OUT STD_LOGIC;
161 burst_f2 : OUT STD_LOGIC;
162 run : OUT STD_LOGIC;
162 addr_data_f0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
163 addr_data_f0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
163 addr_data_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
164 addr_data_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
164 addr_data_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
165 addr_data_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
Show file before | Show file after | Hide comments
@@ -1,16 +1,6
1 lpp_lfr_apbreg.vhd
1 lpp_top_lfr_pkg.vhd
2 lpp_lfr_pkg.vhd
2 lpp_lfr_filter.vhd
3 lpp_lfr_filter.vhd
4 lpp_lfr_apbreg.vhd
3 lpp_lfr_ms.vhd
5 lpp_lfr_ms.vhd
4 lpp_lfr_pkg.vhd
5 lpp_lfr.vhd
6 lpp_lfr.vhd
6 lpp_top_acq.vhd
7 lpp_top_acq.vhd.bak
8 lpp_top_apbreg.vhd
9 lpp_top_lfr_pkg.vhd
10 lpp_top_lfr_pkg.vhd.bak
11 lpp_top_lfr.vhd
12 lpp_top_lfr_wf_picker_ip.vhd
13 lpp_top_lfr_wf_picker_ip_whitout_filter.vhd
14 lpp_top_lfr_wf_picker.vhd
15 top_wf_picker.vhd
16 lpp_top_ms.vhd
Show file before | Show file after | Hide comments
@@ -50,6 +50,8 ENTITY lpp_waveform IS
50 burst_f1 : IN STD_LOGIC;
50 burst_f1 : IN STD_LOGIC;
51 burst_f2 : IN STD_LOGIC;
51 burst_f2 : IN STD_LOGIC;
52
52
53 run : IN STD_LOGIC; -- TODO
54
53 nb_burst_available : IN STD_LOGIC_VECTOR(nb_burst_available_size-1 DOWNTO 0);
55 nb_burst_available : IN STD_LOGIC_VECTOR(nb_burst_available_size-1 DOWNTO 0);
54 nb_snapshot_param : IN STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
56 nb_snapshot_param : IN STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
55 status_full : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
57 status_full : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
@@ -116,6 +118,7 BEGIN -- beh
116 PORT MAP (
118 PORT MAP (
117 clk => clk,
119 clk => clk,
118 rstn => rstn,
120 rstn => rstn,
121 run => run,
119 delta_snapshot => delta_snapshot,
122 delta_snapshot => delta_snapshot,
120 delta_f2_f1 => delta_f2_f1,
123 delta_f2_f1 => delta_f2_f1,
121 delta_f2_f0 => delta_f2_f0,
124 delta_f2_f0 => delta_f2_f0,
@@ -133,6 +136,7 BEGIN -- beh
133 PORT MAP (
136 PORT MAP (
134 clk => clk,
137 clk => clk,
135 rstn => rstn,
138 rstn => rstn,
139 run => run,
136 enable => enable_f0,
140 enable => enable_f0,
137 burst_enable => burst_f0,
141 burst_enable => burst_f0,
138 nb_snapshot_param => nb_snapshot_param,
142 nb_snapshot_param => nb_snapshot_param,
@@ -151,6 +155,7 BEGIN -- beh
151 PORT MAP (
155 PORT MAP (
152 clk => clk,
156 clk => clk,
153 rstn => rstn,
157 rstn => rstn,
158 run => run,
154 enable => enable_f1,
159 enable => enable_f1,
155 burst_enable => burst_f1,
160 burst_enable => burst_f1,
156 nb_snapshot_param => nb_snapshot_param_more_one,
161 nb_snapshot_param => nb_snapshot_param_more_one,
@@ -167,6 +172,7 BEGIN -- beh
167 PORT MAP (
172 PORT MAP (
168 clk => clk,
173 clk => clk,
169 rstn => rstn,
174 rstn => rstn,
175 run => run,
170 enable => enable_f2,
176 enable => enable_f2,
171 burst_enable => burst_f2,
177 burst_enable => burst_f2,
172 nb_snapshot_param => nb_snapshot_param_more_one,
178 nb_snapshot_param => nb_snapshot_param_more_one,
@@ -182,6 +188,7 BEGIN -- beh
182 PORT MAP (
188 PORT MAP (
183 clk => clk,
189 clk => clk,
184 rstn => rstn,
190 rstn => rstn,
191 run => run,
185 enable => enable_f3,
192 enable => enable_f3,
186 data_in => data_f3_in,
193 data_in => data_f3_in,
187 data_in_valid => data_f3_in_valid,
194 data_in_valid => data_f3_in_valid,
@@ -196,6 +203,7 BEGIN -- beh
196 PORT MAP (
203 PORT MAP (
197 HCLK => clk,
204 HCLK => clk,
198 HRESETn => rstn,
205 HRESETn => rstn,
206 run => run,
199 valid_in => valid_in(I),
207 valid_in => valid_in(I),
200 ack_in => valid_ack(I),
208 ack_in => valid_ack(I),
201 valid_out => valid_out(I),
209 valid_out => valid_out(I),
@@ -207,6 +215,7 BEGIN -- beh
207 PORT MAP (
215 PORT MAP (
208 clk => clk,
216 clk => clk,
209 rstn => rstn,
217 rstn => rstn,
218 run => run,
210 data_f0_valid => valid_out(0),
219 data_f0_valid => valid_out(0),
211 data_f1_valid => valid_out(1),
220 data_f1_valid => valid_out(1),
212 data_f2_valid => valid_out(2),
221 data_f2_valid => valid_out(2),
@@ -231,6 +240,7 BEGIN -- beh
231 PORT MAP (
240 PORT MAP (
232 clk => clk,
241 clk => clk,
233 rstn => rstn,
242 rstn => rstn,
243 run => run,
234 time_ready => time_ready,
244 time_ready => time_ready,
235 data_ready => data_ready,
245 data_ready => data_ready,
236 time_ren => time_ren, -- todo
246 time_ren => time_ren, -- todo
@@ -251,7 +261,9 BEGIN -- beh
251 nb_burst_available_size => nb_burst_available_size)
261 nb_burst_available_size => nb_burst_available_size)
252 PORT MAP (
262 PORT MAP (
253 HCLK => clk,
263 HCLK => clk,
254 HRESETn => rstn,
264 HRESETn => rstn,
265 run => run,
266
255 AHB_Master_In => AHB_Master_In,
267 AHB_Master_In => AHB_Master_In,
256 AHB_Master_Out => AHB_Master_Out,
268 AHB_Master_Out => AHB_Master_Out,
257 enable => enable, -- todo
269 enable => enable, -- todo
Show file before | Show file after | Hide comments
@@ -9,6 +9,7 ENTITY lpp_waveform_burst IS
9 PORT (
9 PORT (
10 clk : IN STD_LOGIC;
10 clk : IN STD_LOGIC;
11 rstn : IN STD_LOGIC;
11 rstn : IN STD_LOGIC;
12 run : IN STD_LOGIC;
12
13
13 enable : IN STD_LOGIC;
14 enable : IN STD_LOGIC;
14
15
@@ -31,7 +32,7 BEGIN -- beh
31 data_out_valid <= '0';
32 data_out_valid <= '0';
32 ELSIF clk'EVENT AND clk = '1' THEN
33 ELSIF clk'EVENT AND clk = '1' THEN
33 data_out <= data_in;
34 data_out <= data_in;
34 IF enable = '0' THEN
35 IF enable = '0' OR run = '0' THEN
35 data_out_valid <= '0';
36 data_out_valid <= '0';
36 ELSE
37 ELSE
37 data_out_valid <= data_in_valid;
38 data_out_valid <= data_in_valid;
Show file before | Show file after | Hide comments
@@ -53,6 +53,8 ENTITY lpp_waveform_dma IS
53 -- AMBA AHB system signals
53 -- AMBA AHB system signals
54 HCLK : IN STD_ULOGIC;
54 HCLK : IN STD_ULOGIC;
55 HRESETn : IN STD_ULOGIC;
55 HRESETn : IN STD_ULOGIC;
56 --
57 run : IN STD_LOGIC;
56 -- AMBA AHB Master Interface
58 -- AMBA AHB Master Interface
57 AHB_Master_In : IN AHB_Mst_In_Type;
59 AHB_Master_In : IN AHB_Mst_In_Type;
58 AHB_Master_Out : OUT AHB_Mst_Out_Type;
60 AHB_Master_Out : OUT AHB_Mst_Out_Type;
@@ -351,6 +353,9 BEGIN
351 PORT MAP (
353 PORT MAP (
352 HCLK => HCLK,
354 HCLK => HCLK,
353 HRESETn => HRESETn,
355 HRESETn => HRESETn,
356
357 run => run,
358
354 enable => enable(I),
359 enable => enable(I),
355 update => update_and_sel((2*I)+1 DOWNTO 2*I),
360 update => update_and_sel((2*I)+1 DOWNTO 2*I),
356 nb_burst_available => nb_burst_available,
361 nb_burst_available => nb_burst_available,
@@ -369,4 +374,4 BEGIN
369 -----------------------------------------------------------------------------
374 -----------------------------------------------------------------------------
370
375
371
376
372 END Behavioral; No newline at end of file
377 END Behavioral;
Show file before | Show file after | Hide comments
@@ -31,14 +31,15 USE ieee.numeric_std.ALL;
31
31
32 ENTITY lpp_waveform_dma_gen_valid IS
32 ENTITY lpp_waveform_dma_gen_valid IS
33 PORT (
33 PORT (
34 HCLK : IN STD_LOGIC;
34 HCLK : IN STD_LOGIC;
35 HRESETn : IN STD_LOGIC;
35 HRESETn : IN STD_LOGIC;
36
36 run : IN STD_LOGIC;
37 valid_in : IN STD_LOGIC;
37
38 ack_in : IN STD_LOGIC;
38 valid_in : IN STD_LOGIC;
39
39 ack_in : IN STD_LOGIC;
40 valid_out : OUT STD_LOGIC;
40
41 error : OUT STD_LOGIC
41 valid_out : OUT STD_LOGIC;
42 error : OUT STD_LOGIC
42 );
43 );
43 END;
44 END;
44
45
@@ -50,34 +51,43 BEGIN
50 FSM_SELECT_ADDRESS : PROCESS (HCLK, HRESETn)
51 FSM_SELECT_ADDRESS : PROCESS (HCLK, HRESETn)
51 BEGIN
52 BEGIN
52 IF HRESETn = '0' THEN
53 IF HRESETn = '0' THEN
53 state <= IDLE;
54 state <= IDLE;
54 valid_out <= '0';
55 valid_out <= '0';
55 error <= '0';
56 error <= '0';
56 ELSIF HCLK'EVENT AND HCLK = '1' THEN
57 ELSIF HCLK'EVENT AND HCLK = '1' THEN
57 CASE state IS
58 CASE state IS
58 WHEN IDLE =>
59 WHEN IDLE =>
59 valid_out <= '0';
60 valid_out <= '0';
60 error <= '0';
61 error <= '0';
61 IF valid_in = '1' THEN
62 IF run = '0' THEN
62 state <= VALID;
63 state <= IDLE;
63 valid_out <= '1';
64 valid_out <= '0';
65 ELSIF valid_in = '1' THEN
66 state <= VALID;
67 valid_out <= '1';
64 END IF;
68 END IF;
65
69
66 WHEN VALID =>
70 WHEN VALID =>
67 valid_out <= '1';
71 IF run = '0' THEN
68 error <= '0';
72 state <= IDLE;
69 IF valid_in = '1' THEN
73 valid_out <= '0';
70 IF ack_in = '1' THEN
74 error <= '0';
71 state <= VALID;
75 ELSE
72 valid_out <= '1';
76 valid_out <= '1';
73 ELSE
77 error <= '0';
74 state <= IDLE;
78 IF valid_in = '1' THEN
75 error <= '1';
79 IF ack_in = '1' THEN
76 valid_out <= '0';
80 state <= VALID;
81 valid_out <= '1';
82 ELSE
83 state <= IDLE;
84 error <= '1';
85 valid_out <= '0';
86 END IF;
87 ELSIF ack_in = '1' THEN
88 state <= IDLE;
89 valid_out <= '0';
77 END IF;
90 END IF;
78 ELSIF ack_in = '1' THEN
79 state <= IDLE;
80 valid_out <= '0';
81 END IF;
91 END IF;
82
92
83 WHEN OTHERS => NULL;
93 WHEN OTHERS => NULL;
Show file before | Show file after | Hide comments
@@ -37,6 +37,8 ENTITY lpp_waveform_dma_selectaddress IS
37 HCLK : IN STD_ULOGIC;
37 HCLK : IN STD_ULOGIC;
38 HRESETn : IN STD_ULOGIC;
38 HRESETn : IN STD_ULOGIC;
39
39
40 run : IN STD_ULOGIC;
41
40 enable : IN STD_LOGIC;
42 enable : IN STD_LOGIC;
41 update : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
43 update : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
42
44
@@ -78,55 +80,80 BEGIN
78 status_full_err <= '0';
80 status_full_err <= '0';
79 update_r <= "00";
81 update_r <= "00";
80 ELSIF HCLK'EVENT AND HCLK = '1' THEN
82 ELSIF HCLK'EVENT AND HCLK = '1' THEN
81 update_r <= update;
83 update_r <= update;
82 CASE state IS
84 CASE state IS
83 WHEN IDLE =>
85 WHEN IDLE =>
84 IF enable = '0' THEN
86 IF run = '0' THEN
85 state <= UPDATED;
87 state <= IDLE;
86 elsIF update_s = '1' THEN
88 address <= (OTHERS => '0');
87 state <= ADD;
89 nb_send <= (OTHERS => '0');
90 status_full <= '0';
91 status_full_err <= '0';
92 update_r <= "00";
93 ELSE
94 IF enable = '0' THEN
95 state <= UPDATED;
96 ELSIF update_s = '1' THEN
97 state <= ADD;
98 END IF;
88 END IF;
99 END IF;
89
100
90 WHEN ADD =>
101 WHEN ADD =>
91 IF UNSIGNED(nb_send_next) < UNSIGNED(nb_burst_available) THEN
102 IF run = '0' THEN
92 state <= IDLE;
103 state <= IDLE;
93 IF update_r = "10" THEN
104 ELSE
94 address <= STD_LOGIC_VECTOR(UNSIGNED(address) + 64);
105 IF UNSIGNED(nb_send_next) < UNSIGNED(nb_burst_available) THEN
95 nb_send <= nb_send_next;
106 state <= IDLE;
96 ELSIF update_r = "01" THEN
107 IF update_r = "10" THEN
97 address <= STD_LOGIC_VECTOR(UNSIGNED(address) + 4);
108 address <= STD_LOGIC_VECTOR(UNSIGNED(address) + 64);
109 nb_send <= nb_send_next;
110 ELSIF update_r = "01" THEN
111 address <= STD_LOGIC_VECTOR(UNSIGNED(address) + 4);
112 END IF;
113 ELSE
114 state <= FULL;
115 nb_send <= (OTHERS => '0');
116 status_full <= '1';
98 END IF;
117 END IF;
99 ELSE
100 state <= FULL;
101 nb_send <= (OTHERS => '0');
102 status_full <= '1';
103 END IF;
118 END IF;
104
119
105 WHEN FULL =>
120 WHEN FULL =>
106 status_full <= '0';
121 IF run = '0' THEN
107 IF status_full_ack = '1' THEN
122 state <= IDLE;
108 IF update_s = '1' THEN
109 status_full_err <= '1';
110 END IF;
111 state <= UPDATED;
112 ELSE
123 ELSE
113 IF update_s = '1' THEN
124 status_full <= '0';
114 status_full_err <= '1';
125 IF status_full_ack = '1' THEN
115 state <= ERR;
126 IF update_s = '1' THEN
127 status_full_err <= '1';
128 END IF;
129 state <= UPDATED;
130 ELSE
131 IF update_s = '1' THEN
132 status_full_err <= '1';
133 state <= ERR;
134 END IF;
116 END IF;
135 END IF;
117 END IF;
136 END IF;
118
137
119 WHEN ERR =>
138 WHEN ERR =>
120 status_full_err <= '0';
139 IF run = '0' THEN
121 IF status_full_ack = '1' THEN
140 state <= IDLE;
122 state <= UPDATED;
141 ELSE
142 status_full_err <= '0';
143 IF status_full_ack = '1' THEN
144 state <= UPDATED;
145 END IF;
123 END IF;
146 END IF;
124
147
125 WHEN UPDATED =>
148 WHEN UPDATED =>
126 status_full_err <= '0';
149 IF run = '0' THEN
127 address <= addr_data_reg;
150 state <= IDLE;
128 IF enable = '1' THEN
151 ELSE
129 state <= IDLE;
152 status_full_err <= '0';
153 address <= addr_data_reg;
154 IF enable = '1' THEN
155 state <= IDLE;
156 END IF;
130 END IF;
157 END IF;
131
158
132 WHEN OTHERS => NULL;
159 WHEN OTHERS => NULL;
Show file before | Show file after | Hide comments
@@ -37,6 +37,8 ENTITY lpp_waveform_fifo IS
37 PORT(
37 PORT(
38 clk : IN STD_LOGIC;
38 clk : IN STD_LOGIC;
39 rstn : IN STD_LOGIC;
39 rstn : IN STD_LOGIC;
40 ---------------------------------------------------------------------------
41 run : IN STD_LOGIC;
40
42
41 ---------------------------------------------------------------------------
43 ---------------------------------------------------------------------------
42 time_ready : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); -- FIFO_DATA occupancy is greater than 16 * 32b
44 time_ready : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); -- FIFO_DATA occupancy is greater than 16 * 32b
@@ -120,6 +122,7 BEGIN
120 PORT MAP (
122 PORT MAP (
121 clk => clk,
123 clk => clk,
122 rstn => rstn,
124 rstn => rstn,
125 run => run,
123 ren => time_ren(I),
126 ren => time_ren(I),
124 wen => time_wen(I),
127 wen => time_wen(I),
125 mem_re => time_mem_ren(I),
128 mem_re => time_mem_ren(I),
@@ -138,6 +141,7 BEGIN
138 PORT MAP (
141 PORT MAP (
139 clk => clk,
142 clk => clk,
140 rstn => rstn,
143 rstn => rstn,
144 run => run,
141 ren => data_ren(I),
145 ren => data_ren(I),
142 wen => data_wen(I),
146 wen => data_wen(I),
143 mem_re => data_mem_ren(I),
147 mem_re => data_mem_ren(I),
Show file before | Show file after | Hide comments
@@ -33,7 +33,8 ENTITY lpp_waveform_fifo_arbiter IS
33 PORT(
33 PORT(
34 clk : IN STD_LOGIC;
34 clk : IN STD_LOGIC;
35 rstn : IN STD_LOGIC;
35 rstn : IN STD_LOGIC;
36
36 ---------------------------------------------------------------------------
37 run : IN STD_LOGIC;
37 ---------------------------------------------------------------------------
38 ---------------------------------------------------------------------------
38 data_f0_valid : IN STD_LOGIC;
39 data_f0_valid : IN STD_LOGIC;
39 data_f1_valid : IN STD_LOGIC;
40 data_f1_valid : IN STD_LOGIC;
@@ -111,7 +112,7 BEGIN
111 data_wen <= (OTHERS => '1');
112 data_wen <= (OTHERS => '1');
112 data <= (OTHERS => '0');
113 data <= (OTHERS => '0');
113 data_temp <= (OTHERS => '0');
114 data_temp <= (OTHERS => '0');
114 IF data_ready_to_go = '1' THEN
115 IF data_ready_to_go = '1' AND run = '1' THEN
115 state <= T1;
116 state <= T1;
116 data_valid_ack <= data_valid_selected;
117 data_valid_ack <= data_valid_selected;
117 time_wen <= NOT data_valid_selected;
118 time_wen <= NOT data_valid_selected;
@@ -120,20 +121,32 BEGIN
120 data_temp <= data_selected(159 DOWNTO 32);
121 data_temp <= data_selected(159 DOWNTO 32);
121 END IF;
122 END IF;
122 WHEN T1 =>
123 WHEN T1 =>
123 state <= T2;
124 IF run = '0' THEN
125 state <= IDLE;
126 ELSE
127 state <= T2;
128 END IF;
124 data_valid_ack <= (OTHERS => '0');
129 data_valid_ack <= (OTHERS => '0');
125 data <= data_temp(31 DOWNTO 0);
130 data <= data_temp(31 DOWNTO 0);
126 data_temp(32*3-1 DOWNTO 0) <= data_temp(32*4-1 DOWNTO 32);
131 data_temp(32*3-1 DOWNTO 0) <= data_temp(32*4-1 DOWNTO 32);
127
132
128 WHEN T2 =>
133 WHEN T2 =>
129 state <= D1;
134 IF run = '0' THEN
135 state <= IDLE;
136 ELSE
137 state <= D1;
138 END IF;
130 time_wen <= (OTHERS => '1');
139 time_wen <= (OTHERS => '1');
131 data_wen <= time_en_temp;
140 data_wen <= time_en_temp;
132 data <= data_temp(31 DOWNTO 0);
141 data <= data_temp(31 DOWNTO 0);
133 data_temp(32*3-1 DOWNTO 0) <= data_temp(32*4-1 DOWNTO 32);
142 data_temp(32*3-1 DOWNTO 0) <= data_temp(32*4-1 DOWNTO 32);
134
143
135 WHEN D1 =>
144 WHEN D1 =>
136 state <= D2;
145 IF run = '0' THEN
146 state <= IDLE;
147 ELSE
148 state <= D2;
149 END IF;
137 data <= data_temp(31 DOWNTO 0);
150 data <= data_temp(31 DOWNTO 0);
138 data_temp(32*3-1 DOWNTO 0) <= data_temp(32*4-1 DOWNTO 32);
151 data_temp(32*3-1 DOWNTO 0) <= data_temp(32*4-1 DOWNTO 32);
139
152
Show file before | Show file after | Hide comments
@@ -39,6 +39,8 ENTITY lpp_waveform_fifo_ctrl IS
39 PORT(
39 PORT(
40 clk : IN STD_LOGIC;
40 clk : IN STD_LOGIC;
41 rstn : IN STD_LOGIC;
41 rstn : IN STD_LOGIC;
42
43 run : IN STD_LOGIC;
42
44
43 ren : IN STD_LOGIC;
45 ren : IN STD_LOGIC;
44 wen : IN STD_LOGIC;
46 wen : IN STD_LOGIC;
@@ -92,12 +94,15 BEGIN
92 Raddr_vect <= 0;
94 Raddr_vect <= 0;
93 sempty <= '1';
95 sempty <= '1';
94 ELSIF(clk'EVENT AND clk = '1')then
96 ELSIF(clk'EVENT AND clk = '1')then
95 sEmpty <= sempty_s;
97 IF run = '0' THEN
96
98 Raddr_vect <= 0;
97 IF(sREN = '0' and sempty = '0')then
99 sempty <= '1';
98 Raddr_vect <= Raddr_vect_s;
100 ELSE
101 sEmpty <= sempty_s;
102 IF(sREN = '0' and sempty = '0')then
103 Raddr_vect <= Raddr_vect_s;
104 END IF;
99 END IF;
105 END IF;
100
101 END IF;
106 END IF;
102 END PROCESS;
107 END PROCESS;
103
108
@@ -118,13 +123,16 BEGIN
118 IF(rstn = '0')then
123 IF(rstn = '0')then
119 Waddr_vect <= 0;
124 Waddr_vect <= 0;
120 sfull <= '0';
125 sfull <= '0';
121 ELSIF(clk'EVENT AND clk = '1')then
126 ELSIF(clk'EVENT AND clk = '1')THEN
122 sfull <= sfull_s;
127 IF run = '0' THEN
123
128 Waddr_vect <= 0;
124 IF(sWEN = '0' and sfull = '0')THEN
129 sfull <= '0';
125 Waddr_vect <= Waddr_vect_s;
130 ELSE
131 sfull <= sfull_s;
132 IF(sWEN = '0' and sfull = '0')THEN
133 Waddr_vect <= Waddr_vect_s;
134 END IF;
126 END IF;
135 END IF;
127
128 END IF;
136 END IF;
129 END PROCESS;
137 END PROCESS;
130
138
@@ -168,4 +176,3 END ARCHITECTURE;
168
176
169
177
170
178
171
Show file before | Show file after | Hide comments
@@ -21,6 +21,7 PACKAGE lpp_waveform_pkg IS
21 PORT (
21 PORT (
22 clk : IN STD_LOGIC;
22 clk : IN STD_LOGIC;
23 rstn : IN STD_LOGIC;
23 rstn : IN STD_LOGIC;
24 run : IN STD_LOGIC;
24 enable : IN STD_LOGIC;
25 enable : IN STD_LOGIC;
25 burst_enable : IN STD_LOGIC;
26 burst_enable : IN STD_LOGIC;
26 nb_snapshot_param : IN STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
27 nb_snapshot_param : IN STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
@@ -37,6 +38,7 PACKAGE lpp_waveform_pkg IS
37 PORT (
38 PORT (
38 clk : IN STD_LOGIC;
39 clk : IN STD_LOGIC;
39 rstn : IN STD_LOGIC;
40 rstn : IN STD_LOGIC;
41 run : IN STD_LOGIC;
40 enable : IN STD_LOGIC;
42 enable : IN STD_LOGIC;
41 data_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
43 data_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
42 data_in_valid : IN STD_LOGIC;
44 data_in_valid : IN STD_LOGIC;
@@ -52,6 +54,7 PACKAGE lpp_waveform_pkg IS
52 PORT (
54 PORT (
53 clk : IN STD_LOGIC;
55 clk : IN STD_LOGIC;
54 rstn : IN STD_LOGIC;
56 rstn : IN STD_LOGIC;
57 run : IN STD_LOGIC;
55 delta_snapshot : IN STD_LOGIC_VECTOR(delta_snapshot_size-1 DOWNTO 0);
58 delta_snapshot : IN STD_LOGIC_VECTOR(delta_snapshot_size-1 DOWNTO 0);
56 delta_f2_f1 : IN STD_LOGIC_VECTOR(delta_f2_f1_size-1 DOWNTO 0);
59 delta_f2_f1 : IN STD_LOGIC_VECTOR(delta_f2_f1_size-1 DOWNTO 0);
57 delta_f2_f0 : IN STD_LOGIC_VECTOR(delta_f2_f0_size-1 DOWNTO 0);
60 delta_f2_f0 : IN STD_LOGIC_VECTOR(delta_f2_f0_size-1 DOWNTO 0);
@@ -91,6 +94,7 PACKAGE lpp_waveform_pkg IS
91 burst_f0 : IN STD_LOGIC;
94 burst_f0 : IN STD_LOGIC;
92 burst_f1 : IN STD_LOGIC;
95 burst_f1 : IN STD_LOGIC;
93 burst_f2 : IN STD_LOGIC;
96 burst_f2 : IN STD_LOGIC;
97 run : IN STD_LOGIC;
94 nb_burst_available : IN STD_LOGIC_VECTOR(nb_burst_available_size-1 DOWNTO 0);
98 nb_burst_available : IN STD_LOGIC_VECTOR(nb_burst_available_size-1 DOWNTO 0);
95 nb_snapshot_param : IN STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
99 nb_snapshot_param : IN STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
96 status_full : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
100 status_full : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
@@ -132,6 +136,7 PACKAGE lpp_waveform_pkg IS
132 PORT (
136 PORT (
133 HCLK : IN STD_ULOGIC;
137 HCLK : IN STD_ULOGIC;
134 HRESETn : IN STD_ULOGIC;
138 HRESETn : IN STD_ULOGIC;
139 run : IN STD_LOGIC;
135 enable : IN STD_LOGIC;
140 enable : IN STD_LOGIC;
136 update : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
141 update : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
137 nb_burst_available : IN STD_LOGIC_VECTOR(nb_burst_available_size-1 DOWNTO 0);
142 nb_burst_available : IN STD_LOGIC_VECTOR(nb_burst_available_size-1 DOWNTO 0);
@@ -146,6 +151,7 PACKAGE lpp_waveform_pkg IS
146 PORT (
151 PORT (
147 HCLK : IN STD_LOGIC;
152 HCLK : IN STD_LOGIC;
148 HRESETn : IN STD_LOGIC;
153 HRESETn : IN STD_LOGIC;
154 run : IN STD_LOGIC;
149 valid_in : IN STD_LOGIC;
155 valid_in : IN STD_LOGIC;
150 ack_in : IN STD_LOGIC;
156 ack_in : IN STD_LOGIC;
151 valid_out : OUT STD_LOGIC;
157 valid_out : OUT STD_LOGIC;
@@ -161,6 +167,7 PACKAGE lpp_waveform_pkg IS
161 PORT (
167 PORT (
162 HCLK : IN STD_ULOGIC;
168 HCLK : IN STD_ULOGIC;
163 HRESETn : IN STD_ULOGIC;
169 HRESETn : IN STD_ULOGIC;
170 run : IN STD_LOGIC;
164 AHB_Master_In : IN AHB_Mst_In_Type;
171 AHB_Master_In : IN AHB_Mst_In_Type;
165 AHB_Master_Out : OUT AHB_Mst_Out_Type;
172 AHB_Master_Out : OUT AHB_Mst_Out_Type;
166 enable : IN STD_LOGIC_VECTOR(3 DOWNTO 0); -- todo
173 enable : IN STD_LOGIC_VECTOR(3 DOWNTO 0); -- todo
@@ -196,6 +203,7 PACKAGE lpp_waveform_pkg IS
196 PORT (
203 PORT (
197 clk : IN STD_LOGIC;
204 clk : IN STD_LOGIC;
198 rstn : IN STD_LOGIC;
205 rstn : IN STD_LOGIC;
206 run : IN STD_LOGIC;
199 ren : IN STD_LOGIC;
207 ren : IN STD_LOGIC;
200 wen : IN STD_LOGIC;
208 wen : IN STD_LOGIC;
201 mem_re : OUT STD_LOGIC;
209 mem_re : OUT STD_LOGIC;
@@ -211,6 +219,7 PACKAGE lpp_waveform_pkg IS
211 PORT (
219 PORT (
212 clk : IN STD_LOGIC;
220 clk : IN STD_LOGIC;
213 rstn : IN STD_LOGIC;
221 rstn : IN STD_LOGIC;
222 run : IN STD_LOGIC;
214 data_f0_valid : IN STD_LOGIC;
223 data_f0_valid : IN STD_LOGIC;
215 data_f1_valid : IN STD_LOGIC;
224 data_f1_valid : IN STD_LOGIC;
216 data_f2_valid : IN STD_LOGIC;
225 data_f2_valid : IN STD_LOGIC;
@@ -232,6 +241,7 PACKAGE lpp_waveform_pkg IS
232 PORT (
241 PORT (
233 clk : IN STD_LOGIC;
242 clk : IN STD_LOGIC;
234 rstn : IN STD_LOGIC;
243 rstn : IN STD_LOGIC;
244 run : IN STD_LOGIC;
235 time_ready : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
245 time_ready : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
236 data_ready : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
246 data_ready : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
237 time_ren : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
247 time_ren : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
Show file before | Show file after | Hide comments
@@ -11,6 +11,7 ENTITY lpp_waveform_snapshot IS
11 PORT (
11 PORT (
12 clk : IN STD_LOGIC;
12 clk : IN STD_LOGIC;
13 rstn : IN STD_LOGIC;
13 rstn : IN STD_LOGIC;
14 run : IN STD_LOGIC;
14
15
15 enable : IN STD_LOGIC;
16 enable : IN STD_LOGIC;
16 burst_enable : IN STD_LOGIC;
17 burst_enable : IN STD_LOGIC;
@@ -39,7 +40,7 BEGIN -- beh
39 counter_points_snapshot <= 0;
40 counter_points_snapshot <= 0;
40 ELSIF clk'EVENT AND clk = '1' THEN
41 ELSIF clk'EVENT AND clk = '1' THEN
41 data_out <= data_in;
42 data_out <= data_in;
42 IF enable = '0' THEN
43 IF enable = '0' OR run = '0' THEN
43 data_out_valid <= '0';
44 data_out_valid <= '0';
44 counter_points_snapshot <= 0;
45 counter_points_snapshot <= 0;
45 ELSE
46 ELSE
Show file before | Show file after | Hide comments
@@ -10,17 +10,19 ENTITY lpp_waveform_snapshot_controler I
10 delta_f2_f1_size : INTEGER := 10);
10 delta_f2_f1_size : INTEGER := 10);
11
11
12 PORT (
12 PORT (
13 clk : IN STD_LOGIC;
13 clk : IN STD_LOGIC;
14 rstn : IN STD_LOGIC;
14 rstn : IN STD_LOGIC;
15 --
16 run : IN STD_LOGIC;
15 --config
17 --config
16 delta_snapshot : IN STD_LOGIC_VECTOR(delta_snapshot_size-1 DOWNTO 0);
18 delta_snapshot : IN STD_LOGIC_VECTOR(delta_snapshot_size-1 DOWNTO 0);
17 delta_f2_f1 : IN STD_LOGIC_VECTOR(delta_f2_f1_size-1 DOWNTO 0);
19 delta_f2_f1 : IN STD_LOGIC_VECTOR(delta_f2_f1_size-1 DOWNTO 0);
18 delta_f2_f0 : IN STD_LOGIC_VECTOR(delta_f2_f0_size-1 DOWNTO 0);
20 delta_f2_f0 : IN STD_LOGIC_VECTOR(delta_f2_f0_size-1 DOWNTO 0);
19
21
20 --input
22 --input
21 coarse_time_0 : IN STD_LOGIC;
23 coarse_time_0 : IN STD_LOGIC;
22 data_f0_in_valid : IN STD_LOGIC;
24 data_f0_in_valid : IN STD_LOGIC;
23 data_f2_in_valid : IN STD_LOGIC;
25 data_f2_in_valid : IN STD_LOGIC;
24 --output
26 --output
25 start_snapshot_f0 : OUT STD_LOGIC;
27 start_snapshot_f0 : OUT STD_LOGIC;
26 start_snapshot_f1 : OUT STD_LOGIC;
28 start_snapshot_f1 : OUT STD_LOGIC;
@@ -33,82 +35,94 ARCHITECTURE beh OF lpp_waveform_snapsho
33 SIGNAL counter_delta_snapshot : INTEGER;
35 SIGNAL counter_delta_snapshot : INTEGER;
34 SIGNAL counter_delta_f0 : INTEGER;
36 SIGNAL counter_delta_f0 : INTEGER;
35
37
36 SIGNAL coarse_time_0_r : STD_LOGIC;
38 SIGNAL coarse_time_0_r : STD_LOGIC;
37 SIGNAL start_snapshot_f2_temp : STD_LOGIC;
39 SIGNAL start_snapshot_f2_temp : STD_LOGIC;
38 SIGNAL start_snapshot_fothers_temp : STD_LOGIC;
40 SIGNAL start_snapshot_fothers_temp : STD_LOGIC;
39 BEGIN -- beh
41 BEGIN -- beh
40
42
41 PROCESS (clk, rstn)
43 PROCESS (clk, rstn)
42 BEGIN
44 BEGIN
43 IF rstn = '0' THEN
45 IF rstn = '0' THEN
44 start_snapshot_f0 <= '0';
46 start_snapshot_f0 <= '0';
45 start_snapshot_f1 <= '0';
47 start_snapshot_f1 <= '0';
46 start_snapshot_f2 <= '0';
48 start_snapshot_f2 <= '0';
47 counter_delta_snapshot <= 0;
49 counter_delta_snapshot <= 0;
48 counter_delta_f0 <= 0;
50 counter_delta_f0 <= 0;
49 coarse_time_0_r <= '0';
51 coarse_time_0_r <= '0';
50 start_snapshot_f2_temp <= '0';
52 start_snapshot_f2_temp <= '0';
51 start_snapshot_fothers_temp <= '0';
53 start_snapshot_fothers_temp <= '0';
52 ELSIF clk'EVENT AND clk = '1' THEN
54 ELSIF clk'EVENT AND clk = '1' THEN
53 IF counter_delta_snapshot = UNSIGNED(delta_snapshot) THEN
55 IF run = '0' THEN
54 start_snapshot_f2_temp <= '1';
56 start_snapshot_f0 <= '0';
57 start_snapshot_f1 <= '0';
58 start_snapshot_f2 <= '0';
59 counter_delta_snapshot <= 0;
60 counter_delta_f0 <= 0;
61 coarse_time_0_r <= '0';
62 start_snapshot_f2_temp <= '0';
63 start_snapshot_fothers_temp <= '0';
55 ELSE
64 ELSE
56 start_snapshot_f2_temp <= '0';
65 IF counter_delta_snapshot = UNSIGNED(delta_snapshot) THEN
57 END IF;
66 start_snapshot_f2_temp <= '1';
58 -------------------------------------------------------------------------
67 ELSE
59 IF counter_delta_snapshot = UNSIGNED(delta_snapshot) AND start_snapshot_f2_temp = '0' THEN
68 start_snapshot_f2_temp <= '0';
60 start_snapshot_f2 <= '1';
69 END IF;
61 ELSE
70 -------------------------------------------------------------------------
62 start_snapshot_f2 <= '0';
71 IF counter_delta_snapshot = UNSIGNED(delta_snapshot) AND start_snapshot_f2_temp = '0' THEN
63 END IF;
72 start_snapshot_f2 <= '1';
64 -------------------------------------------------------------------------
65 coarse_time_0_r <= coarse_time_0;
66 IF coarse_time_0 = NOT coarse_time_0_r THEN --AND coarse_time_0 = '1' THEN
67 IF counter_delta_snapshot = 0 THEN
68 counter_delta_snapshot <= to_integer(UNSIGNED(delta_snapshot));
69 ELSE
73 ELSE
70 counter_delta_snapshot <= counter_delta_snapshot - 1;
74 start_snapshot_f2 <= '0';
71 END IF;
75 END IF;
72 END IF;
76 -------------------------------------------------------------------------
73
77 coarse_time_0_r <= coarse_time_0;
74
78 IF coarse_time_0 = NOT coarse_time_0_r THEN --AND coarse_time_0 = '1' THEN
75 -------------------------------------------------------------------------
79 IF counter_delta_snapshot = 0 THEN
80 counter_delta_snapshot <= to_integer(UNSIGNED(delta_snapshot));
81 ELSE
82 counter_delta_snapshot <= counter_delta_snapshot - 1;
83 END IF;
84 END IF;
76
85
77
86
78
87 -------------------------------------------------------------------------
79 IF counter_delta_f0 = UNSIGNED(delta_f2_f1) THEN
88
80 start_snapshot_f1 <= '1';
89
81 ELSE
90
82 start_snapshot_f1 <= '0';
91 IF counter_delta_f0 = UNSIGNED(delta_f2_f1) THEN
83 END IF;
92 start_snapshot_f1 <= '1';
93 ELSE
94 start_snapshot_f1 <= '0';
95 END IF;
96
97 IF counter_delta_f0 = 1 THEN --UNSIGNED(delta_f2_f0) THEN
98 start_snapshot_f0 <= '1';
99 ELSE
100 start_snapshot_f0 <= '0';
101 END IF;
84
102
85 IF counter_delta_f0 = 1 THEN --UNSIGNED(delta_f2_f0) THEN
103 IF counter_delta_snapshot = UNSIGNED(delta_snapshot)
86 start_snapshot_f0 <= '1';
104 AND start_snapshot_f2_temp = '0'
87 ELSE
105 THEN --
88 start_snapshot_f0 <= '0';
106 start_snapshot_fothers_temp <= '1';
107 ELSIF counter_delta_f0 > 0 THEN
108 start_snapshot_fothers_temp <= '0';
109 END IF;
110
111
112 -------------------------------------------------------------------------
113 IF (start_snapshot_fothers_temp = '1' OR (counter_delta_snapshot = UNSIGNED(delta_snapshot) AND start_snapshot_f2_temp = '0')) AND data_f2_in_valid = '1' THEN
114 --counter_delta_snapshot = UNSIGNED(delta_snapshot) AND start_snapshot_f2_temp = '0' THEN --
115 --counter_delta_snapshot = UNSIGNED(delta_snapshot) THEN
116 counter_delta_f0 <= to_integer(UNSIGNED(delta_f2_f0)); --0;
117 ELSE
118 IF ((counter_delta_f0 > 0) AND (data_f0_in_valid = '1')) THEN --<= UNSIGNED(delta_f2_f0) THEN
119 counter_delta_f0 <= counter_delta_f0 - 1; --counter_delta_f0 + 1;
120 END IF;
121 END IF;
122 -------------------------------------------------------------------------
123
89 END IF;
124 END IF;
90
91 IF counter_delta_snapshot = UNSIGNED(delta_snapshot)
92 AND start_snapshot_f2_temp = '0'
93 THEN --
94 start_snapshot_fothers_temp <= '1';
95 ELSIF counter_delta_f0 > 0 THEN
96 start_snapshot_fothers_temp <= '0';
97 END IF;
98
99
100 -------------------------------------------------------------------------
101 IF (start_snapshot_fothers_temp = '1' OR (counter_delta_snapshot = UNSIGNED(delta_snapshot) AND start_snapshot_f2_temp = '0')) AND data_f2_in_valid = '1' THEN
102 --counter_delta_snapshot = UNSIGNED(delta_snapshot) AND start_snapshot_f2_temp = '0' THEN --
103 --counter_delta_snapshot = UNSIGNED(delta_snapshot) THEN
104 counter_delta_f0 <= to_integer(UNSIGNED(delta_f2_f0)); --0;
105 ELSE
106 IF (( counter_delta_f0 > 0 ) AND ( data_f0_in_valid = '1' )) THEN --<= UNSIGNED(delta_f2_f0) THEN
107 counter_delta_f0 <= counter_delta_f0 - 1;--counter_delta_f0 + 1;
108 END IF;
109 END IF;
110 -------------------------------------------------------------------------
111 END IF;
125 END IF;
112 END PROCESS;
126 END PROCESS;
113
127
114 END beh; No newline at end of file
128 END beh;
Show file before | Show file after | Hide comments
@@ -1,13 +1,12
1 lpp_waveform_pkg.vhd
2 lpp_waveform.vhd
1 lpp_waveform_burst.vhd
3 lpp_waveform_burst.vhd
4 lpp_waveform_dma.vhd
2 lpp_waveform_dma_genvalid.vhd
5 lpp_waveform_dma_genvalid.vhd
3 lpp_waveform_dma_selectaddress.vhd
6 lpp_waveform_dma_selectaddress.vhd
4 lpp_waveform_dma_send_Nword.vhd
7 lpp_waveform_dma_send_Nword.vhd
5 lpp_waveform_dma.vhd
8 lpp_waveform_fifo.vhd
6 lpp_waveform_fifo_arbiter.vhd
9 lpp_waveform_fifo_arbiter.vhd
7 lpp_waveform_fifo_ctrl.vhd
10 lpp_waveform_fifo_ctrl.vhd
8 lpp_waveform_fifo.vhd
11 lpp_waveform_snapshot.vhd
9 lpp_waveform_pkg.vhd
10 lpp_waveform_snapshot_controler.vhd
12 lpp_waveform_snapshot_controler.vhd
11 lpp_waveform_snapshot.vhd
12 lpp_waveform_valid_ack.vhd
13 lpp_waveform.vhd
Show file before | Show file after | Hide comments
1 NO CONTENT: file was removed, binary diff hidden
NO CONTENT: file was removed, binary diff hidden
General Comments 0
You need to be logged in to leave comments. Login now