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Synthesis File Updated
pellion -
r229:8ff242376ddf JC
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1 NO CONTENT: new file 100644, binary diff hidden
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@@ -1,23 +1,23
1 ./amba_lcd_16x2_ctrlr
1 ./amba_lcd_16x2_ctrlr
2 ./dsp/iir_filter
3 ./dsp/lpp_downsampling
4 ./dsp/lpp_fft
5 ./general_purpose
2 ./general_purpose
6 ./general_purpose/lpp_AMR
3 ./general_purpose/lpp_AMR
7 ./general_purpose/lpp_balise
4 ./general_purpose/lpp_balise
8 ./general_purpose/lpp_delay
5 ./general_purpose/lpp_delay
6 ./lpp_amba
7 ./dsp/iir_filter
8 ./dsp/lpp_downsampling
9 ./dsp/lpp_fft
9 ./lfr_time_management
10 ./lfr_time_management
10 ./lpp_ad_Conv
11 ./lpp_ad_Conv
11 ./lpp_amba
12 ./lpp_bootloader
12 ./lpp_bootloader
13 ./lpp_cna
13 ./lpp_cna
14 ./lpp_demux
14 ./lpp_demux
15 ./lpp_dma
16 ./lpp_Header
15 ./lpp_Header
17 ./lpp_matrix
16 ./lpp_matrix
18 ./lpp_memory
17 ./lpp_memory
19 ./lpp_top_lfr
18 ./lpp_dma
20 ./lpp_uart
19 ./lpp_uart
21 ./lpp_usb
20 ./lpp_usb
22 ./lpp_waveform
21 ./lpp_waveform
23 ./Rocket_PCM_Encoder
22 ./lpp_top_lfr
23 ./lpp_Header
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@@ -1,19 +1,8
1 APB_IIR_CEL.vhd
1 iir_filter.vhd
2 APB_IIR_Filter.vhd
3 FILTERcfg.vhd
2 FILTERcfg.vhd
4 FilterCTRLR.vhd
3 RAM.vhd
5 FILTER_RAM_CTRLR.vhd
4 RAM_CEL.vhd
6 FILTER.vhd
5 RAM_CTRLR_v2.vhd
7 IIR_CEL_CTRLR_v2_CONTROL.vhd
6 IIR_CEL_CTRLR_v2_CONTROL.vhd
8 IIR_CEL_CTRLR_v2_DATAFLOW.vhd
7 IIR_CEL_CTRLR_v2_DATAFLOW.vhd
9 IIR_CEL_CTRLR_v2.vhd
8 IIR_CEL_CTRLR_v2.vhd
10 IIR_CEL_CTRLR.vhd
11 IIR_CEL_FILTER.vhd
12 iir_filter.vhd
13 RAM_CEL_N.vhd
14 RAM_CEL.vhd
15 RAM_CTRLR2.vhd
16 RAM_CTRLR_v2.vhd
17 RAM.vhd
18 Top_Filtre_IIR.vhd
19 Top_IIR.vhd
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@@ -1,11 +1,16
1 APB_FFT_half.vhd
1 lpp_fft.vhd
2 actar.vhd
3 actram.vhd
4 CoreFFT.vhd
5 fft_components.vhd
6 fftDp.vhd
7 fftSm.vhd
8 primitives.vhd
9 twiddle.vhd
2 APB_FFT.vhd
10 APB_FFT.vhd
3 Driver_FFT.vhd
11 Driver_FFT.vhd
12 FFT.vhd
4 FFTamont.vhd
13 FFTamont.vhd
5 FFTaval.vhd
14 FFTaval.vhd
6 FFT.vhd
7 FFT.vhd.bak
8 Flag_Extremum.vhd
15 Flag_Extremum.vhd
9 Flag_Extremum.vhd.bak
10 Linker_FFT.vhd
16 Linker_FFT.vhd
11 lpp_fft.vhd
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@@ -1,28 +1,21
1 Adder_V0.vhd
1 general_purpose.vhd
2 Adder.vhd
3 ADDRcntr.vhd
2 ADDRcntr.vhd
4 ALU_V0.vhd
5 ALU_V0.vhd~
6 ALU.vhd
3 ALU.vhd
4 Adder.vhd
7 Clk_Divider2.vhd
5 Clk_Divider2.vhd
8 Clk_Divider2.vhd~
9 Clk_divider.vhd
6 Clk_divider.vhd
10 general_purpose.vhd
7 MAC.vhd
11 general_purpose.vhd~
12 MAC_CONTROLER.vhd
8 MAC_CONTROLER.vhd
13 MAC_MUX2.vhd
14 MAC_MUX.vhd
9 MAC_MUX.vhd
10 MAC_MUX2.vhd
15 MAC_REG.vhd
11 MAC_REG.vhd
16 MAC_V0.vhd
17 MAC.vhd
18 Multiplier.vhd
19 MUX2.vhd
12 MUX2.vhd
20 MUXN.vhd
13 MUXN.vhd
14 Multiplier.vhd
21 REG.vhd
15 REG.vhd
16 SYNC_FF.vhd
22 Shifter.vhd
17 Shifter.vhd
23 SYNC_FF.vhd
24 TwoComplementer.vhd
18 TwoComplementer.vhd
25 lpp_front_to_level.vhd
19 lpp_front_to_level.vhd
26 lpp_front_detection.vhd
20 lpp_front_detection.vhd
27 SYNC_VALID_BIT.vhd
21 SYNC_VALID_BIT.vhd
28
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@@ -1,4 +1,4
1 apb_lfr_time_management.vhd
1 lpp_counter.vhd
2 lpp_counter.vhd
2 apb_lfr_time_management.vhd
3 lfr_time_management.vhd
3 lfr_time_management.vhd
4 lpp_lfr_time_management.vhd
4 lpp_lfr_time_management.vhd
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@@ -50,6 +50,78 PACKAGE lpp_ad_conv IS
50
50
51 TYPE Samples IS ARRAY(NATURAL RANGE <>) OF STD_LOGIC_VECTOR(15 DOWNTO 0);
51 TYPE Samples IS ARRAY(NATURAL RANGE <>) OF STD_LOGIC_VECTOR(15 DOWNTO 0);
52
52
53 -----------------------------------------------------------------------------
54 -----------------------------------------------------------------------------
55 SUBTYPE Samples24 IS STD_LOGIC_VECTOR(23 DOWNTO 0);
56
57 SUBTYPE Samples16 IS STD_LOGIC_VECTOR(15 DOWNTO 0);
58
59 SUBTYPE Samples14 IS STD_LOGIC_VECTOR(13 DOWNTO 0);
60
61 SUBTYPE Samples12 IS STD_LOGIC_VECTOR(11 DOWNTO 0);
62
63 SUBTYPE Samples10 IS STD_LOGIC_VECTOR(9 DOWNTO 0);
64
65 SUBTYPE Samples8 IS STD_LOGIC_VECTOR(7 DOWNTO 0);
66
67 TYPE Samples24v IS ARRAY(NATURAL RANGE <>) OF Samples24;
68
69 TYPE Samples16v IS ARRAY(NATURAL RANGE <>) OF Samples16;
70
71 TYPE Samples14v IS ARRAY(NATURAL RANGE <>) OF Samples14;
72
73 TYPE Samples12v IS ARRAY(NATURAL RANGE <>) OF Samples12;
74
75 TYPE Samples10v IS ARRAY(NATURAL RANGE <>) OF Samples10;
76
77 TYPE Samples8v IS ARRAY(NATURAL RANGE <>) OF Samples8;
78
79 COMPONENT RHF1401_drvr IS
80 GENERIC(
81 ChanelCount : INTEGER := 8);
82 PORT (
83 cnv_clk : IN STD_LOGIC;
84 clk : IN STD_LOGIC;
85 rstn : IN STD_LOGIC;
86 ADC_data : IN Samples14;
87 --ADC_smpclk : OUT STD_LOGIC;
88 ADC_nOE : OUT STD_LOGIC_VECTOR(ChanelCount-1 DOWNTO 0);
89 sample : OUT Samples14v(ChanelCount-1 DOWNTO 0);
90 sample_val : OUT STD_LOGIC
91 );
92 END COMPONENT;
93
94 COMPONENT top_ad_conv_RHF1401
95 GENERIC (
96 ChanelCount : INTEGER;
97 ncycle_cnv_high : INTEGER := 79;
98 ncycle_cnv : INTEGER := 500);
99 PORT (
100 cnv_clk : IN STD_LOGIC;
101 cnv_rstn : IN STD_LOGIC;
102 cnv : OUT STD_LOGIC;
103 clk : IN STD_LOGIC;
104 rstn : IN STD_LOGIC;
105 ADC_data : IN Samples14;
106 ADC_nOE : OUT STD_LOGIC_VECTOR(ChanelCount-1 DOWNTO 0);
107 sample : OUT Samples14v(ChanelCount-1 DOWNTO 0);
108 sample_val : OUT STD_LOGIC);
109 END COMPONENT;
110
111 COMPONENT TestModule_RHF1401
112 GENERIC (
113 freq : INTEGER;
114 amplitude : INTEGER;
115 impulsion : INTEGER);
116 PORT (
117 ADC_smpclk : IN STD_LOGIC;
118 ADC_OEB_bar : IN STD_LOGIC;
119 ADC_data : OUT STD_LOGIC_VECTOR(13 DOWNTO 0));
120 END COMPONENT;
121
122 -----------------------------------------------------------------------------
123 -----------------------------------------------------------------------------
124
53 COMPONENT ADS7886_drvr
125 COMPONENT ADS7886_drvr
54 GENERIC (
126 GENERIC (
55 ChanelCount : INTEGER;
127 ChanelCount : INTEGER;
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@@ -1,19 +1,4
1 AD7688_drvr_sync.vhd
2 AD7688_drvr.vhd
3 AD7688_drvr.vhd.orig
4 AD7688_spi_if.vhd
5 ADS1274_drvr.vhd
6 ADS1274_drvr.vhd~
7 ADS1278_drvr.vhd
8 ADS1278_drvr.vhd~
9 ADS7886_drvr.vhd
10 dual_ADS1278_drvr.vhd
11 dual_ADS1278_drvr.vhd~
12 lpp_ad_Conv.vhd
1 lpp_ad_Conv.vhd
13 lpp_ad_Conv.vhd~
14 lpp_ad_Conv.vhd.orig
15 lpp_apb_ad_conv.vhd
16 RHF1401.vhd
2 RHF1401.vhd
17 top_ad_conv_RHF1401.vhd
3 top_ad_conv_RHF1401.vhd
18 top_ad_conv.vhd
4 TestModule_RHF1401.vhd
19 WriteGen_ADC.vhd
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@@ -6,34 +6,36
6 --=================================================================================
6 --=================================================================================
7
7
8
8
9 library ieee;
9 LIBRARY ieee;
10 use ieee.std_logic_1164.all;
10 USE ieee.std_logic_1164.ALL;
11 library grlib;
11 LIBRARY grlib;
12 use grlib.amba.all;
12 USE grlib.amba.ALL;
13 use std.textio.all;
13 USE std.textio.ALL;
14
14
15
15
16 package apb_devices_list is
16 PACKAGE apb_devices_list IS
17
17
18
18
19 constant VENDOR_LPP : amba_vendor_type := 16#19#;
19 CONSTANT VENDOR_LPP : amba_vendor_type := 16#19#;
20
20
21 constant ROCKET_TM : amba_device_type := 16#1#;
21 CONSTANT ROCKET_TM : amba_device_type := 16#1#;
22 constant otherCore : amba_device_type := 16#2#;
22 CONSTANT otherCore : amba_device_type := 16#2#;
23 constant LPP_SIMPLE_DIODE : amba_device_type := 16#3#;
23 CONSTANT LPP_SIMPLE_DIODE : amba_device_type := 16#3#;
24 constant LPP_MULTI_DIODE : amba_device_type := 16#4#;
24 CONSTANT LPP_MULTI_DIODE : amba_device_type := 16#4#;
25 constant LPP_LCD_CTRLR : amba_device_type := 16#5#;
25 CONSTANT LPP_LCD_CTRLR : amba_device_type := 16#5#;
26 constant LPP_UART : amba_device_type := 16#6#;
26 CONSTANT LPP_UART : amba_device_type := 16#6#;
27 constant LPP_CNA : amba_device_type := 16#7#;
27 CONSTANT LPP_CNA : amba_device_type := 16#7#;
28 constant LPP_APB_ADC : amba_device_type := 16#8#;
28 CONSTANT LPP_APB_ADC : amba_device_type := 16#8#;
29 constant LPP_CHENILLARD : amba_device_type := 16#9#;
29 CONSTANT LPP_CHENILLARD : amba_device_type := 16#9#;
30 constant LPP_IIR_CEL_FILTER : amba_device_type := 16#10#;
30 CONSTANT LPP_IIR_CEL_FILTER : amba_device_type := 16#10#;
31 constant LPP_FIFO_PID : amba_device_type := 16#11#;
31 CONSTANT LPP_FIFO_PID : amba_device_type := 16#11#;
32 constant LPP_FFT : amba_device_type := 16#12#;
32 CONSTANT LPP_FFT : amba_device_type := 16#12#;
33 constant LPP_MATRIX : amba_device_type := 16#13#;
33 CONSTANT LPP_MATRIX : amba_device_type := 16#13#;
34 constant LPP_DELAY : amba_device_type := 16#14#;
34 CONSTANT LPP_DELAY : amba_device_type := 16#14#;
35 constant LPP_USB : amba_device_type := 16#15#;
35 CONSTANT LPP_USB : amba_device_type := 16#15#;
36 constant LPP_BALISE : amba_device_type := 16#16#;
36 CONSTANT LPP_BALISE : amba_device_type := 16#16#;
37 CONSTANT LPP_DMA_TYPE : amba_device_type := 16#17#;
38 CONSTANT LPP_BOOTLOADER_TYPE : amba_device_type := 16#18#;
39 CONSTANT LPP_LFR : amba_device_type := 16#19#;
37
40
38
41 END;
39 end;
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@@ -1,4 +1,2
1 apb_devices_list.vhd
1 apb_devices_list.vhd
2 APB_MULTI_DIODE.vhd
3 APB_SIMPLE_DIODE.vhd
4 lpp_amba.vhd
2 lpp_amba.vhd
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@@ -48,6 +48,7 ENTITY lpp_dma_send_1word IS
48 --
48 --
49 send : IN STD_LOGIC;
49 send : IN STD_LOGIC;
50 address : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
50 address : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
51
51 data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
52 data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
52 --
53 --
53 send_ok : OUT STD_LOGIC;
54 send_ok : OUT STD_LOGIC;
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@@ -1,8 +1,6
1 lpp_dma_pkg.vhd
1 fifo_latency_correction.vhd
2 fifo_latency_correction.vhd
2 lpp_dma_apbreg.vhd
3 lpp_dma.vhd
3 lpp_dma_fsm.vhd
4 lpp_dma_ip.vhd
4 lpp_dma_ip.vhd
5 lpp_dma_pkg.vhd
6 lpp_dma_send_16word.vhd
5 lpp_dma_send_16word.vhd
7 lpp_dma_send_1word.vhd
6 lpp_dma_send_1word.vhd
8 lpp_dma.vhd
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@@ -1,17 +1,14
1 ALU_Driver.vhd
1 ALU_Driver.vhd
2 ALU_Driver.vhd.bak
3 APB_Matrix.vhd
2 APB_Matrix.vhd
3 ReUse_CTRLR.vhd
4 Dispatch.vhd
4 Dispatch.vhd
5 DriveInputs.vhd
5 DriveInputs.vhd
6 GetResult.vhd
6 GetResult.vhd
7 lpp_matrix.vhd
8 MatriceSpectrale.vhd
7 MatriceSpectrale.vhd
9 MatriceSpectrale.vhd.bak
10 Matrix.vhd
8 Matrix.vhd
11 ReUse_CTRLR.vhd
12 SpectralMatrix.vhd
9 SpectralMatrix.vhd
13 SpectralMatrix.vhd.bak
14 Starter.vhd
10 Starter.vhd
15 TopMatrix_PDR.vhd
11 TopMatrix_PDR.vhd
12 TopSpecMatrix.vhd
16 Top_MatrixSpec.vhd
13 Top_MatrixSpec.vhd
17 TopSpecMatrix.vhd
14 lpp_matrix.vhd
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@@ -1,11 +1,8
1 lpp_memory.vhd
2 lpp_FIFO.vhd
3 FillFifo.vhd
1 APB_FIFO.vhd
4 APB_FIFO.vhd
2 APB_FIFO.vhd.bak
5 Bridge.vhd
3 FIFO_pipeline.vhd
6 SSRAM_plugin.vhd
4 FillFifo.vhd
7 lppFIFOx5.vhd
5 lpp_FIFO.vhd
6 lppFIFOxN.vhd
8 lppFIFOxN.vhd
7 lppFIFOxN.vhd.bak
8 lpp_memory.vhd
9 lpp_memory.vhd.bak
10 SSRAM_plugin.vhd
11 SSRAM_plugin_vsim.vhd
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@@ -139,6 +139,7 ARCHITECTURE beh OF lpp_lfr IS
139 SIGNAL data_f2_wfp : STD_LOGIC_VECTOR(159 DOWNTO 0) ;
139 SIGNAL data_f2_wfp : STD_LOGIC_VECTOR(159 DOWNTO 0) ;
140 SIGNAL data_f3_wfp : STD_LOGIC_VECTOR(159 DOWNTO 0) ;
140 SIGNAL data_f3_wfp : STD_LOGIC_VECTOR(159 DOWNTO 0) ;
141
141
142 SIGNAL run : STD_LOGIC;
142 -- SIGNAL val_f0_wfp : STD_LOGIC;
143 -- SIGNAL val_f0_wfp : STD_LOGIC;
143 -- SIGNAL val_f1_wfp : STD_LOGIC;
144 -- SIGNAL val_f1_wfp : STD_LOGIC;
144 -- SIGNAL val_f2_wfp : STD_LOGIC;
145 -- SIGNAL val_f2_wfp : STD_LOGIC;
@@ -234,6 +235,7 BEGIN
234 burst_f0 => burst_f0,
235 burst_f0 => burst_f0,
235 burst_f1 => burst_f1,
236 burst_f1 => burst_f1,
236 burst_f2 => burst_f2,
237 burst_f2 => burst_f2,
238 run => run,
237 addr_data_f0 => addr_data_f0,
239 addr_data_f0 => addr_data_f0,
238 addr_data_f1 => addr_data_f1,
240 addr_data_f1 => addr_data_f1,
239 addr_data_f2 => addr_data_f2,
241 addr_data_f2 => addr_data_f2,
@@ -267,6 +269,9 BEGIN
267 burst_f0 => burst_f0,
269 burst_f0 => burst_f0,
268 burst_f1 => burst_f1,
270 burst_f1 => burst_f1,
269 burst_f2 => burst_f2,
271 burst_f2 => burst_f2,
272
273 run => run,
274
270 nb_burst_available => nb_burst_available,
275 nb_burst_available => nb_burst_available,
271 nb_snapshot_param => nb_snapshot_param,
276 nb_snapshot_param => nb_snapshot_param,
272 status_full => status_full,
277 status_full => status_full,
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@@ -111,6 +111,8 ENTITY lpp_lfr_apbreg IS
111 burst_f1 : OUT STD_LOGIC;
111 burst_f1 : OUT STD_LOGIC;
112 burst_f2 : OUT STD_LOGIC;
112 burst_f2 : OUT STD_LOGIC;
113
113
114 run : OUT STD_LOGIC;
115
114 addr_data_f0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
116 addr_data_f0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
115 addr_data_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
117 addr_data_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
116 addr_data_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
118 addr_data_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
@@ -126,7 +128,7 ARCHITECTURE beh OF lpp_lfr_apbreg IS
126 CONSTANT REVISION : INTEGER := 1;
128 CONSTANT REVISION : INTEGER := 1;
127
129
128 CONSTANT pconfig : apb_config_type := (
130 CONSTANT pconfig : apb_config_type := (
129 0 => ahb_device_reg (VENDOR_LPP, LPP_DMA_TYPE, 2, REVISION, pirq_wfp),
131 0 => ahb_device_reg (VENDOR_LPP, LPP_LFR, 2, REVISION, pirq_wfp),
130 1 => apb_iobar(paddr, pmask));
132 1 => apb_iobar(paddr, pmask));
131
133
132 TYPE lpp_SpectralMatrix_regs IS RECORD
134 TYPE lpp_SpectralMatrix_regs IS RECORD
@@ -166,6 +168,7 ARCHITECTURE beh OF lpp_lfr_apbreg IS
166 burst_f0 : STD_LOGIC;
168 burst_f0 : STD_LOGIC;
167 burst_f1 : STD_LOGIC;
169 burst_f1 : STD_LOGIC;
168 burst_f2 : STD_LOGIC;
170 burst_f2 : STD_LOGIC;
171 run : STD_LOGIC;
169 addr_data_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
172 addr_data_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
170 addr_data_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
173 addr_data_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
171 addr_data_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
174 addr_data_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
@@ -213,6 +216,8 BEGIN -- beh
213 burst_f1 <= reg_wp.burst_f1;
216 burst_f1 <= reg_wp.burst_f1;
214 burst_f2 <= reg_wp.burst_f2;
217 burst_f2 <= reg_wp.burst_f2;
215
218
219 run <= reg_wp.run;
220
216 addr_data_f0 <= reg_wp.addr_data_f0;
221 addr_data_f0 <= reg_wp.addr_data_f0;
217 addr_data_f1 <= reg_wp.addr_data_f1;
222 addr_data_f1 <= reg_wp.addr_data_f1;
218 addr_data_f2 <= reg_wp.addr_data_f2;
223 addr_data_f2 <= reg_wp.addr_data_f2;
@@ -252,6 +257,7 BEGIN -- beh
252 reg_wp.burst_f0 <= '0';
257 reg_wp.burst_f0 <= '0';
253 reg_wp.burst_f1 <= '0';
258 reg_wp.burst_f1 <= '0';
254 reg_wp.burst_f2 <= '0';
259 reg_wp.burst_f2 <= '0';
260 reg_wp.run <= '0';
255 reg_wp.addr_data_f0 <= (OTHERS => '0');
261 reg_wp.addr_data_f0 <= (OTHERS => '0');
256 reg_wp.addr_data_f1 <= (OTHERS => '0');
262 reg_wp.addr_data_f1 <= (OTHERS => '0');
257 reg_wp.addr_data_f2 <= (OTHERS => '0');
263 reg_wp.addr_data_f2 <= (OTHERS => '0');
@@ -313,6 +319,7 BEGIN -- beh
313 prdata(4) <= reg_wp.burst_f0;
319 prdata(4) <= reg_wp.burst_f0;
314 prdata(5) <= reg_wp.burst_f1;
320 prdata(5) <= reg_wp.burst_f1;
315 prdata(6) <= reg_wp.burst_f2;
321 prdata(6) <= reg_wp.burst_f2;
322 prdata(7) <= reg_wp.run;
316 WHEN "001010" => prdata <= reg_wp.addr_data_f0;
323 WHEN "001010" => prdata <= reg_wp.addr_data_f0;
317 WHEN "001011" => prdata <= reg_wp.addr_data_f1;
324 WHEN "001011" => prdata <= reg_wp.addr_data_f1;
318 WHEN "001100" => prdata <= reg_wp.addr_data_f2;
325 WHEN "001100" => prdata <= reg_wp.addr_data_f2;
@@ -357,6 +364,7 BEGIN -- beh
357 reg_wp.burst_f0 <= apbi.pwdata(4);
364 reg_wp.burst_f0 <= apbi.pwdata(4);
358 reg_wp.burst_f1 <= apbi.pwdata(5);
365 reg_wp.burst_f1 <= apbi.pwdata(5);
359 reg_wp.burst_f2 <= apbi.pwdata(6);
366 reg_wp.burst_f2 <= apbi.pwdata(6);
367 reg_wp.run <= apbi.pwdata(7);
360 WHEN "001010" => reg_wp.addr_data_f0 <= apbi.pwdata;
368 WHEN "001010" => reg_wp.addr_data_f0 <= apbi.pwdata;
361 WHEN "001011" => reg_wp.addr_data_f1 <= apbi.pwdata;
369 WHEN "001011" => reg_wp.addr_data_f1 <= apbi.pwdata;
362 WHEN "001100" => reg_wp.addr_data_f2 <= apbi.pwdata;
370 WHEN "001100" => reg_wp.addr_data_f2 <= apbi.pwdata;
@@ -404,4 +412,4 BEGIN -- beh
404 apbo.prdata <= prdata;
412 apbo.prdata <= prdata;
405
413
406
414
407 END beh;
415 END beh; No newline at end of file
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@@ -159,6 +159,7 PACKAGE lpp_lfr_pkg IS
159 burst_f0 : OUT STD_LOGIC;
159 burst_f0 : OUT STD_LOGIC;
160 burst_f1 : OUT STD_LOGIC;
160 burst_f1 : OUT STD_LOGIC;
161 burst_f2 : OUT STD_LOGIC;
161 burst_f2 : OUT STD_LOGIC;
162 run : OUT STD_LOGIC;
162 addr_data_f0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
163 addr_data_f0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
163 addr_data_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
164 addr_data_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
164 addr_data_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
165 addr_data_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
Show file before | Show file after | Hide comments
@@ -1,16 +1,6
1 lpp_lfr_apbreg.vhd
1 lpp_top_lfr_pkg.vhd
2 lpp_lfr_pkg.vhd
2 lpp_lfr_filter.vhd
3 lpp_lfr_filter.vhd
4 lpp_lfr_apbreg.vhd
3 lpp_lfr_ms.vhd
5 lpp_lfr_ms.vhd
4 lpp_lfr_pkg.vhd
5 lpp_lfr.vhd
6 lpp_lfr.vhd
6 lpp_top_acq.vhd
7 lpp_top_acq.vhd.bak
8 lpp_top_apbreg.vhd
9 lpp_top_lfr_pkg.vhd
10 lpp_top_lfr_pkg.vhd.bak
11 lpp_top_lfr.vhd
12 lpp_top_lfr_wf_picker_ip.vhd
13 lpp_top_lfr_wf_picker_ip_whitout_filter.vhd
14 lpp_top_lfr_wf_picker.vhd
15 top_wf_picker.vhd
16 lpp_top_ms.vhd
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@@ -50,6 +50,8 ENTITY lpp_waveform IS
50 burst_f1 : IN STD_LOGIC;
50 burst_f1 : IN STD_LOGIC;
51 burst_f2 : IN STD_LOGIC;
51 burst_f2 : IN STD_LOGIC;
52
52
53 run : IN STD_LOGIC; -- TODO
54
53 nb_burst_available : IN STD_LOGIC_VECTOR(nb_burst_available_size-1 DOWNTO 0);
55 nb_burst_available : IN STD_LOGIC_VECTOR(nb_burst_available_size-1 DOWNTO 0);
54 nb_snapshot_param : IN STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
56 nb_snapshot_param : IN STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
55 status_full : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
57 status_full : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
@@ -116,6 +118,7 BEGIN -- beh
116 PORT MAP (
118 PORT MAP (
117 clk => clk,
119 clk => clk,
118 rstn => rstn,
120 rstn => rstn,
121 run => run,
119 delta_snapshot => delta_snapshot,
122 delta_snapshot => delta_snapshot,
120 delta_f2_f1 => delta_f2_f1,
123 delta_f2_f1 => delta_f2_f1,
121 delta_f2_f0 => delta_f2_f0,
124 delta_f2_f0 => delta_f2_f0,
@@ -133,6 +136,7 BEGIN -- beh
133 PORT MAP (
136 PORT MAP (
134 clk => clk,
137 clk => clk,
135 rstn => rstn,
138 rstn => rstn,
139 run => run,
136 enable => enable_f0,
140 enable => enable_f0,
137 burst_enable => burst_f0,
141 burst_enable => burst_f0,
138 nb_snapshot_param => nb_snapshot_param,
142 nb_snapshot_param => nb_snapshot_param,
@@ -151,6 +155,7 BEGIN -- beh
151 PORT MAP (
155 PORT MAP (
152 clk => clk,
156 clk => clk,
153 rstn => rstn,
157 rstn => rstn,
158 run => run,
154 enable => enable_f1,
159 enable => enable_f1,
155 burst_enable => burst_f1,
160 burst_enable => burst_f1,
156 nb_snapshot_param => nb_snapshot_param_more_one,
161 nb_snapshot_param => nb_snapshot_param_more_one,
@@ -167,6 +172,7 BEGIN -- beh
167 PORT MAP (
172 PORT MAP (
168 clk => clk,
173 clk => clk,
169 rstn => rstn,
174 rstn => rstn,
175 run => run,
170 enable => enable_f2,
176 enable => enable_f2,
171 burst_enable => burst_f2,
177 burst_enable => burst_f2,
172 nb_snapshot_param => nb_snapshot_param_more_one,
178 nb_snapshot_param => nb_snapshot_param_more_one,
@@ -182,6 +188,7 BEGIN -- beh
182 PORT MAP (
188 PORT MAP (
183 clk => clk,
189 clk => clk,
184 rstn => rstn,
190 rstn => rstn,
191 run => run,
185 enable => enable_f3,
192 enable => enable_f3,
186 data_in => data_f3_in,
193 data_in => data_f3_in,
187 data_in_valid => data_f3_in_valid,
194 data_in_valid => data_f3_in_valid,
@@ -196,6 +203,7 BEGIN -- beh
196 PORT MAP (
203 PORT MAP (
197 HCLK => clk,
204 HCLK => clk,
198 HRESETn => rstn,
205 HRESETn => rstn,
206 run => run,
199 valid_in => valid_in(I),
207 valid_in => valid_in(I),
200 ack_in => valid_ack(I),
208 ack_in => valid_ack(I),
201 valid_out => valid_out(I),
209 valid_out => valid_out(I),
@@ -207,6 +215,7 BEGIN -- beh
207 PORT MAP (
215 PORT MAP (
208 clk => clk,
216 clk => clk,
209 rstn => rstn,
217 rstn => rstn,
218 run => run,
210 data_f0_valid => valid_out(0),
219 data_f0_valid => valid_out(0),
211 data_f1_valid => valid_out(1),
220 data_f1_valid => valid_out(1),
212 data_f2_valid => valid_out(2),
221 data_f2_valid => valid_out(2),
@@ -231,6 +240,7 BEGIN -- beh
231 PORT MAP (
240 PORT MAP (
232 clk => clk,
241 clk => clk,
233 rstn => rstn,
242 rstn => rstn,
243 run => run,
234 time_ready => time_ready,
244 time_ready => time_ready,
235 data_ready => data_ready,
245 data_ready => data_ready,
236 time_ren => time_ren, -- todo
246 time_ren => time_ren, -- todo
@@ -252,6 +262,8 BEGIN -- beh
252 PORT MAP (
262 PORT MAP (
253 HCLK => clk,
263 HCLK => clk,
254 HRESETn => rstn,
264 HRESETn => rstn,
265 run => run,
266
255 AHB_Master_In => AHB_Master_In,
267 AHB_Master_In => AHB_Master_In,
256 AHB_Master_Out => AHB_Master_Out,
268 AHB_Master_Out => AHB_Master_Out,
257 enable => enable, -- todo
269 enable => enable, -- todo
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@@ -9,6 +9,7 ENTITY lpp_waveform_burst IS
9 PORT (
9 PORT (
10 clk : IN STD_LOGIC;
10 clk : IN STD_LOGIC;
11 rstn : IN STD_LOGIC;
11 rstn : IN STD_LOGIC;
12 run : IN STD_LOGIC;
12
13
13 enable : IN STD_LOGIC;
14 enable : IN STD_LOGIC;
14
15
@@ -31,7 +32,7 BEGIN -- beh
31 data_out_valid <= '0';
32 data_out_valid <= '0';
32 ELSIF clk'EVENT AND clk = '1' THEN
33 ELSIF clk'EVENT AND clk = '1' THEN
33 data_out <= data_in;
34 data_out <= data_in;
34 IF enable = '0' THEN
35 IF enable = '0' OR run = '0' THEN
35 data_out_valid <= '0';
36 data_out_valid <= '0';
36 ELSE
37 ELSE
37 data_out_valid <= data_in_valid;
38 data_out_valid <= data_in_valid;
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@@ -53,6 +53,8 ENTITY lpp_waveform_dma IS
53 -- AMBA AHB system signals
53 -- AMBA AHB system signals
54 HCLK : IN STD_ULOGIC;
54 HCLK : IN STD_ULOGIC;
55 HRESETn : IN STD_ULOGIC;
55 HRESETn : IN STD_ULOGIC;
56 --
57 run : IN STD_LOGIC;
56 -- AMBA AHB Master Interface
58 -- AMBA AHB Master Interface
57 AHB_Master_In : IN AHB_Mst_In_Type;
59 AHB_Master_In : IN AHB_Mst_In_Type;
58 AHB_Master_Out : OUT AHB_Mst_Out_Type;
60 AHB_Master_Out : OUT AHB_Mst_Out_Type;
@@ -351,6 +353,9 BEGIN
351 PORT MAP (
353 PORT MAP (
352 HCLK => HCLK,
354 HCLK => HCLK,
353 HRESETn => HRESETn,
355 HRESETn => HRESETn,
356
357 run => run,
358
354 enable => enable(I),
359 enable => enable(I),
355 update => update_and_sel((2*I)+1 DOWNTO 2*I),
360 update => update_and_sel((2*I)+1 DOWNTO 2*I),
356 nb_burst_available => nb_burst_available,
361 nb_burst_available => nb_burst_available,
@@ -369,4 +374,4 BEGIN
369 -----------------------------------------------------------------------------
374 -----------------------------------------------------------------------------
370
375
371
376
372 END Behavioral; No newline at end of file
377 END Behavioral;
Show file before | Show file after | Hide comments
@@ -33,6 +33,7 ENTITY lpp_waveform_dma_gen_valid IS
33 PORT (
33 PORT (
34 HCLK : IN STD_LOGIC;
34 HCLK : IN STD_LOGIC;
35 HRESETn : IN STD_LOGIC;
35 HRESETn : IN STD_LOGIC;
36 run : IN STD_LOGIC;
36
37
37 valid_in : IN STD_LOGIC;
38 valid_in : IN STD_LOGIC;
38 ack_in : IN STD_LOGIC;
39 ack_in : IN STD_LOGIC;
@@ -58,12 +59,20 BEGIN
58 WHEN IDLE =>
59 WHEN IDLE =>
59 valid_out <= '0';
60 valid_out <= '0';
60 error <= '0';
61 error <= '0';
61 IF valid_in = '1' THEN
62 IF run = '0' THEN
63 state <= IDLE;
64 valid_out <= '0';
65 ELSIF valid_in = '1' THEN
62 state <= VALID;
66 state <= VALID;
63 valid_out <= '1';
67 valid_out <= '1';
64 END IF;
68 END IF;
65
69
66 WHEN VALID =>
70 WHEN VALID =>
71 IF run = '0' THEN
72 state <= IDLE;
73 valid_out <= '0';
74 error <= '0';
75 ELSE
67 valid_out <= '1';
76 valid_out <= '1';
68 error <= '0';
77 error <= '0';
69 IF valid_in = '1' THEN
78 IF valid_in = '1' THEN
@@ -79,6 +88,7 BEGIN
79 state <= IDLE;
88 state <= IDLE;
80 valid_out <= '0';
89 valid_out <= '0';
81 END IF;
90 END IF;
91 END IF;
82
92
83 WHEN OTHERS => NULL;
93 WHEN OTHERS => NULL;
84 END CASE;
94 END CASE;
Show file before | Show file after | Hide comments
@@ -37,6 +37,8 ENTITY lpp_waveform_dma_selectaddress IS
37 HCLK : IN STD_ULOGIC;
37 HCLK : IN STD_ULOGIC;
38 HRESETn : IN STD_ULOGIC;
38 HRESETn : IN STD_ULOGIC;
39
39
40 run : IN STD_ULOGIC;
41
40 enable : IN STD_LOGIC;
42 enable : IN STD_LOGIC;
41 update : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
43 update : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
42
44
@@ -81,13 +83,25 BEGIN
81 update_r <= update;
83 update_r <= update;
82 CASE state IS
84 CASE state IS
83 WHEN IDLE =>
85 WHEN IDLE =>
86 IF run = '0' THEN
87 state <= IDLE;
88 address <= (OTHERS => '0');
89 nb_send <= (OTHERS => '0');
90 status_full <= '0';
91 status_full_err <= '0';
92 update_r <= "00";
93 ELSE
84 IF enable = '0' THEN
94 IF enable = '0' THEN
85 state <= UPDATED;
95 state <= UPDATED;
86 elsIF update_s = '1' THEN
96 ELSIF update_s = '1' THEN
87 state <= ADD;
97 state <= ADD;
88 END IF;
98 END IF;
99 END IF;
89
100
90 WHEN ADD =>
101 WHEN ADD =>
102 IF run = '0' THEN
103 state <= IDLE;
104 ELSE
91 IF UNSIGNED(nb_send_next) < UNSIGNED(nb_burst_available) THEN
105 IF UNSIGNED(nb_send_next) < UNSIGNED(nb_burst_available) THEN
92 state <= IDLE;
106 state <= IDLE;
93 IF update_r = "10" THEN
107 IF update_r = "10" THEN
@@ -101,8 +115,12 BEGIN
101 nb_send <= (OTHERS => '0');
115 nb_send <= (OTHERS => '0');
102 status_full <= '1';
116 status_full <= '1';
103 END IF;
117 END IF;
118 END IF;
104
119
105 WHEN FULL =>
120 WHEN FULL =>
121 IF run = '0' THEN
122 state <= IDLE;
123 ELSE
106 status_full <= '0';
124 status_full <= '0';
107 IF status_full_ack = '1' THEN
125 IF status_full_ack = '1' THEN
108 IF update_s = '1' THEN
126 IF update_s = '1' THEN
@@ -115,19 +133,28 BEGIN
115 state <= ERR;
133 state <= ERR;
116 END IF;
134 END IF;
117 END IF;
135 END IF;
136 END IF;
118
137
119 WHEN ERR =>
138 WHEN ERR =>
139 IF run = '0' THEN
140 state <= IDLE;
141 ELSE
120 status_full_err <= '0';
142 status_full_err <= '0';
121 IF status_full_ack = '1' THEN
143 IF status_full_ack = '1' THEN
122 state <= UPDATED;
144 state <= UPDATED;
123 END IF;
145 END IF;
146 END IF;
124
147
125 WHEN UPDATED =>
148 WHEN UPDATED =>
149 IF run = '0' THEN
150 state <= IDLE;
151 ELSE
126 status_full_err <= '0';
152 status_full_err <= '0';
127 address <= addr_data_reg;
153 address <= addr_data_reg;
128 IF enable = '1' THEN
154 IF enable = '1' THEN
129 state <= IDLE;
155 state <= IDLE;
130 END IF;
156 END IF;
157 END IF;
131
158
132 WHEN OTHERS => NULL;
159 WHEN OTHERS => NULL;
133 END CASE;
160 END CASE;
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@@ -37,6 +37,8 ENTITY lpp_waveform_fifo IS
37 PORT(
37 PORT(
38 clk : IN STD_LOGIC;
38 clk : IN STD_LOGIC;
39 rstn : IN STD_LOGIC;
39 rstn : IN STD_LOGIC;
40 ---------------------------------------------------------------------------
41 run : IN STD_LOGIC;
40
42
41 ---------------------------------------------------------------------------
43 ---------------------------------------------------------------------------
42 time_ready : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); -- FIFO_DATA occupancy is greater than 16 * 32b
44 time_ready : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); -- FIFO_DATA occupancy is greater than 16 * 32b
@@ -120,6 +122,7 BEGIN
120 PORT MAP (
122 PORT MAP (
121 clk => clk,
123 clk => clk,
122 rstn => rstn,
124 rstn => rstn,
125 run => run,
123 ren => time_ren(I),
126 ren => time_ren(I),
124 wen => time_wen(I),
127 wen => time_wen(I),
125 mem_re => time_mem_ren(I),
128 mem_re => time_mem_ren(I),
@@ -138,6 +141,7 BEGIN
138 PORT MAP (
141 PORT MAP (
139 clk => clk,
142 clk => clk,
140 rstn => rstn,
143 rstn => rstn,
144 run => run,
141 ren => data_ren(I),
145 ren => data_ren(I),
142 wen => data_wen(I),
146 wen => data_wen(I),
143 mem_re => data_mem_ren(I),
147 mem_re => data_mem_ren(I),
Show file before | Show file after | Hide comments
@@ -33,7 +33,8 ENTITY lpp_waveform_fifo_arbiter IS
33 PORT(
33 PORT(
34 clk : IN STD_LOGIC;
34 clk : IN STD_LOGIC;
35 rstn : IN STD_LOGIC;
35 rstn : IN STD_LOGIC;
36
36 ---------------------------------------------------------------------------
37 run : IN STD_LOGIC;
37 ---------------------------------------------------------------------------
38 ---------------------------------------------------------------------------
38 data_f0_valid : IN STD_LOGIC;
39 data_f0_valid : IN STD_LOGIC;
39 data_f1_valid : IN STD_LOGIC;
40 data_f1_valid : IN STD_LOGIC;
@@ -111,7 +112,7 BEGIN
111 data_wen <= (OTHERS => '1');
112 data_wen <= (OTHERS => '1');
112 data <= (OTHERS => '0');
113 data <= (OTHERS => '0');
113 data_temp <= (OTHERS => '0');
114 data_temp <= (OTHERS => '0');
114 IF data_ready_to_go = '1' THEN
115 IF data_ready_to_go = '1' AND run = '1' THEN
115 state <= T1;
116 state <= T1;
116 data_valid_ack <= data_valid_selected;
117 data_valid_ack <= data_valid_selected;
117 time_wen <= NOT data_valid_selected;
118 time_wen <= NOT data_valid_selected;
@@ -120,20 +121,32 BEGIN
120 data_temp <= data_selected(159 DOWNTO 32);
121 data_temp <= data_selected(159 DOWNTO 32);
121 END IF;
122 END IF;
122 WHEN T1 =>
123 WHEN T1 =>
124 IF run = '0' THEN
125 state <= IDLE;
126 ELSE
123 state <= T2;
127 state <= T2;
128 END IF;
124 data_valid_ack <= (OTHERS => '0');
129 data_valid_ack <= (OTHERS => '0');
125 data <= data_temp(31 DOWNTO 0);
130 data <= data_temp(31 DOWNTO 0);
126 data_temp(32*3-1 DOWNTO 0) <= data_temp(32*4-1 DOWNTO 32);
131 data_temp(32*3-1 DOWNTO 0) <= data_temp(32*4-1 DOWNTO 32);
127
132
128 WHEN T2 =>
133 WHEN T2 =>
134 IF run = '0' THEN
135 state <= IDLE;
136 ELSE
129 state <= D1;
137 state <= D1;
138 END IF;
130 time_wen <= (OTHERS => '1');
139 time_wen <= (OTHERS => '1');
131 data_wen <= time_en_temp;
140 data_wen <= time_en_temp;
132 data <= data_temp(31 DOWNTO 0);
141 data <= data_temp(31 DOWNTO 0);
133 data_temp(32*3-1 DOWNTO 0) <= data_temp(32*4-1 DOWNTO 32);
142 data_temp(32*3-1 DOWNTO 0) <= data_temp(32*4-1 DOWNTO 32);
134
143
135 WHEN D1 =>
144 WHEN D1 =>
145 IF run = '0' THEN
146 state <= IDLE;
147 ELSE
136 state <= D2;
148 state <= D2;
149 END IF;
137 data <= data_temp(31 DOWNTO 0);
150 data <= data_temp(31 DOWNTO 0);
138 data_temp(32*3-1 DOWNTO 0) <= data_temp(32*4-1 DOWNTO 32);
151 data_temp(32*3-1 DOWNTO 0) <= data_temp(32*4-1 DOWNTO 32);
139
152
Show file before | Show file after | Hide comments
@@ -40,6 +40,8 ENTITY lpp_waveform_fifo_ctrl IS
40 clk : IN STD_LOGIC;
40 clk : IN STD_LOGIC;
41 rstn : IN STD_LOGIC;
41 rstn : IN STD_LOGIC;
42
42
43 run : IN STD_LOGIC;
44
43 ren : IN STD_LOGIC;
45 ren : IN STD_LOGIC;
44 wen : IN STD_LOGIC;
46 wen : IN STD_LOGIC;
45
47
@@ -92,12 +94,15 BEGIN
92 Raddr_vect <= 0;
94 Raddr_vect <= 0;
93 sempty <= '1';
95 sempty <= '1';
94 ELSIF(clk'EVENT AND clk = '1')then
96 ELSIF(clk'EVENT AND clk = '1')then
97 IF run = '0' THEN
98 Raddr_vect <= 0;
99 sempty <= '1';
100 ELSE
95 sEmpty <= sempty_s;
101 sEmpty <= sempty_s;
96
97 IF(sREN = '0' and sempty = '0')then
102 IF(sREN = '0' and sempty = '0')then
98 Raddr_vect <= Raddr_vect_s;
103 Raddr_vect <= Raddr_vect_s;
99 END IF;
104 END IF;
100
105 END IF;
101 END IF;
106 END IF;
102 END PROCESS;
107 END PROCESS;
103
108
@@ -118,13 +123,16 BEGIN
118 IF(rstn = '0')then
123 IF(rstn = '0')then
119 Waddr_vect <= 0;
124 Waddr_vect <= 0;
120 sfull <= '0';
125 sfull <= '0';
121 ELSIF(clk'EVENT AND clk = '1')then
126 ELSIF(clk'EVENT AND clk = '1')THEN
127 IF run = '0' THEN
128 Waddr_vect <= 0;
129 sfull <= '0';
130 ELSE
122 sfull <= sfull_s;
131 sfull <= sfull_s;
123
124 IF(sWEN = '0' and sfull = '0')THEN
132 IF(sWEN = '0' and sfull = '0')THEN
125 Waddr_vect <= Waddr_vect_s;
133 Waddr_vect <= Waddr_vect_s;
126 END IF;
134 END IF;
127
135 END IF;
128 END IF;
136 END IF;
129 END PROCESS;
137 END PROCESS;
130
138
@@ -168,4 +176,3 END ARCHITECTURE;
168
176
169
177
170
178
171
Show file before | Show file after | Hide comments
@@ -21,6 +21,7 PACKAGE lpp_waveform_pkg IS
21 PORT (
21 PORT (
22 clk : IN STD_LOGIC;
22 clk : IN STD_LOGIC;
23 rstn : IN STD_LOGIC;
23 rstn : IN STD_LOGIC;
24 run : IN STD_LOGIC;
24 enable : IN STD_LOGIC;
25 enable : IN STD_LOGIC;
25 burst_enable : IN STD_LOGIC;
26 burst_enable : IN STD_LOGIC;
26 nb_snapshot_param : IN STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
27 nb_snapshot_param : IN STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
@@ -37,6 +38,7 PACKAGE lpp_waveform_pkg IS
37 PORT (
38 PORT (
38 clk : IN STD_LOGIC;
39 clk : IN STD_LOGIC;
39 rstn : IN STD_LOGIC;
40 rstn : IN STD_LOGIC;
41 run : IN STD_LOGIC;
40 enable : IN STD_LOGIC;
42 enable : IN STD_LOGIC;
41 data_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
43 data_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
42 data_in_valid : IN STD_LOGIC;
44 data_in_valid : IN STD_LOGIC;
@@ -52,6 +54,7 PACKAGE lpp_waveform_pkg IS
52 PORT (
54 PORT (
53 clk : IN STD_LOGIC;
55 clk : IN STD_LOGIC;
54 rstn : IN STD_LOGIC;
56 rstn : IN STD_LOGIC;
57 run : IN STD_LOGIC;
55 delta_snapshot : IN STD_LOGIC_VECTOR(delta_snapshot_size-1 DOWNTO 0);
58 delta_snapshot : IN STD_LOGIC_VECTOR(delta_snapshot_size-1 DOWNTO 0);
56 delta_f2_f1 : IN STD_LOGIC_VECTOR(delta_f2_f1_size-1 DOWNTO 0);
59 delta_f2_f1 : IN STD_LOGIC_VECTOR(delta_f2_f1_size-1 DOWNTO 0);
57 delta_f2_f0 : IN STD_LOGIC_VECTOR(delta_f2_f0_size-1 DOWNTO 0);
60 delta_f2_f0 : IN STD_LOGIC_VECTOR(delta_f2_f0_size-1 DOWNTO 0);
@@ -91,6 +94,7 PACKAGE lpp_waveform_pkg IS
91 burst_f0 : IN STD_LOGIC;
94 burst_f0 : IN STD_LOGIC;
92 burst_f1 : IN STD_LOGIC;
95 burst_f1 : IN STD_LOGIC;
93 burst_f2 : IN STD_LOGIC;
96 burst_f2 : IN STD_LOGIC;
97 run : IN STD_LOGIC;
94 nb_burst_available : IN STD_LOGIC_VECTOR(nb_burst_available_size-1 DOWNTO 0);
98 nb_burst_available : IN STD_LOGIC_VECTOR(nb_burst_available_size-1 DOWNTO 0);
95 nb_snapshot_param : IN STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
99 nb_snapshot_param : IN STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
96 status_full : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
100 status_full : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
@@ -132,6 +136,7 PACKAGE lpp_waveform_pkg IS
132 PORT (
136 PORT (
133 HCLK : IN STD_ULOGIC;
137 HCLK : IN STD_ULOGIC;
134 HRESETn : IN STD_ULOGIC;
138 HRESETn : IN STD_ULOGIC;
139 run : IN STD_LOGIC;
135 enable : IN STD_LOGIC;
140 enable : IN STD_LOGIC;
136 update : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
141 update : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
137 nb_burst_available : IN STD_LOGIC_VECTOR(nb_burst_available_size-1 DOWNTO 0);
142 nb_burst_available : IN STD_LOGIC_VECTOR(nb_burst_available_size-1 DOWNTO 0);
@@ -146,6 +151,7 PACKAGE lpp_waveform_pkg IS
146 PORT (
151 PORT (
147 HCLK : IN STD_LOGIC;
152 HCLK : IN STD_LOGIC;
148 HRESETn : IN STD_LOGIC;
153 HRESETn : IN STD_LOGIC;
154 run : IN STD_LOGIC;
149 valid_in : IN STD_LOGIC;
155 valid_in : IN STD_LOGIC;
150 ack_in : IN STD_LOGIC;
156 ack_in : IN STD_LOGIC;
151 valid_out : OUT STD_LOGIC;
157 valid_out : OUT STD_LOGIC;
@@ -161,6 +167,7 PACKAGE lpp_waveform_pkg IS
161 PORT (
167 PORT (
162 HCLK : IN STD_ULOGIC;
168 HCLK : IN STD_ULOGIC;
163 HRESETn : IN STD_ULOGIC;
169 HRESETn : IN STD_ULOGIC;
170 run : IN STD_LOGIC;
164 AHB_Master_In : IN AHB_Mst_In_Type;
171 AHB_Master_In : IN AHB_Mst_In_Type;
165 AHB_Master_Out : OUT AHB_Mst_Out_Type;
172 AHB_Master_Out : OUT AHB_Mst_Out_Type;
166 enable : IN STD_LOGIC_VECTOR(3 DOWNTO 0); -- todo
173 enable : IN STD_LOGIC_VECTOR(3 DOWNTO 0); -- todo
@@ -196,6 +203,7 PACKAGE lpp_waveform_pkg IS
196 PORT (
203 PORT (
197 clk : IN STD_LOGIC;
204 clk : IN STD_LOGIC;
198 rstn : IN STD_LOGIC;
205 rstn : IN STD_LOGIC;
206 run : IN STD_LOGIC;
199 ren : IN STD_LOGIC;
207 ren : IN STD_LOGIC;
200 wen : IN STD_LOGIC;
208 wen : IN STD_LOGIC;
201 mem_re : OUT STD_LOGIC;
209 mem_re : OUT STD_LOGIC;
@@ -211,6 +219,7 PACKAGE lpp_waveform_pkg IS
211 PORT (
219 PORT (
212 clk : IN STD_LOGIC;
220 clk : IN STD_LOGIC;
213 rstn : IN STD_LOGIC;
221 rstn : IN STD_LOGIC;
222 run : IN STD_LOGIC;
214 data_f0_valid : IN STD_LOGIC;
223 data_f0_valid : IN STD_LOGIC;
215 data_f1_valid : IN STD_LOGIC;
224 data_f1_valid : IN STD_LOGIC;
216 data_f2_valid : IN STD_LOGIC;
225 data_f2_valid : IN STD_LOGIC;
@@ -232,6 +241,7 PACKAGE lpp_waveform_pkg IS
232 PORT (
241 PORT (
233 clk : IN STD_LOGIC;
242 clk : IN STD_LOGIC;
234 rstn : IN STD_LOGIC;
243 rstn : IN STD_LOGIC;
244 run : IN STD_LOGIC;
235 time_ready : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
245 time_ready : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
236 data_ready : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
246 data_ready : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
237 time_ren : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
247 time_ren : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
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@@ -11,6 +11,7 ENTITY lpp_waveform_snapshot IS
11 PORT (
11 PORT (
12 clk : IN STD_LOGIC;
12 clk : IN STD_LOGIC;
13 rstn : IN STD_LOGIC;
13 rstn : IN STD_LOGIC;
14 run : IN STD_LOGIC;
14
15
15 enable : IN STD_LOGIC;
16 enable : IN STD_LOGIC;
16 burst_enable : IN STD_LOGIC;
17 burst_enable : IN STD_LOGIC;
@@ -39,7 +40,7 BEGIN -- beh
39 counter_points_snapshot <= 0;
40 counter_points_snapshot <= 0;
40 ELSIF clk'EVENT AND clk = '1' THEN
41 ELSIF clk'EVENT AND clk = '1' THEN
41 data_out <= data_in;
42 data_out <= data_in;
42 IF enable = '0' THEN
43 IF enable = '0' OR run = '0' THEN
43 data_out_valid <= '0';
44 data_out_valid <= '0';
44 counter_points_snapshot <= 0;
45 counter_points_snapshot <= 0;
45 ELSE
46 ELSE
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@@ -12,6 +12,8 ENTITY lpp_waveform_snapshot_controler I
12 PORT (
12 PORT (
13 clk : IN STD_LOGIC;
13 clk : IN STD_LOGIC;
14 rstn : IN STD_LOGIC;
14 rstn : IN STD_LOGIC;
15 --
16 run : IN STD_LOGIC;
15 --config
17 --config
16 delta_snapshot : IN STD_LOGIC_VECTOR(delta_snapshot_size-1 DOWNTO 0);
18 delta_snapshot : IN STD_LOGIC_VECTOR(delta_snapshot_size-1 DOWNTO 0);
17 delta_f2_f1 : IN STD_LOGIC_VECTOR(delta_f2_f1_size-1 DOWNTO 0);
19 delta_f2_f1 : IN STD_LOGIC_VECTOR(delta_f2_f1_size-1 DOWNTO 0);
@@ -50,6 +52,16 BEGIN -- beh
50 start_snapshot_f2_temp <= '0';
52 start_snapshot_f2_temp <= '0';
51 start_snapshot_fothers_temp <= '0';
53 start_snapshot_fothers_temp <= '0';
52 ELSIF clk'EVENT AND clk = '1' THEN
54 ELSIF clk'EVENT AND clk = '1' THEN
55 IF run = '0' THEN
56 start_snapshot_f0 <= '0';
57 start_snapshot_f1 <= '0';
58 start_snapshot_f2 <= '0';
59 counter_delta_snapshot <= 0;
60 counter_delta_f0 <= 0;
61 coarse_time_0_r <= '0';
62 start_snapshot_f2_temp <= '0';
63 start_snapshot_fothers_temp <= '0';
64 ELSE
53 IF counter_delta_snapshot = UNSIGNED(delta_snapshot) THEN
65 IF counter_delta_snapshot = UNSIGNED(delta_snapshot) THEN
54 start_snapshot_f2_temp <= '1';
66 start_snapshot_f2_temp <= '1';
55 ELSE
67 ELSE
@@ -108,7 +120,9 BEGIN -- beh
108 END IF;
120 END IF;
109 END IF;
121 END IF;
110 -------------------------------------------------------------------------
122 -------------------------------------------------------------------------
123
124 END IF;
111 END IF;
125 END IF;
112 END PROCESS;
126 END PROCESS;
113
127
114 END beh; No newline at end of file
128 END beh;
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@@ -1,13 +1,12
1 lpp_waveform_pkg.vhd
2 lpp_waveform.vhd
1 lpp_waveform_burst.vhd
3 lpp_waveform_burst.vhd
4 lpp_waveform_dma.vhd
2 lpp_waveform_dma_genvalid.vhd
5 lpp_waveform_dma_genvalid.vhd
3 lpp_waveform_dma_selectaddress.vhd
6 lpp_waveform_dma_selectaddress.vhd
4 lpp_waveform_dma_send_Nword.vhd
7 lpp_waveform_dma_send_Nword.vhd
5 lpp_waveform_dma.vhd
8 lpp_waveform_fifo.vhd
6 lpp_waveform_fifo_arbiter.vhd
9 lpp_waveform_fifo_arbiter.vhd
7 lpp_waveform_fifo_ctrl.vhd
10 lpp_waveform_fifo_ctrl.vhd
8 lpp_waveform_fifo.vhd
11 lpp_waveform_snapshot.vhd
9 lpp_waveform_pkg.vhd
10 lpp_waveform_snapshot_controler.vhd
12 lpp_waveform_snapshot_controler.vhd
11 lpp_waveform_snapshot.vhd
12 lpp_waveform_valid_ack.vhd
13 lpp_waveform.vhd
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1 NO CONTENT: file was removed, binary diff hidden
NO CONTENT: file was removed, binary diff hidden
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