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1 | # Top Level Design Parameters | |||
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2 | ||||
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3 | # Clocks | |||
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4 | ||||
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5 | create_clock -period 10.000000 -waveform {0.000000 5.000000} clk100MHz | |||
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6 | create_clock -period 20.344999 -waveform {0.000000 10.172500} clk49_152MHz | |||
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7 | create_clock -period 20.000000 -waveform {0.000000 10.000000} clk_50_s:Q | |||
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8 | create_clock -period 40.000000 -waveform {0.000000 20.000000} clk_25:Q | |||
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9 | create_clock -period 40.690000 -waveform {0.000000 20.345100} clk_24:Q | |||
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10 | create_clock -name SPW_CLOCK -period 100.000000 -waveform {0.000000 50.000000} {SPW1_DIN SPW1_SIN SPW2_DIN SPW2_SIN} | |||
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11 | ||||
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12 | ||||
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13 | # False Paths Between Clocks | |||
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14 | ||||
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15 | ||||
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16 | # False Path Constraints | |||
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17 | ||||
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18 | ||||
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19 | # Maximum Delay Constraints | |||
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20 | ||||
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21 | ||||
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22 | # Multicycle Constraints | |||
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23 | ||||
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24 | ||||
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25 | # Virtual Clocks | |||
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26 | # Output Load Constraints | |||
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27 | # Driving Cell Constraints | |||
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28 | # Wire Loads | |||
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29 | # set_wire_load_mode top | |||
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30 | ||||
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31 | # Other Constraints | |||
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1 | # Synplicity, Inc. constraint file | |||
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2 | # /home/jiri/ibm/vhdl/grlib/boards/actel-coremp7-1000/default.sdc | |||
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3 | # Written on Wed Aug 1 19:29:24 2007 | |||
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4 | # by Synplify Pro, Synplify Pro 8.8.0.4 Scope Editor | |||
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5 | ||||
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6 | # | |||
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7 | # Collections | |||
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8 | # | |||
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9 | ||||
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10 | # | |||
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11 | # Clocks | |||
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12 | # | |||
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13 | ||||
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14 | ||||
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15 | define_clock {clk100MHz} -name {clk100MHz} -freq 100 -clockgroup default_clkgroup -route 5 | |||
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16 | define_clock {clk49_152MHz} -name {clk49_152MHz} -freq 49.152 -clockgroup default_clkgroup -route 5 | |||
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17 | ||||
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18 | # | |||
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19 | # Clock to Clock | |||
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20 | # | |||
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21 | ||||
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22 | # | |||
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23 | # Inputs/Outputs | |||
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24 | # | |||
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25 | define_output_delay -disable -default 5.00 -improve 0.00 -route 0.00 -ref {clk:r} | |||
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26 | define_input_delay -disable -default 5.00 -improve 0.00 -route 0.00 -ref {clk:r} | |||
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27 | ||||
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28 | ||||
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29 | # | |||
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30 | # Registers | |||
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31 | # | |||
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32 | ||||
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33 | # | |||
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34 | # Multicycle Path | |||
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35 | # | |||
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36 | ||||
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37 | # | |||
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38 | # False Path | |||
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39 | # | |||
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40 | ||||
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41 | # | |||
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42 | # Path Delay | |||
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43 | # | |||
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44 | ||||
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45 | # | |||
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46 | # Attributes | |||
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47 | # | |||
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48 | define_global_attribute syn_useioff {1} | |||
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49 | define_global_attribute -disable syn_netlist_hierarchy {0} | |||
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50 | define_attribute {etx_clk} syn_noclockbuf {1} | |||
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51 | ||||
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52 | # | |||
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53 | # I/O standards | |||
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54 | # | |||
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55 | ||||
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56 | # | |||
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57 | # Compile Points | |||
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58 | # | |||
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59 | ||||
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60 | # | |||
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61 | # Other Constraints | |||
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62 | # | |||
| @@ -19,6 +19,10 VHDLSYNFILES=LFR-em.vhd | |||||
| 19 | #SDCFILE=$(GRLIB)/boards/$(BOARD)/synplify.sdc |
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19 | #SDCFILE=$(GRLIB)/boards/$(BOARD)/synplify.sdc | |
| 20 | #SDC=$(GRLIB)/boards/$(BOARD)/leon3mp.sdc |
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20 | #SDC=$(GRLIB)/boards/$(BOARD)/leon3mp.sdc | |
| 21 | PDC=$(VHDLIB)/boards/$(BOARD)/em-LeonLPP-A3PE3kL.pdc |
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21 | PDC=$(VHDLIB)/boards/$(BOARD)/em-LeonLPP-A3PE3kL.pdc | |
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22 | ||||
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23 | SDCFILE=$(VHDLIB)/boards/$(BOARD)/LFR_EM_synthesis.sdc | |||
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24 | SDC=$(VHDLIB)/boards/$(BOARD)/LFR_EM_place_and_route.sdc | |||
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25 | ||||
| 22 | BITGEN=$(VHDLIB)/boards/$(BOARD)/default.ut |
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26 | BITGEN=$(VHDLIB)/boards/$(BOARD)/default.ut | |
| 23 | CLEAN=soft-clean |
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27 | CLEAN=soft-clean | |
| 24 |
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28 | |||
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