diff --git a/boards/em-LeonLPP-A3PE3kL-v3-core1/LFR_EM_place_and_route.sdc b/boards/em-LeonLPP-A3PE3kL-v3-core1/LFR_EM_place_and_route.sdc
new file mode 100644
--- /dev/null
+++ b/boards/em-LeonLPP-A3PE3kL-v3-core1/LFR_EM_place_and_route.sdc
@@ -0,0 +1,31 @@
+# Top Level Design Parameters
+
+# Clocks
+
+create_clock -period 10.000000 -waveform {0.000000 5.000000}  clk100MHz
+create_clock -period 20.344999 -waveform {0.000000 10.172500} clk49_152MHz
+create_clock -period 20.000000 -waveform {0.000000 10.000000} clk_50_s:Q
+create_clock -period 40.000000 -waveform {0.000000 20.000000} clk_25:Q
+create_clock -period 40.690000 -waveform {0.000000 20.345100} clk_24:Q
+create_clock -name SPW_CLOCK -period 100.000000 -waveform {0.000000 50.000000} {SPW1_DIN SPW1_SIN SPW2_DIN SPW2_SIN}
+
+
+# False Paths Between Clocks
+
+
+# False Path Constraints
+
+
+# Maximum Delay Constraints
+
+
+# Multicycle Constraints
+
+
+# Virtual Clocks
+# Output Load Constraints
+# Driving Cell Constraints
+# Wire Loads
+# set_wire_load_mode top
+
+# Other Constraints
diff --git a/boards/em-LeonLPP-A3PE3kL-v3-core1/LFR_EM_synthesis.sdc b/boards/em-LeonLPP-A3PE3kL-v3-core1/LFR_EM_synthesis.sdc
new file mode 100644
--- /dev/null
+++ b/boards/em-LeonLPP-A3PE3kL-v3-core1/LFR_EM_synthesis.sdc
@@ -0,0 +1,62 @@
+# Synplicity, Inc. constraint file
+# /home/jiri/ibm/vhdl/grlib/boards/actel-coremp7-1000/default.sdc
+# Written on Wed Aug  1 19:29:24 2007
+# by Synplify Pro, Synplify Pro 8.8.0.4 Scope Editor
+
+#
+# Collections
+#
+
+#
+# Clocks
+#
+
+
+define_clock  {clk100MHz} -name {clk100MHz}  -freq 100    -clockgroup default_clkgroup -route 5
+define_clock  {clk49_152MHz} -name {clk49_152MHz}  -freq 49.152 -clockgroup default_clkgroup -route 5
+
+#
+# Clock to Clock
+#
+
+#
+# Inputs/Outputs
+#
+define_output_delay -disable     -default  5.00 -improve 0.00 -route 0.00 -ref {clk:r}
+define_input_delay -disable      -default  5.00 -improve 0.00 -route 0.00 -ref {clk:r}
+
+
+#
+# Registers
+#
+
+#
+# Multicycle Path
+#
+
+#
+# False Path
+#
+
+#
+# Path Delay
+#
+
+#
+# Attributes
+#
+define_global_attribute          syn_useioff {1}
+define_global_attribute -disable syn_netlist_hierarchy {0}
+define_attribute          {etx_clk} syn_noclockbuf {1}
+
+#
+# I/O standards
+#
+
+#
+# Compile Points
+#
+
+#
+# Other Constraints
+#
diff --git a/designs/LFR-em-WFP_MS/Makefile b/designs/LFR-em-WFP_MS/Makefile
--- a/designs/LFR-em-WFP_MS/Makefile
+++ b/designs/LFR-em-WFP_MS/Makefile
@@ -19,6 +19,10 @@ VHDLSYNFILES=LFR-em.vhd
 #SDCFILE=$(GRLIB)/boards/$(BOARD)/synplify.sdc
 #SDC=$(GRLIB)/boards/$(BOARD)/leon3mp.sdc
 PDC=$(VHDLIB)/boards/$(BOARD)/em-LeonLPP-A3PE3kL.pdc
+
+SDCFILE=$(VHDLIB)/boards/$(BOARD)/LFR_EM_synthesis.sdc
+SDC=$(VHDLIB)/boards/$(BOARD)/LFR_EM_place_and_route.sdc
+
 BITGEN=$(VHDLIB)/boards/$(BOARD)/default.ut
 CLEAN=soft-clean