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##------------------------------------------------------------------------------
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##-- This file is a part of the LPP VHDL IP LIBRARY
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##-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
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##--
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##-- This program is free software; you can redistribute it and/or modify
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##-- it under the terms of the GNU General Public License as published by
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##-- the Free Software Foundation; either version 3 of the License, or
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##-- (at your option) any later version.
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##--
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##-- This program is distributed in the hope that it will be useful,
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##-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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##-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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##-- GNU General Public License for more details.
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##--
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##-- You should have received a copy of the GNU General Public License
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##-- along with this program; if not, write to the Free Software
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##-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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##-------------------------------------------------------------------------------
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##-- Author : Jean-christophe Pellion
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##-- Mail : jean-christophe.pellion@lpp.polytechnique.fr
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##-- jean-christophe.pellion@easii-ic.com
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##-------------------------------------------------------------------------------
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PACKAGE=\"\"
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SPEED=Std
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SYNFREQ=50
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TECHNOLOGY=ProASIC3E
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LIBERO_DIE=IT14X14M4
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PART=A3PE3000
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DESIGNER_VOLTAGE=COM
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DESIGNER_TEMP=COM
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DESIGNER_PACKAGE=FBGA
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DESIGNER_PINS=324
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MANUFACTURER=Actel
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MGCTECHNOLOGY=Proasic3
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MGCPART=$(PART)
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MGCPACKAGE= {$(DESIGNER_PINS) $(DESIGNER_PACKAGE)}
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LIBERO_PACKAGE=fg$(DESIGNER_PINS)
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