##// END OF EJS Templates
HG_REPOSITORIES » LPP » INSTRUMENTATION » USERS » PELLION » VHD_Lib
RSS

Clone from http://pc-instru.lpp.polytechnique.fr:5000/VHD_Lib

Fusion
pellion -
r355:31ae92550df7 merge next
parent child
Show More
Show file before | Show file after | Hide comments
@@ -0,0 +1,224
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more Cdetails.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
19 -- Author : Paul LEROY
20 -- Mail : paul.leroy@lpp.polytechnique.fr
21 -------------------------------------------------------------------------------
22
23 LIBRARY IEEE;
24 USE IEEE.numeric_std.ALL;
25 USE IEEE.std_logic_1164.ALL;
26
27 LIBRARY staging_lpp;
28 --USE lpp.general_purpose.ALL;
29 use staging_lpp.PLE_general_purpose.all;
30 use staging_lpp.PLE_lpp_fft.all;
31
32 ENTITY BUTTERFLY_CTRL IS
33 PORT (
34 rstn : IN STD_LOGIC;
35 clk : IN STD_LOGIC;
36
37 sample_in_val : IN STD_LOGIC;
38 sample_out_val : OUT STD_LOGIC;
39
40 sel_op1 : OUT STD_LOGIC_VECTOR( 4 DOWNTO 0 ); -- Are Aim X Y Z
41 sel_op2 : OUT STD_LOGIC_VECTOR( 4 DOWNTO 0 ); -- Bre Bim C_in cps_in cms_in
42 sel_xyz : OUT STD_LOGIC_VECTOR( 2 DOWNTO 0 ); -- X Y Z
43 sel_out : OUT STD_LOGIC_VECTOR( 3 DOWNTO 0 );
44 alu_ctrl : OUT STD_LOGIC_VECTOR( 2 DOWNTO 0 );
45 alu_comp : OUT STD_LOGIC_VECTOR( 1 DOWNTO 0 )
46 );
47 END BUTTERFLY_CTRL;
48
49 ARCHITECTURE ar_BUTTERFLY_CTRL OF BUTTERFLY_CTRL IS
50
51 TYPE fsm_BUTTERFLY_CTRL_T IS ( waiting,
52 add1,
53 add2,
54 add3,
55 add4,
56 mult5,
57 mac6,
58 mac7,
59 mult8,
60 mac9,
61 last10,
62 last11,
63 last12);
64 SIGNAL BUTTERFLY_CTRL_STATE : fsm_BUTTERFLY_CTRL_T;
65
66 BEGIN
67
68 PROCESS (clk, rstn)
69
70 BEGIN -- PROCESS
71 IF rstn = '0' THEN -- asynchronous reset (active low)
72 --REG -------------------------------------------------------------------
73 sel_xyz <= (OTHERS => '0');
74 sel_out <= (OTHERS => '0');
75 --ALU -------------------------------------------------------------------
76 sel_op1 <= (OTHERS => '0');
77 sel_op2 <= (OTHERS => '0');
78 alu_ctrl <= ctrl_IDLE;
79 alu_comp <= (OTHERS => '0');
80 --OUT
81 sample_out_val <= '0';
82
83 BUTTERFLY_CTRL_STATE <= waiting;
84
85 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
86
87 CASE BUTTERFLY_CTRL_STATE IS
88
89 WHEN waiting =>
90 IF sample_in_val = '1' THEN
91 BUTTERFLY_CTRL_STATE <= add1;
92 END IF;
93 sel_op1 <= "00000"; -- Are
94 sel_op2 <= "00000"; -- Bre
95 alu_comp <= "00";
96 alu_ctrl <= ctrl_IDLE;
97 sel_out <= "0000";
98 sample_out_val <= '0';
99
100 WHEN add1 =>
101 sample_out_val <= '0';
102 sel_op1 <= "10000"; -- Are
103 sel_op2 <= "10000"; -- Bre
104 alu_comp <= "10";
105 alu_ctrl <= ctrl_ADD;
106 sel_out <= "0000";
107 sample_out_val <= '0';
108 BUTTERFLY_CTRL_STATE <= add2;
109
110 WHEN add2 =>
111 sample_out_val <= '0';
112 sel_op1 <= "01000"; -- Aim
113 sel_op2 <= "01000"; -- Bim
114 alu_comp <= "10";
115 alu_ctrl <= ctrl_ADD;
116 sel_out <= "0000";
117 BUTTERFLY_CTRL_STATE <= add3;
118
119 WHEN add3 =>
120 sample_out_val <= '0';
121 sel_op1 <= "10000"; -- Are
122 sel_op2 <= "10000"; -- Bre
123 alu_comp <= "00";
124 alu_ctrl <= ctrl_ADD;
125 sel_out <= "0000";
126 BUTTERFLY_CTRL_STATE <= add4;
127
128 WHEN add4 =>
129 sample_out_val <= '0';
130 sel_op1 <= "01000"; -- Aim
131 sel_op2 <= "01000"; -- Bim
132 alu_comp <= "00";
133 alu_ctrl <= ctrl_ADD;
134 sel_out <= "0000";
135 sel_xyz <= "100"; -- X
136 BUTTERFLY_CTRL_STATE <= mult5;
137
138 WHEN mult5 =>
139 sample_out_val <= '0';
140 sel_op1 <= "00100"; -- X
141 sel_op2 <= "00100"; -- c
142 alu_comp <= "00";
143 alu_ctrl <= ctrl_MULT;
144 sel_out <= "0000";
145 sel_xyz <= "010"; -- Y
146 BUTTERFLY_CTRL_STATE <= mac6;
147
148 WHEN mac6 =>
149 sample_out_val <= '0';
150 sel_op1 <= "00010"; -- Y
151 sel_op2 <= "00100"; -- c
152 alu_comp <= "10";
153 alu_ctrl <= ctrl_MAC;
154 sel_out <= "0001"; -- *** /!\ *** --
155 sample_out_val <= '1';
156 sel_xyz <= "000"; -- Y
157 BUTTERFLY_CTRL_STATE <= mac7;
158
159 WHEN mac7 =>
160 sample_out_val <= '0';
161 sel_op1 <= "00010"; -- Y
162 sel_op2 <= "00001"; -- cms
163 alu_comp <= "00";
164 alu_ctrl <= ctrl_MAC;
165 sel_out <= "0010"; -- *** /!\ *** --
166 sample_out_val <= '1';
167 BUTTERFLY_CTRL_STATE <= mult8;
168
169 WHEN mult8 =>
170 sample_out_val <= '0';
171 sel_op1 <= "00100"; -- X
172 sel_op2 <= "00010"; -- cps
173 alu_comp <= "00";
174 alu_ctrl <= ctrl_MULT;
175 sel_out <= "0000";
176 sample_out_val <= '0';
177 BUTTERFLY_CTRL_STATE <= mac9;
178
179 WHEN mac9 =>
180 sample_out_val <= '0';
181 alu_ctrl <= ctrl_MAC;
182 sel_op1 <= "00000"; -- Z is taken directly from the output of the ALU
183 sel_op2 <= "00000"; -- 1
184 alu_comp <= "10";
185 sel_out <= "0000";
186 sample_out_val <= '0';
187 BUTTERFLY_CTRL_STATE <= last10;
188
189 WHEN last10 =>
190 sample_out_val <= '0';
191 sel_op1 <= "10000";
192 sel_op2 <= "10000";
193 alu_comp <= "10";
194 alu_ctrl <= ctrl_IDLE;
195 sel_out <= "0100"; -- *** /!\ *** --
196 sample_out_val <= '1';
197 BUTTERFLY_CTRL_STATE <= last11;
198
199 WHEN last11 =>
200 sample_out_val <= '0';
201 alu_comp <= "10";
202 alu_ctrl <= ctrl_IDLE;
203 sel_out <= "0000";
204 sample_out_val <= '0';
205 BUTTERFLY_CTRL_STATE <= last12;
206
207 WHEN last12 =>
208 sample_out_val <= '0';
209 alu_comp <= "10";
210 alu_ctrl <= ctrl_IDLE;
211 sel_out <= "1000"; -- *** /!\ *** --
212 sample_out_val <= '1';
213 BUTTERFLY_CTRL_STATE <= waiting;
214
215 WHEN OTHERS =>
216 NULL;
217
218 END CASE;
219
220 END IF;
221
222 END PROCESS;
223
224 END ar_BUTTERFLY_CTRL; No newline at end of file
Show file before | Show file after | Hide comments
@@ -0,0 +1,104
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more Cdetails.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
19 -- Author : Paul LEROY
20 -- Mail : paul.leroy@lpp.polytechnique.fr
21 -------------------------------------------------------------------------------
22
23 LIBRARY IEEE;
24 USE IEEE.numeric_std.ALL;
25 USE IEEE.std_logic_1164.ALL;
26
27 LIBRARY staging_lpp;
28 USE staging_lpp.PLE_general_purpose.ALL;
29 use staging_lpp.PLE_lpp_fft.all;
30
31 ENTITY BUTTERFLY_TOP IS
32 GENERIC (
33 Sample_SZ : INTEGER := 16);
34 PORT (
35 rstn : IN STD_LOGIC;
36 clk : IN STD_LOGIC;
37
38 sample_in_val : IN STD_LOGIC;
39 sample_out_val : OUT STD_LOGIC;
40
41 Are : IN STD_LOGIC_VECTOR ( Sample_SZ-1 DOWNTO 0);
42 Aim : IN STD_LOGIC_VECTOR ( Sample_SZ-1 DOWNTO 0);
43 Bre : IN STD_LOGIC_VECTOR ( Sample_SZ-1 DOWNTO 0);
44 Bim : IN STD_LOGIC_VECTOR ( Sample_SZ-1 DOWNTO 0);
45 c_in : IN STD_LOGIC_VECTOR ( Sample_SZ-1 DOWNTO 0);
46 cps_in : IN STD_LOGIC_VECTOR ( Sample_SZ-1 DOWNTO 0);
47 cms_in : IN STD_LOGIC_VECTOR ( Sample_SZ-1 DOWNTO 0);
48
49 butterfly_out : OUT STD_LOGIC_VECTOR ( 2*Sample_SZ-1 DOWNTO 0);
50 sel_out : OUT STD_LOGIC_VECTOR ( 3 DOWNTO 0)
51 );
52 END BUTTERFLY_TOP;
53
54 ARCHITECTURE ar_BUTTERFLY_TOP OF BUTTERFLY_TOP IS
55
56 SIGNAL sel_op1 : STD_LOGIC_VECTOR( 4 DOWNTO 0 ); -- Are Aim X Y Z
57 SIGNAL sel_op2 : STD_LOGIC_VECTOR( 4 DOWNTO 0 ); -- Bre Bim C_in cps_in cms_in
58 SIGNAL sel_xyz : STD_LOGIC_VECTOR( 2 DOWNTO 0 ); -- X Y Z
59 SIGNAL alu_ctrl_sig : STD_LOGIC_VECTOR( 2 DOWNTO 0 );
60 SIGNAL alu_comp_sig : STD_LOGIC_VECTOR( 1 DOWNTO 0 );
61
62 BEGIN
63
64 BUTTERFLY_DATAFLOW_1 : BUTTERFLY_DATAFLOW
65 GENERIC MAP (
66 Sample_SZ => 16)
67 PORT MAP (
68 rstn => rstn,
69 clk => clk,
70
71 Are => Are,
72 Aim => Aim,
73 Bre => Bre,
74 Bim => Bim,
75 c_in => c_in,
76 cps_in => cps_in,
77 cms_in => cms_in,
78
79 out_alu => butterfly_out,
80
81 sel_op1 => sel_op1,
82 sel_op2 => sel_op2,
83 sel_xyz => sel_xyz,
84 alu_ctrl => alu_ctrl_sig,
85 alu_comp => alu_comp_sig
86 );
87
88 BUTTERFLY_CTRL_1 : BUTTERFLY_CTRL
89 PORT MAP(
90 rstn => rstn,
91 clk => clk,
92
93 sample_in_val => sample_in_val,
94 sample_out_val => sample_out_val,
95
96 sel_op1 => sel_op1,
97 sel_op2 => sel_op2,
98 sel_xyz => sel_xyz,
99 sel_out => sel_out,
100 alu_ctrl => alu_ctrl_sig,
101 alu_comp => alu_comp_sig
102 );
103
104 END ar_BUTTERFLY_TOP; No newline at end of file
Show file before | Show file after | Hide comments
@@ -0,0 +1,133
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more Cdetails.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
19 -- Author : Paul LEROY
20 -- Mail : paul.leroy@lpp.polytechnique.fr
21 -------------------------------------------------------------------------------
22
23 LIBRARY IEEE;
24 USE IEEE.numeric_std.ALL;
25 USE IEEE.std_logic_1164.ALL;
26 LIBRARY staging_lpp;
27 USE staging_lpp.PLE_general_purpose.ALL;
28
29 ENTITY BUTTERFLY_DATAFLOW IS
30 GENERIC (
31 Sample_SZ : INTEGER := 16
32 );
33 PORT (
34 rstn : IN STD_LOGIC;
35 clk : IN STD_LOGIC;
36
37 Are : IN STD_LOGIC_VECTOR ( Sample_SZ-1 DOWNTO 0);
38 Aim : IN STD_LOGIC_VECTOR ( Sample_SZ-1 DOWNTO 0);
39 Bre : IN STD_LOGIC_VECTOR ( Sample_SZ-1 DOWNTO 0);
40 Bim : IN STD_LOGIC_VECTOR ( Sample_SZ-1 DOWNTO 0);
41 c_in : IN STD_LOGIC_VECTOR ( Sample_SZ-1 DOWNTO 0);
42 cps_in : IN STD_LOGIC_VECTOR ( Sample_SZ-1 DOWNTO 0);
43 cms_in : IN STD_LOGIC_VECTOR ( Sample_SZ-1 DOWNTO 0);
44
45 op1 : OUT STD_LOGIC_VECTOR ( Sample_SZ-1 DOWNTO 0);
46 op2 : OUT STD_LOGIC_VECTOR ( Sample_SZ-1 DOWNTO 0);
47
48 out_alu : OUT STD_LOGIC_VECTOR ( 2*Sample_SZ-1 DOWNTO 0);
49
50 sel_op1 : IN STD_LOGIC_VECTOR( 4 DOWNTO 0 ); -- Are Aim X Y Z
51 sel_op2 : IN STD_LOGIC_VECTOR( 4 DOWNTO 0 ); -- Bre Bim C_in cps_in cms_in
52 sel_xyz : IN STD_LOGIC_VECTOR( 2 DOWNTO 0 ); -- X Y Z
53 alu_ctrl : IN STD_LOGIC_VECTOR( 2 DOWNTO 0 );
54 alu_comp : IN STD_LOGIC_VECTOR( 1 DOWNTO 0 )
55 );
56 END BUTTERFLY_DATAFLOW;
57
58 ARCHITECTURE ar_BUTTERFLY_DATAFLOW OF BUTTERFLY_DATAFLOW IS
59
60 SIGNAL X : STD_LOGIC_VECTOR( Sample_SZ-1 DOWNTO 0 );
61 SIGNAL Y : STD_LOGIC_VECTOR( Sample_SZ-1 DOWNTO 0 );
62 SIGNAL Z : STD_LOGIC_VECTOR( Sample_SZ-1 DOWNTO 0 );
63
64 SIGNAL ALU_OP1 : STD_LOGIC_VECTOR( Sample_SZ-1 DOWNTO 0 );
65 SIGNAL ALU_OP2 : STD_LOGIC_VECTOR( Sample_SZ-1 DOWNTO 0 );
66
67 SIGNAL OUT_ALU_SIG : STD_LOGIC_VECTOR ( 2*Sample_SZ-1 DOWNTO 0);
68
69 BEGIN
70
71 out_alu <= OUT_ALU_SIG;
72
73 PROCESS (clk, rstn)
74
75 BEGIN -- PROCESS
76 IF rstn = '0' THEN -- asynchronous reset (active low)
77 X <= (OTHERS => '0');
78 Y <= (OTHERS => '0');
79 Z <= (OTHERS => '0');
80
81 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
82
83 if sel_xyz = "100" THEN
84 X <= STD_LOGIC_VECTOR(resize(SIGNED(OUT_ALU_SIG), Sample_SZ));
85 elsif sel_xyz = "010" THEN
86 Y <= STD_LOGIC_VECTOR(resize(SIGNED(OUT_ALU_SIG), Sample_SZ));
87 elsif sel_xyz = "001" THEN
88 Z <= STD_LOGIC_VECTOR(resize(SIGNED(OUT_ALU_SIG), Sample_SZ));
89 else
90 X <= X;
91 Y <= Y;
92 Z <= Z;
93 end if;
94
95 END IF;
96
97 END PROCESS;
98
99 op1 <= ALU_OP1;
100 op2 <= ALU_OP2;
101
102 ALU_OP1 <= Are WHEN sel_op1 = "10000" ELSE
103 Aim WHEN sel_op1 = "01000" ELSE
104 X WHEN sel_op1 = "00100" ELSE
105 Y WHEN sel_op1 = "00010" ELSE
106 Z WHEN sel_op1 = "00001" ELSE
107 STD_LOGIC_VECTOR(resize(SIGNED(OUT_ALU_SIG), Sample_SZ)) WHEN sel_op1 = "00000" ELSE
108 (OTHERS => '0');
109
110 ALU_OP2 <= Bre WHEN sel_op2 = "10000" ELSE
111 Bim WHEN sel_op2 = "01000" ELSE
112 c_in WHEN sel_op2 = "00100" ELSE
113 cps_in WHEN sel_op2 = "00010" ELSE
114 cms_in WHEN sel_op2 = "00001" ELSE
115 std_logic_vector(TO_SIGNED(1,Sample_SZ)) WHEN sel_op2 = "00000" ELSE
116 (OTHERS => '0');
117
118 ALU_1: ALU
119 GENERIC MAP (
120 Arith_en => 1,
121 Input_SZ_1 => Sample_SZ,
122 Input_SZ_2 => Sample_SZ,
123 COMP_EN => 0) -- comp is enable when COMP_EN is 0
124 PORT MAP (
125 clk => clk,
126 reset => rstn,
127 ctrl => alu_ctrl,
128 comp => alu_comp,
129 OP1 => ALU_OP1,
130 OP2 => ALU_OP2,
131 RES => OUT_ALU_SIG);
132
133 END ar_BUTTERFLY_DATAFLOW; No newline at end of file
Show file before | Show file after | Hide comments
@@ -0,0 +1,120
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
19 -- Author : Paul Leroy
20 -- Mail : paul.leroy@lpp.polytechnique.fr
21 ----------------------------------------------------------------------------
22
23
24 LIBRARY ieee;
25 USE ieee.std_logic_1164.ALL;
26
27 LIBRARY staging_LPP;
28 USE staging_LPP.PLE_iir_filter.ALL;
29
30 PACKAGE PLE_lpp_fft IS
31
32 COMPONENT BUTTERFLY_DATAFLOW
33 GENERIC (
34 Sample_SZ : INTEGER := 16);
35 PORT (
36 rstn : IN STD_LOGIC;
37 clk : IN STD_LOGIC;
38
39 Are : IN STD_LOGIC_VECTOR ( Sample_SZ-1 DOWNTO 0);
40 Aim : IN STD_LOGIC_VECTOR ( Sample_SZ-1 DOWNTO 0);
41 Bre : IN STD_LOGIC_VECTOR ( Sample_SZ-1 DOWNTO 0);
42 Bim : IN STD_LOGIC_VECTOR ( Sample_SZ-1 DOWNTO 0);
43 c_in : IN STD_LOGIC_VECTOR ( Sample_SZ-1 DOWNTO 0);
44 cps_in : IN STD_LOGIC_VECTOR ( Sample_SZ-1 DOWNTO 0);
45 cms_in : IN STD_LOGIC_VECTOR ( Sample_SZ-1 DOWNTO 0);
46
47 out_alu : OUT STD_LOGIC_VECTOR ( 2*Sample_SZ-1 DOWNTO 0);
48
49 sel_op1 : IN STD_LOGIC_VECTOR( 4 DOWNTO 0 ); -- Are Aim X Y Z
50 sel_op2 : IN STD_LOGIC_VECTOR( 4 DOWNTO 0 ); -- Bre Bim C_in cps_in cms_in
51 sel_xyz : IN STD_LOGIC_VECTOR( 2 DOWNTO 0 ); -- X Y Z
52 alu_ctrl : IN STD_LOGIC_VECTOR( 2 DOWNTO 0 );
53 alu_comp : IN STD_LOGIC_VECTOR( 1 DOWNTO 0 )
54 );
55 END COMPONENT;
56
57 COMPONENT BUTTERFLY_CTRL
58 PORT (
59 rstn : IN STD_LOGIC;
60 clk : IN STD_LOGIC;
61
62 sample_in_val : IN STD_LOGIC;
63 sample_out_val : OUT STD_LOGIC;
64
65 sel_op1 : OUT STD_LOGIC_VECTOR( 4 DOWNTO 0 ); -- Are Aim X Y Z
66 sel_op2 : OUT STD_LOGIC_VECTOR( 4 DOWNTO 0 ); -- Bre Bim C_in cps_in cms_in
67 sel_xyz : OUT STD_LOGIC_VECTOR( 2 DOWNTO 0 ); -- X Y Z
68 sel_out : OUT STD_LOGIC_VECTOR( 3 DOWNTO 0 );
69 alu_ctrl : OUT STD_LOGIC_VECTOR( 2 DOWNTO 0 );
70 alu_comp : OUT STD_LOGIC_VECTOR( 1 DOWNTO 0 )
71 );
72 END COMPONENT;
73
74 COMPONENT BUTTERFLY_TOP
75 GENERIC (
76 Sample_SZ : INTEGER := 16);
77 PORT (
78 rstn : IN STD_LOGIC;
79 clk : IN STD_LOGIC;
80
81 sample_in_val : IN STD_LOGIC;
82 sample_out_val : OUT STD_LOGIC;
83
84 Are : IN STD_LOGIC_VECTOR ( Sample_SZ-1 DOWNTO 0);
85 Aim : IN STD_LOGIC_VECTOR ( Sample_SZ-1 DOWNTO 0);
86 Bre : IN STD_LOGIC_VECTOR ( Sample_SZ-1 DOWNTO 0);
87 Bim : IN STD_LOGIC_VECTOR ( Sample_SZ-1 DOWNTO 0);
88 c_in : IN STD_LOGIC_VECTOR ( Sample_SZ-1 DOWNTO 0);
89 cps_in : IN STD_LOGIC_VECTOR ( Sample_SZ-1 DOWNTO 0);
90 cms_in : IN STD_LOGIC_VECTOR ( Sample_SZ-1 DOWNTO 0);
91
92 butterfly_out : OUT STD_LOGIC_VECTOR ( 2*Sample_SZ-1 DOWNTO 0);
93 sel_out : OUT STD_LOGIC_VECTOR ( 3 DOWNTO 0)
94 );
95 END COMPONENT;
96
97 COMPONENT input_buffers_and_coefficients
98 GENERIC(
99 tech : INTEGER := 0;
100 Input_SZ_1 : INTEGER := 16;
101 Mem_use : INTEGER := use_RAM -- 1 use RAM
102 );
103 PORT(
104 rstn : IN STD_LOGIC;
105 clk : IN STD_LOGIC;
106 --*******************
107 -- PLE **************
108 WD_in : IN STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0);
109 RD_out : OUT STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0);
110 WEN_in : IN STD_LOGIC;
111 REN_in : IN STD_LOGIC;
112 RADDR_in : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
113 WADDR_in : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
114 start : IN STD_LOGIC
115 --*******************
116 --*******************
117 );
118 END COMPONENT;
119
120 END; No newline at end of file
Show file before | Show file after | Hide comments
@@ -0,0 +1,30
1 vlib staging_lpp
2 vmap staging_lpp "staging_lpp"
3
4 vcom -93 -explicit -work staging_lpp "../../../general_purpose/general_purpose.vhd"
5 vcom -93 -explicit -work staging_lpp "../../../general_purpose/MAC_CONTROLER.vhd"
6 vcom -93 -explicit -work staging_lpp "../../../general_purpose/Multiplier.vhd"
7 vcom -93 -explicit -work staging_lpp "../../../general_purpose/Adder.vhd"
8 vcom -93 -explicit -work staging_lpp "../../../general_purpose/TwoComplementer.vhd"
9 vcom -93 -explicit -work staging_lpp "../../../general_purpose/MAC_REG.vhd"
10 vcom -93 -explicit -work staging_lpp "../../../general_purpose/MAC_MUX.vhd"
11 vcom -93 -explicit -work staging_lpp "../../../general_purpose/MAC_MUX2.vhd"
12 vcom -93 -explicit -work staging_lpp "../../../general_purpose/MAC.vhd"
13 vcom -93 -explicit -work staging_lpp "../../../general_purpose/ALU.vhd"
14
15 vcom -93 -explicit -work staging_lpp "../lpp_fft.vhd"
16 vcom -93 -explicit -work staging_lpp "../LPP_BUTTERFLY_DATAFLOW.vhd"
17 vcom -93 -explicit -work staging_lpp "../BUTTERFLY_CTRL.vhd"
18 vcom -93 -explicit -work staging_lpp "../BUTTERFLY_TOP.vhd"
19 vcom -93 -explicit -work staging_lpp "testBench_BUTTERFLY_TOP.vhd"
20
21 vsim -L staging_lpp -t 1ps staging_lpp.TestBench_BUTTERFLY_TOP
22
23 do wave.do
24
25 log -R *
26
27 run 1 us
28 # The following lines are commented because no testbench is associated with the project
29 # add wave /testbench/*
30 # run 1000ns
Show file before | Show file after | Hide comments
@@ -0,0 +1,104
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
19 -- Author : Paul Leroy
20 -- Mail : paul.leroy@lpp.polytechnique.fr
21 ----------------------------------------------------------------------------
22 library IEEE;
23 use IEEE.numeric_std.all;
24 use IEEE.std_logic_1164.all;
25
26 library staging_lpp;
27 use staging_lpp.PLE_lpp_fft.all;
28
29 entity TestBench_BUTTERFLY_TOP is
30
31 end TestBench_BUTTERFLY_TOP;
32
33 architecture TestBench_BUTTERFLY_TOP of TestBench_BUTTERFLY_TOP is
34
35 constant Sample_SZ : integer := 16;
36
37 signal clk : std_logic:='0';
38 signal rstn : std_logic:='0';
39
40 signal Are : std_logic_vector( Sample_SZ-1 downto 0 ) := ( others => '0');
41 signal Aim : std_logic_vector( Sample_SZ-1 downto 0 ) := ( others => '0');
42 signal Bre : std_logic_vector( Sample_SZ-1 downto 0 ) := ( others => '0');
43 signal Bim : std_logic_vector( Sample_SZ-1 downto 0 ) := ( others => '0');
44 signal c : std_logic_vector( Sample_SZ-1 downto 0 ) := ( others => '0');
45 signal cps : std_logic_vector( Sample_SZ-1 downto 0 ) := ( others => '0');
46 signal cms : std_logic_vector( Sample_SZ-1 downto 0 ) := ( others => '0');
47
48 signal Resultat : std_logic_vector( 2*Sample_SZ-1 downto 0 );
49
50 signal sel_out : std_logic_vector( 3 downto 0 );
51
52 signal sample_in_val : std_logic := '0';
53 signal sample_out_val : std_logic;
54
55 begin
56
57 BUTTERFLY_TOP1 : BUTTERFLY_TOP
58 generic map(
59 Sample_SZ => Sample_SZ
60 )
61 port map(
62 rstn => rstn,
63 clk => clk,
64
65 sample_in_val => sample_in_val,
66 sample_out_val => sample_out_val,
67
68 Are => Are,
69 Aim => Aim,
70 Bre => Bre,
71 Bim => Bim,
72 c_in => c,
73 cps_in => cps,
74 cms_in => cms,
75
76 butterfly_out => Resultat,
77 sel_out => sel_out
78 );
79
80 clk <= not clk after 25 ns;
81
82 process
83 begin
84
85 if rstn = '0' then
86 wait for 40 ns;
87 rstn <= '1';
88 end if;
89
90 wait for 11 ns;
91 Are <= std_logic_vector(TO_SIGNED(100 ,Sample_SZ));
92 Aim <= std_logic_vector(TO_SIGNED(110 ,Sample_SZ));
93 Bre <= std_logic_vector(TO_SIGNED(-40 ,Sample_SZ));
94 Bim <= std_logic_vector(TO_SIGNED(10 ,Sample_SZ));
95 c <= std_logic_vector(TO_SIGNED(121 ,Sample_SZ));
96 cps <= std_logic_vector(TO_SIGNED(160 ,Sample_SZ));
97 cms <= std_logic_vector(TO_SIGNED(82 ,Sample_SZ));
98
99 wait for 50 ns;
100 sample_in_val <= '1';
101
102 end process;
103
104 end TestBench_BUTTERFLY_TOP;
Show file before | Show file after | Hide comments
@@ -0,0 +1,36
1 onerror {resume}
2 quietly WaveActivateNextPane {} 0
3 add wave -noupdate /testbench_butterfly_top/clk
4 add wave -noupdate /testbench_butterfly_top/rstn
5 add wave -noupdate -radix decimal /testbench_butterfly_top/are
6 add wave -noupdate -radix decimal /testbench_butterfly_top/aim
7 add wave -noupdate -radix decimal /testbench_butterfly_top/bre
8 add wave -noupdate -radix decimal /testbench_butterfly_top/bim
9 add wave -noupdate -radix decimal /testbench_butterfly_top/c
10 add wave -noupdate -radix decimal /testbench_butterfly_top/cps
11 add wave -noupdate -radix decimal /testbench_butterfly_top/cms
12 add wave -noupdate -radix decimal /testbench_butterfly_top/op1
13 add wave -noupdate -radix decimal /testbench_butterfly_top/op2
14 add wave -noupdate -radix decimal /testbench_butterfly_top/resultat
15 add wave -noupdate /testbench_butterfly_top/alu_ctrl_sig
16 add wave -noupdate /testbench_butterfly_top/alu_comp_sig
17 add wave -noupdate /testbench_butterfly_top/sel_out
18 add wave -noupdate /testbench_butterfly_top/sample_in_val
19 add wave -noupdate /testbench_butterfly_top/sample_out_val
20 TreeUpdate [SetDefaultTree]
21 WaveRestoreCursors {{Cursor 1} {149541 ps} 0}
22 configure wave -namecolwidth 150
23 configure wave -valuecolwidth 100
24 configure wave -justifyvalue left
25 configure wave -signalnamewidth 0
26 configure wave -snapdistance 10
27 configure wave -datasetprefix 0
28 configure wave -rowmargin 4
29 configure wave -childrowmargin 2
30 configure wave -gridoffset 0
31 configure wave -gridperiod 1000
32 configure wave -griddelta 40
33 configure wave -timeline 0
34 configure wave -timelineunits ns
35 update
36 WaveRestoreZoom {0 ps} {1050 ns}
Show file before | Show file after | Hide comments
@@ -0,0 +1,467
1 --twiddle_factors_128.vhd
2
3 library IEEE;
4 use IEEE.numeric_std.all;
5 use IEEE.std_logic_1164.all;
6
7 package PLE_twiddle_factors_128 is
8
9 constant Coef_SZ : integer := 16;
10 constant NB_Coeffs : integer := 128;
11
12 --============================================================
13 -- create each initial values for each coefs ============
14 --!!!!!!!!!!It should be interfaced with a software !!!!!!!!!!
15 --============================================================
16
17 constant c_0 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ));
18 constant c_1 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ));
19 constant c_2 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ));
20 constant c_3 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ));
21 constant c_4 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ));
22 constant c_5 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ));
23 constant c_6 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ));
24 constant c_7 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ));
25 constant c_8 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ));
26 constant c_9 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ));
27 constant c_10 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ));
28 constant c_11 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ));
29 constant c_12 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ));
30 constant c_13 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ));
31 constant c_14 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ));
32 constant c_15 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ));
33 constant c_16 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ));
34 constant c_17 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ));
35 constant c_18 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ));
36 constant c_19 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ));
37 constant c_20 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ));
38 constant c_21 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ));
39 constant c_22 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ));
40 constant c_23 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ));
41 constant c_24 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ));
42 constant c_25 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ));
43 constant c_26 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ));
44 constant c_27 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ));
45 constant c_28 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ));
46 constant c_29 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ));
47 constant c_30 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ));
48 constant c_31 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ));
49 constant c_32 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ));
50 constant c_33 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ));
51 constant c_34 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ));
52 constant c_35 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ));
53 constant c_36 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ));
54 constant c_37 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ));
55 constant c_38 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ));
56 constant c_39 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ));
57 constant c_40 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ));
58 constant c_41 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ));
59 constant c_42 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ));
60 constant c_43 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ));
61 constant c_44 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ));
62 constant c_45 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ));
63 constant c_46 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ));
64 constant c_47 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ));
65 constant c_48 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ));
66 constant c_49 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ));
67 constant c_50 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ));
68 constant c_51 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ));
69 constant c_52 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ));
70 constant c_53 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ));
71 constant c_54 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ));
72 constant c_55 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ));
73 constant c_56 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ));
74 constant c_57 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ));
75 constant c_58 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ));
76 constant c_59 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ));
77 constant c_60 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ));
78 constant c_61 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ));
79 constant c_62 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ));
80 constant c_63 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ));
81 constant c_64 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ));
82 constant c_65 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ));
83 constant c_66 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ));
84 constant c_67 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ));
85 constant c_68 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ));
86 constant c_69 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ));
87 constant c_70 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ));
88 constant c_71 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ));
89 constant c_72 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ));
90 constant c_73 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ));
91 constant c_74 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ));
92 constant c_75 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ));
93 constant c_76 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ));
94 constant c_77 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ));
95 constant c_78 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ));
96 constant c_79 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ));
97 constant c_80 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ));
98 constant c_81 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ));
99 constant c_82 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ));
100 constant c_83 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ));
101 constant c_84 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ));
102 constant c_85 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ));
103 constant c_86 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ));
104 constant c_87 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ));
105 constant c_88 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ));
106 constant c_89 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ));
107 constant c_90 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ));
108 constant c_91 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ));
109 constant c_92 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ));
110 constant c_93 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ));
111 constant c_94 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ));
112 constant c_95 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ));
113 constant c_96 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ));
114 constant c_97 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ));
115 constant c_98 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ));
116 constant c_99 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ));
117 constant c_100 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ));
118 constant c_101 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ));
119 constant c_102 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ));
120 constant c_103 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ));
121 constant c_104 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ));
122 constant c_105 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ));
123 constant c_106 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ));
124 constant c_107 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ));
125 constant c_108 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ));
126 constant c_109 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ));
127 constant c_110 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ));
128 constant c_111 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ));
129 constant c_112 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ));
130 constant c_113 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ));
131 constant c_114 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ));
132 constant c_115 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ));
133 constant c_116 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ));
134 constant c_117 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ));
135 constant c_118 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ));
136 constant c_119 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ));
137 constant c_120 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ));
138 constant c_121 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ));
139 constant c_122 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ));
140 constant c_123 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ));
141 constant c_124 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ));
142 constant c_125 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ));
143 constant c_126 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ));
144 constant c_127 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ));
145
146 --************************************************--
147
148 constant cps_0 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ));
149 constant cps_1 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ));
150 constant cps_2 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ));
151 constant cps_3 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ));
152 constant cps_4 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ));
153 constant cps_5 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ));
154 constant cps_6 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ));
155 constant cps_7 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ));
156 constant cps_8 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ));
157 constant cps_9 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ));
158 constant cps_10 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ));
159 constant cps_11 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ));
160 constant cps_12 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ));
161 constant cps_13 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ));
162 constant cps_14 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ));
163 constant cps_15 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ));
164 constant cps_16 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ));
165 constant cps_17 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ));
166 constant cps_18 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ));
167 constant cps_19 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ));
168 constant cps_20 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ));
169 constant cps_21 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ));
170 constant cps_22 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ));
171 constant cps_23 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ));
172 constant cps_24 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ));
173 constant cps_25 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ));
174 constant cps_26 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ));
175 constant cps_27 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ));
176 constant cps_28 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ));
177 constant cps_29 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ));
178 constant cps_30 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ));
179 constant cps_31 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ));
180 constant cps_32 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ));
181 constant cps_33 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ));
182 constant cps_34 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ));
183 constant cps_35 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ));
184 constant cps_36 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ));
185 constant cps_37 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ));
186 constant cps_38 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ));
187 constant cps_39 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ));
188 constant cps_40 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ));
189 constant cps_41 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ));
190 constant cps_42 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ));
191 constant cps_43 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ));
192 constant cps_44 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ));
193 constant cps_45 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ));
194 constant cps_46 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ));
195 constant cps_47 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ));
196 constant cps_48 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ));
197 constant cps_49 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ));
198 constant cps_50 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ));
199 constant cps_51 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ));
200 constant cps_52 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ));
201 constant cps_53 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ));
202 constant cps_54 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ));
203 constant cps_55 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ));
204 constant cps_56 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ));
205 constant cps_57 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ));
206 constant cps_58 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ));
207 constant cps_59 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ));
208 constant cps_60 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ));
209 constant cps_61 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ));
210 constant cps_62 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ));
211 constant cps_63 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ));
212 constant cps_64 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ));
213 constant cps_65 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ));
214 constant cps_66 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ));
215 constant cps_67 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ));
216 constant cps_68 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ));
217 constant cps_69 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ));
218 constant cps_70 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ));
219 constant cps_71 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ));
220 constant cps_72 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ));
221 constant cps_73 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ));
222 constant cps_74 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ));
223 constant cps_75 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ));
224 constant cps_76 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ));
225 constant cps_77 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ));
226 constant cps_78 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ));
227 constant cps_79 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ));
228 constant cps_80 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ));
229 constant cps_81 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ));
230 constant cps_82 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ));
231 constant cps_83 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ));
232 constant cps_84 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ));
233 constant cps_85 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ));
234 constant cps_86 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ));
235 constant cps_87 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ));
236 constant cps_88 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ));
237 constant cps_89 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ));
238 constant cps_90 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ));
239 constant cps_91 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ));
240 constant cps_92 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ));
241 constant cps_93 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ));
242 constant cps_94 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ));
243 constant cps_95 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ));
244 constant cps_96 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ));
245 constant cps_97 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ));
246 constant cps_98 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ));
247 constant cps_99 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ));
248 constant cps_100 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ));
249 constant cps_101 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ));
250 constant cps_102 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ));
251 constant cps_103 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ));
252 constant cps_104 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ));
253 constant cps_105 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ));
254 constant cps_106 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ));
255 constant cps_107 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ));
256 constant cps_108 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ));
257 constant cps_109 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ));
258 constant cps_110 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ));
259 constant cps_111 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ));
260 constant cps_112 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ));
261 constant cps_113 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ));
262 constant cps_114 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ));
263 constant cps_115 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ));
264 constant cps_116 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ));
265 constant cps_117 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ));
266 constant cps_118 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ));
267 constant cps_119 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ));
268 constant cps_120 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ));
269 constant cps_121 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ));
270 constant cps_122 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ));
271 constant cps_123 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ));
272 constant cps_124 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ));
273 constant cps_125 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ));
274 constant cps_126 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ));
275 constant cps_127 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ));
276
277 --************************************************--
278
279 constant cms_0 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ));
280 constant cms_1 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ));
281 constant cms_2 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ));
282 constant cms_3 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ));
283 constant cms_4 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ));
284 constant cms_5 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ));
285 constant cms_6 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ));
286 constant cms_7 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ));
287 constant cms_8 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ));
288 constant cms_9 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ));
289 constant cms_10 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ));
290 constant cms_11 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ));
291 constant cms_12 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ));
292 constant cms_13 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ));
293 constant cms_14 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ));
294 constant cms_15 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ));
295 constant cms_16 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ));
296 constant cms_17 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ));
297 constant cms_18 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ));
298 constant cms_19 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ));
299 constant cms_20 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ));
300 constant cms_21 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ));
301 constant cms_22 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ));
302 constant cms_23 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ));
303 constant cms_24 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ));
304 constant cms_25 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ));
305 constant cms_26 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ));
306 constant cms_27 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ));
307 constant cms_28 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ));
308 constant cms_29 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ));
309 constant cms_30 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ));
310 constant cms_31 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ));
311 constant cms_32 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ));
312 constant cms_33 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ));
313 constant cms_34 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ));
314 constant cms_35 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ));
315 constant cms_36 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ));
316 constant cms_37 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ));
317 constant cms_38 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ));
318 constant cms_39 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ));
319 constant cms_40 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ));
320 constant cms_41 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ));
321 constant cms_42 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ));
322 constant cms_43 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ));
323 constant cms_44 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ));
324 constant cms_45 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ));
325 constant cms_46 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ));
326 constant cms_47 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ));
327 constant cms_48 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ));
328 constant cms_49 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ));
329 constant cms_50 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ));
330 constant cms_51 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ));
331 constant cms_52 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ));
332 constant cms_53 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ));
333 constant cms_54 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ));
334 constant cms_55 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ));
335 constant cms_56 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ));
336 constant cms_57 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ));
337 constant cms_58 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ));
338 constant cms_59 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ));
339 constant cms_60 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ));
340 constant cms_61 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ));
341 constant cms_62 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ));
342 constant cms_63 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ));
343 constant cms_64 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ));
344 constant cms_65 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ));
345 constant cms_66 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ));
346 constant cms_67 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ));
347 constant cms_68 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ));
348 constant cms_69 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ));
349 constant cms_70 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ));
350 constant cms_71 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ));
351 constant cms_72 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ));
352 constant cms_73 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ));
353 constant cms_74 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ));
354 constant cms_75 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ));
355 constant cms_76 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ));
356 constant cms_77 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ));
357 constant cms_78 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ));
358 constant cms_79 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ));
359 constant cms_80 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ));
360 constant cms_81 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ));
361 constant cms_82 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ));
362 constant cms_83 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ));
363 constant cms_84 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ));
364 constant cms_85 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ));
365 constant cms_86 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ));
366 constant cms_87 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ));
367 constant cms_88 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ));
368 constant cms_89 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ));
369 constant cms_90 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ));
370 constant cms_91 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ));
371 constant cms_92 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ));
372 constant cms_93 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ));
373 constant cms_94 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ));
374 constant cms_95 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ));
375 constant cms_96 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ));
376 constant cms_97 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ));
377 constant cms_98 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ));
378 constant cms_99 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ));
379 constant cms_100 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ));
380 constant cms_101 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ));
381 constant cms_102 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ));
382 constant cms_103 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ));
383 constant cms_104 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ));
384 constant cms_105 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ));
385 constant cms_106 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ));
386 constant cms_107 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ));
387 constant cms_108 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ));
388 constant cms_109 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ));
389 constant cms_110 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ));
390 constant cms_111 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ));
391 constant cms_112 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ));
392 constant cms_113 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ));
393 constant cms_114 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ));
394 constant cms_115 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ));
395 constant cms_116 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ));
396 constant cms_117 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ));
397 constant cms_118 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ));
398 constant cms_119 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ));
399 constant cms_120 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ));
400 constant cms_121 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ));
401 constant cms_122 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ));
402 constant cms_123 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ));
403 constant cms_124 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ));
404 constant cms_125 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ));
405 constant cms_126 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ));
406 constant cms_127 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ));
407
408 --************************************************--
409
410 constant twiddleFactors_c : std_logic_vector( (NB_Coeffs * Coef_SZ)-1 downto 0) :=
411 (
412 c_0 & c_1 & c_2 & c_3 & c_4 & c_5 & c_6 & c_7 &
413 c_8 & c_9 & c_10 & c_11 & c_12 & c_13 & c_14 & c_15 &
414 c_16 & c_17 & c_18 & c_19 & c_20 & c_21 & c_22 & c_23 &
415 c_24 & c_25 & c_26 & c_27 & c_28 & c_29 & c_30 & c_31 &
416 c_32 & c_33 & c_34 & c_35 & c_36 & c_37 & c_38 & c_39 &
417 c_40 & c_41 & c_42 & c_43 & c_44 & c_45 & c_46 & c_47 &
418 c_48 & c_49 & c_50 & c_51 & c_52 & c_53 & c_54 & c_55 &
419 c_56 & c_57 & c_58 & c_59 & c_60 & c_61 & c_62 & c_63 &
420 c_64 & c_65 & c_66 & c_67 & c_68 & c_69 & c_70 & c_71 &
421 c_72 & c_73 & c_74 & c_75 & c_76 & c_77 & c_78 & c_79 &
422 c_80 & c_81 & c_82 & c_83 & c_84 & c_85 & c_86 & c_87 &
423 c_88 & c_89 & c_90 & c_91 & c_92 & c_93 & c_94 & c_95 &
424 c_96 & c_97 & c_98 & c_99 & c_100 & c_101 & c_102 & c_103 &
425 c_104 & c_105 & c_106 & c_107 & c_108 & c_109 & c_110 & c_111 &
426 c_112 & c_113 & c_114 & c_115 & c_116 & c_117 & c_118 & c_119 &
427 c_120 & c_121 & c_122 & c_123 & c_124 & c_125 & c_126 & c_127 );
428
429 constant twiddleFactors_cps : std_logic_vector( (NB_Coeffs * Coef_SZ)-1 downto 0) :=
430 (
431 cps_0 & cps_1 & cps_2 & cps_3 & cps_4 & cps_5 & cps_6 & cps_7 &
432 cps_8 & cps_9 & cps_10 & cps_11 & cps_12 & cps_13 & cps_14 & cps_15 &
433 cps_16 & cps_17 & cps_18 & cps_19 & cps_20 & cps_21 & cps_22 & cps_23 &
434 cps_24 & cps_25 & cps_26 & cps_27 & cps_28 & cps_29 & cps_30 & cps_31 &
435 cps_32 & cps_33 & cps_34 & cps_35 & cps_36 & cps_37 & cps_38 & cps_39 &
436 cps_40 & cps_41 & cps_42 & cps_43 & cps_44 & cps_45 & cps_46 & cps_47 &
437 cps_48 & cps_49 & cps_50 & cps_51 & cps_52 & cps_53 & cps_54 & cps_55 &
438 cps_56 & cps_57 & cps_58 & cps_59 & cps_60 & cps_61 & cps_62 & cps_63 &
439 cps_64 & cps_65 & cps_66 & cps_67 & cps_68 & cps_69 & cps_70 & cps_71 &
440 cps_72 & cps_73 & cps_74 & cps_75 & cps_76 & cps_77 & cps_78 & cps_79 &
441 cps_80 & cps_81 & cps_82 & cps_83 & cps_84 & cps_85 & cps_86 & cps_87 &
442 cps_88 & cps_89 & cps_90 & cps_91 & cps_92 & cps_93 & cps_94 & cps_95 &
443 cps_96 & cps_97 & cps_98 & cps_99 & cps_100 & cps_101 & cps_102 & cps_103 &
444 cps_104 & cps_105 & cps_106 & cps_107 & cps_108 & cps_109 & cps_110 & cps_111 &
445 cps_112 & cps_113 & cps_114 & cps_115 & cps_116 & cps_117 & cps_118 & cps_119 &
446 cps_120 & cps_121 & cps_122 & cps_123 & cps_124 & cps_125 & cps_126 & cps_127 );
447
448 constant twiddleFactors_cms : std_logic_vector( (NB_Coeffs * Coef_SZ)-1 downto 0) :=
449 (
450 cms_0 & cms_1 & cms_2 & cms_3 & cms_4 & cms_5 & cms_6 & cms_7 &
451 cms_8 & cms_9 & cms_10 & cms_11 & cms_12 & cms_13 & cms_14 & cms_15 &
452 cms_16 & cms_17 & cms_18 & cms_19 & cms_20 & cms_21 & cms_22 & cms_23 &
453 cms_24 & cms_25 & cms_26 & cms_27 & cms_28 & cms_29 & cms_30 & cms_31 &
454 cms_32 & cms_33 & cms_34 & cms_35 & cms_36 & cms_37 & cms_38 & cms_39 &
455 cms_40 & cms_41 & cms_42 & cms_43 & cms_44 & cms_45 & cms_46 & cms_47 &
456 cms_48 & cms_49 & cms_50 & cms_51 & cms_52 & cms_53 & cms_54 & cms_55 &
457 cms_56 & cms_57 & cms_58 & cms_59 & cms_60 & cms_61 & cms_62 & cms_63 &
458 cms_64 & cms_65 & cms_66 & cms_67 & cms_68 & cms_69 & cms_70 & cms_71 &
459 cms_72 & cms_73 & cms_74 & cms_75 & cms_76 & cms_77 & cms_78 & cms_79 &
460 cms_80 & cms_81 & cms_82 & cms_83 & cms_84 & cms_85 & cms_86 & cms_87 &
461 cms_88 & cms_89 & cms_90 & cms_91 & cms_92 & cms_93 & cms_94 & cms_95 &
462 cms_96 & cms_97 & cms_98 & cms_99 & cms_100 & cms_101 & cms_102 & cms_103 &
463 cms_104 & cms_105 & cms_106 & cms_107 & cms_108 & cms_109 & cms_110 & cms_111 &
464 cms_112 & cms_113 & cms_114 & cms_115 & cms_116 & cms_117 & cms_118 & cms_119 &
465 cms_120 & cms_121 & cms_122 & cms_123 & cms_124 & cms_125 & cms_126 & cms_127 );
466 end;
467
Show file before | Show file after | Hide comments
@@ -0,0 +1,65
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
19 -- Author : Martin Morlot
20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 -------------------------------------------------------------------------------
22 library IEEE;
23 use IEEE.numeric_std.all;
24 use IEEE.std_logic_1164.all;
25 library staging_lpp;
26 use staging_lpp.PLE_general_purpose.all;
27
28 --! Une ALU : Arithmetic and logical unit, permettant de rοΏ½aliser une ou plusieurs opοΏ½ration
29
30 entity ALU is
31 generic(
32 Arith_en : integer := 1;
33 Logic_en : integer := 1;
34 Input_SZ_1 : integer := 16;
35 Input_SZ_2 : integer := 16;
36 COMP_EN : INTEGER := 0 -- 1 => No Comp
37 );
38 port(
39 clk : in std_logic; --! Horloge du composant
40 reset : in std_logic; --! Reset general du composant
41 ctrl : in std_logic_vector(2 downto 0); --! Permet de sοΏ½lectionner la/les opοΏ½ration dοΏ½sirοΏ½e
42 comp : in std_logic_vector(1 downto 0); --! (set) Permet de complοΏ½menter les opοΏ½randes
43 OP1 : in std_logic_vector(Input_SZ_1-1 downto 0); --! Premier OpοΏ½rande
44 OP2 : in std_logic_vector(Input_SZ_2-1 downto 0); --! Second OpοΏ½rande
45 RES : out std_logic_vector(Input_SZ_1+Input_SZ_2-1 downto 0) --! RοΏ½sultat de l'opοΏ½ration
46 );
47 end ALU;
48
49 --! @details SοΏ½lection grace a l'entrοΏ½e "ctrl" :
50 --! Pause : IDLE = 000
51 --! Multiplieur/Accumulateur : MAC = 001
52 --! Multiplication : MULT = 010
53 --! Addition : ADD = 011
54 --! Reset du MAC : CLRMAC = 100
55 architecture ar_ALU of ALU is
56
57 begin
58
59 arith : if Arith_en = 1 generate
60 MACinst : MAC
61 generic map(Input_SZ_1,Input_SZ_2,COMP_EN)
62 port map(clk,reset,ctrl(2),ctrl(1 downto 0),comp,OP1,OP2,RES);
63 end generate;
64
65 end architecture;
Show file before | Show file after | Hide comments
@@ -0,0 +1,71
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
19 -- Author : Alexis Jeandet
20 -- Mail : alexis.jeandet@lpp.polytechnique.fr
21 ----------------------------------------------------------------------------
22 LIBRARY IEEE;
23 USE IEEE.numeric_std.ALL;
24 USE IEEE.std_logic_1164.ALL;
25
26 ENTITY Adder IS
27 GENERIC(
28 Input_SZ_A : INTEGER := 16;
29 Input_SZ_B : INTEGER := 16
30
31 );
32 PORT(
33 clk : IN STD_LOGIC;
34 reset : IN STD_LOGIC;
35 clr : IN STD_LOGIC;
36 load : IN STD_LOGIC;
37 add : IN STD_LOGIC;
38 OP1 : IN STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0);
39 OP2 : IN STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0);
40 RES : OUT STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0)
41 );
42 END ENTITY;
43
44
45
46
47 ARCHITECTURE ar_Adder OF Adder IS
48
49 SIGNAL REG : STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0);
50 SIGNAL RESADD : STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0);
51
52 BEGIN
53
54 RES <= REG;
55 RESADD <= STD_LOGIC_VECTOR(resize(SIGNED(OP1)+SIGNED(OP2), Input_SZ_A));
56
57 PROCESS(clk, reset)
58 BEGIN
59 IF reset = '0' THEN
60 REG <= (OTHERS => '0');
61 ELSIF clk'EVENT AND clk = '1' then
62 IF clr = '1' THEN
63 REG <= (OTHERS => '0');
64 ELSIF add = '1' THEN
65 REG <= RESADD;
66 ELSIF load = '1' THEN
67 REG <= OP2;
68 END IF;
69 END IF;
70 END PROCESS;
71 END ar_Adder;
Show file before | Show file after | Hide comments
@@ -0,0 +1,385
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
19 -- Author : Alexis Jeandet
20 -- Mail : alexis.jeandet@lpp.polytechnique.fr
21 ----------------------------------------------------------------------------
22 LIBRARY IEEE;
23 USE IEEE.numeric_std.ALL;
24 USE IEEE.std_logic_1164.ALL;
25 LIBRARY staging_lpp;
26 USE staging_lpp.PLE_general_purpose.ALL;
27 --TODO
28 --terminer le testbensh puis changer le resize dans les instanciations
29 --par un resize sur un vecteur en combi
30
31
32 ENTITY MAC IS
33 GENERIC(
34 Input_SZ_A : INTEGER := 8;
35 Input_SZ_B : INTEGER := 8;
36 COMP_EN : INTEGER := 0 -- 1 => No Comp
37
38 );
39 PORT(
40 clk : IN STD_LOGIC;
41 reset : IN STD_LOGIC;
42 clr_MAC : IN STD_LOGIC;
43 MAC_MUL_ADD : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
44 Comp_2C : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
45 OP1 : IN STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0);
46 OP2 : IN STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0);
47 RES : OUT STD_LOGIC_VECTOR(Input_SZ_A+Input_SZ_B-1 DOWNTO 0)
48 );
49 END MAC;
50
51
52
53
54 ARCHITECTURE ar_MAC OF MAC IS
55
56 SIGNAL add, mult : STD_LOGIC;
57 SIGNAL MULTout : STD_LOGIC_VECTOR(Input_SZ_A+Input_SZ_B-1 DOWNTO 0);
58
59 SIGNAL ADDERinA : STD_LOGIC_VECTOR(Input_SZ_A+Input_SZ_B-1 DOWNTO 0);
60 SIGNAL ADDERinB : STD_LOGIC_VECTOR(Input_SZ_A+Input_SZ_B-1 DOWNTO 0);
61 SIGNAL ADDERout : STD_LOGIC_VECTOR(Input_SZ_A+Input_SZ_B-1 DOWNTO 0);
62
63 SIGNAL MACMUXsel : STD_LOGIC;
64 SIGNAL OP1_2C_D_Resz : STD_LOGIC_VECTOR(Input_SZ_A+Input_SZ_B-1 DOWNTO 0);
65 SIGNAL OP2_2C_D_Resz : STD_LOGIC_VECTOR(Input_SZ_A+Input_SZ_B-1 DOWNTO 0);
66
67 SIGNAL OP1_2C : STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0);
68 SIGNAL OP2_2C : STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0);
69
70 SIGNAL MACMUX2sel : STD_LOGIC;
71
72 SIGNAL add_D : STD_LOGIC;
73 SIGNAL add_D_D : STD_LOGIC;
74 SIGNAL mult_D : STD_LOGIC;
75 SIGNAL OP1_2C_D : STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0);
76 SIGNAL OP2_2C_D : STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0);
77
78 -- SIGNAL OP1_2C_D_reg : STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0);
79 -- SIGNAL OP2_2C_D_reg : STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0);
80
81 SIGNAL MULTout_D : STD_LOGIC_VECTOR(Input_SZ_A+Input_SZ_B-1 DOWNTO 0);
82 SIGNAL MACMUXsel_D : STD_LOGIC;
83 SIGNAL MACMUXsel_D_D : STD_LOGIC;
84 SIGNAL MACMUX2sel_D : STD_LOGIC;
85 SIGNAL MACMUX2sel_D_D : STD_LOGIC;
86 SIGNAL MACMUX2sel_D_D_D : STD_LOGIC;
87 SIGNAL clr_MAC_D : STD_LOGIC;
88 SIGNAL clr_MAC_D_D : STD_LOGIC;
89 SIGNAL clr_MAC_D_D_D : STD_LOGIC;
90 SIGNAL MAC_MUL_ADD_2C_D : STD_LOGIC_VECTOR(1 DOWNTO 0);
91 SIGNAL MAC_MUL_ADD_2C_D_D : STD_LOGIC_VECTOR(1 DOWNTO 0);
92
93 SIGNAL load_mult_result : STD_LOGIC;
94 SIGNAL load_mult_result_D : STD_LOGIC;
95 SIGNAL load_mult_result_D_D : STD_LOGIC;
96
97 BEGIN
98
99
100
101
102 --==============================================================
103 --=============M A C C O N T R O L E R=========================
104 --==============================================================
105 MAC_CONTROLER1 : MAC_CONTROLER
106 PORT MAP(
107 ctrl => MAC_MUL_ADD,
108 MULT => mult,
109 ADD => add,
110 LOAD_ADDER => load_mult_result,
111 MACMUX_sel => MACMUXsel,
112 MACMUX2_sel => MACMUX2sel
113
114 );
115 --==============================================================
116
117
118 --==============================================================
119 --===================TWO COMPLEMENTERS==========================
120 --==============================================================
121 gen_comp : IF COMP_EN = 0 GENERATE
122 TWO_COMPLEMENTER1 : TwoComplementer
123 GENERIC MAP(
124 Input_SZ => Input_SZ_A
125 )
126 PORT MAP(
127 clk => clk,
128 reset => reset,
129 clr => clr_MAC,
130 TwoComp => Comp_2C(0),
131 OP => OP1,
132 RES => OP1_2C
133 );
134
135 TWO_COMPLEMENTER2 : TwoComplementer
136 GENERIC MAP(
137 Input_SZ => Input_SZ_B
138 )
139 PORT MAP(
140 clk => clk,
141 reset => reset,
142 clr => clr_MAC,
143 TwoComp => Comp_2C(1),
144 OP => OP2,
145 RES => OP2_2C
146 );
147 END GENERATE gen_comp;
148
149 no_gen_comp : IF COMP_EN = 1 GENERATE
150 process(clk,reset)
151 begin
152 if(reset='0')then
153 OP1_2C <= (others => '0');
154 OP2_2C <= (others => '0');
155 elsif clk'event and clk='1' then
156 if clr_MAC = '1' then
157 OP1_2C <= (others => '0');
158 OP2_2C <= (others => '0');
159 else
160 OP1_2C <= OP1;
161 OP2_2C <= OP2;
162 end if;
163 end if;
164 end process;
165
166 END GENERATE no_gen_comp;
167 --==============================================================
168
169 --==============================================================
170 --=============M U L T I P L I E R==============================
171 --==============================================================
172
173 multREG0 : MAC_REG
174 GENERIC MAP(size => 1)
175 PORT MAP(
176 reset => reset,
177 clk => clk,
178 D(0) => mult,
179 Q(0) => mult_D
180 );
181
182 Multiplieri_nst : Multiplier
183 GENERIC MAP(
184 Input_SZ_A => Input_SZ_A,
185 Input_SZ_B => Input_SZ_B
186 )
187 PORT MAP(
188 clk => clk,
189 reset => reset,
190 mult => mult_D,
191 OP1 => OP1_2C,
192 OP2 => OP2_2C,
193 RES => MULTout
194 );
195
196 OP1REG : MAC_REG
197 GENERIC MAP(size => Input_SZ_A)
198 PORT MAP(
199 reset => reset,
200 clk => clk,
201 D => OP1_2C,
202 Q => OP1_2C_D
203 );
204
205 OP2REG : MAC_REG
206 GENERIC MAP(size => Input_SZ_B)
207 PORT MAP(
208 reset => reset,
209 clk => clk,
210 D => OP2_2C,
211 Q => OP2_2C_D
212 );
213
214 --==============================================================
215
216 --==============================================================
217 --======================M A C M U X ===========================
218 --==============================================================
219
220 OP1_2C_D_Resz <= STD_LOGIC_VECTOR(resize(SIGNED(OP1_2C_D), Input_SZ_A+Input_SZ_B));
221 OP2_2C_D_Resz <= STD_LOGIC_VECTOR(resize(SIGNED(OP2_2C_D), Input_SZ_A+Input_SZ_B));
222
223 MACMUXselREG0 : MAC_REG
224 GENERIC MAP(size => 1)
225 PORT MAP(
226 reset => reset,
227 clk => clk,
228 D(0) => MACMUXsel,
229 Q(0) => MACMUXsel_D
230 );
231
232 MACMUXselREG1 : MAC_REG
233 GENERIC MAP(size => 1)
234 PORT MAP(
235 reset => reset,
236 clk => clk,
237 D(0) => MACMUXsel_D,
238 Q(0) => MACMUXsel_D_D
239 );
240
241 MACMUX_inst : MAC_MUX
242 GENERIC MAP(
243 Input_SZ_A => Input_SZ_A+Input_SZ_B,
244 Input_SZ_B => Input_SZ_A+Input_SZ_B
245
246 )
247 PORT MAP(
248 sel => MACMUXsel_D_D,
249 INA1 => ADDERout,
250 INA2 => OP2_2C_D_Resz,
251 INB1 => MULTout,
252 INB2 => OP1_2C_D_Resz,
253 OUTA => ADDERinA,
254 OUTB => ADDERinB
255 );
256
257 --==============================================================
258
259 --==============================================================
260 --======================A D D E R ==============================
261 --==============================================================
262
263 clr_MACREG0 : MAC_REG
264 GENERIC MAP(size => 1)
265 PORT MAP(
266 reset => reset,
267 clk => clk,
268 D(0) => clr_MAC,
269 Q(0) => clr_MAC_D
270 );
271
272 clr_MACREG1 : MAC_REG
273 GENERIC MAP(size => 1)
274 PORT MAP(
275 reset => reset,
276 clk => clk,
277 D(0) => clr_MAC_D,
278 Q(0) => clr_MAC_D_D
279 );
280
281 addREG0 : MAC_REG
282 GENERIC MAP(size => 1)
283 PORT MAP(
284 reset => reset,
285 clk => clk,
286 D(0) => add,
287 Q(0) => add_D
288 );
289
290 addREG1 : MAC_REG
291 GENERIC MAP(size => 1)
292 PORT MAP(
293 reset => reset,
294 clk => clk,
295 D(0) => add_D,
296 Q(0) => add_D_D
297 );
298
299 load_mult_resultREG : MAC_REG
300 GENERIC MAP(size => 1)
301 PORT MAP(
302 reset => reset,
303 clk => clk,
304 D(0) => load_mult_result,
305 Q(0) => load_mult_result_D
306 );
307
308 load_mult_resultREG1 : MAC_REG
309 GENERIC MAP(size => 1)
310 PORT MAP(
311 reset => reset,
312 clk => clk,
313 D(0) => load_mult_result_D,
314 Q(0) => load_mult_result_D_D
315 );
316
317 adder_inst : Adder
318 GENERIC MAP(
319 Input_SZ_A => Input_SZ_A+Input_SZ_B,
320 Input_SZ_B => Input_SZ_A+Input_SZ_B
321 )
322 PORT MAP(
323 clk => clk,
324 reset => reset,
325 clr => clr_MAC_D_D,
326 load => load_mult_result_D_D,
327 add => add_D_D,
328 OP1 => ADDERinA,
329 OP2 => ADDERinB,
330 RES => ADDERout
331 );
332
333 --==============================================================
334
335 --==============================================================
336 --======================M A C M U X2 ==========================
337 --==============================================================
338
339 MULToutREG : MAC_REG
340 GENERIC MAP(size => Input_SZ_A+Input_SZ_B)
341 PORT MAP(
342 reset => reset,
343 clk => clk,
344 D => MULTout,
345 Q => MULTout_D
346 );
347
348 MACMUX2selREG : MAC_REG
349 GENERIC MAP(size => 1)
350 PORT MAP(
351 reset => reset,
352 clk => clk,
353 D(0) => MACMUX2sel,
354 Q(0) => MACMUX2sel_D
355 );
356
357 MACMUX2selREG2_0 : MAC_REG
358 GENERIC MAP(size => 1)
359 PORT MAP(
360 reset => reset,
361 clk => clk,
362 D(0) => MACMUX2sel_D,
363 Q(0) => MACMUX2sel_D_D
364 );
365
366 MACMUX2selREG2_1 : MAC_REG
367 GENERIC MAP(size => 1)
368 PORT MAP(
369 reset => reset,
370 clk => clk,
371 D(0) => MACMUX2sel_D_D,
372 Q(0) => MACMUX2sel_D_D_D
373 );
374
375 MAC_MUX2_inst : MAC_MUX2
376 GENERIC MAP(Input_SZ => Input_SZ_A+Input_SZ_B)
377 PORT MAP(
378 sel => MACMUX2sel_D_D_D,
379 RES2 => MULTout_D,
380 RES1 => ADDERout,
381 RES => RES
382 );
383 --==============================================================
384
385 END ar_MAC; No newline at end of file
Show file before | Show file after | Hide comments
@@ -0,0 +1,71
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
19 -- Author : Alexis Jeandet
20 -- Mail : alexis.jeandet@lpp.polytechnique.fr
21 ----------------------------------------------------------------------------
22 library IEEE;
23 use IEEE.numeric_std.all;
24 use IEEE.std_logic_1164.all;
25
26 --IDLE =00 MAC =01 MULT =10 ADD =11
27
28
29 entity MAC_CONTROLER is
30 port(
31 ctrl : in std_logic_vector(1 downto 0);
32 MULT : out std_logic;
33 ADD : out std_logic;
34 LOAD_ADDER : out std_logic;
35 MACMUX_sel : out std_logic;
36 MACMUX2_sel : out std_logic
37
38 );
39 end MAC_CONTROLER;
40
41
42
43
44
45 architecture ar_MAC_CONTROLER of MAC_CONTROLER is
46
47 begin
48
49
50
51 MULT <= '0' when (ctrl = "00" or ctrl = "11") else '1';
52 ADD <= '0' when (ctrl = "00" or ctrl = "10") else '1';
53 LOAD_ADDER <= '1' when (ctrl = "10") else '0'; -- PATCH JC : mem mult result
54 -- to permit to compute a
55 -- MULT follow by a MAC
56 --MACMUX_sel <= '0' when (ctrl = "00" or ctrl = "01") else '1';
57 MACMUX_sel <= '0' when (ctrl = "00" or ctrl = "01" OR ctrl = "10") else '1';
58 MACMUX2_sel <= '0' when (ctrl = "00" or ctrl = "01" or ctrl = "11") else '1';
59
60
61 end ar_MAC_CONTROLER;
62
63
64
65
66
67
68
69
70
71
Show file before | Show file after | Hide comments
@@ -0,0 +1,53
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
19 -- Author : Alexis Jeandet
20 -- Mail : alexis.jeandet@lpp.polytechnique.fr
21 ----------------------------------------------------------------------------
22 library IEEE;
23 use IEEE.numeric_std.all;
24 use IEEE.std_logic_1164.all;
25
26 entity MAC_MUX is
27 generic(
28 Input_SZ_A : integer := 16;
29 Input_SZ_B : integer := 16
30
31 );
32 port(
33 sel : in std_logic;
34 INA1 : in std_logic_vector(Input_SZ_A-1 downto 0);
35 INA2 : in std_logic_vector(Input_SZ_A-1 downto 0);
36 INB1 : in std_logic_vector(Input_SZ_B-1 downto 0);
37 INB2 : in std_logic_vector(Input_SZ_B-1 downto 0);
38 OUTA : out std_logic_vector(Input_SZ_A-1 downto 0);
39 OUTB : out std_logic_vector(Input_SZ_B-1 downto 0)
40 );
41 end entity;
42
43
44
45
46 architecture ar_MAC_MUX of MAC_MUX is
47
48 begin
49
50 OUTA <= INA1 when sel = '0' else INA2;
51 OUTB <= INB1 when sel = '0' else INB2;
52
53 end ar_MAC_MUX;
Show file before | Show file after | Hide comments
@@ -0,0 +1,46
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
19 -- Author : Alexis Jeandet
20 -- Mail : alexis.jeandet@lpp.polytechnique.fr
21 ----------------------------------------------------------------------------
22 library IEEE;
23 use IEEE.numeric_std.all;
24 use IEEE.std_logic_1164.all;
25
26
27 entity MAC_MUX2 is
28 generic(Input_SZ : integer := 16);
29 port(
30 sel : in std_logic;
31 RES1 : in std_logic_vector(Input_SZ-1 downto 0);
32 RES2 : in std_logic_vector(Input_SZ-1 downto 0);
33 RES : out std_logic_vector(Input_SZ-1 downto 0)
34 );
35 end entity;
36
37
38
39
40 architecture ar_MAC_MUX2 of MAC_MUX2 is
41
42 begin
43
44 RES <= RES1 when sel = '0' else RES2;
45
46 end ar_MAC_MUX2;
Show file before | Show file after | Hide comments
@@ -0,0 +1,58
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
19 -- Author : Alexis Jeandet
20 -- Mail : alexis.jeandet@lpp.polytechnique.fr
21 ----------------------------------------------------------------------------
22 library IEEE;
23 use IEEE.numeric_std.all;
24 use IEEE.std_logic_1164.all;
25
26 entity MAC_REG is
27 generic(size : integer := 16);
28 port(
29 reset : in std_logic;
30 clk : in std_logic;
31 D : in std_logic_vector(size-1 downto 0);
32 Q : out std_logic_vector(size-1 downto 0)
33 );
34 end entity;
35
36
37
38 architecture ar_MAC_REG of MAC_REG is
39 begin
40 process(clk,reset)
41 begin
42 if reset = '0' then
43 Q <= (others => '0');
44 elsif clk'event and clk ='1' then
45 Q <= D;
46 end if;
47 end process;
48 end ar_MAC_REG;
49
50
51
52
53
54
55
56
57
58
Show file before | Show file after | Hide comments
@@ -0,0 +1,75
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
19 -- Author : Alexis Jeandet
20 -- Mail : alexis.jeandet@lpp.polytechnique.fr
21 ----------------------------------------------------------------------------
22 library IEEE;
23 use IEEE.numeric_std.all;
24 use IEEE.std_logic_1164.all;
25
26 entity Multiplier is
27 generic(
28 Input_SZ_A : integer := 16;
29 Input_SZ_B : integer := 16
30
31 );
32 port(
33 clk : in std_logic;
34 reset : in std_logic;
35 mult : in std_logic;
36 OP1 : in std_logic_vector(Input_SZ_A-1 downto 0);
37 OP2 : in std_logic_vector(Input_SZ_B-1 downto 0);
38 RES : out std_logic_vector(Input_SZ_A+Input_SZ_B-1 downto 0)
39 );
40 end Multiplier;
41
42
43
44
45
46 architecture ar_Multiplier of Multiplier is
47
48 signal REG : std_logic_vector(Input_SZ_A+Input_SZ_B-1 downto 0);
49 signal RESMULT : std_logic_vector(Input_SZ_A+Input_SZ_B-1 downto 0);
50
51
52 begin
53
54 RES <= REG;
55 RESMULT <= std_logic_vector(signed(OP1)*signed(OP2));
56 process(clk,reset)
57 begin
58 if reset = '0' then
59 REG <= (others => '0');
60 elsif clk'event and clk ='1' then
61 if mult = '1' then
62 REG <= RESMULT;
63 end if;
64 end if;
65 end process;
66
67 end ar_Multiplier;
68
69
70
71
72
73
74
75
Show file before | Show file after | Hide comments
@@ -0,0 +1,72
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
19 -- Author : Martin Morlot
20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 -------------------------------------------------------------------------------
22 library IEEE;
23 use IEEE.numeric_std.all;
24 use IEEE.std_logic_1164.all;
25
26 --! Programme permetant de complοΏ½menter ou non les entrοΏ½es de l'ALU, et ainsi de travailler avec des nombres nοΏ½gatifs
27
28 entity TwoComplementer is
29 generic(
30 Input_SZ : integer := 16);
31 port(
32 clk : in std_logic; --! Horloge du composant
33 reset : in std_logic; --! Reset general du composant
34 clr : in std_logic; --! Un reset spοΏ½cifique au programme
35 TwoComp : in std_logic; --! Autorise l'utilisation du complοΏ½ment
36 OP : in std_logic_vector(Input_SZ-1 downto 0); --! OpοΏ½rande d'entrοΏ½e
37 RES : out std_logic_vector(Input_SZ-1 downto 0) --! RοΏ½sultat, opοΏ½rande complοΏ½mentοΏ½ ou non
38 );
39 end TwoComplementer;
40
41
42 architecture ar_TwoComplementer of TwoComplementer is
43
44 signal REG : std_logic_vector(Input_SZ-1 downto 0);
45 signal OPinteger : integer;
46 signal RESCOMP : std_logic_vector(Input_SZ-1 downto 0);
47
48 begin
49
50 RES <= REG;
51 OPinteger <= to_integer(signed(OP));
52 RESCOMP <= std_logic_vector(to_signed(-OPinteger,Input_SZ));
53
54 process(clk,reset)
55 begin
56
57 if(reset='0')then
58 REG <= (others => '0');
59 elsif(clk'event and clk='1')then
60
61 if(clr='1')then
62 REG <= (others => '0');
63 elsif(TwoComp='1')then
64 REG <= RESCOMP;
65 else
66 REG <= OP;
67 end if;
68
69 end if;
70
71 end process;
72 end ar_TwoComplementer; No newline at end of file
Show file before | Show file after | Hide comments
@@ -0,0 +1,185
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
19 -- Author : Alexis Jeandet
20 -- Mail : alexis.jeandet@lpp.polytechnique.fr
21 ----------------------------------------------------------------------------
22 --UPDATE
23 -------------------------------------------------------------------------------
24 -- 14-03-2013 - Jean-christophe Pellion
25 -- ADD MUXN (a parametric multiplexor (N stage of MUX2))
26 -------------------------------------------------------------------------------
27
28 LIBRARY ieee;
29 USE ieee.std_logic_1164.ALL;
30
31 PACKAGE PLE_general_purpose IS
32
33 COMPONENT Adder IS
34 GENERIC(
35 Input_SZ_A : INTEGER := 16;
36 Input_SZ_B : INTEGER := 16
37
38 );
39 PORT(
40 clk : IN STD_LOGIC;
41 reset : IN STD_LOGIC;
42 clr : IN STD_LOGIC;
43 load : IN STD_LOGIC;
44 add : IN STD_LOGIC;
45 OP1 : IN STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0);
46 OP2 : IN STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0);
47 RES : OUT STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0)
48 );
49 END COMPONENT;
50
51 COMPONENT ALU IS
52 GENERIC(
53 Arith_en : INTEGER := 1;
54 Logic_en : INTEGER := 1;
55 Input_SZ_1 : INTEGER := 16;
56 Input_SZ_2 : INTEGER := 9;
57 COMP_EN : INTEGER := 0 -- 1 => No Comp
58
59 );
60 PORT(
61 clk : IN STD_LOGIC;
62 reset : IN STD_LOGIC;
63 ctrl : IN STD_LOGIC_VECTOR(2 downto 0);
64 comp : IN STD_LOGIC_VECTOR(1 downto 0);
65 OP1 : IN STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0);
66 OP2 : IN STD_LOGIC_VECTOR(Input_SZ_2-1 DOWNTO 0);
67 RES : OUT STD_LOGIC_VECTOR(Input_SZ_1+Input_SZ_2-1 DOWNTO 0)
68 );
69 END COMPONENT;
70
71 ---------------------------------------------------------
72 -------- // SΓ©lection grace a l'entrΓ©e "ctrl" \\ --------
73 ---------------------------------------------------------
74 Constant ctrl_IDLE : std_logic_vector(2 downto 0) := "000";
75 Constant ctrl_MAC : std_logic_vector(2 downto 0) := "001";
76 Constant ctrl_MULT : std_logic_vector(2 downto 0) := "010";
77 Constant ctrl_ADD : std_logic_vector(2 downto 0) := "011";
78 Constant ctrl_CLRMAC : std_logic_vector(2 downto 0) := "100";
79
80
81 Constant IDLE_V0 : std_logic_vector(3 downto 0) := "0000";
82 Constant MAC_op_V0 : std_logic_vector(3 downto 0) := "0001";
83 Constant MULT_V0 : std_logic_vector(3 downto 0) := "0010";
84 Constant ADD_V0 : std_logic_vector(3 downto 0) := "0011";
85 Constant CLR_MAC_V0 : std_logic_vector(3 downto 0) := "0100";
86 ---------------------------------------------------------
87
88 COMPONENT MAC IS
89 GENERIC(
90 Input_SZ_A : INTEGER := 8;
91 Input_SZ_B : INTEGER := 8;
92 COMP_EN : INTEGER := 0 -- 1 => No Comp
93 );
94 PORT(
95 clk : IN STD_LOGIC;
96 reset : IN STD_LOGIC;
97 clr_MAC : IN STD_LOGIC;
98 MAC_MUL_ADD : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
99 Comp_2C : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
100 OP1 : IN STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0);
101 OP2 : IN STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0);
102 RES : OUT STD_LOGIC_VECTOR(Input_SZ_A+Input_SZ_B-1 DOWNTO 0)
103 );
104 END COMPONENT;
105
106 COMPONENT TwoComplementer is
107 generic(
108 Input_SZ : integer := 16);
109 port(
110 clk : in std_logic; --! Horloge du composant
111 reset : in std_logic; --! Reset general du composant
112 clr : in std_logic; --! Un reset spΓ©cifique au programme
113 TwoComp : in std_logic; --! Autorise l'utilisation du complΓ©ment
114 OP : in std_logic_vector(Input_SZ-1 downto 0); --! OpΓ©rande d'entrΓ©e
115 RES : out std_logic_vector(Input_SZ-1 downto 0) --! RΓ©sultat, opΓ©rande complΓ©mentΓ© ou non
116 );
117 end COMPONENT;
118
119 COMPONENT MAC_CONTROLER IS
120 PORT(
121 ctrl : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
122 MULT : OUT STD_LOGIC;
123 ADD : OUT STD_LOGIC;
124 LOAD_ADDER : out std_logic;
125 MACMUX_sel : OUT STD_LOGIC;
126 MACMUX2_sel : OUT STD_LOGIC
127 );
128 END COMPONENT;
129
130 COMPONENT MAC_MUX IS
131 GENERIC(
132 Input_SZ_A : INTEGER := 16;
133 Input_SZ_B : INTEGER := 16
134
135 );
136 PORT(
137 sel : IN STD_LOGIC;
138 INA1 : IN STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0);
139 INA2 : IN STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0);
140 INB1 : IN STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0);
141 INB2 : IN STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0);
142 OUTA : OUT STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0);
143 OUTB : OUT STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0)
144 );
145 END COMPONENT;
146
147
148 COMPONENT MAC_MUX2 IS
149 GENERIC(Input_SZ : INTEGER := 16);
150 PORT(
151 sel : IN STD_LOGIC;
152 RES1 : IN STD_LOGIC_VECTOR(Input_SZ-1 DOWNTO 0);
153 RES2 : IN STD_LOGIC_VECTOR(Input_SZ-1 DOWNTO 0);
154 RES : OUT STD_LOGIC_VECTOR(Input_SZ-1 DOWNTO 0)
155 );
156 END COMPONENT;
157
158
159 COMPONENT MAC_REG IS
160 GENERIC(size : INTEGER := 16);
161 PORT(
162 reset : IN STD_LOGIC;
163 clk : IN STD_LOGIC;
164 D : IN STD_LOGIC_VECTOR(size-1 DOWNTO 0);
165 Q : OUT STD_LOGIC_VECTOR(size-1 DOWNTO 0)
166 );
167 END COMPONENT;
168
169 COMPONENT Multiplier IS
170 GENERIC(
171 Input_SZ_A : INTEGER := 16;
172 Input_SZ_B : INTEGER := 16
173
174 );
175 PORT(
176 clk : IN STD_LOGIC;
177 reset : IN STD_LOGIC;
178 mult : IN STD_LOGIC;
179 OP1 : IN STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0);
180 OP2 : IN STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0);
181 RES : OUT STD_LOGIC_VECTOR(Input_SZ_A+Input_SZ_B-1 DOWNTO 0)
182 );
183 END COMPONENT;
184
185 END;
General Comments 0
You need to be logged in to leave comments. Login now