diff --git a/lib/staging/LPP/PLE/dsp/lpp_fft/BUTTERFLY_CTRL.vhd b/lib/staging/LPP/PLE/dsp/lpp_fft/BUTTERFLY_CTRL.vhd new file mode 100644 --- /dev/null +++ b/lib/staging/LPP/PLE/dsp/lpp_fft/BUTTERFLY_CTRL.vhd @@ -0,0 +1,224 @@ +------------------------------------------------------------------------------ +-- This file is a part of the LPP VHDL IP LIBRARY +-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 3 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more Cdetails. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +------------------------------------------------------------------------------- +-- Author : Paul LEROY +-- Mail : paul.leroy@lpp.polytechnique.fr +------------------------------------------------------------------------------- + +LIBRARY IEEE; +USE IEEE.numeric_std.ALL; +USE IEEE.std_logic_1164.ALL; + +LIBRARY staging_lpp; +--USE lpp.general_purpose.ALL; +use staging_lpp.PLE_general_purpose.all; +use staging_lpp.PLE_lpp_fft.all; + +ENTITY BUTTERFLY_CTRL IS + PORT ( + rstn : IN STD_LOGIC; + clk : IN STD_LOGIC; + + sample_in_val : IN STD_LOGIC; + sample_out_val : OUT STD_LOGIC; + + sel_op1 : OUT STD_LOGIC_VECTOR( 4 DOWNTO 0 ); -- Are Aim X Y Z + sel_op2 : OUT STD_LOGIC_VECTOR( 4 DOWNTO 0 ); -- Bre Bim C_in cps_in cms_in + sel_xyz : OUT STD_LOGIC_VECTOR( 2 DOWNTO 0 ); -- X Y Z + sel_out : OUT STD_LOGIC_VECTOR( 3 DOWNTO 0 ); + alu_ctrl : OUT STD_LOGIC_VECTOR( 2 DOWNTO 0 ); + alu_comp : OUT STD_LOGIC_VECTOR( 1 DOWNTO 0 ) + ); +END BUTTERFLY_CTRL; + +ARCHITECTURE ar_BUTTERFLY_CTRL OF BUTTERFLY_CTRL IS + + TYPE fsm_BUTTERFLY_CTRL_T IS ( waiting, + add1, + add2, + add3, + add4, + mult5, + mac6, + mac7, + mult8, + mac9, + last10, + last11, + last12); + SIGNAL BUTTERFLY_CTRL_STATE : fsm_BUTTERFLY_CTRL_T; + +BEGIN + +PROCESS (clk, rstn) + + BEGIN -- PROCESS + IF rstn = '0' THEN -- asynchronous reset (active low) + --REG ------------------------------------------------------------------- + sel_xyz <= (OTHERS => '0'); + sel_out <= (OTHERS => '0'); + --ALU ------------------------------------------------------------------- + sel_op1 <= (OTHERS => '0'); + sel_op2 <= (OTHERS => '0'); + alu_ctrl <= ctrl_IDLE; + alu_comp <= (OTHERS => '0'); + --OUT + sample_out_val <= '0'; + + BUTTERFLY_CTRL_STATE <= waiting; + + ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge + + CASE BUTTERFLY_CTRL_STATE IS + + WHEN waiting => + IF sample_in_val = '1' THEN + BUTTERFLY_CTRL_STATE <= add1; + END IF; + sel_op1 <= "00000"; -- Are + sel_op2 <= "00000"; -- Bre + alu_comp <= "00"; + alu_ctrl <= ctrl_IDLE; + sel_out <= "0000"; + sample_out_val <= '0'; + + WHEN add1 => + sample_out_val <= '0'; + sel_op1 <= "10000"; -- Are + sel_op2 <= "10000"; -- Bre + alu_comp <= "10"; + alu_ctrl <= ctrl_ADD; + sel_out <= "0000"; + sample_out_val <= '0'; + BUTTERFLY_CTRL_STATE <= add2; + + WHEN add2 => + sample_out_val <= '0'; + sel_op1 <= "01000"; -- Aim + sel_op2 <= "01000"; -- Bim + alu_comp <= "10"; + alu_ctrl <= ctrl_ADD; + sel_out <= "0000"; + BUTTERFLY_CTRL_STATE <= add3; + + WHEN add3 => + sample_out_val <= '0'; + sel_op1 <= "10000"; -- Are + sel_op2 <= "10000"; -- Bre + alu_comp <= "00"; + alu_ctrl <= ctrl_ADD; + sel_out <= "0000"; + BUTTERFLY_CTRL_STATE <= add4; + + WHEN add4 => + sample_out_val <= '0'; + sel_op1 <= "01000"; -- Aim + sel_op2 <= "01000"; -- Bim + alu_comp <= "00"; + alu_ctrl <= ctrl_ADD; + sel_out <= "0000"; + sel_xyz <= "100"; -- X + BUTTERFLY_CTRL_STATE <= mult5; + + WHEN mult5 => + sample_out_val <= '0'; + sel_op1 <= "00100"; -- X + sel_op2 <= "00100"; -- c + alu_comp <= "00"; + alu_ctrl <= ctrl_MULT; + sel_out <= "0000"; + sel_xyz <= "010"; -- Y + BUTTERFLY_CTRL_STATE <= mac6; + + WHEN mac6 => + sample_out_val <= '0'; + sel_op1 <= "00010"; -- Y + sel_op2 <= "00100"; -- c + alu_comp <= "10"; + alu_ctrl <= ctrl_MAC; + sel_out <= "0001"; -- *** /!\ *** -- + sample_out_val <= '1'; + sel_xyz <= "000"; -- Y + BUTTERFLY_CTRL_STATE <= mac7; + + WHEN mac7 => + sample_out_val <= '0'; + sel_op1 <= "00010"; -- Y + sel_op2 <= "00001"; -- cms + alu_comp <= "00"; + alu_ctrl <= ctrl_MAC; + sel_out <= "0010"; -- *** /!\ *** -- + sample_out_val <= '1'; + BUTTERFLY_CTRL_STATE <= mult8; + + WHEN mult8 => + sample_out_val <= '0'; + sel_op1 <= "00100"; -- X + sel_op2 <= "00010"; -- cps + alu_comp <= "00"; + alu_ctrl <= ctrl_MULT; + sel_out <= "0000"; + sample_out_val <= '0'; + BUTTERFLY_CTRL_STATE <= mac9; + + WHEN mac9 => + sample_out_val <= '0'; + alu_ctrl <= ctrl_MAC; + sel_op1 <= "00000"; -- Z is taken directly from the output of the ALU + sel_op2 <= "00000"; -- 1 + alu_comp <= "10"; + sel_out <= "0000"; + sample_out_val <= '0'; + BUTTERFLY_CTRL_STATE <= last10; + + WHEN last10 => + sample_out_val <= '0'; + sel_op1 <= "10000"; + sel_op2 <= "10000"; + alu_comp <= "10"; + alu_ctrl <= ctrl_IDLE; + sel_out <= "0100"; -- *** /!\ *** -- + sample_out_val <= '1'; + BUTTERFLY_CTRL_STATE <= last11; + + WHEN last11 => + sample_out_val <= '0'; + alu_comp <= "10"; + alu_ctrl <= ctrl_IDLE; + sel_out <= "0000"; + sample_out_val <= '0'; + BUTTERFLY_CTRL_STATE <= last12; + + WHEN last12 => + sample_out_val <= '0'; + alu_comp <= "10"; + alu_ctrl <= ctrl_IDLE; + sel_out <= "1000"; -- *** /!\ *** -- + sample_out_val <= '1'; + BUTTERFLY_CTRL_STATE <= waiting; + + WHEN OTHERS => + NULL; + + END CASE; + + END IF; + + END PROCESS; + +END ar_BUTTERFLY_CTRL; \ No newline at end of file diff --git a/lib/staging/LPP/PLE/dsp/lpp_fft/BUTTERFLY_TOP.vhd b/lib/staging/LPP/PLE/dsp/lpp_fft/BUTTERFLY_TOP.vhd new file mode 100644 --- /dev/null +++ b/lib/staging/LPP/PLE/dsp/lpp_fft/BUTTERFLY_TOP.vhd @@ -0,0 +1,104 @@ +------------------------------------------------------------------------------ +-- This file is a part of the LPP VHDL IP LIBRARY +-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 3 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more Cdetails. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +------------------------------------------------------------------------------- +-- Author : Paul LEROY +-- Mail : paul.leroy@lpp.polytechnique.fr +------------------------------------------------------------------------------- + +LIBRARY IEEE; +USE IEEE.numeric_std.ALL; +USE IEEE.std_logic_1164.ALL; + +LIBRARY staging_lpp; +USE staging_lpp.PLE_general_purpose.ALL; +use staging_lpp.PLE_lpp_fft.all; + +ENTITY BUTTERFLY_TOP IS + GENERIC ( + Sample_SZ : INTEGER := 16); + PORT ( + rstn : IN STD_LOGIC; + clk : IN STD_LOGIC; + + sample_in_val : IN STD_LOGIC; + sample_out_val : OUT STD_LOGIC; + + Are : IN STD_LOGIC_VECTOR ( Sample_SZ-1 DOWNTO 0); + Aim : IN STD_LOGIC_VECTOR ( Sample_SZ-1 DOWNTO 0); + Bre : IN STD_LOGIC_VECTOR ( Sample_SZ-1 DOWNTO 0); + Bim : IN STD_LOGIC_VECTOR ( Sample_SZ-1 DOWNTO 0); + c_in : IN STD_LOGIC_VECTOR ( Sample_SZ-1 DOWNTO 0); + cps_in : IN STD_LOGIC_VECTOR ( Sample_SZ-1 DOWNTO 0); + cms_in : IN STD_LOGIC_VECTOR ( Sample_SZ-1 DOWNTO 0); + + butterfly_out : OUT STD_LOGIC_VECTOR ( 2*Sample_SZ-1 DOWNTO 0); + sel_out : OUT STD_LOGIC_VECTOR ( 3 DOWNTO 0) + ); +END BUTTERFLY_TOP; + +ARCHITECTURE ar_BUTTERFLY_TOP OF BUTTERFLY_TOP IS + +SIGNAL sel_op1 : STD_LOGIC_VECTOR( 4 DOWNTO 0 ); -- Are Aim X Y Z +SIGNAL sel_op2 : STD_LOGIC_VECTOR( 4 DOWNTO 0 ); -- Bre Bim C_in cps_in cms_in +SIGNAL sel_xyz : STD_LOGIC_VECTOR( 2 DOWNTO 0 ); -- X Y Z +SIGNAL alu_ctrl_sig : STD_LOGIC_VECTOR( 2 DOWNTO 0 ); +SIGNAL alu_comp_sig : STD_LOGIC_VECTOR( 1 DOWNTO 0 ); + +BEGIN + + BUTTERFLY_DATAFLOW_1 : BUTTERFLY_DATAFLOW + GENERIC MAP ( + Sample_SZ => 16) + PORT MAP ( + rstn => rstn, + clk => clk, + + Are => Are, + Aim => Aim, + Bre => Bre, + Bim => Bim, + c_in => c_in, + cps_in => cps_in, + cms_in => cms_in, + + out_alu => butterfly_out, + + sel_op1 => sel_op1, + sel_op2 => sel_op2, + sel_xyz => sel_xyz, + alu_ctrl => alu_ctrl_sig, + alu_comp => alu_comp_sig + ); + + BUTTERFLY_CTRL_1 : BUTTERFLY_CTRL + PORT MAP( + rstn => rstn, + clk => clk, + + sample_in_val => sample_in_val, + sample_out_val => sample_out_val, + + sel_op1 => sel_op1, + sel_op2 => sel_op2, + sel_xyz => sel_xyz, + sel_out => sel_out, + alu_ctrl => alu_ctrl_sig, + alu_comp => alu_comp_sig + ); + +END ar_BUTTERFLY_TOP; \ No newline at end of file diff --git a/lib/staging/LPP/PLE/dsp/lpp_fft/LPP_BUTTERFLY_DATAFLOW.vhd b/lib/staging/LPP/PLE/dsp/lpp_fft/LPP_BUTTERFLY_DATAFLOW.vhd new file mode 100644 --- /dev/null +++ b/lib/staging/LPP/PLE/dsp/lpp_fft/LPP_BUTTERFLY_DATAFLOW.vhd @@ -0,0 +1,133 @@ +------------------------------------------------------------------------------ +-- This file is a part of the LPP VHDL IP LIBRARY +-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 3 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more Cdetails. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +------------------------------------------------------------------------------- +-- Author : Paul LEROY +-- Mail : paul.leroy@lpp.polytechnique.fr +------------------------------------------------------------------------------- + +LIBRARY IEEE; +USE IEEE.numeric_std.ALL; +USE IEEE.std_logic_1164.ALL; +LIBRARY staging_lpp; +USE staging_lpp.PLE_general_purpose.ALL; + +ENTITY BUTTERFLY_DATAFLOW IS + GENERIC ( + Sample_SZ : INTEGER := 16 + ); + PORT ( + rstn : IN STD_LOGIC; + clk : IN STD_LOGIC; + + Are : IN STD_LOGIC_VECTOR ( Sample_SZ-1 DOWNTO 0); + Aim : IN STD_LOGIC_VECTOR ( Sample_SZ-1 DOWNTO 0); + Bre : IN STD_LOGIC_VECTOR ( Sample_SZ-1 DOWNTO 0); + Bim : IN STD_LOGIC_VECTOR ( Sample_SZ-1 DOWNTO 0); + c_in : IN STD_LOGIC_VECTOR ( Sample_SZ-1 DOWNTO 0); + cps_in : IN STD_LOGIC_VECTOR ( Sample_SZ-1 DOWNTO 0); + cms_in : IN STD_LOGIC_VECTOR ( Sample_SZ-1 DOWNTO 0); + + op1 : OUT STD_LOGIC_VECTOR ( Sample_SZ-1 DOWNTO 0); + op2 : OUT STD_LOGIC_VECTOR ( Sample_SZ-1 DOWNTO 0); + + out_alu : OUT STD_LOGIC_VECTOR ( 2*Sample_SZ-1 DOWNTO 0); + + sel_op1 : IN STD_LOGIC_VECTOR( 4 DOWNTO 0 ); -- Are Aim X Y Z + sel_op2 : IN STD_LOGIC_VECTOR( 4 DOWNTO 0 ); -- Bre Bim C_in cps_in cms_in + sel_xyz : IN STD_LOGIC_VECTOR( 2 DOWNTO 0 ); -- X Y Z + alu_ctrl : IN STD_LOGIC_VECTOR( 2 DOWNTO 0 ); + alu_comp : IN STD_LOGIC_VECTOR( 1 DOWNTO 0 ) + ); +END BUTTERFLY_DATAFLOW; + +ARCHITECTURE ar_BUTTERFLY_DATAFLOW OF BUTTERFLY_DATAFLOW IS + + SIGNAL X : STD_LOGIC_VECTOR( Sample_SZ-1 DOWNTO 0 ); + SIGNAL Y : STD_LOGIC_VECTOR( Sample_SZ-1 DOWNTO 0 ); + SIGNAL Z : STD_LOGIC_VECTOR( Sample_SZ-1 DOWNTO 0 ); + + SIGNAL ALU_OP1 : STD_LOGIC_VECTOR( Sample_SZ-1 DOWNTO 0 ); + SIGNAL ALU_OP2 : STD_LOGIC_VECTOR( Sample_SZ-1 DOWNTO 0 ); + + SIGNAL OUT_ALU_SIG : STD_LOGIC_VECTOR ( 2*Sample_SZ-1 DOWNTO 0); + +BEGIN + +out_alu <= OUT_ALU_SIG; + +PROCESS (clk, rstn) + + BEGIN -- PROCESS + IF rstn = '0' THEN -- asynchronous reset (active low) + X <= (OTHERS => '0'); + Y <= (OTHERS => '0'); + Z <= (OTHERS => '0'); + + ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge + + if sel_xyz = "100" THEN + X <= STD_LOGIC_VECTOR(resize(SIGNED(OUT_ALU_SIG), Sample_SZ)); + elsif sel_xyz = "010" THEN + Y <= STD_LOGIC_VECTOR(resize(SIGNED(OUT_ALU_SIG), Sample_SZ)); + elsif sel_xyz = "001" THEN + Z <= STD_LOGIC_VECTOR(resize(SIGNED(OUT_ALU_SIG), Sample_SZ)); + else + X <= X; + Y <= Y; + Z <= Z; + end if; + + END IF; + + END PROCESS; + + op1 <= ALU_OP1; + op2 <= ALU_OP2; + +ALU_OP1 <= Are WHEN sel_op1 = "10000" ELSE + Aim WHEN sel_op1 = "01000" ELSE + X WHEN sel_op1 = "00100" ELSE + Y WHEN sel_op1 = "00010" ELSE + Z WHEN sel_op1 = "00001" ELSE + STD_LOGIC_VECTOR(resize(SIGNED(OUT_ALU_SIG), Sample_SZ)) WHEN sel_op1 = "00000" ELSE + (OTHERS => '0'); + +ALU_OP2 <= Bre WHEN sel_op2 = "10000" ELSE + Bim WHEN sel_op2 = "01000" ELSE + c_in WHEN sel_op2 = "00100" ELSE + cps_in WHEN sel_op2 = "00010" ELSE + cms_in WHEN sel_op2 = "00001" ELSE + std_logic_vector(TO_SIGNED(1,Sample_SZ)) WHEN sel_op2 = "00000" ELSE + (OTHERS => '0'); + +ALU_1: ALU + GENERIC MAP ( + Arith_en => 1, + Input_SZ_1 => Sample_SZ, + Input_SZ_2 => Sample_SZ, + COMP_EN => 0) -- comp is enable when COMP_EN is 0 + PORT MAP ( + clk => clk, + reset => rstn, + ctrl => alu_ctrl, + comp => alu_comp, + OP1 => ALU_OP1, + OP2 => ALU_OP2, + RES => OUT_ALU_SIG); + +END ar_BUTTERFLY_DATAFLOW; \ No newline at end of file diff --git a/lib/staging/LPP/PLE/dsp/lpp_fft/lpp_fft.vhd b/lib/staging/LPP/PLE/dsp/lpp_fft/lpp_fft.vhd new file mode 100644 --- /dev/null +++ b/lib/staging/LPP/PLE/dsp/lpp_fft/lpp_fft.vhd @@ -0,0 +1,120 @@ +------------------------------------------------------------------------------ +-- This file is a part of the LPP VHDL IP LIBRARY +-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 3 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +------------------------------------------------------------------------------- +-- Author : Paul Leroy +-- Mail : paul.leroy@lpp.polytechnique.fr +---------------------------------------------------------------------------- + + +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; + +LIBRARY staging_LPP; +USE staging_LPP.PLE_iir_filter.ALL; + +PACKAGE PLE_lpp_fft IS + +COMPONENT BUTTERFLY_DATAFLOW + GENERIC ( + Sample_SZ : INTEGER := 16); + PORT ( + rstn : IN STD_LOGIC; + clk : IN STD_LOGIC; + + Are : IN STD_LOGIC_VECTOR ( Sample_SZ-1 DOWNTO 0); + Aim : IN STD_LOGIC_VECTOR ( Sample_SZ-1 DOWNTO 0); + Bre : IN STD_LOGIC_VECTOR ( Sample_SZ-1 DOWNTO 0); + Bim : IN STD_LOGIC_VECTOR ( Sample_SZ-1 DOWNTO 0); + c_in : IN STD_LOGIC_VECTOR ( Sample_SZ-1 DOWNTO 0); + cps_in : IN STD_LOGIC_VECTOR ( Sample_SZ-1 DOWNTO 0); + cms_in : IN STD_LOGIC_VECTOR ( Sample_SZ-1 DOWNTO 0); + + out_alu : OUT STD_LOGIC_VECTOR ( 2*Sample_SZ-1 DOWNTO 0); + + sel_op1 : IN STD_LOGIC_VECTOR( 4 DOWNTO 0 ); -- Are Aim X Y Z + sel_op2 : IN STD_LOGIC_VECTOR( 4 DOWNTO 0 ); -- Bre Bim C_in cps_in cms_in + sel_xyz : IN STD_LOGIC_VECTOR( 2 DOWNTO 0 ); -- X Y Z + alu_ctrl : IN STD_LOGIC_VECTOR( 2 DOWNTO 0 ); + alu_comp : IN STD_LOGIC_VECTOR( 1 DOWNTO 0 ) + ); +END COMPONENT; + +COMPONENT BUTTERFLY_CTRL + PORT ( + rstn : IN STD_LOGIC; + clk : IN STD_LOGIC; + + sample_in_val : IN STD_LOGIC; + sample_out_val : OUT STD_LOGIC; + + sel_op1 : OUT STD_LOGIC_VECTOR( 4 DOWNTO 0 ); -- Are Aim X Y Z + sel_op2 : OUT STD_LOGIC_VECTOR( 4 DOWNTO 0 ); -- Bre Bim C_in cps_in cms_in + sel_xyz : OUT STD_LOGIC_VECTOR( 2 DOWNTO 0 ); -- X Y Z + sel_out : OUT STD_LOGIC_VECTOR( 3 DOWNTO 0 ); + alu_ctrl : OUT STD_LOGIC_VECTOR( 2 DOWNTO 0 ); + alu_comp : OUT STD_LOGIC_VECTOR( 1 DOWNTO 0 ) + ); +END COMPONENT; + +COMPONENT BUTTERFLY_TOP + GENERIC ( + Sample_SZ : INTEGER := 16); + PORT ( + rstn : IN STD_LOGIC; + clk : IN STD_LOGIC; + + sample_in_val : IN STD_LOGIC; + sample_out_val : OUT STD_LOGIC; + + Are : IN STD_LOGIC_VECTOR ( Sample_SZ-1 DOWNTO 0); + Aim : IN STD_LOGIC_VECTOR ( Sample_SZ-1 DOWNTO 0); + Bre : IN STD_LOGIC_VECTOR ( Sample_SZ-1 DOWNTO 0); + Bim : IN STD_LOGIC_VECTOR ( Sample_SZ-1 DOWNTO 0); + c_in : IN STD_LOGIC_VECTOR ( Sample_SZ-1 DOWNTO 0); + cps_in : IN STD_LOGIC_VECTOR ( Sample_SZ-1 DOWNTO 0); + cms_in : IN STD_LOGIC_VECTOR ( Sample_SZ-1 DOWNTO 0); + + butterfly_out : OUT STD_LOGIC_VECTOR ( 2*Sample_SZ-1 DOWNTO 0); + sel_out : OUT STD_LOGIC_VECTOR ( 3 DOWNTO 0) + ); +END COMPONENT; + +COMPONENT input_buffers_and_coefficients + GENERIC( + tech : INTEGER := 0; + Input_SZ_1 : INTEGER := 16; + Mem_use : INTEGER := use_RAM -- 1 use RAM + ); + PORT( + rstn : IN STD_LOGIC; + clk : IN STD_LOGIC; + --******************* + -- PLE ************** + WD_in : IN STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0); + RD_out : OUT STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0); + WEN_in : IN STD_LOGIC; + REN_in : IN STD_LOGIC; + RADDR_in : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + WADDR_in : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + start : IN STD_LOGIC + --******************* + --******************* + ); +END COMPONENT; + +END; \ No newline at end of file diff --git a/lib/staging/LPP/PLE/dsp/lpp_fft/test/run.do b/lib/staging/LPP/PLE/dsp/lpp_fft/test/run.do new file mode 100644 --- /dev/null +++ b/lib/staging/LPP/PLE/dsp/lpp_fft/test/run.do @@ -0,0 +1,30 @@ +vlib staging_lpp +vmap staging_lpp "staging_lpp" + +vcom -93 -explicit -work staging_lpp "../../../general_purpose/general_purpose.vhd" +vcom -93 -explicit -work staging_lpp "../../../general_purpose/MAC_CONTROLER.vhd" +vcom -93 -explicit -work staging_lpp "../../../general_purpose/Multiplier.vhd" +vcom -93 -explicit -work staging_lpp "../../../general_purpose/Adder.vhd" +vcom -93 -explicit -work staging_lpp "../../../general_purpose/TwoComplementer.vhd" +vcom -93 -explicit -work staging_lpp "../../../general_purpose/MAC_REG.vhd" +vcom -93 -explicit -work staging_lpp "../../../general_purpose/MAC_MUX.vhd" +vcom -93 -explicit -work staging_lpp "../../../general_purpose/MAC_MUX2.vhd" +vcom -93 -explicit -work staging_lpp "../../../general_purpose/MAC.vhd" +vcom -93 -explicit -work staging_lpp "../../../general_purpose/ALU.vhd" + +vcom -93 -explicit -work staging_lpp "../lpp_fft.vhd" +vcom -93 -explicit -work staging_lpp "../LPP_BUTTERFLY_DATAFLOW.vhd" +vcom -93 -explicit -work staging_lpp "../BUTTERFLY_CTRL.vhd" +vcom -93 -explicit -work staging_lpp "../BUTTERFLY_TOP.vhd" +vcom -93 -explicit -work staging_lpp "testBench_BUTTERFLY_TOP.vhd" + +vsim -L staging_lpp -t 1ps staging_lpp.TestBench_BUTTERFLY_TOP + +do wave.do + +log -R * + +run 1 us +# The following lines are commented because no testbench is associated with the project +# add wave /testbench/* +# run 1000ns diff --git a/lib/staging/LPP/PLE/dsp/lpp_fft/test/testBench_BUTTERFLY_TOP.vhd b/lib/staging/LPP/PLE/dsp/lpp_fft/test/testBench_BUTTERFLY_TOP.vhd new file mode 100644 --- /dev/null +++ b/lib/staging/LPP/PLE/dsp/lpp_fft/test/testBench_BUTTERFLY_TOP.vhd @@ -0,0 +1,104 @@ +------------------------------------------------------------------------------ +-- This file is a part of the LPP VHDL IP LIBRARY +-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 3 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +------------------------------------------------------------------------------- +-- Author : Paul Leroy +-- Mail : paul.leroy@lpp.polytechnique.fr +---------------------------------------------------------------------------- +library IEEE; +use IEEE.numeric_std.all; +use IEEE.std_logic_1164.all; + +library staging_lpp; +use staging_lpp.PLE_lpp_fft.all; + +entity TestBench_BUTTERFLY_TOP is + +end TestBench_BUTTERFLY_TOP; + +architecture TestBench_BUTTERFLY_TOP of TestBench_BUTTERFLY_TOP is + +constant Sample_SZ : integer := 16; + +signal clk : std_logic:='0'; +signal rstn : std_logic:='0'; + +signal Are : std_logic_vector( Sample_SZ-1 downto 0 ) := ( others => '0'); +signal Aim : std_logic_vector( Sample_SZ-1 downto 0 ) := ( others => '0'); +signal Bre : std_logic_vector( Sample_SZ-1 downto 0 ) := ( others => '0'); +signal Bim : std_logic_vector( Sample_SZ-1 downto 0 ) := ( others => '0'); +signal c : std_logic_vector( Sample_SZ-1 downto 0 ) := ( others => '0'); +signal cps : std_logic_vector( Sample_SZ-1 downto 0 ) := ( others => '0'); +signal cms : std_logic_vector( Sample_SZ-1 downto 0 ) := ( others => '0'); + +signal Resultat : std_logic_vector( 2*Sample_SZ-1 downto 0 ); + +signal sel_out : std_logic_vector( 3 downto 0 ); + +signal sample_in_val : std_logic := '0'; +signal sample_out_val : std_logic; + +begin + +BUTTERFLY_TOP1 : BUTTERFLY_TOP +generic map( + Sample_SZ => Sample_SZ +) +port map( + rstn => rstn, + clk => clk, + + sample_in_val => sample_in_val, + sample_out_val => sample_out_val, + + Are => Are, + Aim => Aim, + Bre => Bre, + Bim => Bim, + c_in => c, + cps_in => cps, + cms_in => cms, + + butterfly_out => Resultat, + sel_out => sel_out +); + +clk <= not clk after 25 ns; + +process +begin + +if rstn = '0' then + wait for 40 ns; + rstn <= '1'; +end if; + +wait for 11 ns; + Are <= std_logic_vector(TO_SIGNED(100 ,Sample_SZ)); + Aim <= std_logic_vector(TO_SIGNED(110 ,Sample_SZ)); + Bre <= std_logic_vector(TO_SIGNED(-40 ,Sample_SZ)); + Bim <= std_logic_vector(TO_SIGNED(10 ,Sample_SZ)); + c <= std_logic_vector(TO_SIGNED(121 ,Sample_SZ)); + cps <= std_logic_vector(TO_SIGNED(160 ,Sample_SZ)); + cms <= std_logic_vector(TO_SIGNED(82 ,Sample_SZ)); + +wait for 50 ns; + sample_in_val <= '1'; + +end process; + +end TestBench_BUTTERFLY_TOP; diff --git a/lib/staging/LPP/PLE/dsp/lpp_fft/test/wave.do b/lib/staging/LPP/PLE/dsp/lpp_fft/test/wave.do new file mode 100644 --- /dev/null +++ b/lib/staging/LPP/PLE/dsp/lpp_fft/test/wave.do @@ -0,0 +1,36 @@ +onerror {resume} +quietly WaveActivateNextPane {} 0 +add wave -noupdate /testbench_butterfly_top/clk +add wave -noupdate /testbench_butterfly_top/rstn +add wave -noupdate -radix decimal /testbench_butterfly_top/are +add wave -noupdate -radix decimal /testbench_butterfly_top/aim +add wave -noupdate -radix decimal /testbench_butterfly_top/bre +add wave -noupdate -radix decimal /testbench_butterfly_top/bim +add wave -noupdate -radix decimal /testbench_butterfly_top/c +add wave -noupdate -radix decimal /testbench_butterfly_top/cps +add wave -noupdate -radix decimal /testbench_butterfly_top/cms +add wave -noupdate -radix decimal /testbench_butterfly_top/op1 +add wave -noupdate -radix decimal /testbench_butterfly_top/op2 +add wave -noupdate -radix decimal /testbench_butterfly_top/resultat +add wave -noupdate /testbench_butterfly_top/alu_ctrl_sig +add wave -noupdate /testbench_butterfly_top/alu_comp_sig +add wave -noupdate /testbench_butterfly_top/sel_out +add wave -noupdate /testbench_butterfly_top/sample_in_val +add wave -noupdate /testbench_butterfly_top/sample_out_val +TreeUpdate [SetDefaultTree] +WaveRestoreCursors {{Cursor 1} {149541 ps} 0} +configure wave -namecolwidth 150 +configure wave -valuecolwidth 100 +configure wave -justifyvalue left +configure wave -signalnamewidth 0 +configure wave -snapdistance 10 +configure wave -datasetprefix 0 +configure wave -rowmargin 4 +configure wave -childrowmargin 2 +configure wave -gridoffset 0 +configure wave -gridperiod 1000 +configure wave -griddelta 40 +configure wave -timeline 0 +configure wave -timelineunits ns +update +WaveRestoreZoom {0 ps} {1050 ns} diff --git a/lib/staging/LPP/PLE/dsp/lpp_fft/twiddle_factors_128.vhd b/lib/staging/LPP/PLE/dsp/lpp_fft/twiddle_factors_128.vhd new file mode 100644 --- /dev/null +++ b/lib/staging/LPP/PLE/dsp/lpp_fft/twiddle_factors_128.vhd @@ -0,0 +1,467 @@ +--twiddle_factors_128.vhd + +library IEEE; +use IEEE.numeric_std.all; +use IEEE.std_logic_1164.all; + +package PLE_twiddle_factors_128 is + +constant Coef_SZ : integer := 16; +constant NB_Coeffs : integer := 128; + +--============================================================ +-- create each initial values for each coefs ============ +--!!!!!!!!!!It should be interfaced with a software !!!!!!!!!! +--============================================================ + +constant c_0 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ)); +constant c_1 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ)); +constant c_2 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ)); +constant c_3 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ)); +constant c_4 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ)); +constant c_5 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ)); +constant c_6 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ)); +constant c_7 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ)); +constant c_8 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ)); +constant c_9 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ)); +constant c_10 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ)); +constant c_11 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ)); +constant c_12 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ)); +constant c_13 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ)); +constant c_14 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ)); +constant c_15 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ)); +constant c_16 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ)); +constant c_17 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ)); +constant c_18 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ)); +constant c_19 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ)); +constant c_20 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ)); +constant c_21 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ)); +constant c_22 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ)); +constant c_23 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ)); +constant c_24 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ)); +constant c_25 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ)); +constant c_26 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ)); +constant c_27 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ)); +constant c_28 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ)); +constant c_29 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ)); +constant c_30 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ)); +constant c_31 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ)); +constant c_32 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ)); +constant c_33 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ)); +constant c_34 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ)); +constant c_35 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ)); +constant c_36 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ)); +constant c_37 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ)); +constant c_38 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ)); +constant c_39 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ)); +constant c_40 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ)); +constant c_41 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ)); +constant c_42 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ)); +constant c_43 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ)); +constant c_44 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ)); +constant c_45 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ)); +constant c_46 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ)); +constant c_47 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ)); +constant c_48 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ)); +constant c_49 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ)); +constant c_50 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ)); +constant c_51 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ)); +constant c_52 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ)); +constant c_53 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ)); +constant c_54 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ)); +constant c_55 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ)); +constant c_56 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ)); +constant c_57 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ)); +constant c_58 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ)); +constant c_59 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ)); +constant c_60 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ)); +constant c_61 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ)); +constant c_62 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ)); +constant c_63 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ)); +constant c_64 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ)); +constant c_65 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ)); +constant c_66 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ)); +constant c_67 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ)); +constant c_68 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ)); +constant c_69 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ)); +constant c_70 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ)); +constant c_71 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ)); +constant c_72 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ)); +constant c_73 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ)); +constant c_74 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ)); +constant c_75 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ)); +constant c_76 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ)); +constant c_77 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ)); +constant c_78 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ)); +constant c_79 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ)); +constant c_80 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ)); +constant c_81 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ)); +constant c_82 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ)); +constant c_83 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ)); +constant c_84 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ)); +constant c_85 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ)); +constant c_86 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ)); +constant c_87 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ)); +constant c_88 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ)); +constant c_89 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ)); +constant c_90 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ)); +constant c_91 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ)); +constant c_92 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ)); +constant c_93 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ)); +constant c_94 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ)); +constant c_95 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ)); +constant c_96 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ)); +constant c_97 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ)); +constant c_98 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ)); +constant c_99 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ)); +constant c_100 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ)); +constant c_101 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ)); +constant c_102 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ)); +constant c_103 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ)); +constant c_104 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ)); +constant c_105 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ)); +constant c_106 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ)); +constant c_107 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ)); +constant c_108 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ)); +constant c_109 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ)); +constant c_110 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ)); +constant c_111 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ)); +constant c_112 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ)); +constant c_113 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ)); +constant c_114 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ)); +constant c_115 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ)); +constant c_116 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ)); +constant c_117 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ)); +constant c_118 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ)); +constant c_119 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ)); +constant c_120 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ)); +constant c_121 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ)); +constant c_122 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ)); +constant c_123 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ)); +constant c_124 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ)); +constant c_125 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ)); +constant c_126 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ)); +constant c_127 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ)); + +--************************************************-- + +constant cps_0 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ)); +constant cps_1 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ)); +constant cps_2 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ)); +constant cps_3 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ)); +constant cps_4 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ)); +constant cps_5 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ)); +constant cps_6 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ)); +constant cps_7 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ)); +constant cps_8 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ)); +constant cps_9 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ)); +constant cps_10 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ)); +constant cps_11 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ)); +constant cps_12 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ)); +constant cps_13 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ)); +constant cps_14 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ)); +constant cps_15 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ)); +constant cps_16 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ)); +constant cps_17 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ)); +constant cps_18 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ)); +constant cps_19 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ)); +constant cps_20 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ)); +constant cps_21 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ)); +constant cps_22 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ)); +constant cps_23 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ)); +constant cps_24 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ)); +constant cps_25 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ)); +constant cps_26 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ)); +constant cps_27 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ)); +constant cps_28 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ)); +constant cps_29 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ)); +constant cps_30 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ)); +constant cps_31 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ)); +constant cps_32 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ)); +constant cps_33 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ)); +constant cps_34 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ)); +constant cps_35 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ)); +constant cps_36 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ)); +constant cps_37 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ)); +constant cps_38 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ)); +constant cps_39 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ)); +constant cps_40 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ)); +constant cps_41 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ)); +constant cps_42 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ)); +constant cps_43 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ)); +constant cps_44 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ)); +constant cps_45 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ)); +constant cps_46 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ)); +constant cps_47 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ)); +constant cps_48 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ)); +constant cps_49 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ)); +constant cps_50 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ)); +constant cps_51 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ)); +constant cps_52 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ)); +constant cps_53 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ)); +constant cps_54 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ)); +constant cps_55 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ)); +constant cps_56 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ)); +constant cps_57 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ)); +constant cps_58 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ)); +constant cps_59 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ)); +constant cps_60 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ)); +constant cps_61 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ)); +constant cps_62 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ)); +constant cps_63 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ)); +constant cps_64 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ)); +constant cps_65 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ)); +constant cps_66 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ)); +constant cps_67 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ)); +constant cps_68 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ)); +constant cps_69 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ)); +constant cps_70 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ)); +constant cps_71 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ)); +constant cps_72 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ)); +constant cps_73 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ)); +constant cps_74 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ)); +constant cps_75 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ)); +constant cps_76 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ)); +constant cps_77 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ)); +constant cps_78 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ)); +constant cps_79 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ)); +constant cps_80 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ)); +constant cps_81 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ)); +constant cps_82 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ)); +constant cps_83 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ)); +constant cps_84 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ)); +constant cps_85 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ)); +constant cps_86 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ)); +constant cps_87 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ)); +constant cps_88 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ)); +constant cps_89 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ)); +constant cps_90 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ)); +constant cps_91 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ)); +constant cps_92 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ)); +constant cps_93 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ)); +constant cps_94 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ)); +constant cps_95 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ)); +constant cps_96 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ)); +constant cps_97 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ)); +constant cps_98 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ)); +constant cps_99 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ)); +constant cps_100 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ)); +constant cps_101 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ)); +constant cps_102 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ)); +constant cps_103 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ)); +constant cps_104 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ)); +constant cps_105 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ)); +constant cps_106 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ)); +constant cps_107 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ)); +constant cps_108 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ)); +constant cps_109 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ)); +constant cps_110 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ)); +constant cps_111 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ)); +constant cps_112 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ)); +constant cps_113 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ)); +constant cps_114 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ)); +constant cps_115 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ)); +constant cps_116 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ)); +constant cps_117 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ)); +constant cps_118 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ)); +constant cps_119 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ)); +constant cps_120 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ)); +constant cps_121 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ)); +constant cps_122 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ)); +constant cps_123 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ)); +constant cps_124 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ)); +constant cps_125 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ)); +constant cps_126 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ)); +constant cps_127 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ)); + +--************************************************-- + +constant cms_0 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ)); +constant cms_1 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ)); +constant cms_2 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ)); +constant cms_3 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ)); +constant cms_4 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ)); +constant cms_5 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ)); +constant cms_6 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ)); +constant cms_7 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ)); +constant cms_8 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ)); +constant cms_9 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ)); +constant cms_10 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ)); +constant cms_11 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ)); +constant cms_12 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ)); +constant cms_13 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ)); +constant cms_14 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ)); +constant cms_15 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ)); +constant cms_16 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ)); +constant cms_17 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ)); +constant cms_18 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ)); +constant cms_19 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ)); +constant cms_20 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ)); +constant cms_21 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ)); +constant cms_22 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ)); +constant cms_23 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ)); +constant cms_24 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ)); +constant cms_25 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ)); +constant cms_26 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ)); +constant cms_27 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ)); +constant cms_28 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ)); +constant cms_29 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ)); +constant cms_30 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ)); +constant cms_31 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ)); +constant cms_32 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ)); +constant cms_33 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ)); +constant cms_34 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ)); +constant cms_35 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ)); +constant cms_36 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ)); +constant cms_37 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ)); +constant cms_38 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ)); +constant cms_39 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ)); +constant cms_40 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ)); +constant cms_41 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ)); +constant cms_42 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ)); +constant cms_43 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ)); +constant cms_44 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ)); +constant cms_45 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ)); +constant cms_46 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ)); +constant cms_47 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ)); +constant cms_48 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ)); +constant cms_49 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ)); +constant cms_50 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ)); +constant cms_51 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ)); +constant cms_52 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ)); +constant cms_53 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ)); +constant cms_54 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ)); +constant cms_55 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ)); +constant cms_56 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ)); +constant cms_57 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ)); +constant cms_58 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ)); +constant cms_59 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ)); +constant cms_60 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ)); +constant cms_61 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ)); +constant cms_62 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ)); +constant cms_63 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ)); +constant cms_64 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ)); +constant cms_65 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ)); +constant cms_66 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ)); +constant cms_67 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ)); +constant cms_68 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ)); +constant cms_69 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ)); +constant cms_70 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ)); +constant cms_71 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ)); +constant cms_72 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ)); +constant cms_73 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ)); +constant cms_74 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ)); +constant cms_75 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ)); +constant cms_76 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ)); +constant cms_77 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ)); +constant cms_78 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ)); +constant cms_79 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ)); +constant cms_80 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ)); +constant cms_81 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ)); +constant cms_82 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ)); +constant cms_83 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ)); +constant cms_84 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ)); +constant cms_85 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ)); +constant cms_86 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ)); +constant cms_87 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ)); +constant cms_88 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ)); +constant cms_89 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ)); +constant cms_90 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ)); +constant cms_91 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ)); +constant cms_92 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ)); +constant cms_93 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ)); +constant cms_94 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ)); +constant cms_95 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ)); +constant cms_96 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ)); +constant cms_97 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ)); +constant cms_98 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ)); +constant cms_99 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ)); +constant cms_100 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ)); +constant cms_101 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ)); +constant cms_102 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ)); +constant cms_103 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ)); +constant cms_104 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ)); +constant cms_105 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ)); +constant cms_106 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ)); +constant cms_107 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ)); +constant cms_108 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ)); +constant cms_109 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ)); +constant cms_110 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ)); +constant cms_111 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ)); +constant cms_112 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ)); +constant cms_113 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ)); +constant cms_114 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ)); +constant cms_115 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ)); +constant cms_116 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ)); +constant cms_117 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ)); +constant cms_118 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ)); +constant cms_119 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ)); +constant cms_120 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ)); +constant cms_121 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ)); +constant cms_122 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ)); +constant cms_123 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ)); +constant cms_124 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ)); +constant cms_125 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ)); +constant cms_126 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ)); +constant cms_127 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ)); + +--************************************************-- + +constant twiddleFactors_c : std_logic_vector( (NB_Coeffs * Coef_SZ)-1 downto 0) := +( +c_0 & c_1 & c_2 & c_3 & c_4 & c_5 & c_6 & c_7 & +c_8 & c_9 & c_10 & c_11 & c_12 & c_13 & c_14 & c_15 & +c_16 & c_17 & c_18 & c_19 & c_20 & c_21 & c_22 & c_23 & +c_24 & c_25 & c_26 & c_27 & c_28 & c_29 & c_30 & c_31 & +c_32 & c_33 & c_34 & c_35 & c_36 & c_37 & c_38 & c_39 & +c_40 & c_41 & c_42 & c_43 & c_44 & c_45 & c_46 & c_47 & +c_48 & c_49 & c_50 & c_51 & c_52 & c_53 & c_54 & c_55 & +c_56 & c_57 & c_58 & c_59 & c_60 & c_61 & c_62 & c_63 & +c_64 & c_65 & c_66 & c_67 & c_68 & c_69 & c_70 & c_71 & +c_72 & c_73 & c_74 & c_75 & c_76 & c_77 & c_78 & c_79 & +c_80 & c_81 & c_82 & c_83 & c_84 & c_85 & c_86 & c_87 & +c_88 & c_89 & c_90 & c_91 & c_92 & c_93 & c_94 & c_95 & +c_96 & c_97 & c_98 & c_99 & c_100 & c_101 & c_102 & c_103 & +c_104 & c_105 & c_106 & c_107 & c_108 & c_109 & c_110 & c_111 & +c_112 & c_113 & c_114 & c_115 & c_116 & c_117 & c_118 & c_119 & +c_120 & c_121 & c_122 & c_123 & c_124 & c_125 & c_126 & c_127 ); + +constant twiddleFactors_cps : std_logic_vector( (NB_Coeffs * Coef_SZ)-1 downto 0) := +( +cps_0 & cps_1 & cps_2 & cps_3 & cps_4 & cps_5 & cps_6 & cps_7 & +cps_8 & cps_9 & cps_10 & cps_11 & cps_12 & cps_13 & cps_14 & cps_15 & +cps_16 & cps_17 & cps_18 & cps_19 & cps_20 & cps_21 & cps_22 & cps_23 & +cps_24 & cps_25 & cps_26 & cps_27 & cps_28 & cps_29 & cps_30 & cps_31 & +cps_32 & cps_33 & cps_34 & cps_35 & cps_36 & cps_37 & cps_38 & cps_39 & +cps_40 & cps_41 & cps_42 & cps_43 & cps_44 & cps_45 & cps_46 & cps_47 & +cps_48 & cps_49 & cps_50 & cps_51 & cps_52 & cps_53 & cps_54 & cps_55 & +cps_56 & cps_57 & cps_58 & cps_59 & cps_60 & cps_61 & cps_62 & cps_63 & +cps_64 & cps_65 & cps_66 & cps_67 & cps_68 & cps_69 & cps_70 & cps_71 & +cps_72 & cps_73 & cps_74 & cps_75 & cps_76 & cps_77 & cps_78 & cps_79 & +cps_80 & cps_81 & cps_82 & cps_83 & cps_84 & cps_85 & cps_86 & cps_87 & +cps_88 & cps_89 & cps_90 & cps_91 & cps_92 & cps_93 & cps_94 & cps_95 & +cps_96 & cps_97 & cps_98 & cps_99 & cps_100 & cps_101 & cps_102 & cps_103 & +cps_104 & cps_105 & cps_106 & cps_107 & cps_108 & cps_109 & cps_110 & cps_111 & +cps_112 & cps_113 & cps_114 & cps_115 & cps_116 & cps_117 & cps_118 & cps_119 & +cps_120 & cps_121 & cps_122 & cps_123 & cps_124 & cps_125 & cps_126 & cps_127 ); + +constant twiddleFactors_cms : std_logic_vector( (NB_Coeffs * Coef_SZ)-1 downto 0) := +( +cms_0 & cms_1 & cms_2 & cms_3 & cms_4 & cms_5 & cms_6 & cms_7 & +cms_8 & cms_9 & cms_10 & cms_11 & cms_12 & cms_13 & cms_14 & cms_15 & +cms_16 & cms_17 & cms_18 & cms_19 & cms_20 & cms_21 & cms_22 & cms_23 & +cms_24 & cms_25 & cms_26 & cms_27 & cms_28 & cms_29 & cms_30 & cms_31 & +cms_32 & cms_33 & cms_34 & cms_35 & cms_36 & cms_37 & cms_38 & cms_39 & +cms_40 & cms_41 & cms_42 & cms_43 & cms_44 & cms_45 & cms_46 & cms_47 & +cms_48 & cms_49 & cms_50 & cms_51 & cms_52 & cms_53 & cms_54 & cms_55 & +cms_56 & cms_57 & cms_58 & cms_59 & cms_60 & cms_61 & cms_62 & cms_63 & +cms_64 & cms_65 & cms_66 & cms_67 & cms_68 & cms_69 & cms_70 & cms_71 & +cms_72 & cms_73 & cms_74 & cms_75 & cms_76 & cms_77 & cms_78 & cms_79 & +cms_80 & cms_81 & cms_82 & cms_83 & cms_84 & cms_85 & cms_86 & cms_87 & +cms_88 & cms_89 & cms_90 & cms_91 & cms_92 & cms_93 & cms_94 & cms_95 & +cms_96 & cms_97 & cms_98 & cms_99 & cms_100 & cms_101 & cms_102 & cms_103 & +cms_104 & cms_105 & cms_106 & cms_107 & cms_108 & cms_109 & cms_110 & cms_111 & +cms_112 & cms_113 & cms_114 & cms_115 & cms_116 & cms_117 & cms_118 & cms_119 & +cms_120 & cms_121 & cms_122 & cms_123 & cms_124 & cms_125 & cms_126 & cms_127 ); +end; + diff --git a/lib/staging/LPP/PLE/general_purpose/ALU.vhd b/lib/staging/LPP/PLE/general_purpose/ALU.vhd new file mode 100644 --- /dev/null +++ b/lib/staging/LPP/PLE/general_purpose/ALU.vhd @@ -0,0 +1,65 @@ +------------------------------------------------------------------------------ +-- This file is a part of the LPP VHDL IP LIBRARY +-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 3 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +------------------------------------------------------------------------------- +-- Author : Martin Morlot +-- Mail : martin.morlot@lpp.polytechnique.fr +------------------------------------------------------------------------------- +library IEEE; +use IEEE.numeric_std.all; +use IEEE.std_logic_1164.all; +library staging_lpp; +use staging_lpp.PLE_general_purpose.all; + +--! Une ALU : Arithmetic and logical unit, permettant de réaliser une ou plusieurs opération + +entity ALU is +generic( + Arith_en : integer := 1; + Logic_en : integer := 1; + Input_SZ_1 : integer := 16; + Input_SZ_2 : integer := 16; + COMP_EN : INTEGER := 0 -- 1 => No Comp + ); +port( + clk : in std_logic; --! Horloge du composant + reset : in std_logic; --! Reset general du composant + ctrl : in std_logic_vector(2 downto 0); --! Permet de sélectionner la/les opération désirée + comp : in std_logic_vector(1 downto 0); --! (set) Permet de complémenter les opérandes + OP1 : in std_logic_vector(Input_SZ_1-1 downto 0); --! Premier Opérande + OP2 : in std_logic_vector(Input_SZ_2-1 downto 0); --! Second Opérande + RES : out std_logic_vector(Input_SZ_1+Input_SZ_2-1 downto 0) --! Résultat de l'opération +); +end ALU; + +--! @details Sélection grace a l'entrée "ctrl" : +--! Pause : IDLE = 000 +--! Multiplieur/Accumulateur : MAC = 001 +--! Multiplication : MULT = 010 +--! Addition : ADD = 011 +--! Reset du MAC : CLRMAC = 100 +architecture ar_ALU of ALU is + +begin + +arith : if Arith_en = 1 generate +MACinst : MAC +generic map(Input_SZ_1,Input_SZ_2,COMP_EN) +port map(clk,reset,ctrl(2),ctrl(1 downto 0),comp,OP1,OP2,RES); +end generate; + +end architecture; diff --git a/lib/staging/LPP/PLE/general_purpose/Adder.vhd b/lib/staging/LPP/PLE/general_purpose/Adder.vhd new file mode 100644 --- /dev/null +++ b/lib/staging/LPP/PLE/general_purpose/Adder.vhd @@ -0,0 +1,71 @@ +------------------------------------------------------------------------------ +-- This file is a part of the LPP VHDL IP LIBRARY +-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 3 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +------------------------------------------------------------------------------- +-- Author : Alexis Jeandet +-- Mail : alexis.jeandet@lpp.polytechnique.fr +---------------------------------------------------------------------------- +LIBRARY IEEE; +USE IEEE.numeric_std.ALL; +USE IEEE.std_logic_1164.ALL; + +ENTITY Adder IS + GENERIC( + Input_SZ_A : INTEGER := 16; + Input_SZ_B : INTEGER := 16 + + ); + PORT( + clk : IN STD_LOGIC; + reset : IN STD_LOGIC; + clr : IN STD_LOGIC; + load : IN STD_LOGIC; + add : IN STD_LOGIC; + OP1 : IN STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0); + OP2 : IN STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0); + RES : OUT STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0) + ); +END ENTITY; + + + + +ARCHITECTURE ar_Adder OF Adder IS + + SIGNAL REG : STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0); + SIGNAL RESADD : STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0); + +BEGIN + + RES <= REG; + RESADD <= STD_LOGIC_VECTOR(resize(SIGNED(OP1)+SIGNED(OP2), Input_SZ_A)); + + PROCESS(clk, reset) + BEGIN + IF reset = '0' THEN + REG <= (OTHERS => '0'); + ELSIF clk'EVENT AND clk = '1' then + IF clr = '1' THEN + REG <= (OTHERS => '0'); + ELSIF add = '1' THEN + REG <= RESADD; + ELSIF load = '1' THEN + REG <= OP2; + END IF; + END IF; + END PROCESS; +END ar_Adder; diff --git a/lib/staging/LPP/PLE/general_purpose/MAC.vhd b/lib/staging/LPP/PLE/general_purpose/MAC.vhd new file mode 100644 --- /dev/null +++ b/lib/staging/LPP/PLE/general_purpose/MAC.vhd @@ -0,0 +1,385 @@ +------------------------------------------------------------------------------ +-- This file is a part of the LPP VHDL IP LIBRARY +-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 3 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +------------------------------------------------------------------------------- +-- Author : Alexis Jeandet +-- Mail : alexis.jeandet@lpp.polytechnique.fr +---------------------------------------------------------------------------- +LIBRARY IEEE; +USE IEEE.numeric_std.ALL; +USE IEEE.std_logic_1164.ALL; +LIBRARY staging_lpp; +USE staging_lpp.PLE_general_purpose.ALL; +--TODO +--terminer le testbensh puis changer le resize dans les instanciations +--par un resize sur un vecteur en combi + + +ENTITY MAC IS + GENERIC( + Input_SZ_A : INTEGER := 8; + Input_SZ_B : INTEGER := 8; + COMP_EN : INTEGER := 0 -- 1 => No Comp + + ); + PORT( + clk : IN STD_LOGIC; + reset : IN STD_LOGIC; + clr_MAC : IN STD_LOGIC; + MAC_MUL_ADD : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + Comp_2C : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + OP1 : IN STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0); + OP2 : IN STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0); + RES : OUT STD_LOGIC_VECTOR(Input_SZ_A+Input_SZ_B-1 DOWNTO 0) + ); +END MAC; + + + + +ARCHITECTURE ar_MAC OF MAC IS + + SIGNAL add, mult : STD_LOGIC; + SIGNAL MULTout : STD_LOGIC_VECTOR(Input_SZ_A+Input_SZ_B-1 DOWNTO 0); + + SIGNAL ADDERinA : STD_LOGIC_VECTOR(Input_SZ_A+Input_SZ_B-1 DOWNTO 0); + SIGNAL ADDERinB : STD_LOGIC_VECTOR(Input_SZ_A+Input_SZ_B-1 DOWNTO 0); + SIGNAL ADDERout : STD_LOGIC_VECTOR(Input_SZ_A+Input_SZ_B-1 DOWNTO 0); + + SIGNAL MACMUXsel : STD_LOGIC; + SIGNAL OP1_2C_D_Resz : STD_LOGIC_VECTOR(Input_SZ_A+Input_SZ_B-1 DOWNTO 0); + SIGNAL OP2_2C_D_Resz : STD_LOGIC_VECTOR(Input_SZ_A+Input_SZ_B-1 DOWNTO 0); + + SIGNAL OP1_2C : STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0); + SIGNAL OP2_2C : STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0); + + SIGNAL MACMUX2sel : STD_LOGIC; + + SIGNAL add_D : STD_LOGIC; + SIGNAL add_D_D : STD_LOGIC; + SIGNAL mult_D : STD_LOGIC; + SIGNAL OP1_2C_D : STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0); + SIGNAL OP2_2C_D : STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0); + +-- SIGNAL OP1_2C_D_reg : STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0); +-- SIGNAL OP2_2C_D_reg : STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0); + + SIGNAL MULTout_D : STD_LOGIC_VECTOR(Input_SZ_A+Input_SZ_B-1 DOWNTO 0); + SIGNAL MACMUXsel_D : STD_LOGIC; + SIGNAL MACMUXsel_D_D : STD_LOGIC; + SIGNAL MACMUX2sel_D : STD_LOGIC; + SIGNAL MACMUX2sel_D_D : STD_LOGIC; + SIGNAL MACMUX2sel_D_D_D : STD_LOGIC; + SIGNAL clr_MAC_D : STD_LOGIC; + SIGNAL clr_MAC_D_D : STD_LOGIC; + SIGNAL clr_MAC_D_D_D : STD_LOGIC; + SIGNAL MAC_MUL_ADD_2C_D : STD_LOGIC_VECTOR(1 DOWNTO 0); + SIGNAL MAC_MUL_ADD_2C_D_D : STD_LOGIC_VECTOR(1 DOWNTO 0); + + SIGNAL load_mult_result : STD_LOGIC; + SIGNAL load_mult_result_D : STD_LOGIC; + SIGNAL load_mult_result_D_D : STD_LOGIC; + +BEGIN + + + + +--============================================================== +--=============M A C C O N T R O L E R========================= +--============================================================== + MAC_CONTROLER1 : MAC_CONTROLER + PORT MAP( + ctrl => MAC_MUL_ADD, + MULT => mult, + ADD => add, + LOAD_ADDER => load_mult_result, + MACMUX_sel => MACMUXsel, + MACMUX2_sel => MACMUX2sel + + ); +--============================================================== + + +--============================================================== +--===================TWO COMPLEMENTERS========================== +--============================================================== + gen_comp : IF COMP_EN = 0 GENERATE + TWO_COMPLEMENTER1 : TwoComplementer + GENERIC MAP( + Input_SZ => Input_SZ_A + ) + PORT MAP( + clk => clk, + reset => reset, + clr => clr_MAC, + TwoComp => Comp_2C(0), + OP => OP1, + RES => OP1_2C + ); + + TWO_COMPLEMENTER2 : TwoComplementer + GENERIC MAP( + Input_SZ => Input_SZ_B + ) + PORT MAP( + clk => clk, + reset => reset, + clr => clr_MAC, + TwoComp => Comp_2C(1), + OP => OP2, + RES => OP2_2C + ); + END GENERATE gen_comp; + + no_gen_comp : IF COMP_EN = 1 GENERATE + process(clk,reset) + begin + if(reset='0')then + OP1_2C <= (others => '0'); + OP2_2C <= (others => '0'); + elsif clk'event and clk='1' then + if clr_MAC = '1' then + OP1_2C <= (others => '0'); + OP2_2C <= (others => '0'); + else + OP1_2C <= OP1; + OP2_2C <= OP2; + end if; + end if; + end process; + + END GENERATE no_gen_comp; +--============================================================== + +--============================================================== +--=============M U L T I P L I E R============================== +--============================================================== + + multREG0 : MAC_REG + GENERIC MAP(size => 1) + PORT MAP( + reset => reset, + clk => clk, + D(0) => mult, + Q(0) => mult_D + ); + + Multiplieri_nst : Multiplier + GENERIC MAP( + Input_SZ_A => Input_SZ_A, + Input_SZ_B => Input_SZ_B + ) + PORT MAP( + clk => clk, + reset => reset, + mult => mult_D, + OP1 => OP1_2C, + OP2 => OP2_2C, + RES => MULTout + ); + + OP1REG : MAC_REG + GENERIC MAP(size => Input_SZ_A) + PORT MAP( + reset => reset, + clk => clk, + D => OP1_2C, + Q => OP1_2C_D + ); + + OP2REG : MAC_REG + GENERIC MAP(size => Input_SZ_B) + PORT MAP( + reset => reset, + clk => clk, + D => OP2_2C, + Q => OP2_2C_D + ); + +--============================================================== + +--============================================================== +--======================M A C M U X =========================== +--============================================================== + + OP1_2C_D_Resz <= STD_LOGIC_VECTOR(resize(SIGNED(OP1_2C_D), Input_SZ_A+Input_SZ_B)); + OP2_2C_D_Resz <= STD_LOGIC_VECTOR(resize(SIGNED(OP2_2C_D), Input_SZ_A+Input_SZ_B)); + + MACMUXselREG0 : MAC_REG + GENERIC MAP(size => 1) + PORT MAP( + reset => reset, + clk => clk, + D(0) => MACMUXsel, + Q(0) => MACMUXsel_D + ); + + MACMUXselREG1 : MAC_REG + GENERIC MAP(size => 1) + PORT MAP( + reset => reset, + clk => clk, + D(0) => MACMUXsel_D, + Q(0) => MACMUXsel_D_D + ); + + MACMUX_inst : MAC_MUX + GENERIC MAP( + Input_SZ_A => Input_SZ_A+Input_SZ_B, + Input_SZ_B => Input_SZ_A+Input_SZ_B + + ) + PORT MAP( + sel => MACMUXsel_D_D, + INA1 => ADDERout, + INA2 => OP2_2C_D_Resz, + INB1 => MULTout, + INB2 => OP1_2C_D_Resz, + OUTA => ADDERinA, + OUTB => ADDERinB + ); + +--============================================================== + +--============================================================== +--======================A D D E R ============================== +--============================================================== + + clr_MACREG0 : MAC_REG + GENERIC MAP(size => 1) + PORT MAP( + reset => reset, + clk => clk, + D(0) => clr_MAC, + Q(0) => clr_MAC_D + ); + + clr_MACREG1 : MAC_REG + GENERIC MAP(size => 1) + PORT MAP( + reset => reset, + clk => clk, + D(0) => clr_MAC_D, + Q(0) => clr_MAC_D_D + ); + + addREG0 : MAC_REG + GENERIC MAP(size => 1) + PORT MAP( + reset => reset, + clk => clk, + D(0) => add, + Q(0) => add_D + ); + + addREG1 : MAC_REG + GENERIC MAP(size => 1) + PORT MAP( + reset => reset, + clk => clk, + D(0) => add_D, + Q(0) => add_D_D + ); + + load_mult_resultREG : MAC_REG + GENERIC MAP(size => 1) + PORT MAP( + reset => reset, + clk => clk, + D(0) => load_mult_result, + Q(0) => load_mult_result_D + ); + + load_mult_resultREG1 : MAC_REG + GENERIC MAP(size => 1) + PORT MAP( + reset => reset, + clk => clk, + D(0) => load_mult_result_D, + Q(0) => load_mult_result_D_D + ); + + adder_inst : Adder + GENERIC MAP( + Input_SZ_A => Input_SZ_A+Input_SZ_B, + Input_SZ_B => Input_SZ_A+Input_SZ_B + ) + PORT MAP( + clk => clk, + reset => reset, + clr => clr_MAC_D_D, + load => load_mult_result_D_D, + add => add_D_D, + OP1 => ADDERinA, + OP2 => ADDERinB, + RES => ADDERout + ); + +--============================================================== + +--============================================================== +--======================M A C M U X2 ========================== +--============================================================== + + MULToutREG : MAC_REG + GENERIC MAP(size => Input_SZ_A+Input_SZ_B) + PORT MAP( + reset => reset, + clk => clk, + D => MULTout, + Q => MULTout_D + ); + + MACMUX2selREG : MAC_REG + GENERIC MAP(size => 1) + PORT MAP( + reset => reset, + clk => clk, + D(0) => MACMUX2sel, + Q(0) => MACMUX2sel_D + ); + + MACMUX2selREG2_0 : MAC_REG + GENERIC MAP(size => 1) + PORT MAP( + reset => reset, + clk => clk, + D(0) => MACMUX2sel_D, + Q(0) => MACMUX2sel_D_D + ); + + MACMUX2selREG2_1 : MAC_REG + GENERIC MAP(size => 1) + PORT MAP( + reset => reset, + clk => clk, + D(0) => MACMUX2sel_D_D, + Q(0) => MACMUX2sel_D_D_D + ); + + MAC_MUX2_inst : MAC_MUX2 + GENERIC MAP(Input_SZ => Input_SZ_A+Input_SZ_B) + PORT MAP( + sel => MACMUX2sel_D_D_D, + RES2 => MULTout_D, + RES1 => ADDERout, + RES => RES + ); +--============================================================== + +END ar_MAC; \ No newline at end of file diff --git a/lib/staging/LPP/PLE/general_purpose/MAC_CONTROLER.vhd b/lib/staging/LPP/PLE/general_purpose/MAC_CONTROLER.vhd new file mode 100644 --- /dev/null +++ b/lib/staging/LPP/PLE/general_purpose/MAC_CONTROLER.vhd @@ -0,0 +1,71 @@ +------------------------------------------------------------------------------ +-- This file is a part of the LPP VHDL IP LIBRARY +-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 3 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +------------------------------------------------------------------------------- +-- Author : Alexis Jeandet +-- Mail : alexis.jeandet@lpp.polytechnique.fr +---------------------------------------------------------------------------- +library IEEE; +use IEEE.numeric_std.all; +use IEEE.std_logic_1164.all; + +--IDLE =00 MAC =01 MULT =10 ADD =11 + + +entity MAC_CONTROLER is +port( + ctrl : in std_logic_vector(1 downto 0); + MULT : out std_logic; + ADD : out std_logic; + LOAD_ADDER : out std_logic; + MACMUX_sel : out std_logic; + MACMUX2_sel : out std_logic + +); +end MAC_CONTROLER; + + + + + +architecture ar_MAC_CONTROLER of MAC_CONTROLER is + +begin + + + +MULT <= '0' when (ctrl = "00" or ctrl = "11") else '1'; +ADD <= '0' when (ctrl = "00" or ctrl = "10") else '1'; +LOAD_ADDER <= '1' when (ctrl = "10") else '0'; -- PATCH JC : mem mult result + -- to permit to compute a + -- MULT follow by a MAC +--MACMUX_sel <= '0' when (ctrl = "00" or ctrl = "01") else '1'; +MACMUX_sel <= '0' when (ctrl = "00" or ctrl = "01" OR ctrl = "10") else '1'; +MACMUX2_sel <= '0' when (ctrl = "00" or ctrl = "01" or ctrl = "11") else '1'; + + +end ar_MAC_CONTROLER; + + + + + + + + + + diff --git a/lib/staging/LPP/PLE/general_purpose/MAC_MUX.vhd b/lib/staging/LPP/PLE/general_purpose/MAC_MUX.vhd new file mode 100644 --- /dev/null +++ b/lib/staging/LPP/PLE/general_purpose/MAC_MUX.vhd @@ -0,0 +1,53 @@ +------------------------------------------------------------------------------ +-- This file is a part of the LPP VHDL IP LIBRARY +-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 3 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +------------------------------------------------------------------------------- +-- Author : Alexis Jeandet +-- Mail : alexis.jeandet@lpp.polytechnique.fr +---------------------------------------------------------------------------- +library IEEE; +use IEEE.numeric_std.all; +use IEEE.std_logic_1164.all; + +entity MAC_MUX is +generic( + Input_SZ_A : integer := 16; + Input_SZ_B : integer := 16 + +); +port( + sel : in std_logic; + INA1 : in std_logic_vector(Input_SZ_A-1 downto 0); + INA2 : in std_logic_vector(Input_SZ_A-1 downto 0); + INB1 : in std_logic_vector(Input_SZ_B-1 downto 0); + INB2 : in std_logic_vector(Input_SZ_B-1 downto 0); + OUTA : out std_logic_vector(Input_SZ_A-1 downto 0); + OUTB : out std_logic_vector(Input_SZ_B-1 downto 0) +); +end entity; + + + + +architecture ar_MAC_MUX of MAC_MUX is + +begin + +OUTA <= INA1 when sel = '0' else INA2; +OUTB <= INB1 when sel = '0' else INB2; + +end ar_MAC_MUX; diff --git a/lib/staging/LPP/PLE/general_purpose/MAC_MUX2.vhd b/lib/staging/LPP/PLE/general_purpose/MAC_MUX2.vhd new file mode 100644 --- /dev/null +++ b/lib/staging/LPP/PLE/general_purpose/MAC_MUX2.vhd @@ -0,0 +1,46 @@ +------------------------------------------------------------------------------ +-- This file is a part of the LPP VHDL IP LIBRARY +-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 3 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +------------------------------------------------------------------------------- +-- Author : Alexis Jeandet +-- Mail : alexis.jeandet@lpp.polytechnique.fr +---------------------------------------------------------------------------- +library IEEE; +use IEEE.numeric_std.all; +use IEEE.std_logic_1164.all; + + +entity MAC_MUX2 is +generic(Input_SZ : integer := 16); +port( + sel : in std_logic; + RES1 : in std_logic_vector(Input_SZ-1 downto 0); + RES2 : in std_logic_vector(Input_SZ-1 downto 0); + RES : out std_logic_vector(Input_SZ-1 downto 0) +); +end entity; + + + + +architecture ar_MAC_MUX2 of MAC_MUX2 is + +begin + +RES <= RES1 when sel = '0' else RES2; + +end ar_MAC_MUX2; diff --git a/lib/staging/LPP/PLE/general_purpose/MAC_REG.vhd b/lib/staging/LPP/PLE/general_purpose/MAC_REG.vhd new file mode 100644 --- /dev/null +++ b/lib/staging/LPP/PLE/general_purpose/MAC_REG.vhd @@ -0,0 +1,58 @@ +------------------------------------------------------------------------------ +-- This file is a part of the LPP VHDL IP LIBRARY +-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 3 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +------------------------------------------------------------------------------- +-- Author : Alexis Jeandet +-- Mail : alexis.jeandet@lpp.polytechnique.fr +---------------------------------------------------------------------------- +library IEEE; +use IEEE.numeric_std.all; +use IEEE.std_logic_1164.all; + +entity MAC_REG is +generic(size : integer := 16); +port( + reset : in std_logic; + clk : in std_logic; + D : in std_logic_vector(size-1 downto 0); + Q : out std_logic_vector(size-1 downto 0) +); +end entity; + + + +architecture ar_MAC_REG of MAC_REG is +begin +process(clk,reset) +begin +if reset = '0' then + Q <= (others => '0'); +elsif clk'event and clk ='1' then + Q <= D; +end if; +end process; +end ar_MAC_REG; + + + + + + + + + + diff --git a/lib/staging/LPP/PLE/general_purpose/Multiplier.vhd b/lib/staging/LPP/PLE/general_purpose/Multiplier.vhd new file mode 100644 --- /dev/null +++ b/lib/staging/LPP/PLE/general_purpose/Multiplier.vhd @@ -0,0 +1,75 @@ +------------------------------------------------------------------------------ +-- This file is a part of the LPP VHDL IP LIBRARY +-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 3 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +------------------------------------------------------------------------------- +-- Author : Alexis Jeandet +-- Mail : alexis.jeandet@lpp.polytechnique.fr +---------------------------------------------------------------------------- +library IEEE; +use IEEE.numeric_std.all; +use IEEE.std_logic_1164.all; + +entity Multiplier is +generic( + Input_SZ_A : integer := 16; + Input_SZ_B : integer := 16 + +); +port( + clk : in std_logic; + reset : in std_logic; + mult : in std_logic; + OP1 : in std_logic_vector(Input_SZ_A-1 downto 0); + OP2 : in std_logic_vector(Input_SZ_B-1 downto 0); + RES : out std_logic_vector(Input_SZ_A+Input_SZ_B-1 downto 0) +); +end Multiplier; + + + + + +architecture ar_Multiplier of Multiplier is + +signal REG : std_logic_vector(Input_SZ_A+Input_SZ_B-1 downto 0); +signal RESMULT : std_logic_vector(Input_SZ_A+Input_SZ_B-1 downto 0); + + +begin + +RES <= REG; +RESMULT <= std_logic_vector(signed(OP1)*signed(OP2)); +process(clk,reset) +begin +if reset = '0' then + REG <= (others => '0'); +elsif clk'event and clk ='1' then + if mult = '1' then + REG <= RESMULT; + end if; +end if; +end process; + +end ar_Multiplier; + + + + + + + + diff --git a/lib/staging/LPP/PLE/general_purpose/TwoComplementer.vhd b/lib/staging/LPP/PLE/general_purpose/TwoComplementer.vhd new file mode 100644 --- /dev/null +++ b/lib/staging/LPP/PLE/general_purpose/TwoComplementer.vhd @@ -0,0 +1,72 @@ +------------------------------------------------------------------------------ +-- This file is a part of the LPP VHDL IP LIBRARY +-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 3 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +------------------------------------------------------------------------------- +-- Author : Martin Morlot +-- Mail : martin.morlot@lpp.polytechnique.fr +------------------------------------------------------------------------------- +library IEEE; +use IEEE.numeric_std.all; +use IEEE.std_logic_1164.all; + +--! Programme permetant de complémenter ou non les entrées de l'ALU, et ainsi de travailler avec des nombres négatifs + +entity TwoComplementer is +generic( + Input_SZ : integer := 16); +port( + clk : in std_logic; --! Horloge du composant + reset : in std_logic; --! Reset general du composant + clr : in std_logic; --! Un reset spécifique au programme + TwoComp : in std_logic; --! Autorise l'utilisation du complément + OP : in std_logic_vector(Input_SZ-1 downto 0); --! Opérande d'entrée + RES : out std_logic_vector(Input_SZ-1 downto 0) --! Résultat, opérande complémenté ou non +); +end TwoComplementer; + + +architecture ar_TwoComplementer of TwoComplementer is + +signal REG : std_logic_vector(Input_SZ-1 downto 0); +signal OPinteger : integer; +signal RESCOMP : std_logic_vector(Input_SZ-1 downto 0); + +begin + +RES <= REG; +OPinteger <= to_integer(signed(OP)); +RESCOMP <= std_logic_vector(to_signed(-OPinteger,Input_SZ)); + + process(clk,reset) + begin + + if(reset='0')then + REG <= (others => '0'); + elsif(clk'event and clk='1')then + + if(clr='1')then + REG <= (others => '0'); + elsif(TwoComp='1')then + REG <= RESCOMP; + else + REG <= OP; + end if; + + end if; + + end process; +end ar_TwoComplementer; \ No newline at end of file diff --git a/lib/staging/LPP/PLE/general_purpose/general_purpose.vhd b/lib/staging/LPP/PLE/general_purpose/general_purpose.vhd new file mode 100644 --- /dev/null +++ b/lib/staging/LPP/PLE/general_purpose/general_purpose.vhd @@ -0,0 +1,185 @@ +------------------------------------------------------------------------------ +-- This file is a part of the LPP VHDL IP LIBRARY +-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 3 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +------------------------------------------------------------------------------- +-- Author : Alexis Jeandet +-- Mail : alexis.jeandet@lpp.polytechnique.fr +---------------------------------------------------------------------------- +--UPDATE +------------------------------------------------------------------------------- +-- 14-03-2013 - Jean-christophe Pellion +-- ADD MUXN (a parametric multiplexor (N stage of MUX2)) +------------------------------------------------------------------------------- + +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; + +PACKAGE PLE_general_purpose IS + + COMPONENT Adder IS + GENERIC( + Input_SZ_A : INTEGER := 16; + Input_SZ_B : INTEGER := 16 + + ); + PORT( + clk : IN STD_LOGIC; + reset : IN STD_LOGIC; + clr : IN STD_LOGIC; + load : IN STD_LOGIC; + add : IN STD_LOGIC; + OP1 : IN STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0); + OP2 : IN STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0); + RES : OUT STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0) + ); + END COMPONENT; + + COMPONENT ALU IS + GENERIC( + Arith_en : INTEGER := 1; + Logic_en : INTEGER := 1; + Input_SZ_1 : INTEGER := 16; + Input_SZ_2 : INTEGER := 9; + COMP_EN : INTEGER := 0 -- 1 => No Comp + + ); + PORT( + clk : IN STD_LOGIC; + reset : IN STD_LOGIC; + ctrl : IN STD_LOGIC_VECTOR(2 downto 0); + comp : IN STD_LOGIC_VECTOR(1 downto 0); + OP1 : IN STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0); + OP2 : IN STD_LOGIC_VECTOR(Input_SZ_2-1 DOWNTO 0); + RES : OUT STD_LOGIC_VECTOR(Input_SZ_1+Input_SZ_2-1 DOWNTO 0) + ); + END COMPONENT; + +--------------------------------------------------------- +-------- // Sélection grace a l'entrée "ctrl" \\ -------- +--------------------------------------------------------- +Constant ctrl_IDLE : std_logic_vector(2 downto 0) := "000"; +Constant ctrl_MAC : std_logic_vector(2 downto 0) := "001"; +Constant ctrl_MULT : std_logic_vector(2 downto 0) := "010"; +Constant ctrl_ADD : std_logic_vector(2 downto 0) := "011"; +Constant ctrl_CLRMAC : std_logic_vector(2 downto 0) := "100"; + + +Constant IDLE_V0 : std_logic_vector(3 downto 0) := "0000"; +Constant MAC_op_V0 : std_logic_vector(3 downto 0) := "0001"; +Constant MULT_V0 : std_logic_vector(3 downto 0) := "0010"; +Constant ADD_V0 : std_logic_vector(3 downto 0) := "0011"; +Constant CLR_MAC_V0 : std_logic_vector(3 downto 0) := "0100"; +--------------------------------------------------------- + + COMPONENT MAC IS + GENERIC( + Input_SZ_A : INTEGER := 8; + Input_SZ_B : INTEGER := 8; + COMP_EN : INTEGER := 0 -- 1 => No Comp + ); + PORT( + clk : IN STD_LOGIC; + reset : IN STD_LOGIC; + clr_MAC : IN STD_LOGIC; + MAC_MUL_ADD : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + Comp_2C : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + OP1 : IN STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0); + OP2 : IN STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0); + RES : OUT STD_LOGIC_VECTOR(Input_SZ_A+Input_SZ_B-1 DOWNTO 0) + ); + END COMPONENT; + + COMPONENT TwoComplementer is + generic( + Input_SZ : integer := 16); + port( + clk : in std_logic; --! Horloge du composant + reset : in std_logic; --! Reset general du composant + clr : in std_logic; --! Un reset spécifique au programme + TwoComp : in std_logic; --! Autorise l'utilisation du complément + OP : in std_logic_vector(Input_SZ-1 downto 0); --! Opérande d'entrée + RES : out std_logic_vector(Input_SZ-1 downto 0) --! Résultat, opérande complémenté ou non + ); + end COMPONENT; + + COMPONENT MAC_CONTROLER IS + PORT( + ctrl : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + MULT : OUT STD_LOGIC; + ADD : OUT STD_LOGIC; + LOAD_ADDER : out std_logic; + MACMUX_sel : OUT STD_LOGIC; + MACMUX2_sel : OUT STD_LOGIC + ); + END COMPONENT; + + COMPONENT MAC_MUX IS + GENERIC( + Input_SZ_A : INTEGER := 16; + Input_SZ_B : INTEGER := 16 + + ); + PORT( + sel : IN STD_LOGIC; + INA1 : IN STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0); + INA2 : IN STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0); + INB1 : IN STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0); + INB2 : IN STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0); + OUTA : OUT STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0); + OUTB : OUT STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0) + ); + END COMPONENT; + + + COMPONENT MAC_MUX2 IS + GENERIC(Input_SZ : INTEGER := 16); + PORT( + sel : IN STD_LOGIC; + RES1 : IN STD_LOGIC_VECTOR(Input_SZ-1 DOWNTO 0); + RES2 : IN STD_LOGIC_VECTOR(Input_SZ-1 DOWNTO 0); + RES : OUT STD_LOGIC_VECTOR(Input_SZ-1 DOWNTO 0) + ); + END COMPONENT; + + + COMPONENT MAC_REG IS + GENERIC(size : INTEGER := 16); + PORT( + reset : IN STD_LOGIC; + clk : IN STD_LOGIC; + D : IN STD_LOGIC_VECTOR(size-1 DOWNTO 0); + Q : OUT STD_LOGIC_VECTOR(size-1 DOWNTO 0) + ); + END COMPONENT; + + COMPONENT Multiplier IS + GENERIC( + Input_SZ_A : INTEGER := 16; + Input_SZ_B : INTEGER := 16 + + ); + PORT( + clk : IN STD_LOGIC; + reset : IN STD_LOGIC; + mult : IN STD_LOGIC; + OP1 : IN STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0); + OP2 : IN STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0); + RES : OUT STD_LOGIC_VECTOR(Input_SZ_A+Input_SZ_B-1 DOWNTO 0) + ); + END COMPONENT; + +END;