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------------------------------------------------------------------------------
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-- This file is a part of the LPP VHDL IP LIBRARY
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-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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------------------------------------------------------------------------------
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-- Author : Martin Morlot
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-- Mail : martin.morlot@lpp.polytechnique.fr
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------------------------------------------------------------------------------
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library IEEE;
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use IEEE.std_logic_1164.all;
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use IEEE.numeric_std.all;
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library techmap;
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use techmap.gencomp.all;
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use work.FIFO_Config.all;
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use work.config.all;
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--! Programme de la FIFO
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entity Top_FIFO is
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port(
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clk,raz : in std_logic; --! Horloge et reset general du composant
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flag_RE : in std_logic; --! Flag, Demande la lecture de la m�moire
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flag_WR : in std_logic; --! Flag, Demande l'�criture dans la m�moire
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Data_in : in std_logic_vector(Data_sz-1 downto 0); --! Data en entr�e du composant
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full : out std_logic; --! Flag, M�moire pleine
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empty : out std_logic; --! Flag, M�moire vide
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Data_out : out std_logic_vector(Data_sz-1 downto 0) --! Data en sortie du composant
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);
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end Top_FIFO;
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--! @details Une m�moire SRAM de chez Gaisler est utilis�e,
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--! associ�e a deux fifos, une pour �crire l'autre pour lire cette m�moire
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architecture ar_Top_FIFO of Top_FIFO is
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component syncram_2p
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generic (tech : integer := 0; abits : integer := 6; dbits : integer := 8; sepclk : integer
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:= 0);
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port (
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rclk : in std_ulogic;
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renable : in std_ulogic;
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raddress : in std_logic_vector((abits -1) downto 0);
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dataout : out std_logic_vector((dbits -1) downto 0);
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wclk : in std_ulogic;
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write : in std_ulogic;
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waddress : in std_logic_vector((abits -1) downto 0);
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datain : in std_logic_vector((dbits -1) downto 0));
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end component;
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signal RAD : integer range 0 to addr_max_int;
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signal WAD : integer range 0 to addr_max_int;
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signal Raddr : std_logic_vector(addr_sz-1 downto 0);
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signal Waddr : std_logic_vector(addr_sz-1 downto 0);
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begin
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SRAM : syncram_2p
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generic map(CFG_MEMTECH,addr_sz,Data_sz)
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port map(clk,flag_RE,Raddr,Data_out,clk,flag_WR,Waddr,Data_in);
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WR : entity work.Fifo_Write
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port map(clk,raz,flag_WR,RAD,full,WAD,Waddr);
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RE : entity work.Fifo_Read
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port map(clk,raz,flag_RE,WAD,empty,RAD,Raddr);
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end ar_Top_FIFO;
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