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lpp_fifo added
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1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 ------------------------------------------------------------------------------
19 -- Author : Martin Morlot
20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 ------------------------------------------------------------------------------
22 library ieee;
23 use ieee.std_logic_1164.all;
24 library grlib;
25 use grlib.amba.all;
26 use grlib.stdlib.all;
27 use grlib.devices.all;
28 library lpp;
29 use lpp.lpp_amba.all;
30 use lpp.apb_devices_list.all;
31 use lpp.lpp_fifo.all;
32
33 --! Driver APB, va faire le lien entre l'IP VHDL de la FIFO et le bus Amba
34
35 entity APB_FIFO is
36 generic (
37 pindex : integer := 0;
38 paddr : integer := 0;
39 pmask : integer := 16#fff#;
40 pirq : integer := 0;
41 abits : integer := 8);
42 port (
43 clk : in std_logic; --! Horloge du composant
44 rst : in std_logic; --! Reset general du composant
45 apbi : in apb_slv_in_type; --! Registre de gestion des entr�es du bus
46 apbo : out apb_slv_out_type --! Registre de gestion des sorties du bus
47 );
48 end APB_FIFO;
49
50
51 architecture ar_APB_FIFO of APB_FIFO is
52
53 constant REVISION : integer := 1;
54
55 constant pconfig : apb_config_type := (
56 0 => ahb_device_reg (VENDOR_LPP, LPP_FIFO, 0, REVISION, 0),
57 1 => apb_iobar(paddr, pmask));
58
59 type FIFO_ctrlr_Reg is record
60 FIFO_Cfg : std_logic_vector(3 downto 0);
61 FIFO_DataW : std_logic_vector(15 downto 0);
62 FIFO_DataR : std_logic_vector(15 downto 0);
63 end record;
64
65 signal Rec : FIFO_ctrlr_Reg;
66 signal Rdata : std_logic_vector(31 downto 0);
67
68 signal flag_RE : std_logic;
69 signal flag_WR : std_logic;
70 signal full : std_logic;
71 signal empty : std_logic;
72 begin
73
74 flag_RE <= Rec.FIFO_Cfg(0);
75 flag_WR <= Rec.FIFO_Cfg(1);
76 Rec.FIFO_Cfg(2) <= empty;
77 Rec.FIFO_Cfg(3) <= full;
78
79 CONVERTER : entity Work.Top_FIFO
80 port map(clk,rst,flag_RE,flag_WR,Rec.FIFO_DataW,full,empty,Rec.FIFO_DataR);
81
82
83 process(rst,clk)
84 begin
85 if(rst='0')then
86 Rec.FIFO_DataW <= (others => '0');
87
88 elsif(clk'event and clk='1')then
89
90
91 --APB Write OP
92 if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then
93 case apbi.paddr(abits-1 downto 2) is
94 when "000000" =>
95 Rec.FIFO_Cfg(0) <= apbi.pwdata(0);
96 Rec.FIFO_Cfg(1) <= apbi.pwdata(4);
97 when "000001" =>
98 Rec.FIFO_DataW <= apbi.pwdata(15 downto 0);
99 when others =>
100 null;
101 end case;
102 end if;
103
104 --APB READ OP
105 if (apbi.psel(pindex) and (not apbi.pwrite)) = '1' then
106 case apbi.paddr(abits-1 downto 2) is
107 when "000000" =>
108 Rdata(3 downto 0) <= "000" & Rec.FIFO_Cfg(0);
109 Rdata(7 downto 4) <= "000" & Rec.FIFO_Cfg(1);
110 Rdata(11 downto 8) <= "000" & Rec.FIFO_Cfg(2);
111 Rdata(15 downto 12) <= "000" & Rec.FIFO_Cfg(3);
112 Rdata(31 downto 16) <= X"AAAA";
113 when "000001" =>
114 Rdata(31 downto 16) <= X"AAAA";
115 Rdata(15 downto 0) <= Rec.FIFO_DataW;
116 when "000010" =>
117 Rdata(31 downto 16) <= X"AAAA";
118 Rdata(15 downto 0) <= Rec.FIFO_DataR;
119 when others =>
120 Rdata <= (others => '0');
121 end case;
122 end if;
123
124 end if;
125 apbo.pconfig <= pconfig;
126 end process;
127
128 apbo.prdata <= Rdata when apbi.penable = '1';
129 end ar_APB_FIFO;
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1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 ------------------------------------------------------------------------------
19 -- Author : Martin Morlot
20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 ------------------------------------------------------------------------------
22 library IEEE;
23 use IEEE.std_logic_1164.all;
24 use IEEE.numeric_std.all;
25
26 Package FIFO_Config is
27
28 --===========================================================|
29 --================= Generic de Config =======================|
30 --===========================================================|
31 constant Data_sz : integer := 16;
32 constant addr_sz : integer := 8;
33 constant addr_max_int : integer := 256;
34
35
36 end; No newline at end of file
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1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 ------------------------------------------------------------------------------
19 -- Author : Martin Morlot
20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 ------------------------------------------------------------------------------
22 library IEEE;
23 use IEEE.std_logic_1164.all;
24 use IEEE.numeric_std.all;
25 use work.FIFO_Config.all;
26
27 --! Programme de la FIFO de lecture
28
29 entity Fifo_Read is
30 port(
31 clk,raz : in std_logic; --! Horloge et reset general du composant
32 flag_RE : in std_logic; --! Flag, Demande la lecture de la m�moire
33 WAD : in integer range 0 to addr_max_int; --! Adresse du registre d'�criture dans la m�moire (forme enti�re)
34 empty : out std_logic; --! Flag, M�moire vide
35 RAD : out integer range 0 to addr_max_int; --! Adresse du registre de lecture de la m�moire (forme enti�re)
36 Raddr : out std_logic_vector(addr_sz-1 downto 0) --! Adresse du registre de lecture de la m�moire (forme vectorielle)
37 );
38 end Fifo_Read;
39
40 --! @details En aval de la SRAM Gaisler
41
42 architecture ar_Fifo_Read of Fifo_Read is
43
44 signal Rad_int : integer range 0 to addr_max_int;
45
46 begin
47 process (clk,raz)
48 begin
49 if(raz='0')then
50 Rad_int <= 0;
51 empty <= '1';
52
53 elsif(clk' event and clk='1')then
54 if(flag_RE='1')then
55 if(Rad_int=addr_max_int)then
56 Rad_int <= 0;
57 else
58 Rad_int <= Rad_int+1;
59 end if;
60 end if;
61 if(Rad_int=WAD)then
62 empty <= '1';
63 else
64 empty <= '0';
65 end if;
66 end if;
67 end process;
68
69 RAD <= Rad_int;
70 Raddr <= std_logic_vector(to_unsigned(Rad_int,addr_sz));
71 end ar_Fifo_Read; No newline at end of file
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1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 ------------------------------------------------------------------------------
19 -- Author : Martin Morlot
20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 ------------------------------------------------------------------------------
22 library IEEE;
23 use IEEE.std_logic_1164.all;
24 use IEEE.numeric_std.all;
25 use work.FIFO_Config.all;
26
27 --! Programme de la FIFO d'�criture
28
29 entity Fifo_Write is
30 port(
31 clk,raz : in std_logic; --! Horloge et reset general du composant
32 flag_WR : in std_logic; --! Flag, Demande l'�criture dans la m�moire
33 RAD : in integer range 0 to addr_max_int; --! Adresse du registre de lecture de la m�moire (forme enti�re)
34 full : out std_logic; --! Flag, M�moire pleine
35 WAD : out integer range 0 to addr_max_int; --! Adresse du registre d'�criture dans la m�moire (forme enti�re)
36 Waddr : out std_logic_vector(addr_sz-1 downto 0) --! Adresse du registre d'�criture dans la m�moire (forme vectorielle)
37 );
38 end Fifo_Write;
39
40 --! @details En amont de la SRAM Gaisler
41
42 architecture ar_Fifo_Write of Fifo_Write is
43
44 signal Wad_int : integer range 0 to addr_max_int;
45 signal full_int : std_logic;
46
47 begin
48 process (clk,raz)
49 begin
50 if(raz='0')then
51 Wad_int <= 0;
52 full_int <= '0';
53
54 elsif(clk' event and clk='1')then
55 if(flag_WR='1')then
56 if(Wad_int=addr_max_int)then
57 Wad_int <= 0;
58 elsif(full_int='1')then
59 Wad_int <= Wad_int;
60 else
61 Wad_int <= Wad_int+1;
62 end if;
63 end if;
64 if(Wad_int=RAD-1 or (Wad_int=addr_max_int and RAD=0))then
65 full_int <= '1';
66 else
67 full_int <= '0';
68 end if;
69 end if;
70 end process;
71
72 full <= full_int;
73 WAD <= Wad_int;
74 Waddr <= std_logic_vector(to_unsigned(Wad_int,addr_sz));
75 end ar_Fifo_Write; No newline at end of file
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1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 ------------------------------------------------------------------------------
19 -- Author : Martin Morlot
20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 ------------------------------------------------------------------------------
22 library IEEE;
23 use IEEE.std_logic_1164.all;
24 use IEEE.numeric_std.all;
25 library techmap;
26 use techmap.gencomp.all;
27 use work.FIFO_Config.all;
28 use work.config.all;
29
30 --! Programme de la FIFO
31
32 entity Top_FIFO is
33 port(
34 clk,raz : in std_logic; --! Horloge et reset general du composant
35 flag_RE : in std_logic; --! Flag, Demande la lecture de la m�moire
36 flag_WR : in std_logic; --! Flag, Demande l'�criture dans la m�moire
37 Data_in : in std_logic_vector(Data_sz-1 downto 0); --! Data en entr�e du composant
38 full : out std_logic; --! Flag, M�moire pleine
39 empty : out std_logic; --! Flag, M�moire vide
40 Data_out : out std_logic_vector(Data_sz-1 downto 0) --! Data en sortie du composant
41 );
42 end Top_FIFO;
43
44 --! @details Une m�moire SRAM de chez Gaisler est utilis�e,
45 --! associ�e a deux fifos, une pour �crire l'autre pour lire cette m�moire
46
47 architecture ar_Top_FIFO of Top_FIFO is
48
49 component syncram_2p
50 generic (tech : integer := 0; abits : integer := 6; dbits : integer := 8; sepclk : integer
51 := 0);
52 port (
53 rclk : in std_ulogic;
54 renable : in std_ulogic;
55 raddress : in std_logic_vector((abits -1) downto 0);
56 dataout : out std_logic_vector((dbits -1) downto 0);
57 wclk : in std_ulogic;
58 write : in std_ulogic;
59 waddress : in std_logic_vector((abits -1) downto 0);
60 datain : in std_logic_vector((dbits -1) downto 0));
61 end component;
62
63 signal RAD : integer range 0 to addr_max_int;
64 signal WAD : integer range 0 to addr_max_int;
65 signal Raddr : std_logic_vector(addr_sz-1 downto 0);
66 signal Waddr : std_logic_vector(addr_sz-1 downto 0);
67
68 begin
69
70 SRAM : syncram_2p
71 generic map(CFG_MEMTECH,addr_sz,Data_sz)
72 port map(clk,flag_RE,Raddr,Data_out,clk,flag_WR,Waddr,Data_in);
73
74
75 WR : entity work.Fifo_Write
76 port map(clk,raz,flag_WR,RAD,full,WAD,Waddr);
77
78
79 RE : entity work.Fifo_Read
80 port map(clk,raz,flag_RE,WAD,empty,RAD,Raddr);
81
82
83 end ar_Top_FIFO; No newline at end of file
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@@ -0,0 +1,90
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 ------------------------------------------------------------------------------
19 -- Author : Martin Morlot
20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 ------------------------------------------------------------------------------
22 library ieee;
23 use ieee.std_logic_1164.all;
24 library grlib;
25 use grlib.amba.all;
26 use std.textio.all;
27 library lpp;
28 use lpp.lpp_amba.all;
29 use work.FIFO_Config.all;
30
31 --! Package contenant tous les programmes qui forment le composant int�gr� dans le l�on
32
33 package lpp_fifo is
34
35 component APB_FIFO is
36 generic (
37 pindex : integer := 0;
38 paddr : integer := 0;
39 pmask : integer := 16#fff#;
40 pirq : integer := 0;
41 abits : integer := 8);
42 port (
43 clk : in std_logic;
44 rst : in std_logic;
45 apbi : in apb_slv_in_type;
46 apbo : out apb_slv_out_type
47 );
48 end component;
49
50
51 component Top_FIFO is
52 port(
53 clk : in std_logic;
54 raz : in std_logic;
55 flag_RE : in std_logic;
56 flag_WR : in std_logic;
57 Data_in : in std_logic_vector(Data_sz-1 downto 0);
58 full : out std_logic;
59 empty : out std_logic;
60 Data_out : out std_logic_vector(Data_sz-1 downto 0)
61 );
62 end component;
63
64
65 component Fifo_Read is
66 port(
67 clk : in std_logic;
68 raz : in std_logic;
69 flag_RE : in std_logic;
70 WAD : in integer range 0 to addr_max_int;
71 empty : out std_logic;
72 RAD : out integer range 0 to addr_max_int;
73 Raddr : out std_logic_vector(addr_sz-1 downto 0)
74 );
75 end component;
76
77
78 component Fifo_Write is
79 port(
80 clk : in std_logic;
81 raz : in std_logic;
82 flag_WR : in std_logic;
83 RAD : in integer range 0 to addr_max_int;
84 full : out std_logic;
85 WAD : out integer range 0 to addr_max_int;
86 Waddr : out std_logic_vector(addr_sz-1 downto 0)
87 );
88 end component;
89
90 end;
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@@ -10,3 +10,4 device LPP_CNA 7
10 device LPP_APB_ADC 8
10 device LPP_APB_ADC 8
11 device LPP_CHENILLARD 9
11 device LPP_CHENILLARD 9
12 device LPP_IIR_CEL_FILTER 10
12 device LPP_IIR_CEL_FILTER 10
13 device LPP_FIFO 11
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