diff --git a/APB_DEVICES/apb_devices_list.txt b/APB_DEVICES/apb_devices_list.txt --- a/APB_DEVICES/apb_devices_list.txt +++ b/APB_DEVICES/apb_devices_list.txt @@ -10,3 +10,4 @@ device LPP_CNA 7 device LPP_APB_ADC 8 device LPP_CHENILLARD 9 device LPP_IIR_CEL_FILTER 10 +device LPP_FIFO 11 diff --git a/lib/lpp/lpp_fifo/APB_FIFO.vhd b/lib/lpp/lpp_fifo/APB_FIFO.vhd new file mode 100644 --- /dev/null +++ b/lib/lpp/lpp_fifo/APB_FIFO.vhd @@ -0,0 +1,129 @@ +------------------------------------------------------------------------------ +-- This file is a part of the LPP VHDL IP LIBRARY +-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 3 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +------------------------------------------------------------------------------ +-- Author : Martin Morlot +-- Mail : martin.morlot@lpp.polytechnique.fr +------------------------------------------------------------------------------ +library ieee; +use ieee.std_logic_1164.all; +library grlib; +use grlib.amba.all; +use grlib.stdlib.all; +use grlib.devices.all; +library lpp; +use lpp.lpp_amba.all; +use lpp.apb_devices_list.all; +use lpp.lpp_fifo.all; + +--! Driver APB, va faire le lien entre l'IP VHDL de la FIFO et le bus Amba + +entity APB_FIFO is + generic ( + pindex : integer := 0; + paddr : integer := 0; + pmask : integer := 16#fff#; + pirq : integer := 0; + abits : integer := 8); + port ( + clk : in std_logic; --! Horloge du composant + rst : in std_logic; --! Reset general du composant + apbi : in apb_slv_in_type; --! Registre de gestion des entrées du bus + apbo : out apb_slv_out_type --! Registre de gestion des sorties du bus + ); +end APB_FIFO; + + +architecture ar_APB_FIFO of APB_FIFO is + +constant REVISION : integer := 1; + +constant pconfig : apb_config_type := ( + 0 => ahb_device_reg (VENDOR_LPP, LPP_FIFO, 0, REVISION, 0), + 1 => apb_iobar(paddr, pmask)); + +type FIFO_ctrlr_Reg is record + FIFO_Cfg : std_logic_vector(3 downto 0); + FIFO_DataW : std_logic_vector(15 downto 0); + FIFO_DataR : std_logic_vector(15 downto 0); +end record; + +signal Rec : FIFO_ctrlr_Reg; +signal Rdata : std_logic_vector(31 downto 0); + +signal flag_RE : std_logic; +signal flag_WR : std_logic; +signal full : std_logic; +signal empty : std_logic; +begin + +flag_RE <= Rec.FIFO_Cfg(0); +flag_WR <= Rec.FIFO_Cfg(1); +Rec.FIFO_Cfg(2) <= empty; +Rec.FIFO_Cfg(3) <= full; + + CONVERTER : entity Work.Top_FIFO + port map(clk,rst,flag_RE,flag_WR,Rec.FIFO_DataW,full,empty,Rec.FIFO_DataR); + + + process(rst,clk) + begin + if(rst='0')then + Rec.FIFO_DataW <= (others => '0'); + + elsif(clk'event and clk='1')then + + + --APB Write OP + if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then + case apbi.paddr(abits-1 downto 2) is + when "000000" => + Rec.FIFO_Cfg(0) <= apbi.pwdata(0); + Rec.FIFO_Cfg(1) <= apbi.pwdata(4); + when "000001" => + Rec.FIFO_DataW <= apbi.pwdata(15 downto 0); + when others => + null; + end case; + end if; + + --APB READ OP + if (apbi.psel(pindex) and (not apbi.pwrite)) = '1' then + case apbi.paddr(abits-1 downto 2) is + when "000000" => + Rdata(3 downto 0) <= "000" & Rec.FIFO_Cfg(0); + Rdata(7 downto 4) <= "000" & Rec.FIFO_Cfg(1); + Rdata(11 downto 8) <= "000" & Rec.FIFO_Cfg(2); + Rdata(15 downto 12) <= "000" & Rec.FIFO_Cfg(3); + Rdata(31 downto 16) <= X"AAAA"; + when "000001" => + Rdata(31 downto 16) <= X"AAAA"; + Rdata(15 downto 0) <= Rec.FIFO_DataW; + when "000010" => + Rdata(31 downto 16) <= X"AAAA"; + Rdata(15 downto 0) <= Rec.FIFO_DataR; + when others => + Rdata <= (others => '0'); + end case; + end if; + + end if; + apbo.pconfig <= pconfig; + end process; + +apbo.prdata <= Rdata when apbi.penable = '1'; +end ar_APB_FIFO; diff --git a/lib/lpp/lpp_fifo/FIFO_Config.vhd b/lib/lpp/lpp_fifo/FIFO_Config.vhd new file mode 100644 --- /dev/null +++ b/lib/lpp/lpp_fifo/FIFO_Config.vhd @@ -0,0 +1,36 @@ +------------------------------------------------------------------------------ +-- This file is a part of the LPP VHDL IP LIBRARY +-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 3 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +------------------------------------------------------------------------------ +-- Author : Martin Morlot +-- Mail : martin.morlot@lpp.polytechnique.fr +------------------------------------------------------------------------------ +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +Package FIFO_Config is + +--===========================================================| +--================= Generic de Config =======================| +--===========================================================| +constant Data_sz : integer := 16; +constant addr_sz : integer := 8; +constant addr_max_int : integer := 256; + + +end; \ No newline at end of file diff --git a/lib/lpp/lpp_fifo/Fifo_Read.vhd b/lib/lpp/lpp_fifo/Fifo_Read.vhd new file mode 100644 --- /dev/null +++ b/lib/lpp/lpp_fifo/Fifo_Read.vhd @@ -0,0 +1,71 @@ +------------------------------------------------------------------------------ +-- This file is a part of the LPP VHDL IP LIBRARY +-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 3 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +------------------------------------------------------------------------------ +-- Author : Martin Morlot +-- Mail : martin.morlot@lpp.polytechnique.fr +------------------------------------------------------------------------------ +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; +use work.FIFO_Config.all; + +--! Programme de la FIFO de lecture + +entity Fifo_Read is +port( + clk,raz : in std_logic; --! Horloge et reset general du composant + flag_RE : in std_logic; --! Flag, Demande la lecture de la mémoire + WAD : in integer range 0 to addr_max_int; --! Adresse du registre d'écriture dans la mémoire (forme entière) + empty : out std_logic; --! Flag, Mémoire vide + RAD : out integer range 0 to addr_max_int; --! Adresse du registre de lecture de la mémoire (forme entière) + Raddr : out std_logic_vector(addr_sz-1 downto 0) --! Adresse du registre de lecture de la mémoire (forme vectorielle) + ); +end Fifo_Read; + +--! @details En aval de la SRAM Gaisler + +architecture ar_Fifo_Read of Fifo_Read is + +signal Rad_int : integer range 0 to addr_max_int; + +begin + process (clk,raz) + begin + if(raz='0')then + Rad_int <= 0; + empty <= '1'; + + elsif(clk' event and clk='1')then + if(flag_RE='1')then + if(Rad_int=addr_max_int)then + Rad_int <= 0; + else + Rad_int <= Rad_int+1; + end if; + end if; + if(Rad_int=WAD)then + empty <= '1'; + else + empty <= '0'; + end if; + end if; + end process; + +RAD <= Rad_int; +Raddr <= std_logic_vector(to_unsigned(Rad_int,addr_sz)); +end ar_Fifo_Read; \ No newline at end of file diff --git a/lib/lpp/lpp_fifo/Fifo_Write.vhd b/lib/lpp/lpp_fifo/Fifo_Write.vhd new file mode 100644 --- /dev/null +++ b/lib/lpp/lpp_fifo/Fifo_Write.vhd @@ -0,0 +1,75 @@ +------------------------------------------------------------------------------ +-- This file is a part of the LPP VHDL IP LIBRARY +-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 3 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +------------------------------------------------------------------------------ +-- Author : Martin Morlot +-- Mail : martin.morlot@lpp.polytechnique.fr +------------------------------------------------------------------------------ +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; +use work.FIFO_Config.all; + +--! Programme de la FIFO d'écriture + +entity Fifo_Write is +port( + clk,raz : in std_logic; --! Horloge et reset general du composant + flag_WR : in std_logic; --! Flag, Demande l'écriture dans la mémoire + RAD : in integer range 0 to addr_max_int; --! Adresse du registre de lecture de la mémoire (forme entière) + full : out std_logic; --! Flag, Mémoire pleine + WAD : out integer range 0 to addr_max_int; --! Adresse du registre d'écriture dans la mémoire (forme entière) + Waddr : out std_logic_vector(addr_sz-1 downto 0) --! Adresse du registre d'écriture dans la mémoire (forme vectorielle) + ); +end Fifo_Write; + +--! @details En amont de la SRAM Gaisler + +architecture ar_Fifo_Write of Fifo_Write is + +signal Wad_int : integer range 0 to addr_max_int; +signal full_int : std_logic; + +begin + process (clk,raz) + begin + if(raz='0')then + Wad_int <= 0; + full_int <= '0'; + + elsif(clk' event and clk='1')then + if(flag_WR='1')then + if(Wad_int=addr_max_int)then + Wad_int <= 0; + elsif(full_int='1')then + Wad_int <= Wad_int; + else + Wad_int <= Wad_int+1; + end if; + end if; + if(Wad_int=RAD-1 or (Wad_int=addr_max_int and RAD=0))then + full_int <= '1'; + else + full_int <= '0'; + end if; + end if; + end process; + +full <= full_int; +WAD <= Wad_int; +Waddr <= std_logic_vector(to_unsigned(Wad_int,addr_sz)); +end ar_Fifo_Write; \ No newline at end of file diff --git a/lib/lpp/lpp_fifo/Top_FIFO.vhd b/lib/lpp/lpp_fifo/Top_FIFO.vhd new file mode 100644 --- /dev/null +++ b/lib/lpp/lpp_fifo/Top_FIFO.vhd @@ -0,0 +1,83 @@ +------------------------------------------------------------------------------ +-- This file is a part of the LPP VHDL IP LIBRARY +-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 3 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +------------------------------------------------------------------------------ +-- Author : Martin Morlot +-- Mail : martin.morlot@lpp.polytechnique.fr +------------------------------------------------------------------------------ +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; +library techmap; +use techmap.gencomp.all; +use work.FIFO_Config.all; +use work.config.all; + +--! Programme de la FIFO + +entity Top_FIFO is + port( + clk,raz : in std_logic; --! Horloge et reset general du composant + flag_RE : in std_logic; --! Flag, Demande la lecture de la mémoire + flag_WR : in std_logic; --! Flag, Demande l'écriture dans la mémoire + Data_in : in std_logic_vector(Data_sz-1 downto 0); --! Data en entrée du composant + full : out std_logic; --! Flag, Mémoire pleine + empty : out std_logic; --! Flag, Mémoire vide + Data_out : out std_logic_vector(Data_sz-1 downto 0) --! Data en sortie du composant + ); +end Top_FIFO; + +--! @details Une mémoire SRAM de chez Gaisler est utilisée, +--! associée a deux fifos, une pour écrire l'autre pour lire cette mémoire + +architecture ar_Top_FIFO of Top_FIFO is + +component syncram_2p + generic (tech : integer := 0; abits : integer := 6; dbits : integer := 8; sepclk : integer + := 0); + port ( + rclk : in std_ulogic; + renable : in std_ulogic; + raddress : in std_logic_vector((abits -1) downto 0); + dataout : out std_logic_vector((dbits -1) downto 0); + wclk : in std_ulogic; + write : in std_ulogic; + waddress : in std_logic_vector((abits -1) downto 0); + datain : in std_logic_vector((dbits -1) downto 0)); +end component; + +signal RAD : integer range 0 to addr_max_int; +signal WAD : integer range 0 to addr_max_int; +signal Raddr : std_logic_vector(addr_sz-1 downto 0); +signal Waddr : std_logic_vector(addr_sz-1 downto 0); + +begin + + SRAM : syncram_2p + generic map(CFG_MEMTECH,addr_sz,Data_sz) + port map(clk,flag_RE,Raddr,Data_out,clk,flag_WR,Waddr,Data_in); + + + WR : entity work.Fifo_Write + port map(clk,raz,flag_WR,RAD,full,WAD,Waddr); + + + RE : entity work.Fifo_Read + port map(clk,raz,flag_RE,WAD,empty,RAD,Raddr); + + +end ar_Top_FIFO; \ No newline at end of file diff --git a/lib/lpp/lpp_fifo/lpp_fifo.vhd b/lib/lpp/lpp_fifo/lpp_fifo.vhd new file mode 100644 --- /dev/null +++ b/lib/lpp/lpp_fifo/lpp_fifo.vhd @@ -0,0 +1,90 @@ +------------------------------------------------------------------------------ +-- This file is a part of the LPP VHDL IP LIBRARY +-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 3 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +------------------------------------------------------------------------------ +-- Author : Martin Morlot +-- Mail : martin.morlot@lpp.polytechnique.fr +------------------------------------------------------------------------------ +library ieee; +use ieee.std_logic_1164.all; +library grlib; +use grlib.amba.all; +use std.textio.all; +library lpp; +use lpp.lpp_amba.all; +use work.FIFO_Config.all; + +--! Package contenant tous les programmes qui forment le composant intégré dans le léon + +package lpp_fifo is + +component APB_FIFO is + generic ( + pindex : integer := 0; + paddr : integer := 0; + pmask : integer := 16#fff#; + pirq : integer := 0; + abits : integer := 8); + port ( + clk : in std_logic; + rst : in std_logic; + apbi : in apb_slv_in_type; + apbo : out apb_slv_out_type + ); +end component; + + +component Top_FIFO is + port( + clk : in std_logic; + raz : in std_logic; + flag_RE : in std_logic; + flag_WR : in std_logic; + Data_in : in std_logic_vector(Data_sz-1 downto 0); + full : out std_logic; + empty : out std_logic; + Data_out : out std_logic_vector(Data_sz-1 downto 0) + ); +end component; + + +component Fifo_Read is + port( + clk : in std_logic; + raz : in std_logic; + flag_RE : in std_logic; + WAD : in integer range 0 to addr_max_int; + empty : out std_logic; + RAD : out integer range 0 to addr_max_int; + Raddr : out std_logic_vector(addr_sz-1 downto 0) + ); +end component; + + +component Fifo_Write is + port( + clk : in std_logic; + raz : in std_logic; + flag_WR : in std_logic; + RAD : in integer range 0 to addr_max_int; + full : out std_logic; + WAD : out integer range 0 to addr_max_int; + Waddr : out std_logic_vector(addr_sz-1 downto 0) + ); +end component; + +end;