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1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 ------------------------------------------------------------------------------
19 -- Author : Martin Morlot
20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 ------------------------------------------------------------------------------
22 library ieee;
23 use ieee.std_logic_1164.all;
24 library grlib;
25 use grlib.amba.all;
26 use grlib.stdlib.all;
27 use grlib.devices.all;
28 library lpp;
29 use lpp.lpp_amba.all;
30 use lpp.apb_devices_list.all;
31 use lpp.lpp_fifo.all;
32
33 --! Driver APB, va faire le lien entre l'IP VHDL de la FIFO et le bus Amba
34
35 entity APB_FIFO is
36 generic (
37 pindex : integer := 0;
38 paddr : integer := 0;
39 pmask : integer := 16#fff#;
40 pirq : integer := 0;
41 abits : integer := 8);
42 port (
43 clk : in std_logic; --! Horloge du composant
44 rst : in std_logic; --! Reset general du composant
45 apbi : in apb_slv_in_type; --! Registre de gestion des entr�es du bus
46 apbo : out apb_slv_out_type --! Registre de gestion des sorties du bus
47 );
48 end APB_FIFO;
49
50
51 architecture ar_APB_FIFO of APB_FIFO is
52
53 constant REVISION : integer := 1;
54
55 constant pconfig : apb_config_type := (
56 0 => ahb_device_reg (VENDOR_LPP, LPP_FIFO, 0, REVISION, 0),
57 1 => apb_iobar(paddr, pmask));
58
59 type FIFO_ctrlr_Reg is record
60 FIFO_Cfg : std_logic_vector(3 downto 0);
61 FIFO_DataW : std_logic_vector(15 downto 0);
62 FIFO_DataR : std_logic_vector(15 downto 0);
63 end record;
64
65 signal Rec : FIFO_ctrlr_Reg;
66 signal Rdata : std_logic_vector(31 downto 0);
67
68 signal flag_RE : std_logic;
69 signal flag_WR : std_logic;
70 signal full : std_logic;
71 signal empty : std_logic;
72 begin
73
74 flag_RE <= Rec.FIFO_Cfg(0);
75 flag_WR <= Rec.FIFO_Cfg(1);
76 Rec.FIFO_Cfg(2) <= empty;
77 Rec.FIFO_Cfg(3) <= full;
78
79 CONVERTER : entity Work.Top_FIFO
80 port map(clk,rst,flag_RE,flag_WR,Rec.FIFO_DataW,full,empty,Rec.FIFO_DataR);
81
82
83 process(rst,clk)
84 begin
85 if(rst='0')then
86 Rec.FIFO_DataW <= (others => '0');
87
88 elsif(clk'event and clk='1')then
89
90
91 --APB Write OP
92 if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then
93 case apbi.paddr(abits-1 downto 2) is
94 when "000000" =>
95 Rec.FIFO_Cfg(0) <= apbi.pwdata(0);
96 Rec.FIFO_Cfg(1) <= apbi.pwdata(4);
97 when "000001" =>
98 Rec.FIFO_DataW <= apbi.pwdata(15 downto 0);
99 when others =>
100 null;
101 end case;
102 end if;
103
104 --APB READ OP
105 if (apbi.psel(pindex) and (not apbi.pwrite)) = '1' then
106 case apbi.paddr(abits-1 downto 2) is
107 when "000000" =>
108 Rdata(3 downto 0) <= "000" & Rec.FIFO_Cfg(0);
109 Rdata(7 downto 4) <= "000" & Rec.FIFO_Cfg(1);
110 Rdata(11 downto 8) <= "000" & Rec.FIFO_Cfg(2);
111 Rdata(15 downto 12) <= "000" & Rec.FIFO_Cfg(3);
112 Rdata(31 downto 16) <= X"AAAA";
113 when "000001" =>
114 Rdata(31 downto 16) <= X"AAAA";
115 Rdata(15 downto 0) <= Rec.FIFO_DataW;
116 when "000010" =>
117 Rdata(31 downto 16) <= X"AAAA";
118 Rdata(15 downto 0) <= Rec.FIFO_DataR;
119 when others =>
120 Rdata <= (others => '0');
121 end case;
122 end if;
123
124 end if;
125 apbo.pconfig <= pconfig;
126 end process;
127
128 apbo.prdata <= Rdata when apbi.penable = '1';
129 end ar_APB_FIFO;
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1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 ------------------------------------------------------------------------------
19 -- Author : Martin Morlot
20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 ------------------------------------------------------------------------------
22 library IEEE;
23 use IEEE.std_logic_1164.all;
24 use IEEE.numeric_std.all;
25
26 Package FIFO_Config is
27
28 --===========================================================|
29 --================= Generic de Config =======================|
30 --===========================================================|
31 constant Data_sz : integer := 16;
32 constant addr_sz : integer := 8;
33 constant addr_max_int : integer := 256;
34
35
36 end; No newline at end of file
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1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 ------------------------------------------------------------------------------
19 -- Author : Martin Morlot
20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 ------------------------------------------------------------------------------
22 library IEEE;
23 use IEEE.std_logic_1164.all;
24 use IEEE.numeric_std.all;
25 use work.FIFO_Config.all;
26
27 --! Programme de la FIFO de lecture
28
29 entity Fifo_Read is
30 port(
31 clk,raz : in std_logic; --! Horloge et reset general du composant
32 flag_RE : in std_logic; --! Flag, Demande la lecture de la m�moire
33 WAD : in integer range 0 to addr_max_int; --! Adresse du registre d'�criture dans la m�moire (forme enti�re)
34 empty : out std_logic; --! Flag, M�moire vide
35 RAD : out integer range 0 to addr_max_int; --! Adresse du registre de lecture de la m�moire (forme enti�re)
36 Raddr : out std_logic_vector(addr_sz-1 downto 0) --! Adresse du registre de lecture de la m�moire (forme vectorielle)
37 );
38 end Fifo_Read;
39
40 --! @details En aval de la SRAM Gaisler
41
42 architecture ar_Fifo_Read of Fifo_Read is
43
44 signal Rad_int : integer range 0 to addr_max_int;
45
46 begin
47 process (clk,raz)
48 begin
49 if(raz='0')then
50 Rad_int <= 0;
51 empty <= '1';
52
53 elsif(clk' event and clk='1')then
54 if(flag_RE='1')then
55 if(Rad_int=addr_max_int)then
56 Rad_int <= 0;
57 else
58 Rad_int <= Rad_int+1;
59 end if;
60 end if;
61 if(Rad_int=WAD)then
62 empty <= '1';
63 else
64 empty <= '0';
65 end if;
66 end if;
67 end process;
68
69 RAD <= Rad_int;
70 Raddr <= std_logic_vector(to_unsigned(Rad_int,addr_sz));
71 end ar_Fifo_Read; No newline at end of file
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1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 ------------------------------------------------------------------------------
19 -- Author : Martin Morlot
20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 ------------------------------------------------------------------------------
22 library IEEE;
23 use IEEE.std_logic_1164.all;
24 use IEEE.numeric_std.all;
25 use work.FIFO_Config.all;
26
27 --! Programme de la FIFO d'�criture
28
29 entity Fifo_Write is
30 port(
31 clk,raz : in std_logic; --! Horloge et reset general du composant
32 flag_WR : in std_logic; --! Flag, Demande l'�criture dans la m�moire
33 RAD : in integer range 0 to addr_max_int; --! Adresse du registre de lecture de la m�moire (forme enti�re)
34 full : out std_logic; --! Flag, M�moire pleine
35 WAD : out integer range 0 to addr_max_int; --! Adresse du registre d'�criture dans la m�moire (forme enti�re)
36 Waddr : out std_logic_vector(addr_sz-1 downto 0) --! Adresse du registre d'�criture dans la m�moire (forme vectorielle)
37 );
38 end Fifo_Write;
39
40 --! @details En amont de la SRAM Gaisler
41
42 architecture ar_Fifo_Write of Fifo_Write is
43
44 signal Wad_int : integer range 0 to addr_max_int;
45 signal full_int : std_logic;
46
47 begin
48 process (clk,raz)
49 begin
50 if(raz='0')then
51 Wad_int <= 0;
52 full_int <= '0';
53
54 elsif(clk' event and clk='1')then
55 if(flag_WR='1')then
56 if(Wad_int=addr_max_int)then
57 Wad_int <= 0;
58 elsif(full_int='1')then
59 Wad_int <= Wad_int;
60 else
61 Wad_int <= Wad_int+1;
62 end if;
63 end if;
64 if(Wad_int=RAD-1 or (Wad_int=addr_max_int and RAD=0))then
65 full_int <= '1';
66 else
67 full_int <= '0';
68 end if;
69 end if;
70 end process;
71
72 full <= full_int;
73 WAD <= Wad_int;
74 Waddr <= std_logic_vector(to_unsigned(Wad_int,addr_sz));
75 end ar_Fifo_Write; No newline at end of file
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@@ -0,0 +1,83
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 ------------------------------------------------------------------------------
19 -- Author : Martin Morlot
20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 ------------------------------------------------------------------------------
22 library IEEE;
23 use IEEE.std_logic_1164.all;
24 use IEEE.numeric_std.all;
25 library techmap;
26 use techmap.gencomp.all;
27 use work.FIFO_Config.all;
28 use work.config.all;
29
30 --! Programme de la FIFO
31
32 entity Top_FIFO is
33 port(
34 clk,raz : in std_logic; --! Horloge et reset general du composant
35 flag_RE : in std_logic; --! Flag, Demande la lecture de la m�moire
36 flag_WR : in std_logic; --! Flag, Demande l'�criture dans la m�moire
37 Data_in : in std_logic_vector(Data_sz-1 downto 0); --! Data en entr�e du composant
38 full : out std_logic; --! Flag, M�moire pleine
39 empty : out std_logic; --! Flag, M�moire vide
40 Data_out : out std_logic_vector(Data_sz-1 downto 0) --! Data en sortie du composant
41 );
42 end Top_FIFO;
43
44 --! @details Une m�moire SRAM de chez Gaisler est utilis�e,
45 --! associ�e a deux fifos, une pour �crire l'autre pour lire cette m�moire
46
47 architecture ar_Top_FIFO of Top_FIFO is
48
49 component syncram_2p
50 generic (tech : integer := 0; abits : integer := 6; dbits : integer := 8; sepclk : integer
51 := 0);
52 port (
53 rclk : in std_ulogic;
54 renable : in std_ulogic;
55 raddress : in std_logic_vector((abits -1) downto 0);
56 dataout : out std_logic_vector((dbits -1) downto 0);
57 wclk : in std_ulogic;
58 write : in std_ulogic;
59 waddress : in std_logic_vector((abits -1) downto 0);
60 datain : in std_logic_vector((dbits -1) downto 0));
61 end component;
62
63 signal RAD : integer range 0 to addr_max_int;
64 signal WAD : integer range 0 to addr_max_int;
65 signal Raddr : std_logic_vector(addr_sz-1 downto 0);
66 signal Waddr : std_logic_vector(addr_sz-1 downto 0);
67
68 begin
69
70 SRAM : syncram_2p
71 generic map(CFG_MEMTECH,addr_sz,Data_sz)
72 port map(clk,flag_RE,Raddr,Data_out,clk,flag_WR,Waddr,Data_in);
73
74
75 WR : entity work.Fifo_Write
76 port map(clk,raz,flag_WR,RAD,full,WAD,Waddr);
77
78
79 RE : entity work.Fifo_Read
80 port map(clk,raz,flag_RE,WAD,empty,RAD,Raddr);
81
82
83 end ar_Top_FIFO; No newline at end of file
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@@ -0,0 +1,90
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 ------------------------------------------------------------------------------
19 -- Author : Martin Morlot
20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 ------------------------------------------------------------------------------
22 library ieee;
23 use ieee.std_logic_1164.all;
24 library grlib;
25 use grlib.amba.all;
26 use std.textio.all;
27 library lpp;
28 use lpp.lpp_amba.all;
29 use work.FIFO_Config.all;
30
31 --! Package contenant tous les programmes qui forment le composant int�gr� dans le l�on
32
33 package lpp_fifo is
34
35 component APB_FIFO is
36 generic (
37 pindex : integer := 0;
38 paddr : integer := 0;
39 pmask : integer := 16#fff#;
40 pirq : integer := 0;
41 abits : integer := 8);
42 port (
43 clk : in std_logic;
44 rst : in std_logic;
45 apbi : in apb_slv_in_type;
46 apbo : out apb_slv_out_type
47 );
48 end component;
49
50
51 component Top_FIFO is
52 port(
53 clk : in std_logic;
54 raz : in std_logic;
55 flag_RE : in std_logic;
56 flag_WR : in std_logic;
57 Data_in : in std_logic_vector(Data_sz-1 downto 0);
58 full : out std_logic;
59 empty : out std_logic;
60 Data_out : out std_logic_vector(Data_sz-1 downto 0)
61 );
62 end component;
63
64
65 component Fifo_Read is
66 port(
67 clk : in std_logic;
68 raz : in std_logic;
69 flag_RE : in std_logic;
70 WAD : in integer range 0 to addr_max_int;
71 empty : out std_logic;
72 RAD : out integer range 0 to addr_max_int;
73 Raddr : out std_logic_vector(addr_sz-1 downto 0)
74 );
75 end component;
76
77
78 component Fifo_Write is
79 port(
80 clk : in std_logic;
81 raz : in std_logic;
82 flag_WR : in std_logic;
83 RAD : in integer range 0 to addr_max_int;
84 full : out std_logic;
85 WAD : out integer range 0 to addr_max_int;
86 Waddr : out std_logic_vector(addr_sz-1 downto 0)
87 );
88 end component;
89
90 end;
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@@ -27,4 +27,6 syntax: glob
27 27 *.bin
28 28 *~
29 29 LPP_drivers/libsrc/AMBA/apb_devices_list.h
30 apb_devices_list.h
30 31 lib/lpp/lpp_amba/apb_devices_list.vhd
32 apb_devices_list.vhd
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@@ -10,3 +10,4 device LPP_CNA 7
10 10 device LPP_APB_ADC 8
11 11 device LPP_CHENILLARD 9
12 12 device LPP_IIR_CEL_FILTER 10
13 device LPP_FIFO 11
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1 NO CONTENT: modified file, binary diff hidden
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@@ -14,8 +14,11
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------*/
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
19 -- Author : Martin Morlot
20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 -----------------------------------------------------------------------------*/
19 22 #include "apb_dac_Driver.h"
20 23 #include "lpp_apb_functions.h"
21 24 #include <stdio.h>
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@@ -14,8 +14,11
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------*/
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
19 -- Author : Martin Morlot
20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 -----------------------------------------------------------------------------*/
19 22 #ifndef APB_CNA_DRIVER_H
20 23 #define APB_CNA_DRIVER_H
21 24
@@ -28,10 +31,11
28 31 T Y P E S D E F
29 32 ====================================================*/
30 33
34 /** Structure repr�sentant le registre du CNA */
31 35 struct DAC_Driver
32 36 {
33 int configReg;
34 int dataReg;
37 int configReg; /**< Registre de configuration: Flag Ready [1] ; Flag Enable [0] */
38 int dataReg; /**< Registre de donn�e sur 16 bits */
35 39 };
36 40
37 41 typedef struct DAC_Driver DAC_Device;
@@ -40,12 +44,15 typedef struct DAC_Driver DAC_Device;
40 44 F U N C T I O N S
41 45 ====================================================*/
42 46
47 /** Ouvre l'acc� au CNA */
43 48 DAC_Device* DacOpen(int count);
44 49
45 50 //DAC_Device* DacClose(int count);
46 51
52 /** Les donn�es sont lus a partir d'un tableau pour obtenir le signal de CAL (10Khz + 625hz) */
47 53 int DacTable();
48 54
55 /** Les donn�es sont entr�e par l'utilisateur, la conversion se fait a chaque nouvelle donn�e */
49 56 int DacConst();
50 57
51 58
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@@ -1,12 +1,12
1 1 APB_IIR_CEL.vhd
2 FILTER.vhd
3 FILTER_RAM_CTRLR.vhd
2 4 FILTERcfg.vhd
3 5 FilterCTRLR.vhd
4 FILTER_RAM_CTRLR.vhd
5 FILTER.vhd
6 6 IIR_CEL_CTRLR.vhd
7 7 IIR_CEL_FILTER.vhd
8 iir_filter.vhd
8 RAM.vhd
9 9 RAM_CEL.vhd
10 10 RAM_CTRLR2.vhd
11 RAM.vhd
12 11 Top_Filtre_IIR.vhd
12 iir_filter.vhd
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@@ -1,14 +1,14
1 Adder.vhd
2 1 ADDRcntr.vhd
3 2 ALU.vhd
3 Adder.vhd
4 4 Clk_divider.vhd
5 general_purpose.vhd
5 MAC.vhd
6 6 MAC_CONTROLER.vhd
7 MAC_MUX2.vhd
8 7 MAC_MUX.vhd
8 MAC_MUX2.vhd
9 9 MAC_REG.vhd
10 MAC.vhd
10 MUX2.vhd
11 11 Multiplier.vhd
12 MUX2.vhd
13 12 REG.vhd
14 13 Shifter.vhd
14 general_purpose.vhd
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@@ -15,7 +15,10
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
18 ------------------------------------------------------------------------------
19 -- Author : Martin Morlot
20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 ------------------------------------------------------------------------------
19 22 library ieee;
20 23 use ieee.std_logic_1164.all;
21 24 --use ieee.numeric_std.all;
@@ -24,6 +27,7 use grlib.amba.all;
24 27 use grlib.stdlib.all;
25 28 use grlib.devices.all;
26 29 library lpp;
30 use lpp.apb_devices_list.all;
27 31 use lpp.lpp_amba.all;
28 32
29 33
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@@ -27,6 +27,7 use grlib.amba.all;
27 27 use grlib.stdlib.all;
28 28 use grlib.devices.all;
29 29 library lpp;
30 use lpp.apb_devices_list.all;
30 31 use lpp.lpp_amba.all;
31 32
32 33
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@@ -1,23 +1,24
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
19 -- APB_CNA.vhd
20
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 ------------------------------------------------------------------------------
19 -- Author : Martin Morlot
20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 ------------------------------------------------------------------------------
21 22 library ieee;
22 23 use ieee.std_logic_1164.all;
23 24 library grlib;
@@ -29,6 +30,7 use lpp.lpp_amba.all;
29 30 use lpp.apb_devices_list.all;
30 31 use lpp.lpp_cna.all;
31 32
33 --! Driver APB, va faire le lien entre l'IP VHDL du convertisseur et le bus Amba
32 34
33 35 entity APB_CNA is
34 36 generic (
@@ -38,16 +40,18 entity APB_CNA is
38 40 pirq : integer := 0;
39 41 abits : integer := 8);
40 42 port (
41 clk : in std_logic;
42 rst : in std_logic;
43 apbi : in apb_slv_in_type;
44 apbo : out apb_slv_out_type;
45 SYNC : out std_logic;
46 SCLK : out std_logic;
47 DATA : out std_logic
43 clk : in std_logic; --! Horloge du composant
44 rst : in std_logic; --! Reset general du composant
45 apbi : in apb_slv_in_type; --! Registre de gestion des entr�es du bus
46 apbo : out apb_slv_out_type; --! Registre de gestion des sorties du bus
47 SYNC : out std_logic; --! Signal de synchronisation du convertisseur
48 SCLK : out std_logic; --! Horloge systeme du convertisseur
49 DATA : out std_logic --! Donn�e num�rique s�rialis�
48 50 );
49 51 end APB_CNA;
50 52
53 --! @details Les deux registres (apbi,apbo) permettent de g�rer la communication sur le bus
54 --! et les sorties seront cabl�es vers le convertisseur.
51 55
52 56 architecture ar_APB_CNA of APB_CNA is
53 57
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@@ -1,42 +1,46
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
19 -- CNA_TabloC.vhd
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 ------------------------------------------------------------------------------
19 -- Author : Martin Morlot
20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 ------------------------------------------------------------------------------
20 22 library IEEE;
21 23 use IEEE.std_logic_1164.all;
22 24 use IEEE.numeric_std.all;
23 25 use work.Convertisseur_config.all;
24 26
27 --! Programme du Convertisseur Num�rique/Analogique
28
25 29 entity CNA_TabloC is
26 port(
27 clock : in std_logic;
28 rst : in std_logic;
29 enable : in std_logic;
30 --bp : in std_logic;
31 Data_C : in std_logic_vector(15 downto 0);
32 SYNC : out std_logic;
33 SCLK : out std_logic;
34 --Rz : out std_logic;
35 flag_sd : out std_logic;
36 Data : out std_logic
37 );
30 port(
31 clock : in std_logic; --! Horloge du composant
32 rst : in std_logic; --! Reset general du composant
33 enable : in std_logic; --! Autorise ou non l'utilisation du composant
34 Data_C : in std_logic_vector(15 downto 0); --! Donn�e Num�rique d'entr�e sur 16 bits
35 SYNC : out std_logic; --! Signal de synchronisation du convertisseur
36 SCLK : out std_logic; --! Horloge systeme du convertisseur
37 flag_sd : out std_logic; --! Flag, signale la fin de la s�rialisation d'une donn�e
38 Data : out std_logic --! Donn�e num�rique s�rialis�
39 );
38 40 end CNA_TabloC;
39 41
42 --! @details Un driver C va permettre de g�nerer un tableau de donn�es sur 16 bits,
43 --! qui seront s�rialis� pour �tre ensuite dirig�es vers le convertisseur.
40 44
41 45 architecture ar_CNA_TabloC of CNA_TabloC is
42 46
@@ -50,11 +54,9 signal clk : std_logic;
50 54 signal raz : std_logic;
51 55 signal s_SCLK : std_logic;
52 56 signal OKAI_send : std_logic;
53 --signal Data_int : std_logic_vector(15 downto 0);
54 57
55 58 begin
56 59
57
58 60 CLKINT_0 : CLKINT
59 61 port map(A => clock, Y => clk);
60 62
@@ -75,11 +77,6 Serial : entity work.serialize
75 77 port map (clk,raz,s_SCLK,Data_C,OKAI_send,flag_sd,Data);
76 78
77 79
78 --Rz <= raz;
79 80 SCLK <= s_SCLK;
80 81
81 --with bp select
82 -- Data_int <= X"9555" when '1',
83 -- Data_C when others;
84
85 82 end ar_CNA_TabloC; No newline at end of file
Show file before | Show file after | Hide comments
@@ -1,38 +1,30
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
19 -- Convertisseur_config.vhd
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 ------------------------------------------------------------------------------
19 -- Author : Martin Morlot
20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 ------------------------------------------------------------------------------
20 22 library IEEE;
21 23 use IEEE.std_logic_1164.all;
22 24 use IEEE.numeric_std.all;
23 25
24 26 Package Convertisseur_config is
25 27
26
27 --===========================================================|
28 --================= Valeurs Sinus 1Khz ======================|
29 --===========================================================|
30 type Tbl is array(natural range <>) of std_logic_vector(11 downto 0);
31 constant Tablo : Tbl (0 to 49):= (X"800",X"901",X"9FD",X"AF2",X"BDB",X"CB4",X"D7A",X"E2A",X"EC1",X"F3D",X"F9C",X"FDC",X"FFC",X"FFC",X"FDC",X"F9C",X"F3D",X"EC1",X"E2A",X"D7A",X"CB4",X"BDB",X"AF2",X"9FD",X"901",X"800",X"6FF",X"603",X"50E",X"425",X"34C",X"286",X"1D6",X"13F",X"0C3",X"064",X"024",X"004",X"004",X"024",X"064",X"0C3",X"13F",X"1D6",X"286",X"34C",X"425",X"50E",X"603",X"6FF");
32
33 --constant Tablo : Tbl (0 to 49):= (X"C00",X"C80",X"CFF",X"D79",X"DED",X"E5A",X"EBD",X"F15",X"F61",X"F9F",X"FCE",X"FEE",X"FFE",X"FFE",X"FEE",X"FCE",X"F9F",X"F61",X"F15",X"EBD",X"E5A",X"DED",X"D79",X"CFF",X"C80",X"C00",X"B80",X"B01",X"A87",X"A13",X"9A6",X"943",X"8EB",X"89F",X"861",X"832",X"812",X"802",X"802",X"812",X"832",X"861",X"89F",X"8EB",X"943",X"9A6",X"A13",X"A87",X"B01",X"B80");
34
35
36 28 --===========================================================|
37 29 --============= Fr�quence de s�rialisation ==================|
38 30 --===========================================================|
Show file before | Show file after | Hide comments
@@ -1,58 +1,56
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
19 -- Gene_SYNC.vhd
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 ------------------------------------------------------------------------------
19 -- Author : Martin Morlot
20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 ------------------------------------------------------------------------------
20 22 library IEEE;
21 23 use IEEE.std_logic_1164.all;
22 24 use IEEE.numeric_std.all;
23 25
24 entity Gene_SYNC is
26 --! Programme qui va permettre de g�n�rer le signal SYNC
25 27
26 port(
27 SCLK,raz : in std_logic;
28 enable : in std_logic;
29 -- Sysclk : in std_logic;
30 OKAI_send : out std_logic;
31 SYNC : out std_logic
32 );
33
28 entity Gene_SYNC is
29 port(
30 SCLK,raz : in std_logic; --! Horloge systeme et Reset du composant
31 enable : in std_logic; --! Autorise ou non l'utilisation du composant
32 OKAI_send : out std_logic; --! Flag, Autorise l'envoi (s�rialisation) d'une nouvelle donn�e
33 SYNC : out std_logic --! Signal de synchronisation du convertisseur g�n�r�
34 );
34 35 end Gene_SYNC;
35 36
37 --! @details NB: Ce programme est uniquement synchronis� sur l'horloge Systeme (sclk)
36 38
37 39 architecture ar_Gene_SYNC of Gene_SYNC is
38 40
39 --signal Sysclk_reg : std_logic;
40 41 signal count : integer;
41 42
42
43 43 begin
44 44 process (SCLK,raz)
45 45 begin
46 46 if(raz='0')then
47 47 SYNC <= '0';
48 -- Sysclk_reg <= '0';
49 48 count <= 14;
50 49 OKAI_send <= '0';
51 50
52 51 elsif(SCLK' event and SCLK='1')then
53 52 if(enable='1')then
54
55 -- Sysclk_reg <= Sysclk;
53
56 54 if(count=15)then
57 55 SYNC <= '1';
58 56 count <= count+1;
@@ -64,8 +62,8 begin
64 62 count <= count+1;
65 63 OKAI_send <= '0';
66 64 end if;
65
67 66 end if;
68 67 end if;
69 end process;
70
68 end process;
71 69 end ar_Gene_SYNC; No newline at end of file
Show file before | Show file after | Hide comments
@@ -1,104 +1,107
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
19 -- Serialize.vhd
20 library IEEE;
21 use IEEE.numeric_std.all;
22 use IEEE.std_logic_1164.all;
23
24 entity Serialize is
25
26 port(
27 clk,raz : in std_logic;
28 sclk : in std_logic;
29 vectin : in std_logic_vector(15 downto 0);
30 send : in std_logic;
31 sended : out std_logic;
32 Data : out std_logic);
33
34 end Serialize;
35
36
37 architecture ar_Serialize of Serialize is
38
39 type etat is (attente,serialize);
40 signal ect : etat;
41
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 ------------------------------------------------------------------------------
19 -- Author : Martin Morlot
20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 ------------------------------------------------------------------------------
22 library IEEE;
23 use IEEE.numeric_std.all;
24 use IEEE.std_logic_1164.all;
25
26 --! Programme qui permet de s�rialiser un vecteur
27
28 entity Serialize is
29 port(
30 clk,raz : in std_logic; --! Horloge et Reset du composant
31 sclk : in std_logic; --! Horloge Systeme
32 vectin : in std_logic_vector(15 downto 0); --! Vecteur d'entr�e
33 send : in std_logic; --! Flag, Une nouvelle donn�e est pr�sente
34 sended : out std_logic; --! Flag, La donn�e a �t� s�rialis�e
35 Data : out std_logic --! Donn�e num�rique s�rialis�
36 );
37 end Serialize;
38
39
40 architecture ar_Serialize of Serialize is
41
42 type etat is (attente,serialize);
43 signal ect : etat;
44
42 45 signal vector_int : std_logic_vector(16 downto 0);
43 signal vectin_reg : std_logic_vector(15 downto 0);
44 signal load : std_logic;
45 signal N : integer range 0 to 16;
46 signal vectin_reg : std_logic_vector(15 downto 0);
47 signal load : std_logic;
48 signal N : integer range 0 to 16;
46 49 signal CPT_ended : std_logic:='0';
47
48 begin
49 process(clk,raz)
50 begin
51 if(raz='0')then
50
51 begin
52 process(clk,raz)
53 begin
54 if(raz='0')then
52 55 ect <= attente;
53 vectin_reg <= (others=> '0');
56 vectin_reg <= (others=> '0');
54 57 load <= '0';
55 sended <= '1';
56
58 sended <= '1';
59
57 60 elsif(clk'event and clk='1')then
58 vectin_reg <= vectin;
59
60 case ect is
61 when attente =>
61 vectin_reg <= vectin;
62
63 case ect is
64 when attente =>
62 65 if (send='1') then
63 66 sended <= '0';
64 67 load <= '1';
65 68 ect <= serialize;
66 69 else
67 ect <= attente;
68 end if;
69
70 ect <= attente;
71 end if;
72
70 73 when serialize =>
71 load <= '0';
72 if(CPT_ended='1')then
74 load <= '0';
75 if(CPT_ended='1')then
73 76 ect <= attente;
74 sended <= '1';
77 sended <= '1';
75 78 end if;
76
77 end case;
78 end if;
79 end process;
80
81 process(sclk,load,raz)
82 begin
83 if (raz='0')then
84 vector_int <= (others=> '0');
85 N <= 16;
86 elsif(load='1')then
87 vector_int <= vectin & '0';
88 N <= 0;
89 elsif(sclk'event and sclk='1')then
90 if (CPT_ended='0') then
91 vector_int <= vector_int(15 downto 0) & '0';
92 N <= N+1;
93 end if;
94 end if;
95 end process;
96
79
80 end case;
81 end if;
82 end process;
83
84 process(sclk,load,raz)
85 begin
86 if (raz='0')then
87 vector_int <= (others=> '0');
88 N <= 16;
89 elsif(load='1')then
90 vector_int <= vectin & '0';
91 N <= 0;
92 elsif(sclk'event and sclk='1')then
93 if (CPT_ended='0') then
94 vector_int <= vector_int(15 downto 0) & '0';
95 N <= N+1;
96 end if;
97 end if;
98 end process;
99
97 100 CPT_ended <= '1' when N = 16 else '0';
98
99 with ect select
100 Data <= vector_int(16) when serialize,
101 '0' when others;
102
103 end ar_Serialize;
104
101
102 with ect select
103 Data <= vector_int(16) when serialize,
104 '0' when others;
105
106 end ar_Serialize;
107
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@@ -1,22 +1,24
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
19 -- Systeme_Clock.vhd
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 ------------------------------------------------------------------------------
19 -- Author : Martin Morlot
20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 ------------------------------------------------------------------------------
20 22 library IEEE;
21 23 use IEEE.std_logic_1164.all;
22 24 use IEEE.numeric_std.all;
@@ -24,14 +26,15 use IEEE.numeric_std.all;
24 26 --! Programme qui va permetre de g�n�rer l'horloge systeme (sclk)
25 27
26 28 entity Systeme_Clock is
27 generic(N :integer := 695); --! G�n�rique contenant le r�sultat de la division clk/sclk
28 port(
29 clk, raz : in std_logic; --! Horloge et Reset globale
29 generic(N :integer := 695); --! G�n�rique contenant le r�sultat de la division clk/sclk
30 port(
31 clk, raz : in std_logic; --! Horloge et Reset globale du composant
30 32 sclk : out std_logic --! Horloge Systeme g�n�r�e
31 );
33 );
32 34 end Systeme_Clock;
33 35
34 36 --! @details Fonctionne a base d'un compteur (countint) qui va permetre de diviser l'horloge N fois
37
35 38 architecture ar_Systeme_Clock of Systeme_Clock is
36 39
37 40 signal clockint : std_logic;
Show file before | Show file after | Hide comments
@@ -15,17 +15,19
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
18 ------------------------------------------------------------------------------
19 -- Author : Martin Morlot
20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 ------------------------------------------------------------------------------
19 22 library ieee;
20 23 use ieee.std_logic_1164.all;
21 24 library grlib;
22 25 use grlib.amba.all;
23 -- pragma translate_off
24 26 use std.textio.all;
25 -- pragma translate_on
26 27 library lpp;
27 28 use lpp.lpp_amba.all;
28 29
30 --! Package contenant tous les programmes qui forment le composant int�gr� dans le l�on
29 31
30 32 package lpp_cna is
31 33
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@@ -15,7 +15,10
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
18 ------------------------------------------------------------------------------
19 -- Author : Martin Morlot
20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 ------------------------------------------------------------------------------
19 22 library ieee;
20 23 use ieee.std_logic_1164.all;
21 24 library grlib;
@@ -27,6 +30,8 use lpp.lpp_amba.all;
27 30 use lpp.apb_devices_list.all;
28 31 use lpp.lpp_uart.all;
29 32
33 --! Driver APB, va faire le lien entre l'IP VHDL de l'UART et le bus Amba
34
30 35 entity APB_UART is
31 36 generic (
32 37 pindex : integer := 0;
@@ -36,12 +41,12 entity APB_UART is
36 41 abits : integer := 8;
37 42 Data_sz : integer := 8);
38 43 port (
39 clk : in std_logic;
40 rst : in std_logic;
41 apbi : in apb_slv_in_type;
42 apbo : out apb_slv_out_type;
43 TXD : out std_logic;
44 RXD : in std_logic
44 clk : in std_logic; --! Horloge du composant
45 rst : in std_logic; --! Reset general du composant
46 apbi : in apb_slv_in_type; --! Registre de gestion des entr�es du bus
47 apbo : out apb_slv_out_type; --! Registre de gestion des sorties du bus
48 TXD : out std_logic; --! Transmission s�rie, c�t� composant
49 RXD : in std_logic --! Reception s�rie, c�t� composant
45 50 );
46 51 end APB_UART;
47 52
@@ -61,7 +66,7 signal Send : std_logic;
61 66 signal Sended : std_logic;
62 67
63 68 type UART_ctrlr_Reg is record
64 UART_Cfg : std_logic_vector(4 downto 0);
69 UART_Cfg : std_logic_vector(2 downto 0);
65 70 UART_Wdata : std_logic_vector(7 downto 0);
66 71 UART_Rdata : std_logic_vector(7 downto 0);
67 72 UART_BTrig : std_logic_vector(11 downto 0);
@@ -69,14 +74,13 end record;
69 74
70 75 signal Rec : UART_ctrlr_Reg;
71 76 signal Rdata : std_logic_vector(31 downto 0);
77 signal temp_ND : std_logic;
72 78
73 79 begin
74 80
75 81 Capture <= Rec.UART_Cfg(0);
76 --ACK <= Rec.UART_Cfg(1);
77 --Send <= Rec.UART_Cfg(2);
78 Rec.UART_Cfg(3) <= Sended;
79 Rec.UART_Cfg(4) <= NwData;
82 Rec.UART_Cfg(1) <= Sended;
83 Rec.UART_Cfg(2) <= NwData;
80 84
81 85
82 86 COM0 : entity work.UART
@@ -90,41 +94,47 Rec.UART_Cfg(4) <= NwData;
90 94 Rec.UART_Wdata <= (others => '0');
91 95
92 96
93 elsif(clk'event and clk='1')then
94
97 elsif(clk'event and clk='1')then
98 temp_ND <= NwData;
99 if(NwData='1' and temp_ND='1')then
100 ACK <= '1';
101 else
102 ACK <= '0';
103 end if;
95 104
96 105 --APB Write OP
97 106 if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then
98 107 case apbi.paddr(7 downto 2) is
99 108 when "000000" =>
100 Rec.UART_Cfg(2 downto 0) <= apbi.pwdata(2 downto 0);
109 Rec.UART_Cfg(0) <= apbi.pwdata(0);
101 110 when "000001" =>
102 Rec.UART_Wdata <= apbi.pwdata(7 downto 0);
103 Send <= '1';
111 Rec.UART_Wdata(7 downto 0) <= apbi.pwdata(7 downto 0);
112 Send <= '1';
104 113 when others =>
105 114 null;
106 115 end case;
107 else
108 Send <= '0';
116 else
117 Send <= '0';
109 118 end if;
110 119
111 120 --APB READ OP
112 121 if (apbi.psel(pindex) and (not apbi.pwrite)) = '1' then
113 122 case apbi.paddr(7 downto 2) is
114 123 when "000000" =>
115 Rdata(4 downto 0) <= Rec.UART_Cfg;
116 Rdata(26 downto 12) <= (others => '0');
117 Rdata(27 downto 16) <= Rec.UART_BTrig;
124 Rdata(3 downto 0) <= "000" & Rec.UART_Cfg(0);
125 Rdata(7 downto 4) <= "000" & Rec.UART_Cfg(1);
126 Rdata(11 downto 8) <= "000" & Rec.UART_Cfg(2);
127 Rdata(19 downto 12) <= X"EE";
128 Rdata(31 downto 20) <= Rec.UART_BTrig;
118 129 when "000001" =>
130 Rdata(31 downto 8) <= X"EEEEEE";
119 131 Rdata(7 downto 0) <= Rec.UART_Wdata;
120 132 when "000010" =>
133 Rdata(31 downto 8) <= X"EEEEEE";
121 134 Rdata(7 downto 0) <= Rec.UART_Rdata;
122 Ack <= '1';
123 135 when others =>
124 136 Rdata <= (others => '0');
125 137 end case;
126 else
127 Ack <= '0';
128 138 end if;
129 139
130 140 end if;
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@@ -46,6 +46,7 architecture ar_Shift_REG of Shift_REG i
46 46 signal REG : std_logic_vector(Data_sz-1 downto 0);
47 47 signal Serialized_int : std_logic;
48 48 signal Serialize_reg : std_logic;
49 signal Serial_reg : std_logic;
49 50 signal CptBits : std_logic_vector(Data_sz-1 downto 0);
50 51 constant CptBits_trig : std_logic_vector(Data_sz-1 downto 0) := (others => '1');
51 52 signal CptBits_flag : std_logic;
@@ -61,14 +62,16 begin
61 62 if reset = '0' then
62 63 Serialized_int <= '1';
63 64 CptBits_flag_reg <= '0';
65 Serial_reg <= '0';
64 66 Q <= (others => '0');
65 67 elsif clk'event and clk = '1' then
66 68 CptBits_flag_reg <= CptBits_flag;
69 Serial_reg <= Serialize;
67 70
68 71 if CptBits_flag = '1' and CptBits_flag_reg = '0' then
69 72 Serialized_int <= '1';
70 73 Q <= REG;
71 elsif Serialize = '1' then
74 elsif(Serial_reg='0' and Serialize='1')then
72 75 Serialized_int <= '0';
73 76 end if;
74 77 end if;
Show file before | Show file after | Hide comments
@@ -45,9 +45,9 port(
45 45 );
46 46 end entity;
47 47
48
49 48 --! @details Gestion de la Reception/Transmission donc de la Vectorisation/Serialisation
50 --! ainsi que la detection et le reglage de le frequence de transmission optimale sur le bus (Generateur de Bauds)
49 --! ainsi que la detection et le reglage de le frequence de transmission optimale sur le bus (Generateur de Bauds)
50
51 51 architecture ar_UART of UART is
52 52 signal Bclk : std_logic;
53 53
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