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Update SOLO_LFR_LFR-EM timings constraints...
Update SOLO_LFR_LFR-EM timings constraints (due to the fact that we used a A3PE3000L FPGA on the LFR-EM board)
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r406:c218371d90d3 JC
r674:b0efa9138022 default
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run.do
2 lines | 31 B | text/x-stata | StataLexer
/ designs / Validation_RAM_CEL / run.do
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log -R *
do wave.do
run 10 ms