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1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
19 -- Author : Jean-christophe Pellion
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 -------------------------------------------------------------------------------
22 LIBRARY IEEE;
23 USE IEEE.numeric_std.ALL;
24 USE IEEE.std_logic_1164.ALL;
25 LIBRARY grlib;
26 USE grlib.amba.ALL;
27 USE grlib.stdlib.ALL;
28 LIBRARY techmap;
29 USE techmap.gencomp.ALL;
30 LIBRARY gaisler;
31 USE gaisler.memctrl.ALL;
32 USE gaisler.leon3.ALL;
33 USE gaisler.uart.ALL;
34 USE gaisler.misc.ALL;
35 USE gaisler.spacewire.ALL;
36 LIBRARY esa;
37 USE esa.memoryctrl.ALL;
38 LIBRARY lpp;
39 USE lpp.lpp_memory.ALL;
40 USE lpp.lpp_ad_conv.ALL;
41 USE lpp.lpp_lfr_pkg.ALL; -- contains lpp_lfr, not in the 206 rev of the VHD_Lib
42 USE lpp.lpp_top_lfr_pkg.ALL; -- contains top_wf_picker
43 USE lpp.iir_filter.ALL;
44 USE lpp.general_purpose.ALL;
45 USE lpp.lpp_lfr_time_management.ALL;
46 USE lpp.lpp_leon3_soc_pkg.ALL;
47
48 ENTITY MINI_LFR_top IS
49
50 PORT (
51 clk_50 : IN STD_LOGIC;
52 clk_49 : IN STD_LOGIC;
53 reset : IN STD_LOGIC;
54 --BPs
55 BP0 : IN STD_LOGIC;
56 BP1 : IN STD_LOGIC;
57 --LEDs
58 LED0 : OUT STD_LOGIC;
59 LED1 : OUT STD_LOGIC;
60 LED2 : OUT STD_LOGIC;
61 --UARTs
62 TXD1 : IN STD_LOGIC;
63 RXD1 : OUT STD_LOGIC;
64 nCTS1 : OUT STD_LOGIC;
65 nRTS1 : IN STD_LOGIC;
66
67 TXD2 : IN STD_LOGIC;
68 RXD2 : OUT STD_LOGIC;
69 nCTS2 : OUT STD_LOGIC;
70 nDTR2 : IN STD_LOGIC;
71 nRTS2 : IN STD_LOGIC;
72 nDCD2 : OUT STD_LOGIC;
73
74 --EXT CONNECTOR
75 IO0 : INOUT STD_LOGIC;
76 IO1 : INOUT STD_LOGIC;
77 IO2 : INOUT STD_LOGIC;
78 IO3 : INOUT STD_LOGIC;
79 IO4 : INOUT STD_LOGIC;
80 IO5 : INOUT STD_LOGIC;
81 IO6 : INOUT STD_LOGIC;
82 IO7 : INOUT STD_LOGIC;
83 IO8 : INOUT STD_LOGIC;
84 IO9 : INOUT STD_LOGIC;
85 IO10 : INOUT STD_LOGIC;
86 IO11 : INOUT STD_LOGIC;
87
88 --SPACE WIRE
89 SPW_EN : OUT STD_LOGIC; -- 0 => off
90 SPW_NOM_DIN : IN STD_LOGIC; -- NOMINAL LINK
91 SPW_NOM_SIN : IN STD_LOGIC;
92 SPW_NOM_DOUT : OUT STD_LOGIC;
93 SPW_NOM_SOUT : OUT STD_LOGIC;
94 SPW_RED_DIN : IN STD_LOGIC; -- REDUNDANT LINK
95 SPW_RED_SIN : IN STD_LOGIC;
96 SPW_RED_DOUT : OUT STD_LOGIC;
97 SPW_RED_SOUT : OUT STD_LOGIC;
98 -- MINI LFR ADC INPUTS
99 ADC_nCS : OUT STD_LOGIC;
100 ADC_CLK : OUT STD_LOGIC;
101 ADC_SDO : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
102
103 -- SRAM
104 SRAM_nWE : OUT STD_LOGIC;
105 SRAM_CE : OUT STD_LOGIC;
106 SRAM_nOE : OUT STD_LOGIC;
107 SRAM_nBE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
108 SRAM_A : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
109 SRAM_DQ : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0)
110 );
111
112 END MINI_LFR_top;
113
114
115 ARCHITECTURE beh OF MINI_LFR_top IS
116
117 COMPONENT lpp_lfr_ms_tb
118 GENERIC (
119 Mem_use : INTEGER);
120 PORT (
121 clk : IN STD_LOGIC;
122 rstn : IN STD_LOGIC;
123 sample_f0_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
124 sample_f0_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
125 sample_f1_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
126 sample_f1_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
127 sample_f2_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
128 sample_f2_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
129 MEM_IN_SM_locked : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
130 MEM_IN_SM_ReUse : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
131 MEM_IN_SM_ren : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
132 MEM_IN_SM_rData : OUT STD_LOGIC_VECTOR(16*2*5-1 DOWNTO 0);
133 MEM_IN_SM_Full_pad : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
134 MEM_IN_SM_Empty_pad : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
135 error_input_fifo_write : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
136 observation_vector_0 : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
137 observation_vector_1 : OUT STD_LOGIC_VECTOR(11 DOWNTO 0));
138 END COMPONENT;
139
140 COMPONENT lpp_lfr_apbreg_tb
141 GENERIC (
142 pindex : INTEGER;
143 paddr : INTEGER;
144 pmask : INTEGER);
145 PORT (
146 HCLK : IN STD_ULOGIC;
147 HRESETn : IN STD_ULOGIC;
148 apbi : IN apb_slv_in_type;
149 apbo : OUT apb_slv_out_type;
150 sample_f0_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
151 sample_f1_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
152 sample_f2_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
153 sample_f0_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
154 sample_f1_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
155 sample_f2_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
156 MEM_IN_SM_locked : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
157 MEM_IN_SM_ReUse : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
158 MEM_IN_SM_ren : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
159 MEM_IN_SM_rData : IN STD_LOGIC_VECTOR(16*2*5-1 DOWNTO 0);
160 MEM_IN_SM_Full : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
161 MEM_IN_SM_Empty : IN STD_LOGIC_VECTOR(4 DOWNTO 0));
162 END COMPONENT;
163
164
165
166 SIGNAL clk_50_s : STD_LOGIC := '0';
167 SIGNAL clk_25 : STD_LOGIC := '0';
168 SIGNAL clk_24 : STD_LOGIC := '0';
169 -----------------------------------------------------------------------------
170 SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
171 SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0);
172 --
173 SIGNAL errorn : STD_LOGIC;
174 -- UART AHB ---------------------------------------------------------------
175 SIGNAL ahbrxd : STD_ULOGIC; -- DSU rx data
176 SIGNAL ahbtxd : STD_ULOGIC; -- DSU tx data
177
178 -- UART APB ---------------------------------------------------------------
179 SIGNAL urxd1 : STD_ULOGIC; -- UART1 rx data
180 SIGNAL utxd1 : STD_ULOGIC; -- UART1 tx data
181 --
182 SIGNAL I00_s : STD_LOGIC;
183
184 -- CONSTANTS
185 CONSTANT CFG_PADTECH : INTEGER := inferred;
186 --
187 CONSTANT NB_APB_SLAVE : INTEGER := 11; -- 3 = grspw + waveform picker + time manager, 11 allows pindex = f
188 CONSTANT NB_AHB_SLAVE : INTEGER := 1;
189 CONSTANT NB_AHB_MASTER : INTEGER := 2; -- 2 = grspw + waveform picker
190
191 SIGNAL apbi_ext : apb_slv_in_type;
192 SIGNAL apbo_ext : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5) := (OTHERS => apb_none);
193 SIGNAL ahbi_s_ext : ahb_slv_in_type;
194 SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3) := (OTHERS => ahbs_none);
195 SIGNAL ahbi_m_ext : AHB_Mst_In_Type;
196 SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1) := (OTHERS => ahbm_none);
197
198 -- Spacewire signals
199 SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
200 SIGNAL stmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
201 SIGNAL spw_rxclk : STD_LOGIC_VECTOR(1 DOWNTO 0);
202 SIGNAL spw_rxtxclk : STD_ULOGIC;
203 SIGNAL spw_rxclkn : STD_ULOGIC;
204 SIGNAL spw_clk : STD_LOGIC;
205 SIGNAL swni : grspw_in_type;
206 SIGNAL swno : grspw_out_type;
207 -- SIGNAL clkmn : STD_ULOGIC;
208 -- SIGNAL txclk : STD_ULOGIC;
209
210 --GPIO
211 SIGNAL gpioi : gpio_in_type;
212 SIGNAL gpioo : gpio_out_type;
213
214 -- AD Converter ADS7886
215 SIGNAL sample : Samples14v(7 DOWNTO 0);
216 SIGNAL sample_s : Samples(7 DOWNTO 0);
217 SIGNAL sample_val : STD_LOGIC;
218 SIGNAL ADC_nCS_sig : STD_LOGIC;
219 SIGNAL ADC_CLK_sig : STD_LOGIC;
220 SIGNAL ADC_SDO_sig : STD_LOGIC_VECTOR(7 DOWNTO 0);
221
222 SIGNAL bias_fail_sw_sig : STD_LOGIC;
223
224 SIGNAL observation_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
225 SIGNAL observation_vector_0 : STD_LOGIC_VECTOR(11 DOWNTO 0);
226 SIGNAL observation_vector_1 : STD_LOGIC_VECTOR(11 DOWNTO 0);
227 -----------------------------------------------------------------------------
228
229
230 SIGNAL sample_f0_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
231 SIGNAL sample_f0_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
232 --
233 SIGNAL sample_f1_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
234 SIGNAL sample_f1_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
235 --
236 SIGNAL sample_f2_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
237 SIGNAL sample_f2_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
238
239
240 ---------------------------------------------------------------------------
241 --
242 ---------------------------------------------------------------------------
243 SIGNAL MEM_IN_SM_locked : STD_LOGIC_VECTOR(4 DOWNTO 0);
244 SIGNAL MEM_IN_SM_ReUse : STD_LOGIC_VECTOR(4 DOWNTO 0);
245 SIGNAL MEM_IN_SM_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
246 SIGNAL MEM_IN_SM_rData : STD_LOGIC_VECTOR(16*2*5-1 DOWNTO 0);
247 SIGNAL MEM_IN_SM_Full_pad : STD_LOGIC_VECTOR(4 DOWNTO 0);
248 SIGNAL MEM_IN_SM_Empty_pad : STD_LOGIC_VECTOR(4 DOWNTO 0);
249
250
251
252 BEGIN -- beh
253
254 -----------------------------------------------------------------------------
255 -- CLK
256 -----------------------------------------------------------------------------
257
258 PROCESS(clk_50)
259 BEGIN
260 IF clk_50'EVENT AND clk_50 = '1' THEN
261 clk_50_s <= NOT clk_50_s;
262 END IF;
263 END PROCESS;
264
265 PROCESS(clk_50_s)
266 BEGIN
267 IF clk_50_s'EVENT AND clk_50_s = '1' THEN
268 clk_25 <= NOT clk_25;
269 END IF;
270 END PROCESS;
271
272 PROCESS(clk_49)
273 BEGIN
274 IF clk_49'EVENT AND clk_49 = '1' THEN
275 clk_24 <= NOT clk_24;
276 END IF;
277 END PROCESS;
278
279 -----------------------------------------------------------------------------
280
281 PROCESS (clk_25, reset)
282 BEGIN -- PROCESS
283 IF reset = '0' THEN -- asynchronous reset (active low)
284 LED0 <= '0';
285 LED1 <= '0';
286 LED2 <= '0';
287 --IO1 <= '0';
288 --IO2 <= '1';
289 --IO3 <= '0';
290 --IO4 <= '0';
291 --IO5 <= '0';
292 --IO6 <= '0';
293 --IO7 <= '0';
294 --IO8 <= '0';
295 --IO9 <= '0';
296 --IO10 <= '0';
297 --IO11 <= '0';
298 ELSIF clk_25'EVENT AND clk_25 = '1' THEN -- rising clock edge
299 LED0 <= '0';
300 LED1 <= '1';
301 LED2 <= BP0 OR BP1 OR nDTR2 OR nRTS2 OR nRTS1;
302 --IO1 <= '1';
303 --IO2 <= SPW_NOM_DIN OR SPW_NOM_SIN OR SPW_RED_DIN OR SPW_RED_SIN;
304 --IO3 <= ADC_SDO(0);
305 --IO4 <= ADC_SDO(1);
306 --IO5 <= ADC_SDO(2);
307 --IO6 <= ADC_SDO(3);
308 --IO7 <= ADC_SDO(4);
309 --IO8 <= ADC_SDO(5);
310 --IO9 <= ADC_SDO(6);
311 --IO10 <= ADC_SDO(7);
312 --IO11 <= BP1 OR nDTR2 OR nRTS2 OR nRTS1;
313 END IF;
314 END PROCESS;
315
316 PROCESS (clk_24, reset)
317 BEGIN -- PROCESS
318 IF reset = '0' THEN -- asynchronous reset (active low)
319 I00_s <= '0';
320 ELSIF clk_24'EVENT AND clk_24 = '1' THEN -- rising clock edge
321 I00_s <= NOT I00_s;
322 END IF;
323 END PROCESS;
324 -- IO0 <= I00_s;
325
326 --UARTs
327 nCTS1 <= '1';
328 nCTS2 <= '1';
329 nDCD2 <= '1';
330
331 --EXT CONNECTOR
332
333 --SPACE WIRE
334
335 leon3_soc_1 : leon3_soc
336 GENERIC MAP (
337 fabtech => apa3e,
338 memtech => apa3e,
339 padtech => inferred,
340 clktech => inferred,
341 disas => 0,
342 dbguart => 0,
343 pclow => 2,
344 clk_freq => 25000,
345 NB_CPU => 1,
346 ENABLE_FPU => 1,
347 FPU_NETLIST => 0,
348 ENABLE_DSU => 1,
349 ENABLE_AHB_UART => 1,
350 ENABLE_APB_UART => 1,
351 ENABLE_IRQMP => 1,
352 ENABLE_GPT => 1,
353 NB_AHB_MASTER => NB_AHB_MASTER,
354 NB_AHB_SLAVE => NB_AHB_SLAVE,
355 NB_APB_SLAVE => NB_APB_SLAVE)
356 PORT MAP (
357 clk => clk_25,
358 reset => reset,
359 errorn => errorn,
360 ahbrxd => TXD1,
361 ahbtxd => RXD1,
362 urxd1 => TXD2,
363 utxd1 => RXD2,
364 address => SRAM_A,
365 data => SRAM_DQ,
366 nSRAM_BE0 => SRAM_nBE(0),
367 nSRAM_BE1 => SRAM_nBE(1),
368 nSRAM_BE2 => SRAM_nBE(2),
369 nSRAM_BE3 => SRAM_nBE(3),
370 nSRAM_WE => SRAM_nWE,
371 nSRAM_CE => SRAM_CE,
372 nSRAM_OE => SRAM_nOE,
373
374 apbi_ext => apbi_ext,
375 apbo_ext => apbo_ext,
376 ahbi_s_ext => ahbi_s_ext,
377 ahbo_s_ext => ahbo_s_ext,
378 ahbi_m_ext => ahbi_m_ext,
379 ahbo_m_ext => ahbo_m_ext);
380
381 -------------------------------------------------------------------------------
382 -- APB_LFR_TIME_MANAGEMENT ----------------------------------------------------
383 -------------------------------------------------------------------------------
384 apb_lfr_time_management_1 : apb_lfr_time_management
385 GENERIC MAP (
386 pindex => 6,
387 paddr => 6,
388 pmask => 16#fff#,
389 FIRST_DIVISION => 374, -- ((49.152/2) /2^16) - 1 = 375 - 1 = 374
390 NB_SECOND_DESYNC => 60) -- 60 secondes of desynchronization before CoarseTime's MSB is Set
391 PORT MAP (
392 clk25MHz => clk_25,
393 clk24_576MHz => clk_24, -- 49.152MHz/2
394 resetn => reset,
395 grspw_tick => swno.tickout,
396 apbi => apbi_ext,
397 apbo => apbo_ext(6),
398 coarse_time => coarse_time,
399 fine_time => fine_time);
400
401 -----------------------------------------------------------------------
402 --- SpaceWire --------------------------------------------------------
403 -----------------------------------------------------------------------
404
405 SPW_EN <= '1';
406
407 spw_clk <= clk_50_s;
408 spw_rxtxclk <= spw_clk;
409 spw_rxclkn <= NOT spw_rxtxclk;
410
411 -- PADS for SPW1
412 spw1_rxd_pad : inpad GENERIC MAP (tech => inferred)
413 PORT MAP (SPW_NOM_DIN, dtmp(0));
414 spw1_rxs_pad : inpad GENERIC MAP (tech => inferred)
415 PORT MAP (SPW_NOM_SIN, stmp(0));
416 spw1_txd_pad : outpad GENERIC MAP (tech => inferred)
417 PORT MAP (SPW_NOM_DOUT, swno.d(0));
418 spw1_txs_pad : outpad GENERIC MAP (tech => inferred)
419 PORT MAP (SPW_NOM_SOUT, swno.s(0));
420 -- PADS FOR SPW2
421 spw2_rxd_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
422 PORT MAP (SPW_RED_SIN, dtmp(1));
423 spw2_rxs_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
424 PORT MAP (SPW_RED_DIN, stmp(1));
425 spw2_txd_pad : outpad GENERIC MAP (tech => inferred)
426 PORT MAP (SPW_RED_DOUT, swno.d(1));
427 spw2_txs_pad : outpad GENERIC MAP (tech => inferred)
428 PORT MAP (SPW_RED_SOUT, swno.s(1));
429
430 -- GRSPW PHY
431 --spw1_input: if CFG_SPW_GRSPW = 1 generate
432 spw_inputloop : FOR j IN 0 TO 1 GENERATE
433 spw_phy0 : grspw_phy
434 GENERIC MAP(
435 tech => apa3e,
436 rxclkbuftype => 1,
437 scantest => 0)
438 PORT MAP(
439 rxrst => swno.rxrst,
440 di => dtmp(j),
441 si => stmp(j),
442 rxclko => spw_rxclk(j),
443 do => swni.d(j),
444 ndo => swni.nd(j*5+4 DOWNTO j*5),
445 dconnect => swni.dconnect(j*2+1 DOWNTO j*2));
446 END GENERATE spw_inputloop;
447
448 -- SPW core
449 sw0 : grspwm GENERIC MAP(
450 tech => apa3e,
451 hindex => 1,
452 pindex => 5,
453 paddr => 5,
454 pirq => 11,
455 sysfreq => 25000, -- CPU_FREQ
456 rmap => 1,
457 rmapcrc => 1,
458 fifosize1 => 16,
459 fifosize2 => 16,
460 rxclkbuftype => 1,
461 rxunaligned => 0,
462 rmapbufs => 4,
463 ft => 0,
464 netlist => 0,
465 ports => 2,
466 --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1
467 memtech => apa3e,
468 destkey => 2,
469 spwcore => 1
470 --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1
471 --output_type => CFG_SPW_OUTPUT, -- not used byt the spw core 1
472 --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1
473 )
474 PORT MAP(reset, clk_25, spw_rxclk(0),
475 spw_rxclk(1), spw_rxtxclk, spw_rxtxclk,
476 ahbi_m_ext, ahbo_m_ext(1), apbi_ext, apbo_ext(5),
477 swni, swno);
478
479 swni.tickin <= '0';
480 swni.rmapen <= '1';
481 swni.clkdiv10 <= "00000100"; -- 10 MHz / (4 + 1) = 10 MHz
482 swni.tickinraw <= '0';
483 swni.timein <= (OTHERS => '0');
484 swni.dcrstval <= (OTHERS => '0');
485 swni.timerrstval <= (OTHERS => '0');
486
487 -------------------------------------------------------------------------------
488 -- LFR ------------------------------------------------------------------------
489 -------------------------------------------------------------------------------
490 --lpp_lfr_1 : lpp_lfr
491 -- GENERIC MAP (
492 -- Mem_use => use_RAM,
493 -- nb_data_by_buffer_size => 32,
494 -- nb_word_by_buffer_size => 30,
495 -- nb_snapshot_param_size => 32,
496 -- delta_vector_size => 32,
497 -- delta_vector_size_f0_2 => 7, -- log2(96)
498 -- pindex => 15,
499 -- paddr => 15,
500 -- pmask => 16#fff#,
501 -- pirq_ms => 6,
502 -- pirq_wfp => 14,
503 -- hindex => 2,
504 -- top_lfr_version => X"000117") -- aa.bb.cc version
505 -- PORT MAP (
506 -- clk => clk_25,
507 -- rstn => reset,
508 -- sample_B => sample_s(2 DOWNTO 0),
509 -- sample_E => sample_s(7 DOWNTO 3),
510 -- sample_val => sample_val,
511 -- apbi => apbi_ext,
512 -- apbo => apbo_ext(15),
513 -- ahbi => ahbi_m_ext,
514 -- ahbo => ahbo_m_ext(2),
515 -- coarse_time => coarse_time,
516 -- fine_time => fine_time,
517 -- data_shaping_BW => bias_fail_sw_sig,
518 -- observation_vector_0=> observation_vector_0,
519 -- observation_vector_1 => observation_vector_1,
520 -- observation_reg => observation_reg);
521
522 lpp_lfr_apbreg_1 : lpp_lfr_apbreg_tb
523 GENERIC MAP (
524 pindex => 15,
525 paddr => 15,
526 pmask => 16#fff#)
527 PORT MAP (
528 HCLK => clk_25,
529 HRESETn => reset,
530 apbi => apbi_ext,
531 apbo => apbo_ext(15),
532
533 sample_f0_wen => sample_f0_wen,
534 sample_f1_wen => sample_f1_wen,
535 sample_f2_wen => sample_f2_wen,
536 sample_f0_wdata => sample_f0_wdata,
537 sample_f1_wdata => sample_f1_wdata,
538 sample_f2_wdata => sample_f2_wdata,
539 MEM_IN_SM_locked => MEM_IN_SM_locked,
540 MEM_IN_SM_ReUse => MEM_IN_SM_ReUse,
541 MEM_IN_SM_ren => MEM_IN_SM_ren,
542 MEM_IN_SM_rData => MEM_IN_SM_rData,
543 MEM_IN_SM_Full => MEM_IN_SM_Full_pad,
544 MEM_IN_SM_Empty => MEM_IN_SM_Empty_pad);
545
546 lpp_lfr_ms_tb_1 : lpp_lfr_ms_tb
547 GENERIC MAP (
548 Mem_use =>use_RAM)
549 PORT MAP (
550 clk => clk_25,
551 rstn => reset,
552 sample_f0_wen => sample_f0_wen,
553 sample_f0_wdata => sample_f0_wdata,
554 sample_f1_wen => sample_f1_wen,
555 sample_f1_wdata => sample_f1_wdata,
556 sample_f2_wen => sample_f2_wen,
557 sample_f2_wdata => sample_f2_wdata,
558
559 MEM_IN_SM_locked => MEM_IN_SM_locked,
560 MEM_IN_SM_ReUse => MEM_IN_SM_ReUse,
561 MEM_IN_SM_ren => MEM_IN_SM_ren,
562 MEM_IN_SM_rData => MEM_IN_SM_rData,
563 MEM_IN_SM_Full_pad => MEM_IN_SM_Full_pad,
564 MEM_IN_SM_Empty_pad => MEM_IN_SM_Empty_pad,
565
566 error_input_fifo_write => OPEN,
567 observation_vector_0 => observation_vector_0,
568 observation_vector_1 => observation_vector_1);
569
570 -----------------------------------------------------------------------------
571
572
573
574
575
576 all_sample : FOR I IN 7 DOWNTO 0 GENERATE
577 sample_s(I) <= sample(I)(11 DOWNTO 0) & '0' & '0' & '0' & '0';
578 END GENERATE all_sample;
579
580
581
582 top_ad_conv_ADS7886_v2_1 : top_ad_conv_ADS7886_v2
583 GENERIC MAP(
584 ChannelCount => 8,
585 SampleNbBits => 14,
586 ncycle_cnv_high => 40, -- at least 32 cycles at 25 MHz, 32 * 49.152 / 25 /2 = 31.5
587 ncycle_cnv => 249) -- 49 152 000 / 98304 /2
588 PORT MAP (
589 -- CONV
590 cnv_clk => clk_24,
591 cnv_rstn => reset,
592 cnv => ADC_nCS_sig,
593 -- DATA
594 clk => clk_25,
595 rstn => reset,
596 sck => ADC_CLK_sig,
597 sdo => ADC_SDO_sig,
598 -- SAMPLE
599 sample => sample,
600 sample_val => sample_val);
601
602 --IO10 <= ADC_SDO_sig(5);
603 --IO9 <= ADC_SDO_sig(4);
604 --IO8 <= ADC_SDO_sig(3);
605
606 ADC_nCS <= ADC_nCS_sig;
607 ADC_CLK <= ADC_CLK_sig;
608 ADC_SDO_sig <= ADC_SDO;
609
610 ----------------------------------------------------------------------
611 --- GPIO -----------------------------------------------------------
612 ----------------------------------------------------------------------
613
614 grgpio0 : grgpio
615 GENERIC MAP(pindex => 11, paddr => 11, imask => 16#0000#, nbits => 8)
616 PORT MAP(reset, clk_25, apbi_ext, apbo_ext(11), gpioi, gpioo);
617
618 --pio_pad_0 : iopad
619 -- GENERIC MAP (tech => CFG_PADTECH)
620 -- PORT MAP (IO0, gpioo.dout(0), gpioo.oen(0), gpioi.din(0));
621 --pio_pad_1 : iopad
622 -- GENERIC MAP (tech => CFG_PADTECH)
623 -- PORT MAP (IO1, gpioo.dout(1), gpioo.oen(1), gpioi.din(1));
624 --pio_pad_2 : iopad
625 -- GENERIC MAP (tech => CFG_PADTECH)
626 -- PORT MAP (IO2, gpioo.dout(2), gpioo.oen(2), gpioi.din(2));
627 --pio_pad_3 : iopad
628 -- GENERIC MAP (tech => CFG_PADTECH)
629 -- PORT MAP (IO3, gpioo.dout(3), gpioo.oen(3), gpioi.din(3));
630 --pio_pad_4 : iopad
631 -- GENERIC MAP (tech => CFG_PADTECH)
632 -- PORT MAP (IO4, gpioo.dout(4), gpioo.oen(4), gpioi.din(4));
633 --pio_pad_5 : iopad
634 -- GENERIC MAP (tech => CFG_PADTECH)
635 -- PORT MAP (IO5, gpioo.dout(5), gpioo.oen(5), gpioi.din(5));
636 --pio_pad_6 : iopad
637 -- GENERIC MAP (tech => CFG_PADTECH)
638 -- PORT MAP (IO6, gpioo.dout(6), gpioo.oen(6), gpioi.din(6));
639 --pio_pad_7 : iopad
640 -- GENERIC MAP (tech => CFG_PADTECH)
641 -- PORT MAP (IO7, gpioo.dout(7), gpioo.oen(7), gpioi.din(7));
642
643 PROCESS (clk_25, reset)
644 BEGIN -- PROCESS
645 IF reset = '0' THEN -- asynchronous reset (active low)
646 IO0 <= '0';
647 IO1 <= '0';
648 IO2 <= '0';
649 IO3 <= '0';
650 IO4 <= '0';
651 IO5 <= '0';
652 IO6 <= '0';
653 IO7 <= '0';
654 IO8 <= '0';
655 IO9 <= '0';
656 IO10 <= '0';
657 IO11 <= '0';
658 ELSIF clk_25'EVENT AND clk_25 = '1' THEN -- rising clock edge
659 CASE gpioo.dout(2 DOWNTO 0) IS
660 WHEN "011" =>
661 IO0 <= observation_reg(0);
662 IO1 <= observation_reg(1);
663 IO2 <= observation_reg(2);
664 IO3 <= observation_reg(3);
665 IO4 <= observation_reg(4);
666 IO5 <= observation_reg(5);
667 IO6 <= observation_reg(6);
668 IO7 <= observation_reg(7);
669 IO8 <= observation_reg(8);
670 IO9 <= observation_reg(9);
671 IO10 <= observation_reg(10);
672 IO11 <= observation_reg(11);
673 WHEN "001" =>
674 IO0 <= observation_reg(0 + 12);
675 IO1 <= observation_reg(1 + 12);
676 IO2 <= observation_reg(2 + 12);
677 IO3 <= observation_reg(3 + 12);
678 IO4 <= observation_reg(4 + 12);
679 IO5 <= observation_reg(5 + 12);
680 IO6 <= observation_reg(6 + 12);
681 IO7 <= observation_reg(7 + 12);
682 IO8 <= observation_reg(8 + 12);
683 IO9 <= observation_reg(9 + 12);
684 IO10 <= observation_reg(10 + 12);
685 IO11 <= observation_reg(11 + 12);
686 WHEN "010" =>
687 IO0 <= observation_reg(0 + 12 + 12);
688 IO1 <= observation_reg(1 + 12 + 12);
689 IO2 <= observation_reg(2 + 12 + 12);
690 IO3 <= observation_reg(3 + 12 + 12);
691 IO4 <= observation_reg(4 + 12 + 12);
692 IO5 <= observation_reg(5 + 12 + 12);
693 IO6 <= observation_reg(6 + 12 + 12);
694 IO7 <= observation_reg(7 + 12 + 12);
695 IO8 <= ADC_SDO(0) OR ADC_SDO(1) OR ADC_SDO(2);
696 IO9 <= ADC_SDO(3) OR ADC_SDO(4) OR ADC_SDO(5);
697 IO10 <= ADC_SDO(6) OR ADC_SDO(7) ;
698 IO11 <= '0';
699 WHEN "000" =>
700 IO0 <= observation_vector_0(0);
701 IO1 <= observation_vector_0(1);
702 IO2 <= observation_vector_0(2);
703 IO3 <= observation_vector_0(3);
704 IO4 <= observation_vector_0(4);
705 IO5 <= observation_vector_0(5);
706 IO6 <= observation_vector_0(6);
707 IO7 <= observation_vector_0(7);
708 IO8 <= observation_vector_0(8);
709 IO9 <= observation_vector_0(9);
710 IO10 <= observation_vector_0(10);
711 IO11 <= observation_vector_0(11);
712 WHEN "100" =>
713 IO0 <= observation_vector_1(0);
714 IO1 <= observation_vector_1(1);
715 IO2 <= observation_vector_1(2);
716 IO3 <= observation_vector_1(3);
717 IO4 <= observation_vector_1(4);
718 IO5 <= observation_vector_1(5);
719 IO6 <= observation_vector_1(6);
720 IO7 <= observation_vector_1(7);
721 IO8 <= observation_vector_1(8);
722 IO9 <= observation_vector_1(9);
723 IO10 <= observation_vector_1(10);
724 IO11 <= observation_vector_1(11);
725 WHEN OTHERS => NULL;
726 END CASE;
727
728 END IF;
729 END PROCESS;
730
731 END beh;
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1 VHDLIB=../..
2 SCRIPTSDIR=$(VHDLIB)/scripts/
3 GRLIB := $(shell sh $(VHDLIB)/scripts/lpp_relpath.sh)
4 TOP=MINI_LFR_top
5 BOARD=MINI-LFR
6 include $(VHDLIB)/boards/$(BOARD)/Makefile.inc
7 DEVICE=$(PART)-$(PACKAGE)$(SPEED)
8 UCF=$(VHDLIB)/boards/$(BOARD)/$(TOP).ucf
9 QSF=$(VHDLIB)/boards/$(BOARD)/$(TOP).qsf
10 EFFORT=high
11 XSTOPT=
12 SYNPOPT="set_option -pipe 0; set_option -retiming 0; set_option -write_apr_constraint 0"
13 VHDLSYNFILES= MINI_LFR_top.vhd lpp_lfr_apbreg.vhd lpp_lfr_ms_validation.vhd
14
15 PDC=$(VHDLIB)/boards/$(BOARD)/default.pdc
16 BITGEN=$(VHDLIB)/boards/$(BOARD)/default.ut
17 CLEAN=soft-clean
18
19 TECHLIBS = proasic3e
20
21 LIBSKIP = core1553bbc core1553brm core1553brt gr1553 corePCIF \
22 tmtc openchip hynix ihp gleichmann micron usbhc
23
24 DIRSKIP = b1553 pcif leon2 leon2ft crypto satcan ddr usb ata i2c \
25 pci grusbhc haps slink ascs pwm coremp7 spi ac97 \
26 ./amba_lcd_16x2_ctrlr \
27 ./general_purpose/lpp_AMR \
28 ./general_purpose/lpp_balise \
29 ./general_purpose/lpp_delay \
30 ./lpp_bootloader \
31 ./lpp_cna \
32 ./lpp_uart \
33 ./lpp_usb \
34 ./dsp/lpp_fft_rtax \
35 ./lpp_sim/CY7C1061DV33 \
36
37 FILESKIP =i2cmst.vhd \
38 APB_MULTI_DIODE.vhd \
39 APB_SIMPLE_DIODE.vhd \
40 Top_MatrixSpec.vhd \
41 APB_FFT.vhd
42
43 include $(GRLIB)/bin/Makefile
44 include $(GRLIB)/software/leon3/Makefile
45
46 ################## project specific targets ##########################
47
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1 LIBRARY ieee;
2 USE ieee.std_logic_1164.ALL;
3
4
5 LIBRARY lpp;
6 USE lpp.lpp_memory.ALL;
7 USE lpp.iir_filter.ALL;
8 USE lpp.spectral_matrix_package.ALL;
9 USE lpp.lpp_dma_pkg.ALL;
10 USE lpp.lpp_Header.ALL;
11 USE lpp.lpp_matrix.ALL;
12 USE lpp.lpp_matrix.ALL;
13 USE lpp.lpp_lfr_pkg.ALL;
14 USE lpp.lpp_fft.ALL;
15 USE lpp.fft_components.ALL;
16
17 ENTITY lpp_lfr_ms IS
18 GENERIC (
19 Mem_use : INTEGER := use_RAM
20 );
21 PORT (
22 clk : IN STD_LOGIC;
23 rstn : IN STD_LOGIC;
24
25 );
26 END;
27
28 ARCHITECTURE Behavioral OF lpp_lfr_ms IS
29
30 BEGIN
31
32 -----------------------------------------------------------------------------
33
34 lppFIFOxN_f0_a : lppFIFOxN
35 GENERIC MAP (
36 tech => 0,
37 Mem_use => Mem_use,
38 Data_sz => 16,
39 Addr_sz => 8,
40 FifoCnt => 5)
41 PORT MAP (
42 clk => clk,
43 rstn => rstn,
44
45 ReUse => (OTHERS => '0'),
46
47 wen => sample_f0_A_wen,
48 wdata => sample_f0_wdata,
49
50 ren => sample_f0_A_ren,
51 rdata => sample_f0_A_rdata,
52
53 empty => sample_f0_A_empty,
54 full => sample_f0_A_full,
55 almost_full => OPEN);
56
57 -----------------------------------------------------------------------------
58
59 lpp_lfr_ms_FFT_1 : lpp_lfr_ms_FFT
60 PORT MAP (
61 clk => clk,
62 rstn => rstn,
63 sample_valid => sample_valid, -- WRITE in
64 fft_read => fft_read, -- READ in
65 sample_data => sample_data, -- WRITE in
66 sample_load => sample_load, -- WRITE out
67 fft_pong => fft_pong, -- READ out
68 fft_data_im => fft_data_im, -- READ out
69 fft_data_re => fft_data_re, -- READ out
70 fft_data_valid => fft_data_valid, -- READ out
71 fft_ready => fft_ready); -- READ out
72
73 -----------------------------------------------------------------------------
74
75 END Behavioral;
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1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
19 -- Author : Jean-christophe Pellion
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 -- jean-christophe.pellion@easii-ic.com
22 ----------------------------------------------------------------------------
23 LIBRARY ieee;
24 USE ieee.std_logic_1164.ALL;
25 USE ieee.numeric_std.ALL;
26 LIBRARY grlib;
27 USE grlib.amba.ALL;
28 USE grlib.stdlib.ALL;
29 USE grlib.devices.ALL;
30 LIBRARY lpp;
31 USE lpp.lpp_lfr_pkg.ALL;
32 --USE lpp.lpp_amba.ALL;
33 USE lpp.apb_devices_list.ALL;
34 USE lpp.lpp_memory.ALL;
35 LIBRARY techmap;
36 USE techmap.gencomp.ALL;
37
38 ENTITY lpp_lfr_apbreg_tb IS
39 GENERIC (
40 pindex : INTEGER := 4;
41 paddr : INTEGER := 4;
42 pmask : INTEGER := 16#fff#);
43 PORT (
44 -- AMBA AHB system signals
45 HCLK : IN STD_ULOGIC;
46 HRESETn : IN STD_ULOGIC;
47
48 -- AMBA APB Slave Interface
49 apbi : IN apb_slv_in_type;
50 apbo : OUT apb_slv_out_type;
51
52 ---------------------------------------------------------------------------
53 sample_f0_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
54 sample_f1_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
55 sample_f2_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
56
57 sample_f0_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
58 sample_f1_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
59 sample_f2_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
60 ---------------------------------------------------------------------------
61 MEM_IN_SM_locked : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
62 MEM_IN_SM_ReUse : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
63 MEM_IN_SM_ren : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
64 MEM_IN_SM_rData : IN STD_LOGIC_VECTOR(16*2*5-1 DOWNTO 0);
65 MEM_IN_SM_Full : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
66 MEM_IN_SM_Empty : IN STD_LOGIC_VECTOR(4 DOWNTO 0)
67 ---------------------------------------------------------------------------
68 );
69
70 END lpp_lfr_apbreg_tb;
71
72 ARCHITECTURE beh OF lpp_lfr_apbreg_tb IS
73
74 CONSTANT REVISION : INTEGER := 1;
75
76 CONSTANT pconfig : apb_config_type := (
77 0 => ahb_device_reg (VENDOR_LPP, LPP_LFR, 0, REVISION, 1),
78 1 => apb_iobar(paddr, pmask));
79
80 TYPE reg_debug_fft IS RECORD
81 in_data_f0 : STD_LOGIC_VECTOR(5*16-1 DOWNTO 0);
82 in_data_f1 : STD_LOGIC_VECTOR(5*16-1 DOWNTO 0);
83 in_data_f2 : STD_LOGIC_VECTOR(5*16-1 DOWNTO 0);
84
85 in_wen_f0 : STD_LOGIC_VECTOR(4 DOWNTO 0);
86 in_wen_f1 : STD_LOGIC_VECTOR(4 DOWNTO 0);
87 in_wen_f2 : STD_LOGIC_VECTOR(4 DOWNTO 0);
88 --
89 out_reuse : STD_LOGIC_VECTOR(4 DOWNTO 0);
90 out_locked : STD_LOGIC_VECTOR(4 DOWNTO 0);
91 out_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
92 END RECORD;
93 SIGNAL reg_ftt : reg_debug_fft;
94
95 SIGNAL prdata : STD_LOGIC_VECTOR(31 DOWNTO 0);
96
97 BEGIN -- beh
98
99 ---------------------------------------------------------------------------
100 sample_f0_wen <= reg_ftt.in_wen_f0;
101 sample_f1_wen <= reg_ftt.in_wen_f1;
102 sample_f2_wen <= reg_ftt.in_wen_f2;
103
104 sample_f0_wdata <= reg_ftt.in_data_f0;
105 sample_f1_wdata <= reg_ftt.in_data_f1;
106 sample_f2_wdata <= reg_ftt.in_data_f2;
107 ---------------------------------------------------------------------------
108 MEM_IN_SM_ReUse <= reg_ftt.out_reuse;
109 MEM_IN_SM_locked <= reg_ftt.out_locked;
110 MEM_IN_SM_ren <= reg_ftt.out_ren;
111 ---------------------------------------------------------------------------
112
113 lpp_lfr_apbreg : PROCESS (HCLK, HRESETn)
114 VARIABLE paddr : STD_LOGIC_VECTOR(7 DOWNTO 2);
115 BEGIN
116 IF HRESETn = '0' THEN
117
118 reg_ftt.in_data_f0 <= (OTHERS => '0');
119 reg_ftt.in_data_f1 <= (OTHERS => '0');
120 reg_ftt.in_data_f2 <= (OTHERS => '0');
121
122 reg_ftt.in_wen_f0 <= (OTHERS => '1');
123 reg_ftt.in_wen_f1 <= (OTHERS => '1');
124 reg_ftt.in_wen_f2 <= (OTHERS => '1');
125
126
127 reg_ftt.out_reuse <= (OTHERS => '0');
128 reg_ftt.out_locked <= (OTHERS => '0');
129 reg_ftt.out_ren <= (OTHERS => '1');
130
131 ELSIF HCLK'EVENT AND HCLK = '1' THEN -- rising clock edge
132
133
134 reg_ftt.in_wen_f0 <= (OTHERS => '1');
135 reg_ftt.in_wen_f1 <= (OTHERS => '1');
136 reg_ftt.in_wen_f2 <= (OTHERS => '1');
137 reg_ftt.out_ren <= (OTHERS => '1');
138
139 paddr := "000000";
140 paddr(7 DOWNTO 2) := apbi.paddr(7 DOWNTO 2);
141 prdata <= (OTHERS => '0');
142 IF apbi.psel(pindex) = '1' THEN
143 -- APB DMA READ --
144 CASE paddr(7 DOWNTO 2) IS
145 --0
146 WHEN "000000" => prdata(31 DOWNTO 0) <= reg_ftt.in_data_f0(31 DOWNTO 0);
147 WHEN "000001" => prdata(31 DOWNTO 0) <= reg_ftt.in_data_f0(63 DOWNTO 32);
148 WHEN "000010" => prdata(15 DOWNTO 0) <= reg_ftt.in_data_f0(79 DOWNTO 64);
149 WHEN "000011" => prdata(4 DOWNTO 0) <= reg_ftt.in_wen_f0;
150
151 WHEN "000100" => prdata(31 DOWNTO 0) <= reg_ftt.in_data_f1(31 DOWNTO 0);
152 WHEN "000101" => prdata(31 DOWNTO 0) <= reg_ftt.in_data_f1(63 DOWNTO 32);
153 WHEN "000110" => prdata(15 DOWNTO 0) <= reg_ftt.in_data_f1(79 DOWNTO 64);
154 WHEN "000111" => prdata(4 DOWNTO 0) <= reg_ftt.in_wen_f1;
155
156 WHEN "001000" => prdata(31 DOWNTO 0) <= reg_ftt.in_data_f2(31 DOWNTO 0);
157 WHEN "001001" => prdata(31 DOWNTO 0) <= reg_ftt.in_data_f2(63 DOWNTO 32);
158 WHEN "001010" => prdata(15 DOWNTO 0) <= reg_ftt.in_data_f2(79 DOWNTO 64);
159 WHEN "001011" => prdata(4 DOWNTO 0) <= reg_ftt.in_wen_f2;
160
161 WHEN "001100" => prdata(31 DOWNTO 0) <= MEM_IN_SM_rData(32*1-1 DOWNTO 32*0);
162 WHEN "001101" => prdata(31 DOWNTO 0) <= MEM_IN_SM_rData(32*2-1 DOWNTO 32*1);
163 WHEN "001110" => prdata(31 DOWNTO 0) <= MEM_IN_SM_rData(32*3-1 DOWNTO 32*2);
164 WHEN "001111" => prdata(31 DOWNTO 0) <= MEM_IN_SM_rData(32*4-1 DOWNTO 32*3);
165 WHEN "010000" => prdata(31 DOWNTO 0) <= MEM_IN_SM_rData(32*5-1 DOWNTO 32*4);
166
167 WHEN "010001" => prdata(4 DOWNTO 0) <= reg_ftt.out_ren;
168 prdata(9 DOWNTO 5) <= reg_ftt.out_reuse;
169 prdata(14 DOWNTO 10) <= reg_ftt.out_locked;
170 prdata(19 DOWNTO 15) <= MEM_IN_SM_Full;
171 prdata(24 DOWNTO 20) <= MEM_IN_SM_Empty;
172 WHEN OTHERS => NULL;
173
174 END CASE;
175 IF (apbi.pwrite AND apbi.penable) = '1' THEN
176 -- APB DMA WRITE --
177 CASE paddr(7 DOWNTO 2) IS
178 WHEN "000000" => reg_ftt.in_data_f0(31 DOWNTO 0) <= apbi.pwdata;
179 WHEN "000001" => reg_ftt.in_data_f0(63 DOWNTO 32) <= apbi.pwdata;
180 WHEN "000010" => reg_ftt.in_data_f0(79 DOWNTO 64) <= apbi.pwdata(15 DOWNTO 0);
181 WHEN "000011" => reg_ftt.in_wen_f0 <= apbi.pwdata(4 DOWNTO 0);
182
183 WHEN "000100" => reg_ftt.in_data_f1(31 DOWNTO 0) <= apbi.pwdata;
184 WHEN "000101" => reg_ftt.in_data_f1(63 DOWNTO 32) <= apbi.pwdata;
185 WHEN "000110" => reg_ftt.in_data_f1(79 DOWNTO 64) <= apbi.pwdata(15 DOWNTO 0);
186 WHEN "000111" => reg_ftt.in_wen_f1 <= apbi.pwdata(4 DOWNTO 0);
187
188 WHEN "001000" => reg_ftt.in_data_f2(31 DOWNTO 0) <= apbi.pwdata;
189 WHEN "001001" => reg_ftt.in_data_f2(63 DOWNTO 32) <= apbi.pwdata;
190 WHEN "001010" => reg_ftt.in_data_f2(79 DOWNTO 64) <= apbi.pwdata(15 DOWNTO 0);
191 WHEN "001011" => reg_ftt.in_wen_f2 <= apbi.pwdata(4 DOWNTO 0);
192
193 WHEN "010001" => reg_ftt.out_ren <= apbi.pwdata(4 DOWNTO 0);
194 reg_ftt.out_reuse <= apbi.pwdata(9 DOWNTO 5);
195 reg_ftt.out_locked <= apbi.pwdata(14 DOWNTO 10);
196
197 WHEN OTHERS => NULL;
198 END CASE;
199 END IF;
200 END IF;
201
202 END IF;
203 END PROCESS lpp_lfr_apbreg;
204
205 apbo.pindex <= pindex;
206 apbo.pconfig <= pconfig;
207 apbo.prdata <= prdata;
208
209 END beh;
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@@ -0,0 +1,209
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
19 -- Author : Jean-christophe Pellion
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 -- jean-christophe.pellion@easii-ic.com
22 ----------------------------------------------------------------------------
23 LIBRARY ieee;
24 USE ieee.std_logic_1164.ALL;
25 USE ieee.numeric_std.ALL;
26 LIBRARY grlib;
27 USE grlib.amba.ALL;
28 USE grlib.stdlib.ALL;
29 USE grlib.devices.ALL;
30 LIBRARY lpp;
31 USE lpp.lpp_lfr_pkg.ALL;
32 --USE lpp.lpp_amba.ALL;
33 USE lpp.apb_devices_list.ALL;
34 USE lpp.lpp_memory.ALL;
35 LIBRARY techmap;
36 USE techmap.gencomp.ALL;
37
38 ENTITY lpp_lfr_apbreg_tb IS
39 GENERIC (
40 pindex : INTEGER := 4;
41 paddr : INTEGER := 4;
42 pmask : INTEGER := 16#fff#);
43 PORT (
44 -- AMBA AHB system signals
45 HCLK : IN STD_ULOGIC;
46 HRESETn : IN STD_ULOGIC;
47
48 -- AMBA APB Slave Interface
49 apbi : IN apb_slv_in_type;
50 apbo : OUT apb_slv_out_type;
51
52 ---------------------------------------------------------------------------
53 sample_f0_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
54 sample_f1_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
55 sample_f2_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
56
57 sample_f0_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
58 sample_f1_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
59 sample_f2_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
60 ---------------------------------------------------------------------------
61 MEM_IN_SM_locked : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
62 MEM_IN_SM_ReUse : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
63 MEM_IN_SM_ren : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
64 MEM_IN_SM_rData : IN STD_LOGIC_VECTOR(16*2*5-1 DOWNTO 0);
65 MEM_IN_SM_Full : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
66 MEM_IN_SM_Empty : IN STD_LOGIC_VECTOR(4 DOWNTO 0)
67 ---------------------------------------------------------------------------
68 );
69
70 END lpp_lfr_apbreg_tb;
71
72 ARCHITECTURE beh OF lpp_lfr_apbreg_tb IS
73
74 CONSTANT REVISION : INTEGER := 1;
75
76 CONSTANT pconfig : apb_config_type := (
77 0 => ahb_device_reg (VENDOR_LPP, LPP_LFR, 0, REVISION, 1),
78 1 => apb_iobar(paddr, pmask));
79
80 TYPE reg_debug_fft IS RECORD
81 in_data_f0 : STD_LOGIC_VECTOR(5*16-1 DOWNTO 0);
82 in_data_f1 : STD_LOGIC_VECTOR(5*16-1 DOWNTO 0);
83 in_data_f2 : STD_LOGIC_VECTOR(5*16-1 DOWNTO 0);
84
85 in_wen_f0 : STD_LOGIC_VECTOR(4 DOWNTO 0);
86 in_wen_f1 : STD_LOGIC_VECTOR(4 DOWNTO 0);
87 in_wen_f2 : STD_LOGIC_VECTOR(4 DOWNTO 0);
88 --
89 out_reuse : STD_LOGIC_VECTOR(4 DOWNTO 0);
90 out_locked : STD_LOGIC_VECTOR(4 DOWNTO 0);
91 out_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
92 END RECORD;
93 SIGNAL reg_ftt : reg_debug_fft;
94
95 SIGNAL prdata : STD_LOGIC_VECTOR(31 DOWNTO 0);
96
97 BEGIN -- beh
98
99 ---------------------------------------------------------------------------
100 sample_f0_wen <= reg_ftt.in_wen_f0;
101 sample_f1_wen <= reg_ftt.in_wen_f1;
102 sample_f2_wen <= reg_ftt.in_wen_f2;
103
104 sample_f0_wdata <= reg_ftt.in_data_f0;
105 sample_f1_wdata <= reg_ftt.in_data_f1;
106 sample_f2_wdata <= reg_ftt.in_data_f2;
107 ---------------------------------------------------------------------------
108 MEM_IN_SM_ReUse <= reg_ftt.out_reuse;
109 MEM_IN_SM_locked <= reg_ftt.out_locked;
110 MEM_IN_SM_ren <= reg_ftt.out_ren;
111 ---------------------------------------------------------------------------
112
113 lpp_lfr_apbreg : PROCESS (HCLK, HRESETn)
114 VARIABLE paddr : STD_LOGIC_VECTOR(7 DOWNTO 2);
115 BEGIN
116 IF HRESETn = '0' THEN
117
118 reg_ftt.in_data_f0 <= (OTHERS => '0');
119 reg_ftt.in_data_f1 <= (OTHERS => '0');
120 reg_ftt.in_data_f2 <= (OTHERS => '0');
121
122 reg_ftt.in_wen_f0 <= (OTHERS => '1');
123 reg_ftt.in_wen_f1 <= (OTHERS => '1');
124 reg_ftt.in_wen_f2 <= (OTHERS => '1');
125
126
127 reg_ftt.out_reuse <= (OTHERS => '0');
128 reg_ftt.out_locked <= (OTHERS => '0');
129 reg_ftt.out_ren <= (OTHERS => '1');
130
131 ELSIF HCLK'EVENT AND HCLK = '1' THEN -- rising clock edge
132
133
134 reg_ftt.in_wen_f0 <= (OTHERS => '1');
135 reg_ftt.in_wen_f1 <= (OTHERS => '1');
136 reg_ftt.in_wen_f2 <= (OTHERS => '1');
137 reg_ftt.out_ren <= (OTHERS => '1');
138
139 paddr := "000000";
140 paddr(7 DOWNTO 2) := apbi.paddr(7 DOWNTO 2);
141 prdata <= (OTHERS => '0');
142 IF apbi.psel(pindex) = '1' THEN
143 -- APB DMA READ --
144 CASE paddr(7 DOWNTO 2) IS
145 --0
146 WHEN "000000" => prdata(31 DOWNTO 0) <= reg_ftt.in_data_f0(31 DOWNTO 0);
147 WHEN "000001" => prdata(31 DOWNTO 0) <= reg_ftt.in_data_f0(63 DOWNTO 32);
148 WHEN "000010" => prdata(15 DOWNTO 0) <= reg_ftt.in_data_f0(79 DOWNTO 64);
149 WHEN "000011" => prdata(4 DOWNTO 0) <= reg_ftt.in_wen_f0;
150
151 WHEN "000100" => prdata(31 DOWNTO 0) <= reg_ftt.in_data_f1(31 DOWNTO 0);
152 WHEN "000101" => prdata(31 DOWNTO 0) <= reg_ftt.in_data_f1(63 DOWNTO 32);
153 WHEN "000110" => prdata(15 DOWNTO 0) <= reg_ftt.in_data_f1(79 DOWNTO 64);
154 WHEN "000111" => prdata(4 DOWNTO 0) <= reg_ftt.in_wen_f1;
155
156 WHEN "001000" => prdata(31 DOWNTO 0) <= reg_ftt.in_data_f2(31 DOWNTO 0);
157 WHEN "001001" => prdata(31 DOWNTO 0) <= reg_ftt.in_data_f2(63 DOWNTO 32);
158 WHEN "001010" => prdata(15 DOWNTO 0) <= reg_ftt.in_data_f2(79 DOWNTO 64);
159 WHEN "001011" => prdata(4 DOWNTO 0) <= reg_ftt.in_wen_f2;
160
161 WHEN "001100" => prdata(31 DOWNTO 0) <= MEM_IN_SM_rData(32*1-1 DOWNTO 32*0);
162 WHEN "001101" => prdata(31 DOWNTO 0) <= MEM_IN_SM_rData(32*2-1 DOWNTO 32*1);
163 WHEN "001110" => prdata(31 DOWNTO 0) <= MEM_IN_SM_rData(32*3-1 DOWNTO 32*2);
164 WHEN "001111" => prdata(31 DOWNTO 0) <= MEM_IN_SM_rData(32*4-1 DOWNTO 32*3);
165 WHEN "010000" => prdata(31 DOWNTO 0) <= MEM_IN_SM_rData(32*5-1 DOWNTO 32*4);
166
167 WHEN "010001" => prdata(4 DOWNTO 0) <= reg_ftt.out_ren;
168 prdata(9 DOWNTO 5) <= reg_ftt.out_reuse;
169 prdata(14 DOWNTO 10) <= reg_ftt.out_locked;
170 prdata(19 DOWNTO 15) <= MEM_IN_SM_Full;
171 prdata(24 DOWNTO 20) <= MEM_IN_SM_Empty;
172 WHEN OTHERS => NULL;
173
174 END CASE;
175 IF (apbi.pwrite AND apbi.penable) = '1' THEN
176 -- APB DMA WRITE --
177 CASE paddr(7 DOWNTO 2) IS
178 WHEN "000000" => reg_ftt.in_data_f0(31 DOWNTO 0) <= apbi.pwdata;
179 WHEN "000001" => reg_ftt.in_data_f0(63 DOWNTO 32) <= apbi.pwdata;
180 WHEN "000010" => reg_ftt.in_data_f0(79 DOWNTO 64) <= apbi.pwdata(15 DOWNTO 0);
181 WHEN "000011" => reg_ftt.in_wen_f0 <= apbi.pwdata(4 DOWNTO 0);
182
183 WHEN "000100" => reg_ftt.in_data_f1(31 DOWNTO 0) <= apbi.pwdata;
184 WHEN "000101" => reg_ftt.in_data_f1(63 DOWNTO 32) <= apbi.pwdata;
185 WHEN "000110" => reg_ftt.in_data_f1(79 DOWNTO 64) <= apbi.pwdata(15 DOWNTO 0);
186 WHEN "000111" => reg_ftt.in_wen_f1 <= apbi.pwdata(4 DOWNTO 0);
187
188 WHEN "001000" => reg_ftt.in_data_f2(31 DOWNTO 0) <= apbi.pwdata;
189 WHEN "001001" => reg_ftt.in_data_f2(63 DOWNTO 32) <= apbi.pwdata;
190 WHEN "001010" => reg_ftt.in_data_f2(79 DOWNTO 64) <= apbi.pwdata(15 DOWNTO 0);
191 WHEN "001011" => reg_ftt.in_wen_f2 <= apbi.pwdata(4 DOWNTO 0);
192
193 WHEN "010001" => reg_ftt.out_ren <= apbi.pwdata(4 DOWNTO 0);
194 reg_ftt.out_reuse <= apbi.pwdata(9 DOWNTO 5);
195 reg_ftt.out_locked <= apbi.pwdata(14 DOWNTO 10);
196
197 WHEN OTHERS => NULL;
198 END CASE;
199 END IF;
200 END IF;
201
202 END IF;
203 END PROCESS lpp_lfr_apbreg;
204
205 apbo.pindex <= pindex;
206 apbo.pconfig <= pconfig;
207 apbo.prdata <= prdata;
208
209 END beh;
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1 LIBRARY ieee;
2 USE ieee.std_logic_1164.ALL;
3
4
5 LIBRARY lpp;
6 USE lpp.lpp_memory.ALL;
7 USE lpp.iir_filter.ALL;
8 USE lpp.spectral_matrix_package.ALL;
9 USE lpp.lpp_dma_pkg.ALL;
10 USE lpp.lpp_Header.ALL;
11 USE lpp.lpp_matrix.ALL;
12 USE lpp.lpp_matrix.ALL;
13 USE lpp.lpp_lfr_pkg.ALL;
14 USE lpp.lpp_fft.ALL;
15 USE lpp.fft_components.ALL;
16
17 ENTITY lpp_lfr_ms_tb IS
18 GENERIC (
19 Mem_use : INTEGER := use_RAM
20 );
21 PORT (
22 clk : IN STD_LOGIC;
23 rstn : IN STD_LOGIC;
24
25 ---------------------------------------------------------------------------
26 --
27 ---------------------------------------------------------------------------
28 sample_f0_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
29 sample_f0_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
30 --
31 sample_f1_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
32 sample_f1_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
33 --
34 sample_f2_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
35 sample_f2_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
36
37
38 ---------------------------------------------------------------------------
39 --
40 ---------------------------------------------------------------------------
41 MEM_IN_SM_locked : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
42 MEM_IN_SM_ReUse : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
43 MEM_IN_SM_ren : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
44 MEM_IN_SM_rData : OUT STD_LOGIC_VECTOR(16*2*5-1 DOWNTO 0);
45 MEM_IN_SM_Full_pad : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
46 MEM_IN_SM_Empty_pad : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
47
48
49 ---------------------------------------------------------------------------
50 --
51 ---------------------------------------------------------------------------
52 error_input_fifo_write : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
53 --
54 observation_vector_0: OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
55 observation_vector_1: OUT STD_LOGIC_VECTOR(11 DOWNTO 0)
56 );
57 END;
58
59 ARCHITECTURE Behavioral OF lpp_lfr_ms_tb IS
60
61 SIGNAL sample_f0_A_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
62 SIGNAL sample_f0_A_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
63 SIGNAL sample_f0_A_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
64 SIGNAL sample_f0_A_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
65 SIGNAL sample_f0_A_empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
66
67 SIGNAL sample_f0_B_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
68 SIGNAL sample_f0_B_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
69 SIGNAL sample_f0_B_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
70 SIGNAL sample_f0_B_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
71 SIGNAL sample_f0_B_empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
72
73 SIGNAL sample_f1_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
74 SIGNAL sample_f1_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
75 SIGNAL sample_f1_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
76 SIGNAL sample_f1_empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
77
78 SIGNAL sample_f1_almost_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
79
80 SIGNAL sample_f2_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
81 SIGNAL sample_f2_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
82 SIGNAL sample_f2_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
83 SIGNAL sample_f2_empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
84
85 SIGNAL error_wen_f0 : STD_LOGIC;
86 SIGNAL error_wen_f1 : STD_LOGIC;
87 SIGNAL error_wen_f2 : STD_LOGIC;
88
89 SIGNAL one_sample_f1_full : STD_LOGIC;
90 SIGNAL one_sample_f1_wen : STD_LOGIC;
91 SIGNAL one_sample_f2_full : STD_LOGIC;
92 SIGNAL one_sample_f2_wen : STD_LOGIC;
93
94 -----------------------------------------------------------------------------
95 -- FSM / SWITCH SELECT CHANNEL
96 -----------------------------------------------------------------------------
97 TYPE fsm_select_channel IS (IDLE, SWITCH_F0_A, SWITCH_F0_B, SWITCH_F1, SWITCH_F2);
98 SIGNAL state_fsm_select_channel : fsm_select_channel;
99 SIGNAL pre_state_fsm_select_channel : fsm_select_channel;
100
101 SIGNAL sample_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
102 SIGNAL sample_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
103 SIGNAL sample_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
104 SIGNAL sample_empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
105
106 -----------------------------------------------------------------------------
107 -- FSM LOAD FFT
108 -----------------------------------------------------------------------------
109 TYPE fsm_load_FFT IS (IDLE, FIFO_1, FIFO_2, FIFO_3, FIFO_4, FIFO_5);
110 SIGNAL state_fsm_load_FFT : fsm_load_FFT;
111 SIGNAL next_state_fsm_load_FFT : fsm_load_FFT;
112
113 SIGNAL sample_ren_s : STD_LOGIC_VECTOR(4 DOWNTO 0);
114 SIGNAL sample_load : STD_LOGIC;
115 SIGNAL sample_valid : STD_LOGIC;
116 SIGNAL sample_valid_r : STD_LOGIC;
117 SIGNAL sample_data : STD_LOGIC_VECTOR(15 DOWNTO 0);
118
119
120 -----------------------------------------------------------------------------
121 -- FFT
122 -----------------------------------------------------------------------------
123 SIGNAL fft_read : STD_LOGIC;
124 SIGNAL fft_pong : STD_LOGIC;
125 SIGNAL fft_data_im : STD_LOGIC_VECTOR(15 DOWNTO 0);
126 SIGNAL fft_data_re : STD_LOGIC_VECTOR(15 DOWNTO 0);
127 SIGNAL fft_data_valid : STD_LOGIC;
128 SIGNAL fft_ready : STD_LOGIC;
129 -----------------------------------------------------------------------------
130 -- SIGNAL fft_linker_ReUse : STD_LOGIC_VECTOR(4 DOWNTO 0);
131 -----------------------------------------------------------------------------
132 TYPE fsm_load_MS_memory IS (IDLE, LOAD_FIFO, TRASH_FFT);
133 SIGNAL state_fsm_load_MS_memory : fsm_load_MS_memory;
134 SIGNAL current_fifo_load : STD_LOGIC_VECTOR(4 DOWNTO 0);
135 SIGNAL current_fifo_empty : STD_LOGIC;
136 SIGNAL current_fifo_locked : STD_LOGIC;
137 SIGNAL current_fifo_full : STD_LOGIC;
138 -- SIGNAL MEM_IN_SM_locked : STD_LOGIC_VECTOR(4 DOWNTO 0);
139
140 -----------------------------------------------------------------------------
141 -- SIGNAL MEM_IN_SM_ReUse : STD_LOGIC_VECTOR(4 DOWNTO 0);
142 SIGNAL MEM_IN_SM_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
143 SIGNAL MEM_IN_SM_wen_s : STD_LOGIC_VECTOR(4 DOWNTO 0);
144 SIGNAL MEM_IN_SM_wData : STD_LOGIC_VECTOR(16*2*5-1 DOWNTO 0);
145
146 -- SIGNAL MEM_IN_SM_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
147 -- SIGNAL MEM_IN_SM_rData : STD_LOGIC_VECTOR(16*2*5-1 DOWNTO 0);
148 SIGNAL MEM_IN_SM_Full : STD_LOGIC_VECTOR(4 DOWNTO 0);
149 SIGNAL MEM_IN_SM_Empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
150 -----------------------------------------------------------------------------
151 SIGNAL SM_in_data : STD_LOGIC_VECTOR(32*2-1 DOWNTO 0);
152 SIGNAL SM_in_ren : STD_LOGIC_VECTOR(1 DOWNTO 0);
153 SIGNAL SM_in_empty : STD_LOGIC_VECTOR(1 DOWNTO 0);
154
155 SIGNAL SM_correlation_start : STD_LOGIC;
156 SIGNAL SM_correlation_auto : STD_LOGIC;
157 SIGNAL SM_correlation_done : STD_LOGIC;
158 SIGNAL SM_correlation_done_reg1 : STD_LOGIC;
159 SIGNAL SM_correlation_done_reg2 : STD_LOGIC;
160 SIGNAL SM_correlation_done_reg3 : STD_LOGIC;
161 SIGNAL SM_correlation_begin : STD_LOGIC;
162
163 SIGNAL MEM_OUT_SM_Full_s : STD_LOGIC;
164 SIGNAL MEM_OUT_SM_Data_in_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
165 SIGNAL MEM_OUT_SM_Write_s : STD_LOGIC;
166
167 SIGNAL current_matrix_write : STD_LOGIC;
168 SIGNAL current_matrix_wait_empty : STD_LOGIC;
169 -----------------------------------------------------------------------------
170 SIGNAL fifo_0_ready : STD_LOGIC;
171 SIGNAL fifo_1_ready : STD_LOGIC;
172 SIGNAL fifo_ongoing : STD_LOGIC;
173
174 SIGNAL FSM_DMA_fifo_ren : STD_LOGIC;
175 SIGNAL FSM_DMA_fifo_empty : STD_LOGIC;
176 SIGNAL FSM_DMA_fifo_data : STD_LOGIC_VECTOR(31 DOWNTO 0);
177 SIGNAL FSM_DMA_fifo_status : STD_LOGIC_VECTOR(53 DOWNTO 0);
178 -----------------------------------------------------------------------------
179 SIGNAL MEM_OUT_SM_Write : STD_LOGIC_VECTOR(1 DOWNTO 0);
180 SIGNAL MEM_OUT_SM_Read : STD_LOGIC_VECTOR(1 DOWNTO 0);
181 SIGNAL MEM_OUT_SM_Data_in : STD_LOGIC_VECTOR(63 DOWNTO 0);
182 SIGNAL MEM_OUT_SM_Data_out : STD_LOGIC_VECTOR(63 DOWNTO 0);
183 SIGNAL MEM_OUT_SM_Full : STD_LOGIC_VECTOR(1 DOWNTO 0);
184 SIGNAL MEM_OUT_SM_Empty : STD_LOGIC_VECTOR(1 DOWNTO 0);
185
186 -----------------------------------------------------------------------------
187 -- TIME REG & INFOs
188 -----------------------------------------------------------------------------
189 SIGNAL all_time : STD_LOGIC_VECTOR(47 DOWNTO 0);
190
191 SIGNAL f_empty : STD_LOGIC_VECTOR(3 DOWNTO 0);
192 SIGNAL f_empty_reg : STD_LOGIC_VECTOR(3 DOWNTO 0);
193 SIGNAL time_update_f : STD_LOGIC_VECTOR(3 DOWNTO 0);
194 SIGNAL time_reg_f : STD_LOGIC_VECTOR(48*4-1 DOWNTO 0);
195
196 SIGNAL time_reg_f0_A : STD_LOGIC_VECTOR(47 DOWNTO 0);
197 SIGNAL time_reg_f0_B : STD_LOGIC_VECTOR(47 DOWNTO 0);
198 SIGNAL time_reg_f1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
199 SIGNAL time_reg_f2 : STD_LOGIC_VECTOR(47 DOWNTO 0);
200
201 --SIGNAL time_update_f0_A : STD_LOGIC;
202 --SIGNAL time_update_f0_B : STD_LOGIC;
203 --SIGNAL time_update_f1 : STD_LOGIC;
204 --SIGNAL time_update_f2 : STD_LOGIC;
205 --
206 SIGNAL status_channel : STD_LOGIC_VECTOR(49 DOWNTO 0);
207 SIGNAL status_MS_input : STD_LOGIC_VECTOR(49 DOWNTO 0);
208 SIGNAL status_component : STD_LOGIC_VECTOR(53 DOWNTO 0);
209
210 SIGNAL status_component_fifo_0 : STD_LOGIC_VECTOR(53 DOWNTO 0);
211 SIGNAL status_component_fifo_1 : STD_LOGIC_VECTOR(53 DOWNTO 0);
212 SIGNAL status_component_fifo_0_end : STD_LOGIC;
213 SIGNAL status_component_fifo_1_end : STD_LOGIC;
214 -----------------------------------------------------------------------------
215 SIGNAL fft_ongoing_counter : STD_LOGIC;--_VECTOR(1 DOWNTO 0);
216
217 SIGNAL fft_ready_reg : STD_LOGIC;
218 SIGNAL fft_ready_rising_down : STD_LOGIC;
219
220 SIGNAL sample_load_reg : STD_LOGIC;
221 SIGNAL sample_load_rising_down : STD_LOGIC;
222
223 -----------------------------------------------------------------------------
224 SIGNAL sample_f1_wen_head : STD_LOGIC_VECTOR(4 DOWNTO 0);
225 SIGNAL sample_f1_wen_head_in : STD_LOGIC;
226 SIGNAL sample_f1_wen_head_out : STD_LOGIC;
227 SIGNAL sample_f1_full_head_in : STD_LOGIC;
228 SIGNAL sample_f1_full_head_out : STD_LOGIC;
229 SIGNAL sample_f1_empty_head_in : STD_LOGIC;
230
231 SIGNAL sample_f1_wdata_head : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
232
233 BEGIN
234
235
236 error_input_fifo_write <= error_wen_f2 & error_wen_f1 & error_wen_f0;
237
238
239 switch_f0_inst : spectral_matrix_switch_f0
240 PORT MAP (
241 clk => clk,
242 rstn => rstn,
243
244 sample_wen => sample_f0_wen,
245
246 fifo_A_empty => sample_f0_A_empty,
247 fifo_A_full => sample_f0_A_full,
248 fifo_A_wen => sample_f0_A_wen,
249
250 fifo_B_empty => sample_f0_B_empty,
251 fifo_B_full => sample_f0_B_full,
252 fifo_B_wen => sample_f0_B_wen,
253
254 error_wen => error_wen_f0); -- TODO
255
256 -----------------------------------------------------------------------------
257 -- FIFO IN
258 -----------------------------------------------------------------------------
259 lppFIFOxN_f0_a : lppFIFOxN
260 GENERIC MAP (
261 tech => 0,
262 Mem_use => Mem_use,
263 Data_sz => 16,
264 Addr_sz => 8,
265 FifoCnt => 5)
266 PORT MAP (
267 clk => clk,
268 rstn => rstn,
269
270 ReUse => (OTHERS => '0'),
271
272 wen => sample_f0_A_wen,
273 wdata => sample_f0_wdata,
274
275 ren => sample_f0_A_ren,
276 rdata => sample_f0_A_rdata,
277
278 empty => sample_f0_A_empty,
279 full => sample_f0_A_full,
280 almost_full => OPEN);
281
282 lppFIFOxN_f0_b : lppFIFOxN
283 GENERIC MAP (
284 tech => 0,
285 Mem_use => Mem_use,
286 Data_sz => 16,
287 Addr_sz => 8,
288 FifoCnt => 5)
289 PORT MAP (
290 clk => clk,
291 rstn => rstn,
292
293 ReUse => (OTHERS => '0'),
294
295 wen => sample_f0_B_wen,
296 wdata => sample_f0_wdata,
297 ren => sample_f0_B_ren,
298 rdata => sample_f0_B_rdata,
299 empty => sample_f0_B_empty,
300 full => sample_f0_B_full,
301 almost_full => OPEN);
302
303 -----------------------------------------------------------------------------
304 -- sample_f1_wen in
305 -- sample_f1_wdata in
306 -- sample_f1_full OUT
307
308 sample_f1_wen_head_in <= '0' WHEN sample_f1_wen = "00000" ELSE '1';
309 sample_f1_full_head_in <= '0' WHEN sample_f1_full = "00000" ELSE '1';
310 sample_f1_empty_head_in <= '1' WHEN sample_f1_empty = "11111" ELSE '0';
311
312 lpp_lfr_ms_reg_head_1:lpp_lfr_ms_reg_head
313 PORT MAP (
314 clk => clk,
315 rstn => rstn,
316 in_wen => sample_f1_wen_head_in,
317 in_data => sample_f1_wdata,
318 in_full => sample_f1_full_head_in,
319 in_empty => sample_f1_empty_head_in,
320 out_wen => sample_f1_wen_head_out,
321 out_data => sample_f1_wdata_head,
322 out_full => sample_f1_full_head_out);
323
324 sample_f1_wen_head <= sample_f1_wen_head_out & sample_f1_wen_head_out & sample_f1_wen_head_out & sample_f1_wen_head_out & sample_f1_wen_head_out;
325
326
327 lppFIFOxN_f1 : lppFIFOxN
328 GENERIC MAP (
329 tech => 0,
330 Mem_use => Mem_use,
331 Data_sz => 16,
332 Addr_sz => 8,
333 FifoCnt => 5)
334 PORT MAP (
335 clk => clk,
336 rstn => rstn,
337
338 ReUse => (OTHERS => '0'),
339
340 wen => sample_f1_wen_head,
341 wdata => sample_f1_wdata_head,
342 ren => sample_f1_ren,
343 rdata => sample_f1_rdata,
344 empty => sample_f1_empty,
345 full => sample_f1_full,
346 almost_full => sample_f1_almost_full);
347
348
349 one_sample_f1_wen <= '0' WHEN sample_f1_wen = "11111" ELSE '1';
350
351 PROCESS (clk, rstn)
352 BEGIN -- PROCESS
353 IF rstn = '0' THEN -- asynchronous reset (active low)
354 one_sample_f1_full <= '0';
355 error_wen_f1 <= '0';
356 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
357 IF sample_f1_full_head_out = '0' THEN
358 one_sample_f1_full <= '0';
359 ELSE
360 one_sample_f1_full <= '1';
361 END IF;
362 error_wen_f1 <= one_sample_f1_wen AND one_sample_f1_full;
363 END IF;
364 END PROCESS;
365
366 -----------------------------------------------------------------------------
367
368
369 lppFIFOxN_f2 : lppFIFOxN
370 GENERIC MAP (
371 tech => 0,
372 Mem_use => Mem_use,
373 Data_sz => 16,
374 Addr_sz => 8,
375 FifoCnt => 5)
376 PORT MAP (
377 clk => clk,
378 rstn => rstn,
379
380 ReUse => (OTHERS => '0'),
381
382 wen => sample_f2_wen,
383 wdata => sample_f2_wdata,
384 ren => sample_f2_ren,
385 rdata => sample_f2_rdata,
386 empty => sample_f2_empty,
387 full => sample_f2_full,
388 almost_full => OPEN);
389
390
391 one_sample_f2_wen <= '0' WHEN sample_f2_wen = "11111" ELSE '1';
392
393 PROCESS (clk, rstn)
394 BEGIN -- PROCESS
395 IF rstn = '0' THEN -- asynchronous reset (active low)
396 one_sample_f2_full <= '0';
397 error_wen_f2 <= '0';
398 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
399 IF sample_f2_full = "00000" THEN
400 one_sample_f2_full <= '0';
401 ELSE
402 one_sample_f2_full <= '1';
403 END IF;
404 error_wen_f2 <= one_sample_f2_wen AND one_sample_f2_full;
405 END IF;
406 END PROCESS;
407
408 -----------------------------------------------------------------------------
409 -- FSM SELECT CHANNEL
410 -----------------------------------------------------------------------------
411 PROCESS (clk, rstn)
412 BEGIN
413 IF rstn = '0' THEN
414 state_fsm_select_channel <= IDLE;
415 ELSIF clk'EVENT AND clk = '1' THEN
416 CASE state_fsm_select_channel IS
417 WHEN IDLE =>
418 IF sample_f1_full = "11111" THEN
419 state_fsm_select_channel <= SWITCH_F1;
420 ELSIF sample_f1_almost_full = "00000" THEN
421 IF sample_f0_A_full = "11111" THEN
422 state_fsm_select_channel <= SWITCH_F0_A;
423 ELSIF sample_f0_B_full = "11111" THEN
424 state_fsm_select_channel <= SWITCH_F0_B;
425 ELSIF sample_f2_full = "11111" THEN
426 state_fsm_select_channel <= SWITCH_F2;
427 END IF;
428 END IF;
429
430 WHEN SWITCH_F0_A =>
431 IF sample_f0_A_empty = "11111" THEN
432 state_fsm_select_channel <= IDLE;
433 END IF;
434 WHEN SWITCH_F0_B =>
435 IF sample_f0_B_empty = "11111" THEN
436 state_fsm_select_channel <= IDLE;
437 END IF;
438 WHEN SWITCH_F1 =>
439 IF sample_f1_empty = "11111" THEN
440 state_fsm_select_channel <= IDLE;
441 END IF;
442 WHEN SWITCH_F2 =>
443 IF sample_f2_empty = "11111" THEN
444 state_fsm_select_channel <= IDLE;
445 END IF;
446 WHEN OTHERS => NULL;
447 END CASE;
448
449 END IF;
450 END PROCESS;
451
452 PROCESS (clk, rstn)
453 BEGIN
454 IF rstn = '0' THEN
455 pre_state_fsm_select_channel <= IDLE;
456 ELSIF clk'EVENT AND clk = '1' THEN
457 pre_state_fsm_select_channel <= state_fsm_select_channel;
458 END IF;
459 END PROCESS;
460
461
462 -----------------------------------------------------------------------------
463 -- SWITCH SELECT CHANNEL
464 -----------------------------------------------------------------------------
465 sample_empty <= sample_f0_A_empty WHEN state_fsm_select_channel = SWITCH_F0_A ELSE
466 sample_f0_B_empty WHEN state_fsm_select_channel = SWITCH_F0_B ELSE
467 sample_f1_empty WHEN state_fsm_select_channel = SWITCH_F1 ELSE
468 sample_f2_empty WHEN state_fsm_select_channel = SWITCH_F2 ELSE
469 (OTHERS => '1');
470
471 sample_full <= sample_f0_A_full WHEN state_fsm_select_channel = SWITCH_F0_A ELSE
472 sample_f0_B_full WHEN state_fsm_select_channel = SWITCH_F0_B ELSE
473 sample_f1_full WHEN state_fsm_select_channel = SWITCH_F1 ELSE
474 sample_f2_full WHEN state_fsm_select_channel = SWITCH_F2 ELSE
475 (OTHERS => '0');
476
477 sample_rdata <= sample_f0_A_rdata WHEN pre_state_fsm_select_channel = SWITCH_F0_A ELSE
478 sample_f0_B_rdata WHEN pre_state_fsm_select_channel = SWITCH_F0_B ELSE
479 sample_f1_rdata WHEN pre_state_fsm_select_channel = SWITCH_F1 ELSE
480 sample_f2_rdata; -- WHEN state_fsm_select_channel = SWITCH_F2 ELSE
481
482
483 sample_f0_A_ren <= sample_ren WHEN state_fsm_select_channel = SWITCH_F0_A ELSE (OTHERS => '1');
484 sample_f0_B_ren <= sample_ren WHEN state_fsm_select_channel = SWITCH_F0_B ELSE (OTHERS => '1');
485 sample_f1_ren <= sample_ren WHEN state_fsm_select_channel = SWITCH_F1 ELSE (OTHERS => '1');
486 sample_f2_ren <= sample_ren WHEN state_fsm_select_channel = SWITCH_F2 ELSE (OTHERS => '1');
487
488
489 status_channel <= time_reg_f0_A & "00" WHEN state_fsm_select_channel = SWITCH_F0_A ELSE
490 time_reg_f0_B & "00" WHEN state_fsm_select_channel = SWITCH_F0_B ELSE
491 time_reg_f1 & "01" WHEN state_fsm_select_channel = SWITCH_F1 ELSE
492 time_reg_f2 & "10"; -- WHEN state_fsm_select_channel = SWITCH_F2
493
494 -----------------------------------------------------------------------------
495 -- FSM LOAD FFT
496 -----------------------------------------------------------------------------
497
498 sample_ren <= (OTHERS => '1') WHEN fft_ongoing_counter = '1' ELSE
499 sample_ren_s WHEN sample_load = '1' ELSE
500 (OTHERS => '1');
501
502 PROCESS (clk, rstn)
503 BEGIN
504 IF rstn = '0' THEN
505 sample_ren_s <= (OTHERS => '1');
506 state_fsm_load_FFT <= IDLE;
507 status_MS_input <= (OTHERS => '0');
508 --next_state_fsm_load_FFT <= IDLE;
509 --sample_valid <= '0';
510 ELSIF clk'EVENT AND clk = '1' THEN
511 CASE state_fsm_load_FFT IS
512 WHEN IDLE =>
513 --sample_valid <= '0';
514 sample_ren_s <= (OTHERS => '1');
515 IF sample_full = "11111" AND sample_load = '1' THEN
516 state_fsm_load_FFT <= FIFO_1;
517 status_MS_input <= status_channel;
518 END IF;
519
520 WHEN FIFO_1 =>
521 sample_ren_s <= "1111" & NOT(sample_load);
522 IF sample_empty(0) = '1' THEN
523 sample_ren_s <= (OTHERS => '1');
524 state_fsm_load_FFT <= FIFO_2;
525 END IF;
526
527 WHEN FIFO_2 =>
528 sample_ren_s <= "111" & NOT(sample_load) & '1';
529 IF sample_empty(1) = '1' THEN
530 sample_ren_s <= (OTHERS => '1');
531 state_fsm_load_FFT <= FIFO_3;
532 END IF;
533
534 WHEN FIFO_3 =>
535 sample_ren_s <= "11" & NOT(sample_load) & "11";
536 IF sample_empty(2) = '1' THEN
537 sample_ren_s <= (OTHERS => '1');
538 state_fsm_load_FFT <= FIFO_4;
539 END IF;
540
541 WHEN FIFO_4 =>
542 sample_ren_s <= '1' & NOT(sample_load) & "111";
543 IF sample_empty(3) = '1' THEN
544 sample_ren_s <= (OTHERS => '1');
545 state_fsm_load_FFT <= FIFO_5;
546 END IF;
547
548 WHEN FIFO_5 =>
549 sample_ren_s <= NOT(sample_load) & "1111";
550 IF sample_empty(4) = '1' THEN
551 sample_ren_s <= (OTHERS => '1');
552 state_fsm_load_FFT <= IDLE;
553 END IF;
554 WHEN OTHERS => NULL;
555 END CASE;
556 END IF;
557 END PROCESS;
558
559 PROCESS (clk, rstn)
560 BEGIN
561 IF rstn = '0' THEN
562 sample_valid_r <= '0';
563 next_state_fsm_load_FFT <= IDLE;
564 ELSIF clk'EVENT AND clk = '1' THEN
565 next_state_fsm_load_FFT <= state_fsm_load_FFT;
566 IF sample_ren_s = "11111" THEN
567 sample_valid_r <= '0';
568 ELSE
569 sample_valid_r <= '1';
570 END IF;
571 END IF;
572 END PROCESS;
573
574 sample_valid <= '0' WHEN fft_ongoing_counter = '1' ELSE sample_valid_r AND sample_load;
575
576 sample_data <= sample_rdata(16*1-1 DOWNTO 16*0) WHEN next_state_fsm_load_FFT = FIFO_1 ELSE
577 sample_rdata(16*2-1 DOWNTO 16*1) WHEN next_state_fsm_load_FFT = FIFO_2 ELSE
578 sample_rdata(16*3-1 DOWNTO 16*2) WHEN next_state_fsm_load_FFT = FIFO_3 ELSE
579 sample_rdata(16*4-1 DOWNTO 16*3) WHEN next_state_fsm_load_FFT = FIFO_4 ELSE
580 sample_rdata(16*5-1 DOWNTO 16*4); --WHEN next_state_fsm_load_FFT = FIFO_5 ELSE
581
582 -----------------------------------------------------------------------------
583 -- FFT
584 -----------------------------------------------------------------------------
585 lpp_lfr_ms_FFT_1 : lpp_lfr_ms_FFT
586 PORT MAP (
587 clk => clk,
588 rstn => rstn,
589 sample_valid => sample_valid,
590 fft_read => fft_read,
591 sample_data => sample_data,
592 sample_load => sample_load,
593 fft_pong => fft_pong,
594 fft_data_im => fft_data_im,
595 fft_data_re => fft_data_re,
596 fft_data_valid => fft_data_valid,
597 fft_ready => fft_ready);
598
599 observation_vector_0(11 DOWNTO 0) <= "000" & --11 10
600 fft_ongoing_counter & --9 8
601 sample_load_rising_down & --7
602 fft_ready_rising_down & --6
603 fft_ready & --5
604 fft_data_valid & --4
605 fft_pong & --3
606 sample_load & --2
607 fft_read & --1
608 sample_valid; --0
609
610 -----------------------------------------------------------------------------
611 fft_ready_rising_down <= fft_ready_reg AND NOT fft_ready;
612 sample_load_rising_down <= sample_load_reg AND NOT sample_load;
613
614 PROCESS (clk, rstn)
615 BEGIN
616 IF rstn = '0' THEN
617 fft_ready_reg <= '0';
618 sample_load_reg <= '0';
619
620 fft_ongoing_counter <= '0';
621 ELSIF clk'event AND clk = '1' THEN
622 fft_ready_reg <= fft_ready;
623 sample_load_reg <= sample_load;
624
625 IF fft_ready_rising_down = '1' AND sample_load_rising_down = '0' THEN
626 fft_ongoing_counter <= '0';
627
628 -- CASE fft_ongoing_counter IS
629 -- WHEN "01" => fft_ongoing_counter <= "00";
630 ---- WHEN "10" => fft_ongoing_counter <= "01";
631 -- WHEN OTHERS => NULL;
632 -- END CASE;
633 ELSIF fft_ready_rising_down = '0' AND sample_load_rising_down = '1' THEN
634 fft_ongoing_counter <= '1';
635 -- CASE fft_ongoing_counter IS
636 -- WHEN "00" => fft_ongoing_counter <= "01";
637 ---- WHEN "01" => fft_ongoing_counter <= "10";
638 -- WHEN OTHERS => NULL;
639 -- END CASE;
640 END IF;
641
642 END IF;
643 END PROCESS;
644
645 -----------------------------------------------------------------------------
646 PROCESS (clk, rstn)
647 BEGIN
648 IF rstn = '0' THEN
649 state_fsm_load_MS_memory <= IDLE;
650 current_fifo_load <= "00001";
651 ELSIF clk'EVENT AND clk = '1' THEN
652 CASE state_fsm_load_MS_memory IS
653 WHEN IDLE =>
654 IF current_fifo_empty = '1' AND fft_ready = '1' AND current_fifo_locked = '0' THEN
655 state_fsm_load_MS_memory <= LOAD_FIFO;
656 END IF;
657 WHEN LOAD_FIFO =>
658 IF current_fifo_full = '1' THEN
659 state_fsm_load_MS_memory <= TRASH_FFT;
660 END IF;
661 WHEN TRASH_FFT =>
662 IF fft_ready = '0' THEN
663 state_fsm_load_MS_memory <= IDLE;
664 current_fifo_load <= current_fifo_load(3 DOWNTO 0) & current_fifo_load(4);
665 END IF;
666 WHEN OTHERS => NULL;
667 END CASE;
668
669 END IF;
670 END PROCESS;
671
672 current_fifo_empty <= MEM_IN_SM_Empty(0) WHEN current_fifo_load(0) = '1' ELSE
673 MEM_IN_SM_Empty(1) WHEN current_fifo_load(1) = '1' ELSE
674 MEM_IN_SM_Empty(2) WHEN current_fifo_load(2) = '1' ELSE
675 MEM_IN_SM_Empty(3) WHEN current_fifo_load(3) = '1' ELSE
676 MEM_IN_SM_Empty(4); -- WHEN current_fifo_load(3) = '1' ELSE
677
678 current_fifo_full <= MEM_IN_SM_Full(0) WHEN current_fifo_load(0) = '1' ELSE
679 MEM_IN_SM_Full(1) WHEN current_fifo_load(1) = '1' ELSE
680 MEM_IN_SM_Full(2) WHEN current_fifo_load(2) = '1' ELSE
681 MEM_IN_SM_Full(3) WHEN current_fifo_load(3) = '1' ELSE
682 MEM_IN_SM_Full(4); -- WHEN current_fifo_load(3) = '1' ELSE
683
684 current_fifo_locked <= MEM_IN_SM_locked(0) WHEN current_fifo_load(0) = '1' ELSE
685 MEM_IN_SM_locked(1) WHEN current_fifo_load(1) = '1' ELSE
686 MEM_IN_SM_locked(2) WHEN current_fifo_load(2) = '1' ELSE
687 MEM_IN_SM_locked(3) WHEN current_fifo_load(3) = '1' ELSE
688 MEM_IN_SM_locked(4); -- WHEN current_fifo_load(3) = '1' ELSE
689
690 fft_read <= '0' WHEN state_fsm_load_MS_memory = IDLE ELSE '1';
691
692 all_fifo : FOR I IN 4 DOWNTO 0 GENERATE
693 MEM_IN_SM_wen_s(I) <= '0' WHEN fft_data_valid = '1'
694 AND state_fsm_load_MS_memory = LOAD_FIFO
695 AND current_fifo_load(I) = '1'
696 ELSE '1';
697 END GENERATE all_fifo;
698
699 PROCESS (clk, rstn)
700 BEGIN
701 IF rstn = '0' THEN
702 MEM_IN_SM_wen <= (OTHERS => '1');
703 ELSIF clk'EVENT AND clk = '1' THEN
704 MEM_IN_SM_wen <= MEM_IN_SM_wen_s;
705 END IF;
706 END PROCESS;
707
708 MEM_IN_SM_wData <= (fft_data_im & fft_data_re) &
709 (fft_data_im & fft_data_re) &
710 (fft_data_im & fft_data_re) &
711 (fft_data_im & fft_data_re) &
712 (fft_data_im & fft_data_re);
713 -----------------------------------------------------------------------------
714
715
716 -----------------------------------------------------------------------------
717 Mem_In_SpectralMatrix : lppFIFOxN
718 GENERIC MAP (
719 tech => 0,
720 Mem_use => Mem_use,
721 Data_sz => 32, --16,
722 Addr_sz => 8, --8
723 FifoCnt => 5)
724 PORT MAP (
725 clk => clk,
726 rstn => rstn,
727
728 ReUse => MEM_IN_SM_ReUse,
729
730 wen => MEM_IN_SM_wen,
731 wdata => MEM_IN_SM_wData,
732
733 ren => MEM_IN_SM_ren,
734 rdata => MEM_IN_SM_rData,
735 full => MEM_IN_SM_Full,
736 empty => MEM_IN_SM_Empty,
737 almost_full => OPEN);
738
739 MEM_IN_SM_Full_pad <= MEM_IN_SM_Full;
740 MEM_IN_SM_Empty_pad <= MEM_IN_SM_Empty;
741
742 -------------------------------------------------------------------------------
743
744 --observation_vector_1(11 DOWNTO 0) <= '0' &
745 -- SM_correlation_done & --4
746 -- SM_correlation_auto & --3
747 -- SM_correlation_start &
748 -- SM_correlation_start & --7
749 -- status_MS_input(1 DOWNTO 0)& --6..5
750 -- MEM_IN_SM_locked(4 DOWNTO 0); --4..0
751
752 -------------------------------------------------------------------------------
753 --MS_control_1 : MS_control
754 -- PORT MAP (
755 -- clk => clk,
756 -- rstn => rstn,
757
758 -- current_status_ms => status_MS_input,
759
760 -- fifo_in_lock => MEM_IN_SM_locked,
761 -- fifo_in_data => MEM_IN_SM_rdata,
762 -- fifo_in_full => MEM_IN_SM_Full,
763 -- fifo_in_empty => MEM_IN_SM_Empty,
764 -- fifo_in_ren => MEM_IN_SM_ren,
765 -- fifo_in_reuse => MEM_IN_SM_ReUse,
766
767 -- fifo_out_data => SM_in_data,
768 -- fifo_out_ren => SM_in_ren,
769 -- fifo_out_empty => SM_in_empty,
770
771 -- current_status_component => status_component,
772
773 -- correlation_start => SM_correlation_start,
774 -- correlation_auto => SM_correlation_auto,
775 -- correlation_done => SM_correlation_done);
776
777
778 --MS_calculation_1 : MS_calculation
779 -- PORT MAP (
780 -- clk => clk,
781 -- rstn => rstn,
782
783 -- fifo_in_data => SM_in_data,
784 -- fifo_in_ren => SM_in_ren,
785 -- fifo_in_empty => SM_in_empty,
786
787 -- fifo_out_data => MEM_OUT_SM_Data_in_s, -- TODO
788 -- fifo_out_wen => MEM_OUT_SM_Write_s, -- TODO
789 -- fifo_out_full => MEM_OUT_SM_Full_s, -- TODO
790
791 -- correlation_start => SM_correlation_start,
792 -- correlation_auto => SM_correlation_auto,
793 -- correlation_begin => SM_correlation_begin,
794 -- correlation_done => SM_correlation_done);
795
796 -------------------------------------------------------------------------------
797 --PROCESS (clk, rstn)
798 --BEGIN -- PROCESS
799 -- IF rstn = '0' THEN -- asynchronous reset (active low)
800 -- current_matrix_write <= '0';
801 -- current_matrix_wait_empty <= '1';
802 -- status_component_fifo_0 <= (OTHERS => '0');
803 -- status_component_fifo_1 <= (OTHERS => '0');
804 -- status_component_fifo_0_end <= '0';
805 -- status_component_fifo_1_end <= '0';
806 -- SM_correlation_done_reg1 <= '0';
807 -- SM_correlation_done_reg2 <= '0';
808 -- SM_correlation_done_reg3 <= '0';
809
810 -- ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
811 -- SM_correlation_done_reg1 <= SM_correlation_done;
812 -- SM_correlation_done_reg2 <= SM_correlation_done_reg1;
813 -- SM_correlation_done_reg3 <= SM_correlation_done_reg2;
814 -- status_component_fifo_0_end <= '0';
815 -- status_component_fifo_1_end <= '0';
816 -- IF SM_correlation_begin = '1' THEN
817 -- IF current_matrix_write = '0' THEN
818 -- status_component_fifo_0 <= status_component;
819 -- ELSE
820 -- status_component_fifo_1 <= status_component;
821 -- END IF;
822 -- END IF;
823
824 -- IF SM_correlation_done_reg3 = '1' THEN
825 -- IF current_matrix_write = '0' THEN
826 -- status_component_fifo_0_end <= '1';
827 -- ELSE
828 -- status_component_fifo_1_end <= '1';
829 -- END IF;
830 -- current_matrix_wait_empty <= '1';
831 -- current_matrix_write <= NOT current_matrix_write;
832 -- END IF;
833
834 -- IF current_matrix_wait_empty <= '1' THEN
835 -- IF current_matrix_write = '0' THEN
836 -- current_matrix_wait_empty <= NOT MEM_OUT_SM_Empty(0);
837 -- ELSE
838 -- current_matrix_wait_empty <= NOT MEM_OUT_SM_Empty(1);
839 -- END IF;
840 -- END IF;
841
842 -- END IF;
843 --END PROCESS;
844
845 --MEM_OUT_SM_Full_s <= '1' WHEN SM_correlation_done = '1' ELSE
846 -- '1' WHEN SM_correlation_done_reg1 = '1' ELSE
847 -- '1' WHEN SM_correlation_done_reg2 = '1' ELSE
848 -- '1' WHEN SM_correlation_done_reg3 = '1' ELSE
849 -- '1' WHEN current_matrix_wait_empty = '1' ELSE
850 -- MEM_OUT_SM_Full(0) WHEN current_matrix_write = '0' ELSE
851 -- MEM_OUT_SM_Full(1);
852
853 --MEM_OUT_SM_Write(0) <= MEM_OUT_SM_Write_s WHEN current_matrix_write = '0' ELSE '1';
854 --MEM_OUT_SM_Write(1) <= MEM_OUT_SM_Write_s WHEN current_matrix_write = '1' ELSE '1';
855
856 --MEM_OUT_SM_Data_in <= MEM_OUT_SM_Data_in_s & MEM_OUT_SM_Data_in_s;
857 -------------------------------------------------------------------------------
858
859 --Mem_Out_SpectralMatrix : lppFIFOxN
860 -- GENERIC MAP (
861 -- tech => 0,
862 -- Mem_use => Mem_use,
863 -- Data_sz => 32,
864 -- Addr_sz => 8,
865 -- FifoCnt => 2)
866 -- PORT MAP (
867 -- clk => clk,
868 -- rstn => rstn,
869
870 -- ReUse => (OTHERS => '0'),
871
872 -- wen => MEM_OUT_SM_Write,
873 -- wdata => MEM_OUT_SM_Data_in,
874
875 -- ren => MEM_OUT_SM_Read,
876 -- rdata => MEM_OUT_SM_Data_out,
877
878 -- full => MEM_OUT_SM_Full,
879 -- empty => MEM_OUT_SM_Empty,
880 -- almost_full => OPEN);
881
882 -- -----------------------------------------------------------------------------
883 ---- MEM_OUT_SM_Read <= "00";
884 -- PROCESS (clk, rstn)
885 -- BEGIN
886 -- IF rstn = '0' THEN
887 -- fifo_0_ready <= '0';
888 -- fifo_1_ready <= '0';
889 -- fifo_ongoing <= '0';
890 -- ELSIF clk'EVENT AND clk = '1' THEN
891 -- IF fifo_0_ready = '1' AND MEM_OUT_SM_Empty(0) = '1' THEN
892 -- fifo_ongoing <= '1';
893 -- fifo_0_ready <= '0';
894 -- ELSIF status_component_fifo_0_end = '1' THEN
895 -- fifo_0_ready <= '1';
896 -- END IF;
897
898 -- IF fifo_1_ready = '1' AND MEM_OUT_SM_Empty(1) = '1' THEN
899 -- fifo_ongoing <= '0';
900 -- fifo_1_ready <= '0';
901 -- ELSIF status_component_fifo_1_end = '1' THEN
902 -- fifo_1_ready <= '1';
903 -- END IF;
904
905 -- END IF;
906 -- END PROCESS;
907
908 -- MEM_OUT_SM_Read(0) <= '1' WHEN fifo_ongoing = '1' ELSE
909 -- '1' WHEN fifo_0_ready = '0' ELSE
910 -- FSM_DMA_fifo_ren;
911
912 -- MEM_OUT_SM_Read(1) <= '1' WHEN fifo_ongoing = '0' ELSE
913 -- '1' WHEN fifo_1_ready = '0' ELSE
914 -- FSM_DMA_fifo_ren;
915
916 -- FSM_DMA_fifo_empty <= MEM_OUT_SM_Empty(0) WHEN fifo_ongoing = '0' AND fifo_0_ready = '1' ELSE
917 -- MEM_OUT_SM_Empty(1) WHEN fifo_ongoing = '1' AND fifo_1_ready = '1' ELSE
918 -- '1';
919
920 -- FSM_DMA_fifo_status <= status_component_fifo_0 WHEN fifo_ongoing = '0' ELSE
921 -- status_component_fifo_1;
922
923 -- FSM_DMA_fifo_data <= MEM_OUT_SM_Data_out(31 DOWNTO 0) WHEN fifo_ongoing = '0' ELSE
924 -- MEM_OUT_SM_Data_out(63 DOWNTO 32);
925
926 -- -----------------------------------------------------------------------------
927 -- lpp_lfr_ms_fsmdma_1 : lpp_lfr_ms_fsmdma
928 -- PORT MAP (
929 -- HCLK => clk,
930 -- HRESETn => rstn,
931
932 -- fifo_matrix_type => FSM_DMA_fifo_status(5 DOWNTO 4),
933 -- fifo_matrix_component => FSM_DMA_fifo_status(3 DOWNTO 0),
934 -- fifo_matrix_time => FSM_DMA_fifo_status(53 DOWNTO 6),
935 -- fifo_data => FSM_DMA_fifo_data,
936 -- fifo_empty => FSM_DMA_fifo_empty,
937 -- fifo_ren => FSM_DMA_fifo_ren,
938
939 -- dma_addr => dma_addr,
940 -- dma_data => dma_data,
941 -- dma_valid => dma_valid,
942 -- dma_valid_burst => dma_valid_burst,
943 -- dma_ren => dma_ren,
944 -- dma_done => dma_done,
945
946 -- ready_matrix_f0 => ready_matrix_f0,
947 -- ready_matrix_f1 => ready_matrix_f1,
948 -- ready_matrix_f2 => ready_matrix_f2,
949
950 -- error_bad_component_error => error_bad_component_error,
951 -- error_buffer_full => error_buffer_full,
952
953 -- debug_reg => debug_reg,
954 -- status_ready_matrix_f0 => status_ready_matrix_f0,
955 -- status_ready_matrix_f1 => status_ready_matrix_f1,
956 -- status_ready_matrix_f2 => status_ready_matrix_f2,
957
958 -- config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix,
959 -- config_active_interruption_onError => config_active_interruption_onError,
960
961 -- addr_matrix_f0 => addr_matrix_f0,
962 -- addr_matrix_f1 => addr_matrix_f1,
963 -- addr_matrix_f2 => addr_matrix_f2,
964
965 -- matrix_time_f0 => matrix_time_f0,
966 -- matrix_time_f1 => matrix_time_f1,
967 -- matrix_time_f2 => matrix_time_f2
968 -- );
969 -- -----------------------------------------------------------------------------
970
971
972
973
974
975 -- -----------------------------------------------------------------------------
976 -- -- TIME MANAGMENT
977 -- -----------------------------------------------------------------------------
978 -- all_time <= coarse_time & fine_time;
979 -- --
980 -- f_empty(0) <= '1' WHEN sample_f0_A_empty = "11111" ELSE '0';
981 -- f_empty(1) <= '1' WHEN sample_f0_B_empty = "11111" ELSE '0';
982 -- f_empty(2) <= '1' WHEN sample_f1_empty = "11111" ELSE '0';
983 -- f_empty(3) <= '1' WHEN sample_f2_empty = "11111" ELSE '0';
984
985 -- all_time_reg: FOR I IN 0 TO 3 GENERATE
986
987 -- PROCESS (clk, rstn)
988 -- BEGIN
989 -- IF rstn = '0' THEN
990 -- f_empty_reg(I) <= '1';
991 -- ELSIF clk'event AND clk = '1' THEN
992 -- f_empty_reg(I) <= f_empty(I);
993 -- END IF;
994 -- END PROCESS;
995
996 -- time_update_f(I) <= '1' WHEN f_empty(I) = '0' AND f_empty_reg(I) = '1' ELSE '0';
997
998 -- s_m_t_m_f0_A : spectral_matrix_time_managment
999 -- PORT MAP (
1000 -- clk => clk,
1001 -- rstn => rstn,
1002 -- time_in => all_time,
1003 -- update_1 => time_update_f(I),
1004 -- time_out => time_reg_f((I+1)*48-1 DOWNTO I*48)
1005 -- );
1006
1007 -- END GENERATE all_time_reg;
1008
1009 -- time_reg_f0_A <= time_reg_f((0+1)*48-1 DOWNTO 0*48);
1010 -- time_reg_f0_B <= time_reg_f((1+1)*48-1 DOWNTO 1*48);
1011 -- time_reg_f1 <= time_reg_f((2+1)*48-1 DOWNTO 2*48);
1012 -- time_reg_f2 <= time_reg_f((3+1)*48-1 DOWNTO 3*48);
1013
1014 -- -----------------------------------------------------------------------------
1015
1016 END Behavioral;
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1 VHDLIB=../..
2 SCRIPTSDIR=$(VHDLIB)/scripts/
3
4 GRLIB := $(shell sh $(VHDLIB)/scripts/lpp_relpath.sh)
5 TOP=TB
6
7 CMD_VLIB=vlib
8 CMD_VMAP=vmap
9 CMD_VCOM=@vcom -quiet -93 -work
10
11 ################## project specific targets ##########################
12
13 all:
14 @echo "make vsim"
15 @echo "make libs"
16 @echo "make clean"
17 @echo "make vcom_grlib vcom_lpp vcom_tb"
18
19 run:
20 @vsim work.TB -do run.do
21
22 vsim: libs vcom run
23
24 libs:
25 @$(CMD_VLIB) modelsim
26 @$(CMD_VMAP) modelsim modelsim
27 @$(CMD_VLIB) modelsim/techmap
28 @$(CMD_VMAP) techmap modelsim/techmap
29 @$(CMD_VLIB) modelsim/grlib
30 @$(CMD_VMAP) grlib modelsim/grlib
31 @$(CMD_VLIB) modelsim/work
32 @$(CMD_VMAP) work modelsim/work
33 @echo "libs done"
34
35
36 clean:
37 @rm -Rf modelsim
38 @rm -Rf modelsim.ini
39 @rm -Rf *~
40 @rm -Rf transcript
41 @rm -Rf wlft*
42 @rm -Rf *.wlf
43 @rm -Rf vish_stacktrace.vstf
44 @rm -Rf libs.do
45
46 vcom: vcom_grlib vcom_techmap vcom_tb
47
48
49 vcom_tb:
50 $(CMD_VCOM) work $(VHDLIB)/lib/lpp/./dsp/iir_filter/RAM_CEL.vhd
51 $(CMD_VCOM) work TB.vhd
52
53 vcom_grlib:
54 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/stdlib/version.vhd
55 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/stdlib/config_types.vhd
56 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/stdlib/config.vhd
57 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/stdlib/stdlib.vhd
58
59 vcom_techmap:
60 $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/gencomp/gencomp.vhd
61 $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/inferred/memory_inferred.vhd
62 $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/allmem.vhd
63 $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/syncram.vhd
64 $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/syncram_2p.vhd
65
66
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@@ -0,0 +1,171
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
19 -- Author : Jean-christophe Pellion
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 -------------------------------------------------------------------------------
22
23 LIBRARY IEEE;
24 USE IEEE.STD_LOGIC_1164.ALL;
25 USE IEEE.MATH_REAL.ALL;
26 USE IEEE.NUMERIC_STD.ALL;
27
28 --LIBRARY lpp;
29 --USE lpp.iir_filter.ALL;
30
31 LIBRARY techmap;
32 USE techmap.gencomp.ALL;
33
34 ENTITY TB IS
35
36
37 END TB;
38
39
40 ARCHITECTURE beh OF TB IS
41
42 COMPONENT RAM_CEL
43 GENERIC (
44 DataSz : integer range 1 to 32;
45 abits : integer range 2 to 12);
46 PORT (
47 WD : in std_logic_vector(DataSz-1 downto 0);
48 RD : out std_logic_vector(DataSz-1 downto 0);
49 WEN, REN : in std_logic;
50 WADDR : in std_logic_vector(abits-1 downto 0);
51 RADDR : in std_logic_vector(abits-1 downto 0);
52 RWCLK, RESET : in std_logic);
53 END COMPONENT;
54
55 CONSTANT DATA_SIZE : INTEGER := 8;
56 CONSTANT ADDR_BIT_NUMBER : INTEGER := 8;
57
58 -----------------------------------------------------------------------------
59 SIGNAL clk : STD_LOGIC := '0';
60 SIGNAL rstn : STD_LOGIC := '0';
61
62 -----------------------------------------------------------------------------
63 SIGNAL write_data : STD_LOGIC_VECTOR(DATA_SIZE-1 DOWNTO 0);
64 SIGNAL write_addr : STD_LOGIC_VECTOR(ADDR_BIT_NUMBER-1 DOWNTO 0);
65 SIGNAL write_enable : STD_LOGIC;
66 SIGNAL write_enable_n : STD_LOGIC;
67
68 SIGNAL read_data_ram : STD_LOGIC_VECTOR(DATA_SIZE-1 DOWNTO 0);
69 SIGNAL read_data_cel : STD_LOGIC_VECTOR(DATA_SIZE-1 DOWNTO 0);
70 SIGNAL read_addr : STD_LOGIC_VECTOR(ADDR_BIT_NUMBER-1 DOWNTO 0);
71 SIGNAL read_enable : STD_LOGIC;
72 SIGNAL read_enable_n : STD_LOGIC;
73 -----------------------------------------------------------------------------
74 CONSTANT RANDOM_VECTOR_SIZE : INTEGER := DATA_SIZE + ADDR_BIT_NUMBER + ADDR_BIT_NUMBER + 2;
75 CONSTANT TWO_POWER_RANDOM_VECTOR_SIZE : real := (2**RANDOM_VECTOR_SIZE)*1.0;
76 SIGNAL random_vector : STD_LOGIC_VECTOR(RANDOM_VECTOR_SIZE-1 DOWNTO 0);
77
78 -----------------------------------------------------------------------------
79 SIGNAL error_value : STD_LOGIC;
80 SIGNAL warning_value : STD_LOGIC;
81 SIGNAL warning_value_clocked : STD_LOGIC;
82
83 CONSTANT READ_DATA_ALL_X : STD_LOGIC_VECTOR(DATA_SIZE-1 DOWNTO 0) := (OTHERS => 'X');
84 CONSTANT READ_DATA_ALL_U : STD_LOGIC_VECTOR(DATA_SIZE-1 DOWNTO 0) := (OTHERS => 'U');
85 CONSTANT READ_DATA_ALL_0 : STD_LOGIC_VECTOR(DATA_SIZE-1 DOWNTO 0) := (OTHERS => '0');
86
87
88
89 BEGIN -- beh
90
91 clk <= NOT clk AFTER 10 ns;
92 rstn <= '1' AFTER 30 ns;
93 -----------------------------------------------------------------------------
94
95 CEL: RAM_CEL
96 GENERIC MAP (
97 DataSz => DATA_SIZE,
98 abits => ADDR_BIT_NUMBER)
99 PORT MAP (
100 WD => write_data,
101 RD => read_data_cel,
102 WEN => write_enable_n,
103 REN => read_enable_n,
104 WADDR => write_addr,
105 RADDR => read_addr,
106
107 RWCLK => clk,
108 RESET => rstn);
109
110 RAM : syncram_2p
111 GENERIC MAP(tech => 0, abits => ADDR_BIT_NUMBER, dbits => DATA_SIZE)
112 PORT MAP(rclk => clk, renable => read_enable, raddress => read_addr, dataout => read_data_ram,
113 wclk => clk, write => write_enable, waddress => write_addr, datain => write_data);
114
115 -----------------------------------------------------------------------------
116
117 PROCESS (clk, rstn)
118 VARIABLE seed1, seed2 : POSITIVE;
119 VARIABLE rand1 : REAL;
120 VARIABLE RANDOM_VECTOR_VAR : STD_LOGIC_VECTOR(RANDOM_VECTOR_SIZE-1 DOWNTO 0);
121 BEGIN -- PROCESS
122 IF rstn = '0' THEN -- asynchronous reset (active low)
123 random_vector <= (OTHERS => '0');
124 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
125 UNIFORM(seed1,seed2,rand1);
126 RANDOM_VECTOR_VAR := STD_LOGIC_VECTOR(
127 to_unsigned(INTEGER(TRUNC(rand1*TWO_POWER_RANDOM_VECTOR_SIZE)),
128 RANDOM_VECTOR_VAR'LENGTH)
129 );
130
131 random_vector <= RANDOM_VECTOR_VAR ;
132
133 END IF;
134 END PROCESS;
135
136 -----------------------------------------------------------------------------
137 write_data <= random_vector(DATA_SIZE-1 DOWNTO 0);
138 write_addr <= random_vector(DATA_SIZE+ADDR_BIT_NUMBER-1 DOWNTO DATA_SIZE);
139 read_addr <= random_vector(DATA_SIZE+ADDR_BIT_NUMBER+ADDR_BIT_NUMBER-1 DOWNTO DATA_SIZE+ADDR_BIT_NUMBER);
140 read_enable <= random_vector(RANDOM_VECTOR_SIZE-2);
141 write_enable <= random_vector(RANDOM_VECTOR_SIZE-1);
142
143 read_enable_n <= NOT read_enable;
144 write_enable_n <= NOT write_enable;
145
146 -----------------------------------------------------------------------------
147 warning_value <= '0' WHEN read_data_ram = read_data_cel ELSE
148 '1';
149
150 PROCESS (clk, rstn)
151 BEGIN -- PROCESS
152 IF rstn = '0' THEN -- asynchronous reset (active low)
153 error_value <= '0';
154 warning_value_clocked <= '0';
155 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
156 IF read_data_ram = read_data_cel THEN
157 error_value <= '0';
158 warning_value_clocked <= '0';
159 ELSE
160 warning_value_clocked <= '1';
161 IF read_data_ram = READ_DATA_ALL_U AND read_data_cel = READ_DATA_ALL_0 THEN
162 error_value <= '0';
163 ELSE
164 error_value <= '1';
165 END IF;
166 END IF;
167 END IF;
168 END PROCESS;
169
170 END beh;
171
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@@ -0,0 +1,3
1 log -R *
2 do wave.do
3 run 10 ms No newline at end of file
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@@ -0,0 +1,34
1 onerror {resume}
2 quietly WaveActivateNextPane {} 0
3 add wave -noupdate -expand -group COMMON /tb/clk
4 add wave -noupdate -expand -group COMMON /tb/rstn
5 add wave -noupdate -expand -group COMMON /tb/random_vector
6 add wave -noupdate -expand -group WRITE -radix hexadecimal /tb/write_data
7 add wave -noupdate -expand -group WRITE -radix hexadecimal /tb/write_addr
8 add wave -noupdate -expand -group WRITE -radix hexadecimal /tb/write_enable
9 add wave -noupdate -expand -group WRITE -radix hexadecimal /tb/write_enable_n
10 add wave -noupdate -expand -group READ -radix hexadecimal /tb/read_data_ram
11 add wave -noupdate -expand -group READ -radix hexadecimal /tb/read_data_cel
12 add wave -noupdate -expand -group READ -radix hexadecimal /tb/read_addr
13 add wave -noupdate -expand -group READ -radix hexadecimal /tb/read_enable
14 add wave -noupdate -expand -group READ -radix hexadecimal /tb/read_enable_n
15 add wave -noupdate -radix hexadecimal /tb/warning_value
16 add wave -noupdate -radix hexadecimal /tb/warning_value_clocked
17 add wave -noupdate -radix hexadecimal /tb/error_value
18 TreeUpdate [SetDefaultTree]
19 WaveRestoreCursors {{Cursor 1} {5926078 ps} 0} {{Cursor 2} {200000 ps} 0}
20 configure wave -namecolwidth 403
21 configure wave -valuecolwidth 198
22 configure wave -justifyvalue left
23 configure wave -signalnamewidth 0
24 configure wave -snapdistance 10
25 configure wave -datasetprefix 0
26 configure wave -rowmargin 4
27 configure wave -childrowmargin 2
28 configure wave -gridoffset 0
29 configure wave -gridperiod 1
30 configure wave -griddelta 40
31 configure wave -timeline 0
32 configure wave -timelineunits ps
33 update
34 WaveRestoreZoom {0 ps} {25526182 ps}
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