# HG changeset patch # User pellion # Date 2014-08-25 13:39:28 # Node ID c218371d90d3de2454049fdee4376ff8ffe62469 # Parent 51bb00f3c0ced3210e8e5b2581604f5c77b1341a temp diff --git a/designs/MINI-LFR_testFFTb/MINI_LFR_top.vhd b/designs/MINI-LFR_testFFTb/MINI_LFR_top.vhd new file mode 100644 --- /dev/null +++ b/designs/MINI-LFR_testFFTb/MINI_LFR_top.vhd @@ -0,0 +1,731 @@ +------------------------------------------------------------------------------ +-- This file is a part of the LPP VHDL IP LIBRARY +-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 3 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +------------------------------------------------------------------------------- +-- Author : Jean-christophe Pellion +-- Mail : jean-christophe.pellion@lpp.polytechnique.fr +------------------------------------------------------------------------------- +LIBRARY IEEE; +USE IEEE.numeric_std.ALL; +USE IEEE.std_logic_1164.ALL; +LIBRARY grlib; +USE grlib.amba.ALL; +USE grlib.stdlib.ALL; +LIBRARY techmap; +USE techmap.gencomp.ALL; +LIBRARY gaisler; +USE gaisler.memctrl.ALL; +USE gaisler.leon3.ALL; +USE gaisler.uart.ALL; +USE gaisler.misc.ALL; +USE gaisler.spacewire.ALL; +LIBRARY esa; +USE esa.memoryctrl.ALL; +LIBRARY lpp; +USE lpp.lpp_memory.ALL; +USE lpp.lpp_ad_conv.ALL; +USE lpp.lpp_lfr_pkg.ALL; -- contains lpp_lfr, not in the 206 rev of the VHD_Lib +USE lpp.lpp_top_lfr_pkg.ALL; -- contains top_wf_picker +USE lpp.iir_filter.ALL; +USE lpp.general_purpose.ALL; +USE lpp.lpp_lfr_time_management.ALL; +USE lpp.lpp_leon3_soc_pkg.ALL; + +ENTITY MINI_LFR_top IS + + PORT ( + clk_50 : IN STD_LOGIC; + clk_49 : IN STD_LOGIC; + reset : IN STD_LOGIC; + --BPs + BP0 : IN STD_LOGIC; + BP1 : IN STD_LOGIC; + --LEDs + LED0 : OUT STD_LOGIC; + LED1 : OUT STD_LOGIC; + LED2 : OUT STD_LOGIC; + --UARTs + TXD1 : IN STD_LOGIC; + RXD1 : OUT STD_LOGIC; + nCTS1 : OUT STD_LOGIC; + nRTS1 : IN STD_LOGIC; + + TXD2 : IN STD_LOGIC; + RXD2 : OUT STD_LOGIC; + nCTS2 : OUT STD_LOGIC; + nDTR2 : IN STD_LOGIC; + nRTS2 : IN STD_LOGIC; + nDCD2 : OUT STD_LOGIC; + + --EXT CONNECTOR + IO0 : INOUT STD_LOGIC; + IO1 : INOUT STD_LOGIC; + IO2 : INOUT STD_LOGIC; + IO3 : INOUT STD_LOGIC; + IO4 : INOUT STD_LOGIC; + IO5 : INOUT STD_LOGIC; + IO6 : INOUT STD_LOGIC; + IO7 : INOUT STD_LOGIC; + IO8 : INOUT STD_LOGIC; + IO9 : INOUT STD_LOGIC; + IO10 : INOUT STD_LOGIC; + IO11 : INOUT STD_LOGIC; + + --SPACE WIRE + SPW_EN : OUT STD_LOGIC; -- 0 => off + SPW_NOM_DIN : IN STD_LOGIC; -- NOMINAL LINK + SPW_NOM_SIN : IN STD_LOGIC; + SPW_NOM_DOUT : OUT STD_LOGIC; + SPW_NOM_SOUT : OUT STD_LOGIC; + SPW_RED_DIN : IN STD_LOGIC; -- REDUNDANT LINK + SPW_RED_SIN : IN STD_LOGIC; + SPW_RED_DOUT : OUT STD_LOGIC; + SPW_RED_SOUT : OUT STD_LOGIC; + -- MINI LFR ADC INPUTS + ADC_nCS : OUT STD_LOGIC; + ADC_CLK : OUT STD_LOGIC; + ADC_SDO : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + + -- SRAM + SRAM_nWE : OUT STD_LOGIC; + SRAM_CE : OUT STD_LOGIC; + SRAM_nOE : OUT STD_LOGIC; + SRAM_nBE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + SRAM_A : OUT STD_LOGIC_VECTOR(19 DOWNTO 0); + SRAM_DQ : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0) + ); + +END MINI_LFR_top; + + +ARCHITECTURE beh OF MINI_LFR_top IS + + COMPONENT lpp_lfr_ms_tb + GENERIC ( + Mem_use : INTEGER); + PORT ( + clk : IN STD_LOGIC; + rstn : IN STD_LOGIC; + sample_f0_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0); + sample_f0_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); + sample_f1_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0); + sample_f1_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); + sample_f2_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0); + sample_f2_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); + MEM_IN_SM_locked : IN STD_LOGIC_VECTOR(4 DOWNTO 0); + MEM_IN_SM_ReUse : IN STD_LOGIC_VECTOR(4 DOWNTO 0); + MEM_IN_SM_ren : IN STD_LOGIC_VECTOR(4 DOWNTO 0); + MEM_IN_SM_rData : OUT STD_LOGIC_VECTOR(16*2*5-1 DOWNTO 0); + MEM_IN_SM_Full_pad : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); + MEM_IN_SM_Empty_pad : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); + error_input_fifo_write : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); + observation_vector_0 : OUT STD_LOGIC_VECTOR(11 DOWNTO 0); + observation_vector_1 : OUT STD_LOGIC_VECTOR(11 DOWNTO 0)); + END COMPONENT; + + COMPONENT lpp_lfr_apbreg_tb + GENERIC ( + pindex : INTEGER; + paddr : INTEGER; + pmask : INTEGER); + PORT ( + HCLK : IN STD_ULOGIC; + HRESETn : IN STD_ULOGIC; + apbi : IN apb_slv_in_type; + apbo : OUT apb_slv_out_type; + sample_f0_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); + sample_f1_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); + sample_f2_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); + sample_f0_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); + sample_f1_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); + sample_f2_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); + MEM_IN_SM_locked : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); + MEM_IN_SM_ReUse : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); + MEM_IN_SM_ren : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); + MEM_IN_SM_rData : IN STD_LOGIC_VECTOR(16*2*5-1 DOWNTO 0); + MEM_IN_SM_Full : IN STD_LOGIC_VECTOR(4 DOWNTO 0); + MEM_IN_SM_Empty : IN STD_LOGIC_VECTOR(4 DOWNTO 0)); + END COMPONENT; + + + + SIGNAL clk_50_s : STD_LOGIC := '0'; + SIGNAL clk_25 : STD_LOGIC := '0'; + SIGNAL clk_24 : STD_LOGIC := '0'; + ----------------------------------------------------------------------------- + SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0); + SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0); + -- + SIGNAL errorn : STD_LOGIC; + -- UART AHB --------------------------------------------------------------- + SIGNAL ahbrxd : STD_ULOGIC; -- DSU rx data + SIGNAL ahbtxd : STD_ULOGIC; -- DSU tx data + + -- UART APB --------------------------------------------------------------- + SIGNAL urxd1 : STD_ULOGIC; -- UART1 rx data + SIGNAL utxd1 : STD_ULOGIC; -- UART1 tx data + -- + SIGNAL I00_s : STD_LOGIC; + + -- CONSTANTS + CONSTANT CFG_PADTECH : INTEGER := inferred; + -- + CONSTANT NB_APB_SLAVE : INTEGER := 11; -- 3 = grspw + waveform picker + time manager, 11 allows pindex = f + CONSTANT NB_AHB_SLAVE : INTEGER := 1; + CONSTANT NB_AHB_MASTER : INTEGER := 2; -- 2 = grspw + waveform picker + + SIGNAL apbi_ext : apb_slv_in_type; + SIGNAL apbo_ext : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5) := (OTHERS => apb_none); + SIGNAL ahbi_s_ext : ahb_slv_in_type; + SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3) := (OTHERS => ahbs_none); + SIGNAL ahbi_m_ext : AHB_Mst_In_Type; + SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1) := (OTHERS => ahbm_none); + +-- Spacewire signals + SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0); + SIGNAL stmp : STD_LOGIC_VECTOR(1 DOWNTO 0); + SIGNAL spw_rxclk : STD_LOGIC_VECTOR(1 DOWNTO 0); + SIGNAL spw_rxtxclk : STD_ULOGIC; + SIGNAL spw_rxclkn : STD_ULOGIC; + SIGNAL spw_clk : STD_LOGIC; + SIGNAL swni : grspw_in_type; + SIGNAL swno : grspw_out_type; +-- SIGNAL clkmn : STD_ULOGIC; +-- SIGNAL txclk : STD_ULOGIC; + +--GPIO + SIGNAL gpioi : gpio_in_type; + SIGNAL gpioo : gpio_out_type; + +-- AD Converter ADS7886 + SIGNAL sample : Samples14v(7 DOWNTO 0); + SIGNAL sample_s : Samples(7 DOWNTO 0); + SIGNAL sample_val : STD_LOGIC; + SIGNAL ADC_nCS_sig : STD_LOGIC; + SIGNAL ADC_CLK_sig : STD_LOGIC; + SIGNAL ADC_SDO_sig : STD_LOGIC_VECTOR(7 DOWNTO 0); + + SIGNAL bias_fail_sw_sig : STD_LOGIC; + + SIGNAL observation_reg : STD_LOGIC_VECTOR(31 DOWNTO 0); + SIGNAL observation_vector_0 : STD_LOGIC_VECTOR(11 DOWNTO 0); + SIGNAL observation_vector_1 : STD_LOGIC_VECTOR(11 DOWNTO 0); + ----------------------------------------------------------------------------- + + + SIGNAL sample_f0_wen : STD_LOGIC_VECTOR(4 DOWNTO 0); + SIGNAL sample_f0_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); + -- + SIGNAL sample_f1_wen : STD_LOGIC_VECTOR(4 DOWNTO 0); + SIGNAL sample_f1_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); + -- + SIGNAL sample_f2_wen : STD_LOGIC_VECTOR(4 DOWNTO 0); + SIGNAL sample_f2_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); + + + --------------------------------------------------------------------------- + -- + --------------------------------------------------------------------------- + SIGNAL MEM_IN_SM_locked : STD_LOGIC_VECTOR(4 DOWNTO 0); + SIGNAL MEM_IN_SM_ReUse : STD_LOGIC_VECTOR(4 DOWNTO 0); + SIGNAL MEM_IN_SM_ren : STD_LOGIC_VECTOR(4 DOWNTO 0); + SIGNAL MEM_IN_SM_rData : STD_LOGIC_VECTOR(16*2*5-1 DOWNTO 0); + SIGNAL MEM_IN_SM_Full_pad : STD_LOGIC_VECTOR(4 DOWNTO 0); + SIGNAL MEM_IN_SM_Empty_pad : STD_LOGIC_VECTOR(4 DOWNTO 0); + + + +BEGIN -- beh + + ----------------------------------------------------------------------------- + -- CLK + ----------------------------------------------------------------------------- + + PROCESS(clk_50) + BEGIN + IF clk_50'EVENT AND clk_50 = '1' THEN + clk_50_s <= NOT clk_50_s; + END IF; + END PROCESS; + + PROCESS(clk_50_s) + BEGIN + IF clk_50_s'EVENT AND clk_50_s = '1' THEN + clk_25 <= NOT clk_25; + END IF; + END PROCESS; + + PROCESS(clk_49) + BEGIN + IF clk_49'EVENT AND clk_49 = '1' THEN + clk_24 <= NOT clk_24; + END IF; + END PROCESS; + + ----------------------------------------------------------------------------- + + PROCESS (clk_25, reset) + BEGIN -- PROCESS + IF reset = '0' THEN -- asynchronous reset (active low) + LED0 <= '0'; + LED1 <= '0'; + LED2 <= '0'; + --IO1 <= '0'; + --IO2 <= '1'; + --IO3 <= '0'; + --IO4 <= '0'; + --IO5 <= '0'; + --IO6 <= '0'; + --IO7 <= '0'; + --IO8 <= '0'; + --IO9 <= '0'; + --IO10 <= '0'; + --IO11 <= '0'; + ELSIF clk_25'EVENT AND clk_25 = '1' THEN -- rising clock edge + LED0 <= '0'; + LED1 <= '1'; + LED2 <= BP0 OR BP1 OR nDTR2 OR nRTS2 OR nRTS1; + --IO1 <= '1'; + --IO2 <= SPW_NOM_DIN OR SPW_NOM_SIN OR SPW_RED_DIN OR SPW_RED_SIN; + --IO3 <= ADC_SDO(0); + --IO4 <= ADC_SDO(1); + --IO5 <= ADC_SDO(2); + --IO6 <= ADC_SDO(3); + --IO7 <= ADC_SDO(4); + --IO8 <= ADC_SDO(5); + --IO9 <= ADC_SDO(6); + --IO10 <= ADC_SDO(7); + --IO11 <= BP1 OR nDTR2 OR nRTS2 OR nRTS1; + END IF; + END PROCESS; + + PROCESS (clk_24, reset) + BEGIN -- PROCESS + IF reset = '0' THEN -- asynchronous reset (active low) + I00_s <= '0'; + ELSIF clk_24'EVENT AND clk_24 = '1' THEN -- rising clock edge + I00_s <= NOT I00_s; + END IF; + END PROCESS; +-- IO0 <= I00_s; + + --UARTs + nCTS1 <= '1'; + nCTS2 <= '1'; + nDCD2 <= '1'; + + --EXT CONNECTOR + + --SPACE WIRE + + leon3_soc_1 : leon3_soc + GENERIC MAP ( + fabtech => apa3e, + memtech => apa3e, + padtech => inferred, + clktech => inferred, + disas => 0, + dbguart => 0, + pclow => 2, + clk_freq => 25000, + NB_CPU => 1, + ENABLE_FPU => 1, + FPU_NETLIST => 0, + ENABLE_DSU => 1, + ENABLE_AHB_UART => 1, + ENABLE_APB_UART => 1, + ENABLE_IRQMP => 1, + ENABLE_GPT => 1, + NB_AHB_MASTER => NB_AHB_MASTER, + NB_AHB_SLAVE => NB_AHB_SLAVE, + NB_APB_SLAVE => NB_APB_SLAVE) + PORT MAP ( + clk => clk_25, + reset => reset, + errorn => errorn, + ahbrxd => TXD1, + ahbtxd => RXD1, + urxd1 => TXD2, + utxd1 => RXD2, + address => SRAM_A, + data => SRAM_DQ, + nSRAM_BE0 => SRAM_nBE(0), + nSRAM_BE1 => SRAM_nBE(1), + nSRAM_BE2 => SRAM_nBE(2), + nSRAM_BE3 => SRAM_nBE(3), + nSRAM_WE => SRAM_nWE, + nSRAM_CE => SRAM_CE, + nSRAM_OE => SRAM_nOE, + + apbi_ext => apbi_ext, + apbo_ext => apbo_ext, + ahbi_s_ext => ahbi_s_ext, + ahbo_s_ext => ahbo_s_ext, + ahbi_m_ext => ahbi_m_ext, + ahbo_m_ext => ahbo_m_ext); + +------------------------------------------------------------------------------- +-- APB_LFR_TIME_MANAGEMENT ---------------------------------------------------- +------------------------------------------------------------------------------- + apb_lfr_time_management_1 : apb_lfr_time_management + GENERIC MAP ( + pindex => 6, + paddr => 6, + pmask => 16#fff#, + FIRST_DIVISION => 374, -- ((49.152/2) /2^16) - 1 = 375 - 1 = 374 + NB_SECOND_DESYNC => 60) -- 60 secondes of desynchronization before CoarseTime's MSB is Set + PORT MAP ( + clk25MHz => clk_25, + clk24_576MHz => clk_24, -- 49.152MHz/2 + resetn => reset, + grspw_tick => swno.tickout, + apbi => apbi_ext, + apbo => apbo_ext(6), + coarse_time => coarse_time, + fine_time => fine_time); + +----------------------------------------------------------------------- +--- SpaceWire -------------------------------------------------------- +----------------------------------------------------------------------- + + SPW_EN <= '1'; + + spw_clk <= clk_50_s; + spw_rxtxclk <= spw_clk; + spw_rxclkn <= NOT spw_rxtxclk; + + -- PADS for SPW1 + spw1_rxd_pad : inpad GENERIC MAP (tech => inferred) + PORT MAP (SPW_NOM_DIN, dtmp(0)); + spw1_rxs_pad : inpad GENERIC MAP (tech => inferred) + PORT MAP (SPW_NOM_SIN, stmp(0)); + spw1_txd_pad : outpad GENERIC MAP (tech => inferred) + PORT MAP (SPW_NOM_DOUT, swno.d(0)); + spw1_txs_pad : outpad GENERIC MAP (tech => inferred) + PORT MAP (SPW_NOM_SOUT, swno.s(0)); + -- PADS FOR SPW2 + spw2_rxd_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\ + PORT MAP (SPW_RED_SIN, dtmp(1)); + spw2_rxs_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\ + PORT MAP (SPW_RED_DIN, stmp(1)); + spw2_txd_pad : outpad GENERIC MAP (tech => inferred) + PORT MAP (SPW_RED_DOUT, swno.d(1)); + spw2_txs_pad : outpad GENERIC MAP (tech => inferred) + PORT MAP (SPW_RED_SOUT, swno.s(1)); + + -- GRSPW PHY + --spw1_input: if CFG_SPW_GRSPW = 1 generate + spw_inputloop : FOR j IN 0 TO 1 GENERATE + spw_phy0 : grspw_phy + GENERIC MAP( + tech => apa3e, + rxclkbuftype => 1, + scantest => 0) + PORT MAP( + rxrst => swno.rxrst, + di => dtmp(j), + si => stmp(j), + rxclko => spw_rxclk(j), + do => swni.d(j), + ndo => swni.nd(j*5+4 DOWNTO j*5), + dconnect => swni.dconnect(j*2+1 DOWNTO j*2)); + END GENERATE spw_inputloop; + + -- SPW core + sw0 : grspwm GENERIC MAP( + tech => apa3e, + hindex => 1, + pindex => 5, + paddr => 5, + pirq => 11, + sysfreq => 25000, -- CPU_FREQ + rmap => 1, + rmapcrc => 1, + fifosize1 => 16, + fifosize2 => 16, + rxclkbuftype => 1, + rxunaligned => 0, + rmapbufs => 4, + ft => 0, + netlist => 0, + ports => 2, + --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1 + memtech => apa3e, + destkey => 2, + spwcore => 1 + --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1 + --output_type => CFG_SPW_OUTPUT, -- not used byt the spw core 1 + --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1 + ) + PORT MAP(reset, clk_25, spw_rxclk(0), + spw_rxclk(1), spw_rxtxclk, spw_rxtxclk, + ahbi_m_ext, ahbo_m_ext(1), apbi_ext, apbo_ext(5), + swni, swno); + + swni.tickin <= '0'; + swni.rmapen <= '1'; + swni.clkdiv10 <= "00000100"; -- 10 MHz / (4 + 1) = 10 MHz + swni.tickinraw <= '0'; + swni.timein <= (OTHERS => '0'); + swni.dcrstval <= (OTHERS => '0'); + swni.timerrstval <= (OTHERS => '0'); + +------------------------------------------------------------------------------- +-- LFR ------------------------------------------------------------------------ +------------------------------------------------------------------------------- + --lpp_lfr_1 : lpp_lfr + -- GENERIC MAP ( + -- Mem_use => use_RAM, + -- nb_data_by_buffer_size => 32, + -- nb_word_by_buffer_size => 30, + -- nb_snapshot_param_size => 32, + -- delta_vector_size => 32, + -- delta_vector_size_f0_2 => 7, -- log2(96) + -- pindex => 15, + -- paddr => 15, + -- pmask => 16#fff#, + -- pirq_ms => 6, + -- pirq_wfp => 14, + -- hindex => 2, + -- top_lfr_version => X"000117") -- aa.bb.cc version + -- PORT MAP ( + -- clk => clk_25, + -- rstn => reset, + -- sample_B => sample_s(2 DOWNTO 0), + -- sample_E => sample_s(7 DOWNTO 3), + -- sample_val => sample_val, + -- apbi => apbi_ext, + -- apbo => apbo_ext(15), + -- ahbi => ahbi_m_ext, + -- ahbo => ahbo_m_ext(2), + -- coarse_time => coarse_time, + -- fine_time => fine_time, + -- data_shaping_BW => bias_fail_sw_sig, + -- observation_vector_0=> observation_vector_0, + -- observation_vector_1 => observation_vector_1, + -- observation_reg => observation_reg); + + lpp_lfr_apbreg_1 : lpp_lfr_apbreg_tb + GENERIC MAP ( + pindex => 15, + paddr => 15, + pmask => 16#fff#) + PORT MAP ( + HCLK => clk_25, + HRESETn => reset, + apbi => apbi_ext, + apbo => apbo_ext(15), + + sample_f0_wen => sample_f0_wen, + sample_f1_wen => sample_f1_wen, + sample_f2_wen => sample_f2_wen, + sample_f0_wdata => sample_f0_wdata, + sample_f1_wdata => sample_f1_wdata, + sample_f2_wdata => sample_f2_wdata, + MEM_IN_SM_locked => MEM_IN_SM_locked, + MEM_IN_SM_ReUse => MEM_IN_SM_ReUse, + MEM_IN_SM_ren => MEM_IN_SM_ren, + MEM_IN_SM_rData => MEM_IN_SM_rData, + MEM_IN_SM_Full => MEM_IN_SM_Full_pad, + MEM_IN_SM_Empty => MEM_IN_SM_Empty_pad); + + lpp_lfr_ms_tb_1 : lpp_lfr_ms_tb + GENERIC MAP ( + Mem_use =>use_RAM) + PORT MAP ( + clk => clk_25, + rstn => reset, + sample_f0_wen => sample_f0_wen, + sample_f0_wdata => sample_f0_wdata, + sample_f1_wen => sample_f1_wen, + sample_f1_wdata => sample_f1_wdata, + sample_f2_wen => sample_f2_wen, + sample_f2_wdata => sample_f2_wdata, + + MEM_IN_SM_locked => MEM_IN_SM_locked, + MEM_IN_SM_ReUse => MEM_IN_SM_ReUse, + MEM_IN_SM_ren => MEM_IN_SM_ren, + MEM_IN_SM_rData => MEM_IN_SM_rData, + MEM_IN_SM_Full_pad => MEM_IN_SM_Full_pad, + MEM_IN_SM_Empty_pad => MEM_IN_SM_Empty_pad, + + error_input_fifo_write => OPEN, + observation_vector_0 => observation_vector_0, + observation_vector_1 => observation_vector_1); + + ----------------------------------------------------------------------------- + + + + + + all_sample : FOR I IN 7 DOWNTO 0 GENERATE + sample_s(I) <= sample(I)(11 DOWNTO 0) & '0' & '0' & '0' & '0'; + END GENERATE all_sample; + + + + top_ad_conv_ADS7886_v2_1 : top_ad_conv_ADS7886_v2 + GENERIC MAP( + ChannelCount => 8, + SampleNbBits => 14, + ncycle_cnv_high => 40, -- at least 32 cycles at 25 MHz, 32 * 49.152 / 25 /2 = 31.5 + ncycle_cnv => 249) -- 49 152 000 / 98304 /2 + PORT MAP ( + -- CONV + cnv_clk => clk_24, + cnv_rstn => reset, + cnv => ADC_nCS_sig, + -- DATA + clk => clk_25, + rstn => reset, + sck => ADC_CLK_sig, + sdo => ADC_SDO_sig, + -- SAMPLE + sample => sample, + sample_val => sample_val); + + --IO10 <= ADC_SDO_sig(5); + --IO9 <= ADC_SDO_sig(4); + --IO8 <= ADC_SDO_sig(3); + + ADC_nCS <= ADC_nCS_sig; + ADC_CLK <= ADC_CLK_sig; + ADC_SDO_sig <= ADC_SDO; + +---------------------------------------------------------------------- +--- GPIO ----------------------------------------------------------- +---------------------------------------------------------------------- + + grgpio0 : grgpio + GENERIC MAP(pindex => 11, paddr => 11, imask => 16#0000#, nbits => 8) + PORT MAP(reset, clk_25, apbi_ext, apbo_ext(11), gpioi, gpioo); + + --pio_pad_0 : iopad + -- GENERIC MAP (tech => CFG_PADTECH) + -- PORT MAP (IO0, gpioo.dout(0), gpioo.oen(0), gpioi.din(0)); + --pio_pad_1 : iopad + -- GENERIC MAP (tech => CFG_PADTECH) + -- PORT MAP (IO1, gpioo.dout(1), gpioo.oen(1), gpioi.din(1)); + --pio_pad_2 : iopad + -- GENERIC MAP (tech => CFG_PADTECH) + -- PORT MAP (IO2, gpioo.dout(2), gpioo.oen(2), gpioi.din(2)); + --pio_pad_3 : iopad + -- GENERIC MAP (tech => CFG_PADTECH) + -- PORT MAP (IO3, gpioo.dout(3), gpioo.oen(3), gpioi.din(3)); + --pio_pad_4 : iopad + -- GENERIC MAP (tech => CFG_PADTECH) + -- PORT MAP (IO4, gpioo.dout(4), gpioo.oen(4), gpioi.din(4)); + --pio_pad_5 : iopad + -- GENERIC MAP (tech => CFG_PADTECH) + -- PORT MAP (IO5, gpioo.dout(5), gpioo.oen(5), gpioi.din(5)); + --pio_pad_6 : iopad + -- GENERIC MAP (tech => CFG_PADTECH) + -- PORT MAP (IO6, gpioo.dout(6), gpioo.oen(6), gpioi.din(6)); + --pio_pad_7 : iopad + -- GENERIC MAP (tech => CFG_PADTECH) + -- PORT MAP (IO7, gpioo.dout(7), gpioo.oen(7), gpioi.din(7)); + + PROCESS (clk_25, reset) + BEGIN -- PROCESS + IF reset = '0' THEN -- asynchronous reset (active low) + IO0 <= '0'; + IO1 <= '0'; + IO2 <= '0'; + IO3 <= '0'; + IO4 <= '0'; + IO5 <= '0'; + IO6 <= '0'; + IO7 <= '0'; + IO8 <= '0'; + IO9 <= '0'; + IO10 <= '0'; + IO11 <= '0'; + ELSIF clk_25'EVENT AND clk_25 = '1' THEN -- rising clock edge + CASE gpioo.dout(2 DOWNTO 0) IS + WHEN "011" => + IO0 <= observation_reg(0); + IO1 <= observation_reg(1); + IO2 <= observation_reg(2); + IO3 <= observation_reg(3); + IO4 <= observation_reg(4); + IO5 <= observation_reg(5); + IO6 <= observation_reg(6); + IO7 <= observation_reg(7); + IO8 <= observation_reg(8); + IO9 <= observation_reg(9); + IO10 <= observation_reg(10); + IO11 <= observation_reg(11); + WHEN "001" => + IO0 <= observation_reg(0 + 12); + IO1 <= observation_reg(1 + 12); + IO2 <= observation_reg(2 + 12); + IO3 <= observation_reg(3 + 12); + IO4 <= observation_reg(4 + 12); + IO5 <= observation_reg(5 + 12); + IO6 <= observation_reg(6 + 12); + IO7 <= observation_reg(7 + 12); + IO8 <= observation_reg(8 + 12); + IO9 <= observation_reg(9 + 12); + IO10 <= observation_reg(10 + 12); + IO11 <= observation_reg(11 + 12); + WHEN "010" => + IO0 <= observation_reg(0 + 12 + 12); + IO1 <= observation_reg(1 + 12 + 12); + IO2 <= observation_reg(2 + 12 + 12); + IO3 <= observation_reg(3 + 12 + 12); + IO4 <= observation_reg(4 + 12 + 12); + IO5 <= observation_reg(5 + 12 + 12); + IO6 <= observation_reg(6 + 12 + 12); + IO7 <= observation_reg(7 + 12 + 12); + IO8 <= ADC_SDO(0) OR ADC_SDO(1) OR ADC_SDO(2); + IO9 <= ADC_SDO(3) OR ADC_SDO(4) OR ADC_SDO(5); + IO10 <= ADC_SDO(6) OR ADC_SDO(7) ; + IO11 <= '0'; + WHEN "000" => + IO0 <= observation_vector_0(0); + IO1 <= observation_vector_0(1); + IO2 <= observation_vector_0(2); + IO3 <= observation_vector_0(3); + IO4 <= observation_vector_0(4); + IO5 <= observation_vector_0(5); + IO6 <= observation_vector_0(6); + IO7 <= observation_vector_0(7); + IO8 <= observation_vector_0(8); + IO9 <= observation_vector_0(9); + IO10 <= observation_vector_0(10); + IO11 <= observation_vector_0(11); + WHEN "100" => + IO0 <= observation_vector_1(0); + IO1 <= observation_vector_1(1); + IO2 <= observation_vector_1(2); + IO3 <= observation_vector_1(3); + IO4 <= observation_vector_1(4); + IO5 <= observation_vector_1(5); + IO6 <= observation_vector_1(6); + IO7 <= observation_vector_1(7); + IO8 <= observation_vector_1(8); + IO9 <= observation_vector_1(9); + IO10 <= observation_vector_1(10); + IO11 <= observation_vector_1(11); + WHEN OTHERS => NULL; + END CASE; + + END IF; + END PROCESS; + +END beh; diff --git a/designs/MINI-LFR_testFFTb/Makefile b/designs/MINI-LFR_testFFTb/Makefile new file mode 100644 --- /dev/null +++ b/designs/MINI-LFR_testFFTb/Makefile @@ -0,0 +1,47 @@ +VHDLIB=../.. +SCRIPTSDIR=$(VHDLIB)/scripts/ +GRLIB := $(shell sh $(VHDLIB)/scripts/lpp_relpath.sh) +TOP=MINI_LFR_top +BOARD=MINI-LFR +include $(VHDLIB)/boards/$(BOARD)/Makefile.inc +DEVICE=$(PART)-$(PACKAGE)$(SPEED) +UCF=$(VHDLIB)/boards/$(BOARD)/$(TOP).ucf +QSF=$(VHDLIB)/boards/$(BOARD)/$(TOP).qsf +EFFORT=high +XSTOPT= +SYNPOPT="set_option -pipe 0; set_option -retiming 0; set_option -write_apr_constraint 0" +VHDLSYNFILES= MINI_LFR_top.vhd lpp_lfr_apbreg.vhd lpp_lfr_ms_validation.vhd + +PDC=$(VHDLIB)/boards/$(BOARD)/default.pdc +BITGEN=$(VHDLIB)/boards/$(BOARD)/default.ut +CLEAN=soft-clean + +TECHLIBS = proasic3e + +LIBSKIP = core1553bbc core1553brm core1553brt gr1553 corePCIF \ + tmtc openchip hynix ihp gleichmann micron usbhc + +DIRSKIP = b1553 pcif leon2 leon2ft crypto satcan ddr usb ata i2c \ + pci grusbhc haps slink ascs pwm coremp7 spi ac97 \ + ./amba_lcd_16x2_ctrlr \ + ./general_purpose/lpp_AMR \ + ./general_purpose/lpp_balise \ + ./general_purpose/lpp_delay \ + ./lpp_bootloader \ + ./lpp_cna \ + ./lpp_uart \ + ./lpp_usb \ + ./dsp/lpp_fft_rtax \ + ./lpp_sim/CY7C1061DV33 \ + +FILESKIP =i2cmst.vhd \ + APB_MULTI_DIODE.vhd \ + APB_SIMPLE_DIODE.vhd \ + Top_MatrixSpec.vhd \ + APB_FFT.vhd + +include $(GRLIB)/bin/Makefile +include $(GRLIB)/software/leon3/Makefile + +################## project specific targets ########################## + diff --git a/designs/MINI-LFR_testFFTb/fft_test.vhd b/designs/MINI-LFR_testFFTb/fft_test.vhd new file mode 100644 --- /dev/null +++ b/designs/MINI-LFR_testFFTb/fft_test.vhd @@ -0,0 +1,75 @@ +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; + + +LIBRARY lpp; +USE lpp.lpp_memory.ALL; +USE lpp.iir_filter.ALL; +USE lpp.spectral_matrix_package.ALL; +USE lpp.lpp_dma_pkg.ALL; +USE lpp.lpp_Header.ALL; +USE lpp.lpp_matrix.ALL; +USE lpp.lpp_matrix.ALL; +USE lpp.lpp_lfr_pkg.ALL; +USE lpp.lpp_fft.ALL; +USE lpp.fft_components.ALL; + +ENTITY lpp_lfr_ms IS + GENERIC ( + Mem_use : INTEGER := use_RAM + ); + PORT ( + clk : IN STD_LOGIC; + rstn : IN STD_LOGIC; + + ); +END; + +ARCHITECTURE Behavioral OF lpp_lfr_ms IS + +BEGIN + + ----------------------------------------------------------------------------- + + lppFIFOxN_f0_a : lppFIFOxN + GENERIC MAP ( + tech => 0, + Mem_use => Mem_use, + Data_sz => 16, + Addr_sz => 8, + FifoCnt => 5) + PORT MAP ( + clk => clk, + rstn => rstn, + + ReUse => (OTHERS => '0'), + + wen => sample_f0_A_wen, + wdata => sample_f0_wdata, + + ren => sample_f0_A_ren, + rdata => sample_f0_A_rdata, + + empty => sample_f0_A_empty, + full => sample_f0_A_full, + almost_full => OPEN); + + ----------------------------------------------------------------------------- + + lpp_lfr_ms_FFT_1 : lpp_lfr_ms_FFT + PORT MAP ( + clk => clk, + rstn => rstn, + sample_valid => sample_valid, -- WRITE in + fft_read => fft_read, -- READ in + sample_data => sample_data, -- WRITE in + sample_load => sample_load, -- WRITE out + fft_pong => fft_pong, -- READ out + fft_data_im => fft_data_im, -- READ out + fft_data_re => fft_data_re, -- READ out + fft_data_valid => fft_data_valid, -- READ out + fft_ready => fft_ready); -- READ out + + ----------------------------------------------------------------------------- + +END Behavioral; diff --git a/designs/MINI-LFR_testFFTb/lpp_lfr_apbreg.vhd b/designs/MINI-LFR_testFFTb/lpp_lfr_apbreg.vhd new file mode 100644 --- /dev/null +++ b/designs/MINI-LFR_testFFTb/lpp_lfr_apbreg.vhd @@ -0,0 +1,209 @@ +------------------------------------------------------------------------------ +-- This file is a part of the LPP VHDL IP LIBRARY +-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 3 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +------------------------------------------------------------------------------- +-- Author : Jean-christophe Pellion +-- Mail : jean-christophe.pellion@lpp.polytechnique.fr +-- jean-christophe.pellion@easii-ic.com +---------------------------------------------------------------------------- +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.numeric_std.ALL; +LIBRARY grlib; +USE grlib.amba.ALL; +USE grlib.stdlib.ALL; +USE grlib.devices.ALL; +LIBRARY lpp; +USE lpp.lpp_lfr_pkg.ALL; +--USE lpp.lpp_amba.ALL; +USE lpp.apb_devices_list.ALL; +USE lpp.lpp_memory.ALL; +LIBRARY techmap; +USE techmap.gencomp.ALL; + +ENTITY lpp_lfr_apbreg_tb IS + GENERIC ( + pindex : INTEGER := 4; + paddr : INTEGER := 4; + pmask : INTEGER := 16#fff#); + PORT ( + -- AMBA AHB system signals + HCLK : IN STD_ULOGIC; + HRESETn : IN STD_ULOGIC; + + -- AMBA APB Slave Interface + apbi : IN apb_slv_in_type; + apbo : OUT apb_slv_out_type; + + --------------------------------------------------------------------------- + sample_f0_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); + sample_f1_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); + sample_f2_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); + + sample_f0_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); + sample_f1_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); + sample_f2_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); + --------------------------------------------------------------------------- + MEM_IN_SM_locked : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); + MEM_IN_SM_ReUse : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); + MEM_IN_SM_ren : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); + MEM_IN_SM_rData : IN STD_LOGIC_VECTOR(16*2*5-1 DOWNTO 0); + MEM_IN_SM_Full : IN STD_LOGIC_VECTOR(4 DOWNTO 0); + MEM_IN_SM_Empty : IN STD_LOGIC_VECTOR(4 DOWNTO 0) + --------------------------------------------------------------------------- + ); + +END lpp_lfr_apbreg_tb; + +ARCHITECTURE beh OF lpp_lfr_apbreg_tb IS + + CONSTANT REVISION : INTEGER := 1; + + CONSTANT pconfig : apb_config_type := ( + 0 => ahb_device_reg (VENDOR_LPP, LPP_LFR, 0, REVISION, 1), + 1 => apb_iobar(paddr, pmask)); + + TYPE reg_debug_fft IS RECORD + in_data_f0 : STD_LOGIC_VECTOR(5*16-1 DOWNTO 0); + in_data_f1 : STD_LOGIC_VECTOR(5*16-1 DOWNTO 0); + in_data_f2 : STD_LOGIC_VECTOR(5*16-1 DOWNTO 0); + + in_wen_f0 : STD_LOGIC_VECTOR(4 DOWNTO 0); + in_wen_f1 : STD_LOGIC_VECTOR(4 DOWNTO 0); + in_wen_f2 : STD_LOGIC_VECTOR(4 DOWNTO 0); + -- + out_reuse : STD_LOGIC_VECTOR(4 DOWNTO 0); + out_locked : STD_LOGIC_VECTOR(4 DOWNTO 0); + out_ren : STD_LOGIC_VECTOR(4 DOWNTO 0); + END RECORD; + SIGNAL reg_ftt : reg_debug_fft; + + SIGNAL prdata : STD_LOGIC_VECTOR(31 DOWNTO 0); + +BEGIN -- beh + + --------------------------------------------------------------------------- + sample_f0_wen <= reg_ftt.in_wen_f0; + sample_f1_wen <= reg_ftt.in_wen_f1; + sample_f2_wen <= reg_ftt.in_wen_f2; + + sample_f0_wdata <= reg_ftt.in_data_f0; + sample_f1_wdata <= reg_ftt.in_data_f1; + sample_f2_wdata <= reg_ftt.in_data_f2; + --------------------------------------------------------------------------- + MEM_IN_SM_ReUse <= reg_ftt.out_reuse; + MEM_IN_SM_locked <= reg_ftt.out_locked; + MEM_IN_SM_ren <= reg_ftt.out_ren; + --------------------------------------------------------------------------- + + lpp_lfr_apbreg : PROCESS (HCLK, HRESETn) + VARIABLE paddr : STD_LOGIC_VECTOR(7 DOWNTO 2); + BEGIN + IF HRESETn = '0' THEN + + reg_ftt.in_data_f0 <= (OTHERS => '0'); + reg_ftt.in_data_f1 <= (OTHERS => '0'); + reg_ftt.in_data_f2 <= (OTHERS => '0'); + + reg_ftt.in_wen_f0 <= (OTHERS => '1'); + reg_ftt.in_wen_f1 <= (OTHERS => '1'); + reg_ftt.in_wen_f2 <= (OTHERS => '1'); + + + reg_ftt.out_reuse <= (OTHERS => '0'); + reg_ftt.out_locked <= (OTHERS => '0'); + reg_ftt.out_ren <= (OTHERS => '1'); + + ELSIF HCLK'EVENT AND HCLK = '1' THEN -- rising clock edge + + + reg_ftt.in_wen_f0 <= (OTHERS => '1'); + reg_ftt.in_wen_f1 <= (OTHERS => '1'); + reg_ftt.in_wen_f2 <= (OTHERS => '1'); + reg_ftt.out_ren <= (OTHERS => '1'); + + paddr := "000000"; + paddr(7 DOWNTO 2) := apbi.paddr(7 DOWNTO 2); + prdata <= (OTHERS => '0'); + IF apbi.psel(pindex) = '1' THEN + -- APB DMA READ -- + CASE paddr(7 DOWNTO 2) IS + --0 + WHEN "000000" => prdata(31 DOWNTO 0) <= reg_ftt.in_data_f0(31 DOWNTO 0); + WHEN "000001" => prdata(31 DOWNTO 0) <= reg_ftt.in_data_f0(63 DOWNTO 32); + WHEN "000010" => prdata(15 DOWNTO 0) <= reg_ftt.in_data_f0(79 DOWNTO 64); + WHEN "000011" => prdata(4 DOWNTO 0) <= reg_ftt.in_wen_f0; + + WHEN "000100" => prdata(31 DOWNTO 0) <= reg_ftt.in_data_f1(31 DOWNTO 0); + WHEN "000101" => prdata(31 DOWNTO 0) <= reg_ftt.in_data_f1(63 DOWNTO 32); + WHEN "000110" => prdata(15 DOWNTO 0) <= reg_ftt.in_data_f1(79 DOWNTO 64); + WHEN "000111" => prdata(4 DOWNTO 0) <= reg_ftt.in_wen_f1; + + WHEN "001000" => prdata(31 DOWNTO 0) <= reg_ftt.in_data_f2(31 DOWNTO 0); + WHEN "001001" => prdata(31 DOWNTO 0) <= reg_ftt.in_data_f2(63 DOWNTO 32); + WHEN "001010" => prdata(15 DOWNTO 0) <= reg_ftt.in_data_f2(79 DOWNTO 64); + WHEN "001011" => prdata(4 DOWNTO 0) <= reg_ftt.in_wen_f2; + + WHEN "001100" => prdata(31 DOWNTO 0) <= MEM_IN_SM_rData(32*1-1 DOWNTO 32*0); + WHEN "001101" => prdata(31 DOWNTO 0) <= MEM_IN_SM_rData(32*2-1 DOWNTO 32*1); + WHEN "001110" => prdata(31 DOWNTO 0) <= MEM_IN_SM_rData(32*3-1 DOWNTO 32*2); + WHEN "001111" => prdata(31 DOWNTO 0) <= MEM_IN_SM_rData(32*4-1 DOWNTO 32*3); + WHEN "010000" => prdata(31 DOWNTO 0) <= MEM_IN_SM_rData(32*5-1 DOWNTO 32*4); + + WHEN "010001" => prdata(4 DOWNTO 0) <= reg_ftt.out_ren; + prdata(9 DOWNTO 5) <= reg_ftt.out_reuse; + prdata(14 DOWNTO 10) <= reg_ftt.out_locked; + prdata(19 DOWNTO 15) <= MEM_IN_SM_Full; + prdata(24 DOWNTO 20) <= MEM_IN_SM_Empty; + WHEN OTHERS => NULL; + + END CASE; + IF (apbi.pwrite AND apbi.penable) = '1' THEN + -- APB DMA WRITE -- + CASE paddr(7 DOWNTO 2) IS + WHEN "000000" => reg_ftt.in_data_f0(31 DOWNTO 0) <= apbi.pwdata; + WHEN "000001" => reg_ftt.in_data_f0(63 DOWNTO 32) <= apbi.pwdata; + WHEN "000010" => reg_ftt.in_data_f0(79 DOWNTO 64) <= apbi.pwdata(15 DOWNTO 0); + WHEN "000011" => reg_ftt.in_wen_f0 <= apbi.pwdata(4 DOWNTO 0); + + WHEN "000100" => reg_ftt.in_data_f1(31 DOWNTO 0) <= apbi.pwdata; + WHEN "000101" => reg_ftt.in_data_f1(63 DOWNTO 32) <= apbi.pwdata; + WHEN "000110" => reg_ftt.in_data_f1(79 DOWNTO 64) <= apbi.pwdata(15 DOWNTO 0); + WHEN "000111" => reg_ftt.in_wen_f1 <= apbi.pwdata(4 DOWNTO 0); + + WHEN "001000" => reg_ftt.in_data_f2(31 DOWNTO 0) <= apbi.pwdata; + WHEN "001001" => reg_ftt.in_data_f2(63 DOWNTO 32) <= apbi.pwdata; + WHEN "001010" => reg_ftt.in_data_f2(79 DOWNTO 64) <= apbi.pwdata(15 DOWNTO 0); + WHEN "001011" => reg_ftt.in_wen_f2 <= apbi.pwdata(4 DOWNTO 0); + + WHEN "010001" => reg_ftt.out_ren <= apbi.pwdata(4 DOWNTO 0); + reg_ftt.out_reuse <= apbi.pwdata(9 DOWNTO 5); + reg_ftt.out_locked <= apbi.pwdata(14 DOWNTO 10); + + WHEN OTHERS => NULL; + END CASE; + END IF; + END IF; + + END IF; + END PROCESS lpp_lfr_apbreg; + + apbo.pindex <= pindex; + apbo.pconfig <= pconfig; + apbo.prdata <= prdata; + +END beh; diff --git a/designs/MINI-LFR_testFFTb/lpp_lfr_apbreg_2.vhd b/designs/MINI-LFR_testFFTb/lpp_lfr_apbreg_2.vhd new file mode 100644 --- /dev/null +++ b/designs/MINI-LFR_testFFTb/lpp_lfr_apbreg_2.vhd @@ -0,0 +1,209 @@ +------------------------------------------------------------------------------ +-- This file is a part of the LPP VHDL IP LIBRARY +-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 3 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +------------------------------------------------------------------------------- +-- Author : Jean-christophe Pellion +-- Mail : jean-christophe.pellion@lpp.polytechnique.fr +-- jean-christophe.pellion@easii-ic.com +---------------------------------------------------------------------------- +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.numeric_std.ALL; +LIBRARY grlib; +USE grlib.amba.ALL; +USE grlib.stdlib.ALL; +USE grlib.devices.ALL; +LIBRARY lpp; +USE lpp.lpp_lfr_pkg.ALL; +--USE lpp.lpp_amba.ALL; +USE lpp.apb_devices_list.ALL; +USE lpp.lpp_memory.ALL; +LIBRARY techmap; +USE techmap.gencomp.ALL; + +ENTITY lpp_lfr_apbreg_tb IS + GENERIC ( + pindex : INTEGER := 4; + paddr : INTEGER := 4; + pmask : INTEGER := 16#fff#); + PORT ( + -- AMBA AHB system signals + HCLK : IN STD_ULOGIC; + HRESETn : IN STD_ULOGIC; + + -- AMBA APB Slave Interface + apbi : IN apb_slv_in_type; + apbo : OUT apb_slv_out_type; + + --------------------------------------------------------------------------- + sample_f0_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); + sample_f1_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); + sample_f2_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); + + sample_f0_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); + sample_f1_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); + sample_f2_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); + --------------------------------------------------------------------------- + MEM_IN_SM_locked : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); + MEM_IN_SM_ReUse : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); + MEM_IN_SM_ren : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); + MEM_IN_SM_rData : IN STD_LOGIC_VECTOR(16*2*5-1 DOWNTO 0); + MEM_IN_SM_Full : IN STD_LOGIC_VECTOR(4 DOWNTO 0); + MEM_IN_SM_Empty : IN STD_LOGIC_VECTOR(4 DOWNTO 0) + --------------------------------------------------------------------------- + ); + +END lpp_lfr_apbreg_tb; + +ARCHITECTURE beh OF lpp_lfr_apbreg_tb IS + + CONSTANT REVISION : INTEGER := 1; + + CONSTANT pconfig : apb_config_type := ( + 0 => ahb_device_reg (VENDOR_LPP, LPP_LFR, 0, REVISION, 1), + 1 => apb_iobar(paddr, pmask)); + + TYPE reg_debug_fft IS RECORD + in_data_f0 : STD_LOGIC_VECTOR(5*16-1 DOWNTO 0); + in_data_f1 : STD_LOGIC_VECTOR(5*16-1 DOWNTO 0); + in_data_f2 : STD_LOGIC_VECTOR(5*16-1 DOWNTO 0); + + in_wen_f0 : STD_LOGIC_VECTOR(4 DOWNTO 0); + in_wen_f1 : STD_LOGIC_VECTOR(4 DOWNTO 0); + in_wen_f2 : STD_LOGIC_VECTOR(4 DOWNTO 0); + -- + out_reuse : STD_LOGIC_VECTOR(4 DOWNTO 0); + out_locked : STD_LOGIC_VECTOR(4 DOWNTO 0); + out_ren : STD_LOGIC_VECTOR(4 DOWNTO 0); + END RECORD; + SIGNAL reg_ftt : reg_debug_fft; + + SIGNAL prdata : STD_LOGIC_VECTOR(31 DOWNTO 0); + +BEGIN -- beh + + --------------------------------------------------------------------------- + sample_f0_wen <= reg_ftt.in_wen_f0; + sample_f1_wen <= reg_ftt.in_wen_f1; + sample_f2_wen <= reg_ftt.in_wen_f2; + + sample_f0_wdata <= reg_ftt.in_data_f0; + sample_f1_wdata <= reg_ftt.in_data_f1; + sample_f2_wdata <= reg_ftt.in_data_f2; + --------------------------------------------------------------------------- + MEM_IN_SM_ReUse <= reg_ftt.out_reuse; + MEM_IN_SM_locked <= reg_ftt.out_locked; + MEM_IN_SM_ren <= reg_ftt.out_ren; + --------------------------------------------------------------------------- + + lpp_lfr_apbreg : PROCESS (HCLK, HRESETn) + VARIABLE paddr : STD_LOGIC_VECTOR(7 DOWNTO 2); + BEGIN + IF HRESETn = '0' THEN + + reg_ftt.in_data_f0 <= (OTHERS => '0'); + reg_ftt.in_data_f1 <= (OTHERS => '0'); + reg_ftt.in_data_f2 <= (OTHERS => '0'); + + reg_ftt.in_wen_f0 <= (OTHERS => '1'); + reg_ftt.in_wen_f1 <= (OTHERS => '1'); + reg_ftt.in_wen_f2 <= (OTHERS => '1'); + + + reg_ftt.out_reuse <= (OTHERS => '0'); + reg_ftt.out_locked <= (OTHERS => '0'); + reg_ftt.out_ren <= (OTHERS => '1'); + + ELSIF HCLK'EVENT AND HCLK = '1' THEN -- rising clock edge + + + reg_ftt.in_wen_f0 <= (OTHERS => '1'); + reg_ftt.in_wen_f1 <= (OTHERS => '1'); + reg_ftt.in_wen_f2 <= (OTHERS => '1'); + reg_ftt.out_ren <= (OTHERS => '1'); + + paddr := "000000"; + paddr(7 DOWNTO 2) := apbi.paddr(7 DOWNTO 2); + prdata <= (OTHERS => '0'); + IF apbi.psel(pindex) = '1' THEN + -- APB DMA READ -- + CASE paddr(7 DOWNTO 2) IS + --0 + WHEN "000000" => prdata(31 DOWNTO 0) <= reg_ftt.in_data_f0(31 DOWNTO 0); + WHEN "000001" => prdata(31 DOWNTO 0) <= reg_ftt.in_data_f0(63 DOWNTO 32); + WHEN "000010" => prdata(15 DOWNTO 0) <= reg_ftt.in_data_f0(79 DOWNTO 64); + WHEN "000011" => prdata(4 DOWNTO 0) <= reg_ftt.in_wen_f0; + + WHEN "000100" => prdata(31 DOWNTO 0) <= reg_ftt.in_data_f1(31 DOWNTO 0); + WHEN "000101" => prdata(31 DOWNTO 0) <= reg_ftt.in_data_f1(63 DOWNTO 32); + WHEN "000110" => prdata(15 DOWNTO 0) <= reg_ftt.in_data_f1(79 DOWNTO 64); + WHEN "000111" => prdata(4 DOWNTO 0) <= reg_ftt.in_wen_f1; + + WHEN "001000" => prdata(31 DOWNTO 0) <= reg_ftt.in_data_f2(31 DOWNTO 0); + WHEN "001001" => prdata(31 DOWNTO 0) <= reg_ftt.in_data_f2(63 DOWNTO 32); + WHEN "001010" => prdata(15 DOWNTO 0) <= reg_ftt.in_data_f2(79 DOWNTO 64); + WHEN "001011" => prdata(4 DOWNTO 0) <= reg_ftt.in_wen_f2; + + WHEN "001100" => prdata(31 DOWNTO 0) <= MEM_IN_SM_rData(32*1-1 DOWNTO 32*0); + WHEN "001101" => prdata(31 DOWNTO 0) <= MEM_IN_SM_rData(32*2-1 DOWNTO 32*1); + WHEN "001110" => prdata(31 DOWNTO 0) <= MEM_IN_SM_rData(32*3-1 DOWNTO 32*2); + WHEN "001111" => prdata(31 DOWNTO 0) <= MEM_IN_SM_rData(32*4-1 DOWNTO 32*3); + WHEN "010000" => prdata(31 DOWNTO 0) <= MEM_IN_SM_rData(32*5-1 DOWNTO 32*4); + + WHEN "010001" => prdata(4 DOWNTO 0) <= reg_ftt.out_ren; + prdata(9 DOWNTO 5) <= reg_ftt.out_reuse; + prdata(14 DOWNTO 10) <= reg_ftt.out_locked; + prdata(19 DOWNTO 15) <= MEM_IN_SM_Full; + prdata(24 DOWNTO 20) <= MEM_IN_SM_Empty; + WHEN OTHERS => NULL; + + END CASE; + IF (apbi.pwrite AND apbi.penable) = '1' THEN + -- APB DMA WRITE -- + CASE paddr(7 DOWNTO 2) IS + WHEN "000000" => reg_ftt.in_data_f0(31 DOWNTO 0) <= apbi.pwdata; + WHEN "000001" => reg_ftt.in_data_f0(63 DOWNTO 32) <= apbi.pwdata; + WHEN "000010" => reg_ftt.in_data_f0(79 DOWNTO 64) <= apbi.pwdata(15 DOWNTO 0); + WHEN "000011" => reg_ftt.in_wen_f0 <= apbi.pwdata(4 DOWNTO 0); + + WHEN "000100" => reg_ftt.in_data_f1(31 DOWNTO 0) <= apbi.pwdata; + WHEN "000101" => reg_ftt.in_data_f1(63 DOWNTO 32) <= apbi.pwdata; + WHEN "000110" => reg_ftt.in_data_f1(79 DOWNTO 64) <= apbi.pwdata(15 DOWNTO 0); + WHEN "000111" => reg_ftt.in_wen_f1 <= apbi.pwdata(4 DOWNTO 0); + + WHEN "001000" => reg_ftt.in_data_f2(31 DOWNTO 0) <= apbi.pwdata; + WHEN "001001" => reg_ftt.in_data_f2(63 DOWNTO 32) <= apbi.pwdata; + WHEN "001010" => reg_ftt.in_data_f2(79 DOWNTO 64) <= apbi.pwdata(15 DOWNTO 0); + WHEN "001011" => reg_ftt.in_wen_f2 <= apbi.pwdata(4 DOWNTO 0); + + WHEN "010001" => reg_ftt.out_ren <= apbi.pwdata(4 DOWNTO 0); + reg_ftt.out_reuse <= apbi.pwdata(9 DOWNTO 5); + reg_ftt.out_locked <= apbi.pwdata(14 DOWNTO 10); + + WHEN OTHERS => NULL; + END CASE; + END IF; + END IF; + + END IF; + END PROCESS lpp_lfr_apbreg; + + apbo.pindex <= pindex; + apbo.pconfig <= pconfig; + apbo.prdata <= prdata; + +END beh; diff --git a/designs/MINI-LFR_testFFTb/lpp_lfr_ms_validation.vhd b/designs/MINI-LFR_testFFTb/lpp_lfr_ms_validation.vhd new file mode 100644 --- /dev/null +++ b/designs/MINI-LFR_testFFTb/lpp_lfr_ms_validation.vhd @@ -0,0 +1,1016 @@ +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; + + +LIBRARY lpp; +USE lpp.lpp_memory.ALL; +USE lpp.iir_filter.ALL; +USE lpp.spectral_matrix_package.ALL; +USE lpp.lpp_dma_pkg.ALL; +USE lpp.lpp_Header.ALL; +USE lpp.lpp_matrix.ALL; +USE lpp.lpp_matrix.ALL; +USE lpp.lpp_lfr_pkg.ALL; +USE lpp.lpp_fft.ALL; +USE lpp.fft_components.ALL; + +ENTITY lpp_lfr_ms_tb IS + GENERIC ( + Mem_use : INTEGER := use_RAM + ); + PORT ( + clk : IN STD_LOGIC; + rstn : IN STD_LOGIC; + + --------------------------------------------------------------------------- + -- + --------------------------------------------------------------------------- + sample_f0_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0); + sample_f0_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); + -- + sample_f1_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0); + sample_f1_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); + -- + sample_f2_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0); + sample_f2_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); + + + --------------------------------------------------------------------------- + -- + --------------------------------------------------------------------------- + MEM_IN_SM_locked : IN STD_LOGIC_VECTOR(4 DOWNTO 0); + MEM_IN_SM_ReUse : IN STD_LOGIC_VECTOR(4 DOWNTO 0); + MEM_IN_SM_ren : IN STD_LOGIC_VECTOR(4 DOWNTO 0); + MEM_IN_SM_rData : OUT STD_LOGIC_VECTOR(16*2*5-1 DOWNTO 0); + MEM_IN_SM_Full_pad : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); + MEM_IN_SM_Empty_pad : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); + + + --------------------------------------------------------------------------- + -- + --------------------------------------------------------------------------- + error_input_fifo_write : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); + -- + observation_vector_0: OUT STD_LOGIC_VECTOR(11 DOWNTO 0); + observation_vector_1: OUT STD_LOGIC_VECTOR(11 DOWNTO 0) + ); +END; + +ARCHITECTURE Behavioral OF lpp_lfr_ms_tb IS + + SIGNAL sample_f0_A_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); + SIGNAL sample_f0_A_ren : STD_LOGIC_VECTOR(4 DOWNTO 0); + SIGNAL sample_f0_A_wen : STD_LOGIC_VECTOR(4 DOWNTO 0); + SIGNAL sample_f0_A_full : STD_LOGIC_VECTOR(4 DOWNTO 0); + SIGNAL sample_f0_A_empty : STD_LOGIC_VECTOR(4 DOWNTO 0); + + SIGNAL sample_f0_B_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); + SIGNAL sample_f0_B_ren : STD_LOGIC_VECTOR(4 DOWNTO 0); + SIGNAL sample_f0_B_wen : STD_LOGIC_VECTOR(4 DOWNTO 0); + SIGNAL sample_f0_B_full : STD_LOGIC_VECTOR(4 DOWNTO 0); + SIGNAL sample_f0_B_empty : STD_LOGIC_VECTOR(4 DOWNTO 0); + + SIGNAL sample_f1_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); + SIGNAL sample_f1_ren : STD_LOGIC_VECTOR(4 DOWNTO 0); + SIGNAL sample_f1_full : STD_LOGIC_VECTOR(4 DOWNTO 0); + SIGNAL sample_f1_empty : STD_LOGIC_VECTOR(4 DOWNTO 0); + + SIGNAL sample_f1_almost_full : STD_LOGIC_VECTOR(4 DOWNTO 0); + + SIGNAL sample_f2_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); + SIGNAL sample_f2_ren : STD_LOGIC_VECTOR(4 DOWNTO 0); + SIGNAL sample_f2_full : STD_LOGIC_VECTOR(4 DOWNTO 0); + SIGNAL sample_f2_empty : STD_LOGIC_VECTOR(4 DOWNTO 0); + + SIGNAL error_wen_f0 : STD_LOGIC; + SIGNAL error_wen_f1 : STD_LOGIC; + SIGNAL error_wen_f2 : STD_LOGIC; + + SIGNAL one_sample_f1_full : STD_LOGIC; + SIGNAL one_sample_f1_wen : STD_LOGIC; + SIGNAL one_sample_f2_full : STD_LOGIC; + SIGNAL one_sample_f2_wen : STD_LOGIC; + + ----------------------------------------------------------------------------- + -- FSM / SWITCH SELECT CHANNEL + ----------------------------------------------------------------------------- + TYPE fsm_select_channel IS (IDLE, SWITCH_F0_A, SWITCH_F0_B, SWITCH_F1, SWITCH_F2); + SIGNAL state_fsm_select_channel : fsm_select_channel; + SIGNAL pre_state_fsm_select_channel : fsm_select_channel; + + SIGNAL sample_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); + SIGNAL sample_ren : STD_LOGIC_VECTOR(4 DOWNTO 0); + SIGNAL sample_full : STD_LOGIC_VECTOR(4 DOWNTO 0); + SIGNAL sample_empty : STD_LOGIC_VECTOR(4 DOWNTO 0); + + ----------------------------------------------------------------------------- + -- FSM LOAD FFT + ----------------------------------------------------------------------------- + TYPE fsm_load_FFT IS (IDLE, FIFO_1, FIFO_2, FIFO_3, FIFO_4, FIFO_5); + SIGNAL state_fsm_load_FFT : fsm_load_FFT; + SIGNAL next_state_fsm_load_FFT : fsm_load_FFT; + + SIGNAL sample_ren_s : STD_LOGIC_VECTOR(4 DOWNTO 0); + SIGNAL sample_load : STD_LOGIC; + SIGNAL sample_valid : STD_LOGIC; + SIGNAL sample_valid_r : STD_LOGIC; + SIGNAL sample_data : STD_LOGIC_VECTOR(15 DOWNTO 0); + + + ----------------------------------------------------------------------------- + -- FFT + ----------------------------------------------------------------------------- + SIGNAL fft_read : STD_LOGIC; + SIGNAL fft_pong : STD_LOGIC; + SIGNAL fft_data_im : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL fft_data_re : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL fft_data_valid : STD_LOGIC; + SIGNAL fft_ready : STD_LOGIC; + ----------------------------------------------------------------------------- +-- SIGNAL fft_linker_ReUse : STD_LOGIC_VECTOR(4 DOWNTO 0); + ----------------------------------------------------------------------------- + TYPE fsm_load_MS_memory IS (IDLE, LOAD_FIFO, TRASH_FFT); + SIGNAL state_fsm_load_MS_memory : fsm_load_MS_memory; + SIGNAL current_fifo_load : STD_LOGIC_VECTOR(4 DOWNTO 0); + SIGNAL current_fifo_empty : STD_LOGIC; + SIGNAL current_fifo_locked : STD_LOGIC; + SIGNAL current_fifo_full : STD_LOGIC; +-- SIGNAL MEM_IN_SM_locked : STD_LOGIC_VECTOR(4 DOWNTO 0); + + ----------------------------------------------------------------------------- +-- SIGNAL MEM_IN_SM_ReUse : STD_LOGIC_VECTOR(4 DOWNTO 0); + SIGNAL MEM_IN_SM_wen : STD_LOGIC_VECTOR(4 DOWNTO 0); + SIGNAL MEM_IN_SM_wen_s : STD_LOGIC_VECTOR(4 DOWNTO 0); + SIGNAL MEM_IN_SM_wData : STD_LOGIC_VECTOR(16*2*5-1 DOWNTO 0); + +-- SIGNAL MEM_IN_SM_ren : STD_LOGIC_VECTOR(4 DOWNTO 0); +-- SIGNAL MEM_IN_SM_rData : STD_LOGIC_VECTOR(16*2*5-1 DOWNTO 0); + SIGNAL MEM_IN_SM_Full : STD_LOGIC_VECTOR(4 DOWNTO 0); + SIGNAL MEM_IN_SM_Empty : STD_LOGIC_VECTOR(4 DOWNTO 0); + ----------------------------------------------------------------------------- + SIGNAL SM_in_data : STD_LOGIC_VECTOR(32*2-1 DOWNTO 0); + SIGNAL SM_in_ren : STD_LOGIC_VECTOR(1 DOWNTO 0); + SIGNAL SM_in_empty : STD_LOGIC_VECTOR(1 DOWNTO 0); + + SIGNAL SM_correlation_start : STD_LOGIC; + SIGNAL SM_correlation_auto : STD_LOGIC; + SIGNAL SM_correlation_done : STD_LOGIC; + SIGNAL SM_correlation_done_reg1 : STD_LOGIC; + SIGNAL SM_correlation_done_reg2 : STD_LOGIC; + SIGNAL SM_correlation_done_reg3 : STD_LOGIC; + SIGNAL SM_correlation_begin : STD_LOGIC; + + SIGNAL MEM_OUT_SM_Full_s : STD_LOGIC; + SIGNAL MEM_OUT_SM_Data_in_s : STD_LOGIC_VECTOR(31 DOWNTO 0); + SIGNAL MEM_OUT_SM_Write_s : STD_LOGIC; + + SIGNAL current_matrix_write : STD_LOGIC; + SIGNAL current_matrix_wait_empty : STD_LOGIC; + ----------------------------------------------------------------------------- + SIGNAL fifo_0_ready : STD_LOGIC; + SIGNAL fifo_1_ready : STD_LOGIC; + SIGNAL fifo_ongoing : STD_LOGIC; + + SIGNAL FSM_DMA_fifo_ren : STD_LOGIC; + SIGNAL FSM_DMA_fifo_empty : STD_LOGIC; + SIGNAL FSM_DMA_fifo_data : STD_LOGIC_VECTOR(31 DOWNTO 0); + SIGNAL FSM_DMA_fifo_status : STD_LOGIC_VECTOR(53 DOWNTO 0); + ----------------------------------------------------------------------------- + SIGNAL MEM_OUT_SM_Write : STD_LOGIC_VECTOR(1 DOWNTO 0); + SIGNAL MEM_OUT_SM_Read : STD_LOGIC_VECTOR(1 DOWNTO 0); + SIGNAL MEM_OUT_SM_Data_in : STD_LOGIC_VECTOR(63 DOWNTO 0); + SIGNAL MEM_OUT_SM_Data_out : STD_LOGIC_VECTOR(63 DOWNTO 0); + SIGNAL MEM_OUT_SM_Full : STD_LOGIC_VECTOR(1 DOWNTO 0); + SIGNAL MEM_OUT_SM_Empty : STD_LOGIC_VECTOR(1 DOWNTO 0); + + ----------------------------------------------------------------------------- + -- TIME REG & INFOs + ----------------------------------------------------------------------------- + SIGNAL all_time : STD_LOGIC_VECTOR(47 DOWNTO 0); + + SIGNAL f_empty : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL f_empty_reg : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL time_update_f : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL time_reg_f : STD_LOGIC_VECTOR(48*4-1 DOWNTO 0); + + SIGNAL time_reg_f0_A : STD_LOGIC_VECTOR(47 DOWNTO 0); + SIGNAL time_reg_f0_B : STD_LOGIC_VECTOR(47 DOWNTO 0); + SIGNAL time_reg_f1 : STD_LOGIC_VECTOR(47 DOWNTO 0); + SIGNAL time_reg_f2 : STD_LOGIC_VECTOR(47 DOWNTO 0); + + --SIGNAL time_update_f0_A : STD_LOGIC; + --SIGNAL time_update_f0_B : STD_LOGIC; + --SIGNAL time_update_f1 : STD_LOGIC; + --SIGNAL time_update_f2 : STD_LOGIC; + -- + SIGNAL status_channel : STD_LOGIC_VECTOR(49 DOWNTO 0); + SIGNAL status_MS_input : STD_LOGIC_VECTOR(49 DOWNTO 0); + SIGNAL status_component : STD_LOGIC_VECTOR(53 DOWNTO 0); + + SIGNAL status_component_fifo_0 : STD_LOGIC_VECTOR(53 DOWNTO 0); + SIGNAL status_component_fifo_1 : STD_LOGIC_VECTOR(53 DOWNTO 0); + SIGNAL status_component_fifo_0_end : STD_LOGIC; + SIGNAL status_component_fifo_1_end : STD_LOGIC; + ----------------------------------------------------------------------------- + SIGNAL fft_ongoing_counter : STD_LOGIC;--_VECTOR(1 DOWNTO 0); + + SIGNAL fft_ready_reg : STD_LOGIC; + SIGNAL fft_ready_rising_down : STD_LOGIC; + + SIGNAL sample_load_reg : STD_LOGIC; + SIGNAL sample_load_rising_down : STD_LOGIC; + + ----------------------------------------------------------------------------- + SIGNAL sample_f1_wen_head : STD_LOGIC_VECTOR(4 DOWNTO 0); + SIGNAL sample_f1_wen_head_in : STD_LOGIC; + SIGNAL sample_f1_wen_head_out : STD_LOGIC; + SIGNAL sample_f1_full_head_in : STD_LOGIC; + SIGNAL sample_f1_full_head_out : STD_LOGIC; + SIGNAL sample_f1_empty_head_in : STD_LOGIC; + + SIGNAL sample_f1_wdata_head : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); + +BEGIN + + + error_input_fifo_write <= error_wen_f2 & error_wen_f1 & error_wen_f0; + + + switch_f0_inst : spectral_matrix_switch_f0 + PORT MAP ( + clk => clk, + rstn => rstn, + + sample_wen => sample_f0_wen, + + fifo_A_empty => sample_f0_A_empty, + fifo_A_full => sample_f0_A_full, + fifo_A_wen => sample_f0_A_wen, + + fifo_B_empty => sample_f0_B_empty, + fifo_B_full => sample_f0_B_full, + fifo_B_wen => sample_f0_B_wen, + + error_wen => error_wen_f0); -- TODO + + ----------------------------------------------------------------------------- + -- FIFO IN + ----------------------------------------------------------------------------- + lppFIFOxN_f0_a : lppFIFOxN + GENERIC MAP ( + tech => 0, + Mem_use => Mem_use, + Data_sz => 16, + Addr_sz => 8, + FifoCnt => 5) + PORT MAP ( + clk => clk, + rstn => rstn, + + ReUse => (OTHERS => '0'), + + wen => sample_f0_A_wen, + wdata => sample_f0_wdata, + + ren => sample_f0_A_ren, + rdata => sample_f0_A_rdata, + + empty => sample_f0_A_empty, + full => sample_f0_A_full, + almost_full => OPEN); + + lppFIFOxN_f0_b : lppFIFOxN + GENERIC MAP ( + tech => 0, + Mem_use => Mem_use, + Data_sz => 16, + Addr_sz => 8, + FifoCnt => 5) + PORT MAP ( + clk => clk, + rstn => rstn, + + ReUse => (OTHERS => '0'), + + wen => sample_f0_B_wen, + wdata => sample_f0_wdata, + ren => sample_f0_B_ren, + rdata => sample_f0_B_rdata, + empty => sample_f0_B_empty, + full => sample_f0_B_full, + almost_full => OPEN); + + ----------------------------------------------------------------------------- + -- sample_f1_wen in + -- sample_f1_wdata in + -- sample_f1_full OUT + + sample_f1_wen_head_in <= '0' WHEN sample_f1_wen = "00000" ELSE '1'; + sample_f1_full_head_in <= '0' WHEN sample_f1_full = "00000" ELSE '1'; + sample_f1_empty_head_in <= '1' WHEN sample_f1_empty = "11111" ELSE '0'; + + lpp_lfr_ms_reg_head_1:lpp_lfr_ms_reg_head + PORT MAP ( + clk => clk, + rstn => rstn, + in_wen => sample_f1_wen_head_in, + in_data => sample_f1_wdata, + in_full => sample_f1_full_head_in, + in_empty => sample_f1_empty_head_in, + out_wen => sample_f1_wen_head_out, + out_data => sample_f1_wdata_head, + out_full => sample_f1_full_head_out); + + sample_f1_wen_head <= sample_f1_wen_head_out & sample_f1_wen_head_out & sample_f1_wen_head_out & sample_f1_wen_head_out & sample_f1_wen_head_out; + + + lppFIFOxN_f1 : lppFIFOxN + GENERIC MAP ( + tech => 0, + Mem_use => Mem_use, + Data_sz => 16, + Addr_sz => 8, + FifoCnt => 5) + PORT MAP ( + clk => clk, + rstn => rstn, + + ReUse => (OTHERS => '0'), + + wen => sample_f1_wen_head, + wdata => sample_f1_wdata_head, + ren => sample_f1_ren, + rdata => sample_f1_rdata, + empty => sample_f1_empty, + full => sample_f1_full, + almost_full => sample_f1_almost_full); + + + one_sample_f1_wen <= '0' WHEN sample_f1_wen = "11111" ELSE '1'; + + PROCESS (clk, rstn) + BEGIN -- PROCESS + IF rstn = '0' THEN -- asynchronous reset (active low) + one_sample_f1_full <= '0'; + error_wen_f1 <= '0'; + ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge + IF sample_f1_full_head_out = '0' THEN + one_sample_f1_full <= '0'; + ELSE + one_sample_f1_full <= '1'; + END IF; + error_wen_f1 <= one_sample_f1_wen AND one_sample_f1_full; + END IF; + END PROCESS; + + ----------------------------------------------------------------------------- + + + lppFIFOxN_f2 : lppFIFOxN + GENERIC MAP ( + tech => 0, + Mem_use => Mem_use, + Data_sz => 16, + Addr_sz => 8, + FifoCnt => 5) + PORT MAP ( + clk => clk, + rstn => rstn, + + ReUse => (OTHERS => '0'), + + wen => sample_f2_wen, + wdata => sample_f2_wdata, + ren => sample_f2_ren, + rdata => sample_f2_rdata, + empty => sample_f2_empty, + full => sample_f2_full, + almost_full => OPEN); + + + one_sample_f2_wen <= '0' WHEN sample_f2_wen = "11111" ELSE '1'; + + PROCESS (clk, rstn) + BEGIN -- PROCESS + IF rstn = '0' THEN -- asynchronous reset (active low) + one_sample_f2_full <= '0'; + error_wen_f2 <= '0'; + ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge + IF sample_f2_full = "00000" THEN + one_sample_f2_full <= '0'; + ELSE + one_sample_f2_full <= '1'; + END IF; + error_wen_f2 <= one_sample_f2_wen AND one_sample_f2_full; + END IF; + END PROCESS; + + ----------------------------------------------------------------------------- + -- FSM SELECT CHANNEL + ----------------------------------------------------------------------------- + PROCESS (clk, rstn) + BEGIN + IF rstn = '0' THEN + state_fsm_select_channel <= IDLE; + ELSIF clk'EVENT AND clk = '1' THEN + CASE state_fsm_select_channel IS + WHEN IDLE => + IF sample_f1_full = "11111" THEN + state_fsm_select_channel <= SWITCH_F1; + ELSIF sample_f1_almost_full = "00000" THEN + IF sample_f0_A_full = "11111" THEN + state_fsm_select_channel <= SWITCH_F0_A; + ELSIF sample_f0_B_full = "11111" THEN + state_fsm_select_channel <= SWITCH_F0_B; + ELSIF sample_f2_full = "11111" THEN + state_fsm_select_channel <= SWITCH_F2; + END IF; + END IF; + + WHEN SWITCH_F0_A => + IF sample_f0_A_empty = "11111" THEN + state_fsm_select_channel <= IDLE; + END IF; + WHEN SWITCH_F0_B => + IF sample_f0_B_empty = "11111" THEN + state_fsm_select_channel <= IDLE; + END IF; + WHEN SWITCH_F1 => + IF sample_f1_empty = "11111" THEN + state_fsm_select_channel <= IDLE; + END IF; + WHEN SWITCH_F2 => + IF sample_f2_empty = "11111" THEN + state_fsm_select_channel <= IDLE; + END IF; + WHEN OTHERS => NULL; + END CASE; + + END IF; + END PROCESS; + + PROCESS (clk, rstn) + BEGIN + IF rstn = '0' THEN + pre_state_fsm_select_channel <= IDLE; + ELSIF clk'EVENT AND clk = '1' THEN + pre_state_fsm_select_channel <= state_fsm_select_channel; + END IF; + END PROCESS; + + + ----------------------------------------------------------------------------- + -- SWITCH SELECT CHANNEL + ----------------------------------------------------------------------------- + sample_empty <= sample_f0_A_empty WHEN state_fsm_select_channel = SWITCH_F0_A ELSE + sample_f0_B_empty WHEN state_fsm_select_channel = SWITCH_F0_B ELSE + sample_f1_empty WHEN state_fsm_select_channel = SWITCH_F1 ELSE + sample_f2_empty WHEN state_fsm_select_channel = SWITCH_F2 ELSE + (OTHERS => '1'); + + sample_full <= sample_f0_A_full WHEN state_fsm_select_channel = SWITCH_F0_A ELSE + sample_f0_B_full WHEN state_fsm_select_channel = SWITCH_F0_B ELSE + sample_f1_full WHEN state_fsm_select_channel = SWITCH_F1 ELSE + sample_f2_full WHEN state_fsm_select_channel = SWITCH_F2 ELSE + (OTHERS => '0'); + + sample_rdata <= sample_f0_A_rdata WHEN pre_state_fsm_select_channel = SWITCH_F0_A ELSE + sample_f0_B_rdata WHEN pre_state_fsm_select_channel = SWITCH_F0_B ELSE + sample_f1_rdata WHEN pre_state_fsm_select_channel = SWITCH_F1 ELSE + sample_f2_rdata; -- WHEN state_fsm_select_channel = SWITCH_F2 ELSE + + + sample_f0_A_ren <= sample_ren WHEN state_fsm_select_channel = SWITCH_F0_A ELSE (OTHERS => '1'); + sample_f0_B_ren <= sample_ren WHEN state_fsm_select_channel = SWITCH_F0_B ELSE (OTHERS => '1'); + sample_f1_ren <= sample_ren WHEN state_fsm_select_channel = SWITCH_F1 ELSE (OTHERS => '1'); + sample_f2_ren <= sample_ren WHEN state_fsm_select_channel = SWITCH_F2 ELSE (OTHERS => '1'); + + + status_channel <= time_reg_f0_A & "00" WHEN state_fsm_select_channel = SWITCH_F0_A ELSE + time_reg_f0_B & "00" WHEN state_fsm_select_channel = SWITCH_F0_B ELSE + time_reg_f1 & "01" WHEN state_fsm_select_channel = SWITCH_F1 ELSE + time_reg_f2 & "10"; -- WHEN state_fsm_select_channel = SWITCH_F2 + + ----------------------------------------------------------------------------- + -- FSM LOAD FFT + ----------------------------------------------------------------------------- + + sample_ren <= (OTHERS => '1') WHEN fft_ongoing_counter = '1' ELSE + sample_ren_s WHEN sample_load = '1' ELSE + (OTHERS => '1'); + + PROCESS (clk, rstn) + BEGIN + IF rstn = '0' THEN + sample_ren_s <= (OTHERS => '1'); + state_fsm_load_FFT <= IDLE; + status_MS_input <= (OTHERS => '0'); + --next_state_fsm_load_FFT <= IDLE; + --sample_valid <= '0'; + ELSIF clk'EVENT AND clk = '1' THEN + CASE state_fsm_load_FFT IS + WHEN IDLE => + --sample_valid <= '0'; + sample_ren_s <= (OTHERS => '1'); + IF sample_full = "11111" AND sample_load = '1' THEN + state_fsm_load_FFT <= FIFO_1; + status_MS_input <= status_channel; + END IF; + + WHEN FIFO_1 => + sample_ren_s <= "1111" & NOT(sample_load); + IF sample_empty(0) = '1' THEN + sample_ren_s <= (OTHERS => '1'); + state_fsm_load_FFT <= FIFO_2; + END IF; + + WHEN FIFO_2 => + sample_ren_s <= "111" & NOT(sample_load) & '1'; + IF sample_empty(1) = '1' THEN + sample_ren_s <= (OTHERS => '1'); + state_fsm_load_FFT <= FIFO_3; + END IF; + + WHEN FIFO_3 => + sample_ren_s <= "11" & NOT(sample_load) & "11"; + IF sample_empty(2) = '1' THEN + sample_ren_s <= (OTHERS => '1'); + state_fsm_load_FFT <= FIFO_4; + END IF; + + WHEN FIFO_4 => + sample_ren_s <= '1' & NOT(sample_load) & "111"; + IF sample_empty(3) = '1' THEN + sample_ren_s <= (OTHERS => '1'); + state_fsm_load_FFT <= FIFO_5; + END IF; + + WHEN FIFO_5 => + sample_ren_s <= NOT(sample_load) & "1111"; + IF sample_empty(4) = '1' THEN + sample_ren_s <= (OTHERS => '1'); + state_fsm_load_FFT <= IDLE; + END IF; + WHEN OTHERS => NULL; + END CASE; + END IF; + END PROCESS; + + PROCESS (clk, rstn) + BEGIN + IF rstn = '0' THEN + sample_valid_r <= '0'; + next_state_fsm_load_FFT <= IDLE; + ELSIF clk'EVENT AND clk = '1' THEN + next_state_fsm_load_FFT <= state_fsm_load_FFT; + IF sample_ren_s = "11111" THEN + sample_valid_r <= '0'; + ELSE + sample_valid_r <= '1'; + END IF; + END IF; + END PROCESS; + + sample_valid <= '0' WHEN fft_ongoing_counter = '1' ELSE sample_valid_r AND sample_load; + + sample_data <= sample_rdata(16*1-1 DOWNTO 16*0) WHEN next_state_fsm_load_FFT = FIFO_1 ELSE + sample_rdata(16*2-1 DOWNTO 16*1) WHEN next_state_fsm_load_FFT = FIFO_2 ELSE + sample_rdata(16*3-1 DOWNTO 16*2) WHEN next_state_fsm_load_FFT = FIFO_3 ELSE + sample_rdata(16*4-1 DOWNTO 16*3) WHEN next_state_fsm_load_FFT = FIFO_4 ELSE + sample_rdata(16*5-1 DOWNTO 16*4); --WHEN next_state_fsm_load_FFT = FIFO_5 ELSE + + ----------------------------------------------------------------------------- + -- FFT + ----------------------------------------------------------------------------- + lpp_lfr_ms_FFT_1 : lpp_lfr_ms_FFT + PORT MAP ( + clk => clk, + rstn => rstn, + sample_valid => sample_valid, + fft_read => fft_read, + sample_data => sample_data, + sample_load => sample_load, + fft_pong => fft_pong, + fft_data_im => fft_data_im, + fft_data_re => fft_data_re, + fft_data_valid => fft_data_valid, + fft_ready => fft_ready); + + observation_vector_0(11 DOWNTO 0) <= "000" & --11 10 + fft_ongoing_counter & --9 8 + sample_load_rising_down & --7 + fft_ready_rising_down & --6 + fft_ready & --5 + fft_data_valid & --4 + fft_pong & --3 + sample_load & --2 + fft_read & --1 + sample_valid; --0 + + ----------------------------------------------------------------------------- + fft_ready_rising_down <= fft_ready_reg AND NOT fft_ready; + sample_load_rising_down <= sample_load_reg AND NOT sample_load; + + PROCESS (clk, rstn) + BEGIN + IF rstn = '0' THEN + fft_ready_reg <= '0'; + sample_load_reg <= '0'; + + fft_ongoing_counter <= '0'; + ELSIF clk'event AND clk = '1' THEN + fft_ready_reg <= fft_ready; + sample_load_reg <= sample_load; + + IF fft_ready_rising_down = '1' AND sample_load_rising_down = '0' THEN + fft_ongoing_counter <= '0'; + +-- CASE fft_ongoing_counter IS +-- WHEN "01" => fft_ongoing_counter <= "00"; +---- WHEN "10" => fft_ongoing_counter <= "01"; +-- WHEN OTHERS => NULL; +-- END CASE; + ELSIF fft_ready_rising_down = '0' AND sample_load_rising_down = '1' THEN + fft_ongoing_counter <= '1'; +-- CASE fft_ongoing_counter IS +-- WHEN "00" => fft_ongoing_counter <= "01"; +---- WHEN "01" => fft_ongoing_counter <= "10"; +-- WHEN OTHERS => NULL; +-- END CASE; + END IF; + + END IF; + END PROCESS; + + ----------------------------------------------------------------------------- + PROCESS (clk, rstn) + BEGIN + IF rstn = '0' THEN + state_fsm_load_MS_memory <= IDLE; + current_fifo_load <= "00001"; + ELSIF clk'EVENT AND clk = '1' THEN + CASE state_fsm_load_MS_memory IS + WHEN IDLE => + IF current_fifo_empty = '1' AND fft_ready = '1' AND current_fifo_locked = '0' THEN + state_fsm_load_MS_memory <= LOAD_FIFO; + END IF; + WHEN LOAD_FIFO => + IF current_fifo_full = '1' THEN + state_fsm_load_MS_memory <= TRASH_FFT; + END IF; + WHEN TRASH_FFT => + IF fft_ready = '0' THEN + state_fsm_load_MS_memory <= IDLE; + current_fifo_load <= current_fifo_load(3 DOWNTO 0) & current_fifo_load(4); + END IF; + WHEN OTHERS => NULL; + END CASE; + + END IF; + END PROCESS; + + current_fifo_empty <= MEM_IN_SM_Empty(0) WHEN current_fifo_load(0) = '1' ELSE + MEM_IN_SM_Empty(1) WHEN current_fifo_load(1) = '1' ELSE + MEM_IN_SM_Empty(2) WHEN current_fifo_load(2) = '1' ELSE + MEM_IN_SM_Empty(3) WHEN current_fifo_load(3) = '1' ELSE + MEM_IN_SM_Empty(4); -- WHEN current_fifo_load(3) = '1' ELSE + + current_fifo_full <= MEM_IN_SM_Full(0) WHEN current_fifo_load(0) = '1' ELSE + MEM_IN_SM_Full(1) WHEN current_fifo_load(1) = '1' ELSE + MEM_IN_SM_Full(2) WHEN current_fifo_load(2) = '1' ELSE + MEM_IN_SM_Full(3) WHEN current_fifo_load(3) = '1' ELSE + MEM_IN_SM_Full(4); -- WHEN current_fifo_load(3) = '1' ELSE + + current_fifo_locked <= MEM_IN_SM_locked(0) WHEN current_fifo_load(0) = '1' ELSE + MEM_IN_SM_locked(1) WHEN current_fifo_load(1) = '1' ELSE + MEM_IN_SM_locked(2) WHEN current_fifo_load(2) = '1' ELSE + MEM_IN_SM_locked(3) WHEN current_fifo_load(3) = '1' ELSE + MEM_IN_SM_locked(4); -- WHEN current_fifo_load(3) = '1' ELSE + + fft_read <= '0' WHEN state_fsm_load_MS_memory = IDLE ELSE '1'; + + all_fifo : FOR I IN 4 DOWNTO 0 GENERATE + MEM_IN_SM_wen_s(I) <= '0' WHEN fft_data_valid = '1' + AND state_fsm_load_MS_memory = LOAD_FIFO + AND current_fifo_load(I) = '1' + ELSE '1'; + END GENERATE all_fifo; + + PROCESS (clk, rstn) + BEGIN + IF rstn = '0' THEN + MEM_IN_SM_wen <= (OTHERS => '1'); + ELSIF clk'EVENT AND clk = '1' THEN + MEM_IN_SM_wen <= MEM_IN_SM_wen_s; + END IF; + END PROCESS; + + MEM_IN_SM_wData <= (fft_data_im & fft_data_re) & + (fft_data_im & fft_data_re) & + (fft_data_im & fft_data_re) & + (fft_data_im & fft_data_re) & + (fft_data_im & fft_data_re); + ----------------------------------------------------------------------------- + + + ----------------------------------------------------------------------------- + Mem_In_SpectralMatrix : lppFIFOxN + GENERIC MAP ( + tech => 0, + Mem_use => Mem_use, + Data_sz => 32, --16, + Addr_sz => 8, --8 + FifoCnt => 5) + PORT MAP ( + clk => clk, + rstn => rstn, + + ReUse => MEM_IN_SM_ReUse, + + wen => MEM_IN_SM_wen, + wdata => MEM_IN_SM_wData, + + ren => MEM_IN_SM_ren, + rdata => MEM_IN_SM_rData, + full => MEM_IN_SM_Full, + empty => MEM_IN_SM_Empty, + almost_full => OPEN); + + MEM_IN_SM_Full_pad <= MEM_IN_SM_Full; + MEM_IN_SM_Empty_pad <= MEM_IN_SM_Empty; + + ------------------------------------------------------------------------------- + + --observation_vector_1(11 DOWNTO 0) <= '0' & + -- SM_correlation_done & --4 + -- SM_correlation_auto & --3 + -- SM_correlation_start & + -- SM_correlation_start & --7 + -- status_MS_input(1 DOWNTO 0)& --6..5 + -- MEM_IN_SM_locked(4 DOWNTO 0); --4..0 + + ------------------------------------------------------------------------------- + --MS_control_1 : MS_control + -- PORT MAP ( + -- clk => clk, + -- rstn => rstn, + + -- current_status_ms => status_MS_input, + + -- fifo_in_lock => MEM_IN_SM_locked, + -- fifo_in_data => MEM_IN_SM_rdata, + -- fifo_in_full => MEM_IN_SM_Full, + -- fifo_in_empty => MEM_IN_SM_Empty, + -- fifo_in_ren => MEM_IN_SM_ren, + -- fifo_in_reuse => MEM_IN_SM_ReUse, + + -- fifo_out_data => SM_in_data, + -- fifo_out_ren => SM_in_ren, + -- fifo_out_empty => SM_in_empty, + + -- current_status_component => status_component, + + -- correlation_start => SM_correlation_start, + -- correlation_auto => SM_correlation_auto, + -- correlation_done => SM_correlation_done); + + + --MS_calculation_1 : MS_calculation + -- PORT MAP ( + -- clk => clk, + -- rstn => rstn, + + -- fifo_in_data => SM_in_data, + -- fifo_in_ren => SM_in_ren, + -- fifo_in_empty => SM_in_empty, + + -- fifo_out_data => MEM_OUT_SM_Data_in_s, -- TODO + -- fifo_out_wen => MEM_OUT_SM_Write_s, -- TODO + -- fifo_out_full => MEM_OUT_SM_Full_s, -- TODO + + -- correlation_start => SM_correlation_start, + -- correlation_auto => SM_correlation_auto, + -- correlation_begin => SM_correlation_begin, + -- correlation_done => SM_correlation_done); + + ------------------------------------------------------------------------------- + --PROCESS (clk, rstn) + --BEGIN -- PROCESS + -- IF rstn = '0' THEN -- asynchronous reset (active low) + -- current_matrix_write <= '0'; + -- current_matrix_wait_empty <= '1'; + -- status_component_fifo_0 <= (OTHERS => '0'); + -- status_component_fifo_1 <= (OTHERS => '0'); + -- status_component_fifo_0_end <= '0'; + -- status_component_fifo_1_end <= '0'; + -- SM_correlation_done_reg1 <= '0'; + -- SM_correlation_done_reg2 <= '0'; + -- SM_correlation_done_reg3 <= '0'; + + -- ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge + -- SM_correlation_done_reg1 <= SM_correlation_done; + -- SM_correlation_done_reg2 <= SM_correlation_done_reg1; + -- SM_correlation_done_reg3 <= SM_correlation_done_reg2; + -- status_component_fifo_0_end <= '0'; + -- status_component_fifo_1_end <= '0'; + -- IF SM_correlation_begin = '1' THEN + -- IF current_matrix_write = '0' THEN + -- status_component_fifo_0 <= status_component; + -- ELSE + -- status_component_fifo_1 <= status_component; + -- END IF; + -- END IF; + + -- IF SM_correlation_done_reg3 = '1' THEN + -- IF current_matrix_write = '0' THEN + -- status_component_fifo_0_end <= '1'; + -- ELSE + -- status_component_fifo_1_end <= '1'; + -- END IF; + -- current_matrix_wait_empty <= '1'; + -- current_matrix_write <= NOT current_matrix_write; + -- END IF; + + -- IF current_matrix_wait_empty <= '1' THEN + -- IF current_matrix_write = '0' THEN + -- current_matrix_wait_empty <= NOT MEM_OUT_SM_Empty(0); + -- ELSE + -- current_matrix_wait_empty <= NOT MEM_OUT_SM_Empty(1); + -- END IF; + -- END IF; + + -- END IF; + --END PROCESS; + + --MEM_OUT_SM_Full_s <= '1' WHEN SM_correlation_done = '1' ELSE + -- '1' WHEN SM_correlation_done_reg1 = '1' ELSE + -- '1' WHEN SM_correlation_done_reg2 = '1' ELSE + -- '1' WHEN SM_correlation_done_reg3 = '1' ELSE + -- '1' WHEN current_matrix_wait_empty = '1' ELSE + -- MEM_OUT_SM_Full(0) WHEN current_matrix_write = '0' ELSE + -- MEM_OUT_SM_Full(1); + + --MEM_OUT_SM_Write(0) <= MEM_OUT_SM_Write_s WHEN current_matrix_write = '0' ELSE '1'; + --MEM_OUT_SM_Write(1) <= MEM_OUT_SM_Write_s WHEN current_matrix_write = '1' ELSE '1'; + + --MEM_OUT_SM_Data_in <= MEM_OUT_SM_Data_in_s & MEM_OUT_SM_Data_in_s; + ------------------------------------------------------------------------------- + + --Mem_Out_SpectralMatrix : lppFIFOxN + -- GENERIC MAP ( + -- tech => 0, + -- Mem_use => Mem_use, + -- Data_sz => 32, + -- Addr_sz => 8, + -- FifoCnt => 2) + -- PORT MAP ( + -- clk => clk, + -- rstn => rstn, + + -- ReUse => (OTHERS => '0'), + + -- wen => MEM_OUT_SM_Write, + -- wdata => MEM_OUT_SM_Data_in, + + -- ren => MEM_OUT_SM_Read, + -- rdata => MEM_OUT_SM_Data_out, + + -- full => MEM_OUT_SM_Full, + -- empty => MEM_OUT_SM_Empty, + -- almost_full => OPEN); + +-- ----------------------------------------------------------------------------- +---- MEM_OUT_SM_Read <= "00"; +-- PROCESS (clk, rstn) +-- BEGIN +-- IF rstn = '0' THEN +-- fifo_0_ready <= '0'; +-- fifo_1_ready <= '0'; +-- fifo_ongoing <= '0'; +-- ELSIF clk'EVENT AND clk = '1' THEN +-- IF fifo_0_ready = '1' AND MEM_OUT_SM_Empty(0) = '1' THEN +-- fifo_ongoing <= '1'; +-- fifo_0_ready <= '0'; +-- ELSIF status_component_fifo_0_end = '1' THEN +-- fifo_0_ready <= '1'; +-- END IF; + +-- IF fifo_1_ready = '1' AND MEM_OUT_SM_Empty(1) = '1' THEN +-- fifo_ongoing <= '0'; +-- fifo_1_ready <= '0'; +-- ELSIF status_component_fifo_1_end = '1' THEN +-- fifo_1_ready <= '1'; +-- END IF; + +-- END IF; +-- END PROCESS; + +-- MEM_OUT_SM_Read(0) <= '1' WHEN fifo_ongoing = '1' ELSE +-- '1' WHEN fifo_0_ready = '0' ELSE +-- FSM_DMA_fifo_ren; + +-- MEM_OUT_SM_Read(1) <= '1' WHEN fifo_ongoing = '0' ELSE +-- '1' WHEN fifo_1_ready = '0' ELSE +-- FSM_DMA_fifo_ren; + +-- FSM_DMA_fifo_empty <= MEM_OUT_SM_Empty(0) WHEN fifo_ongoing = '0' AND fifo_0_ready = '1' ELSE +-- MEM_OUT_SM_Empty(1) WHEN fifo_ongoing = '1' AND fifo_1_ready = '1' ELSE +-- '1'; + +-- FSM_DMA_fifo_status <= status_component_fifo_0 WHEN fifo_ongoing = '0' ELSE +-- status_component_fifo_1; + +-- FSM_DMA_fifo_data <= MEM_OUT_SM_Data_out(31 DOWNTO 0) WHEN fifo_ongoing = '0' ELSE +-- MEM_OUT_SM_Data_out(63 DOWNTO 32); + +-- ----------------------------------------------------------------------------- +-- lpp_lfr_ms_fsmdma_1 : lpp_lfr_ms_fsmdma +-- PORT MAP ( +-- HCLK => clk, +-- HRESETn => rstn, + +-- fifo_matrix_type => FSM_DMA_fifo_status(5 DOWNTO 4), +-- fifo_matrix_component => FSM_DMA_fifo_status(3 DOWNTO 0), +-- fifo_matrix_time => FSM_DMA_fifo_status(53 DOWNTO 6), +-- fifo_data => FSM_DMA_fifo_data, +-- fifo_empty => FSM_DMA_fifo_empty, +-- fifo_ren => FSM_DMA_fifo_ren, + +-- dma_addr => dma_addr, +-- dma_data => dma_data, +-- dma_valid => dma_valid, +-- dma_valid_burst => dma_valid_burst, +-- dma_ren => dma_ren, +-- dma_done => dma_done, + +-- ready_matrix_f0 => ready_matrix_f0, +-- ready_matrix_f1 => ready_matrix_f1, +-- ready_matrix_f2 => ready_matrix_f2, + +-- error_bad_component_error => error_bad_component_error, +-- error_buffer_full => error_buffer_full, + +-- debug_reg => debug_reg, +-- status_ready_matrix_f0 => status_ready_matrix_f0, +-- status_ready_matrix_f1 => status_ready_matrix_f1, +-- status_ready_matrix_f2 => status_ready_matrix_f2, + +-- config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix, +-- config_active_interruption_onError => config_active_interruption_onError, + +-- addr_matrix_f0 => addr_matrix_f0, +-- addr_matrix_f1 => addr_matrix_f1, +-- addr_matrix_f2 => addr_matrix_f2, + +-- matrix_time_f0 => matrix_time_f0, +-- matrix_time_f1 => matrix_time_f1, +-- matrix_time_f2 => matrix_time_f2 +-- ); +-- ----------------------------------------------------------------------------- + + + + + +-- ----------------------------------------------------------------------------- +-- -- TIME MANAGMENT +-- ----------------------------------------------------------------------------- +-- all_time <= coarse_time & fine_time; +-- -- +-- f_empty(0) <= '1' WHEN sample_f0_A_empty = "11111" ELSE '0'; +-- f_empty(1) <= '1' WHEN sample_f0_B_empty = "11111" ELSE '0'; +-- f_empty(2) <= '1' WHEN sample_f1_empty = "11111" ELSE '0'; +-- f_empty(3) <= '1' WHEN sample_f2_empty = "11111" ELSE '0'; + +-- all_time_reg: FOR I IN 0 TO 3 GENERATE + +-- PROCESS (clk, rstn) +-- BEGIN +-- IF rstn = '0' THEN +-- f_empty_reg(I) <= '1'; +-- ELSIF clk'event AND clk = '1' THEN +-- f_empty_reg(I) <= f_empty(I); +-- END IF; +-- END PROCESS; + +-- time_update_f(I) <= '1' WHEN f_empty(I) = '0' AND f_empty_reg(I) = '1' ELSE '0'; + +-- s_m_t_m_f0_A : spectral_matrix_time_managment +-- PORT MAP ( +-- clk => clk, +-- rstn => rstn, +-- time_in => all_time, +-- update_1 => time_update_f(I), +-- time_out => time_reg_f((I+1)*48-1 DOWNTO I*48) +-- ); + +-- END GENERATE all_time_reg; + +-- time_reg_f0_A <= time_reg_f((0+1)*48-1 DOWNTO 0*48); +-- time_reg_f0_B <= time_reg_f((1+1)*48-1 DOWNTO 1*48); +-- time_reg_f1 <= time_reg_f((2+1)*48-1 DOWNTO 2*48); +-- time_reg_f2 <= time_reg_f((3+1)*48-1 DOWNTO 3*48); + +-- ----------------------------------------------------------------------------- + +END Behavioral; diff --git a/designs/Validation_RAM_CEL/Makefile b/designs/Validation_RAM_CEL/Makefile new file mode 100644 --- /dev/null +++ b/designs/Validation_RAM_CEL/Makefile @@ -0,0 +1,66 @@ +VHDLIB=../.. +SCRIPTSDIR=$(VHDLIB)/scripts/ + +GRLIB := $(shell sh $(VHDLIB)/scripts/lpp_relpath.sh) +TOP=TB + +CMD_VLIB=vlib +CMD_VMAP=vmap +CMD_VCOM=@vcom -quiet -93 -work + +################## project specific targets ########################## + +all: + @echo "make vsim" + @echo "make libs" + @echo "make clean" + @echo "make vcom_grlib vcom_lpp vcom_tb" + +run: + @vsim work.TB -do run.do + +vsim: libs vcom run + +libs: + @$(CMD_VLIB) modelsim + @$(CMD_VMAP) modelsim modelsim + @$(CMD_VLIB) modelsim/techmap + @$(CMD_VMAP) techmap modelsim/techmap + @$(CMD_VLIB) modelsim/grlib + @$(CMD_VMAP) grlib modelsim/grlib + @$(CMD_VLIB) modelsim/work + @$(CMD_VMAP) work modelsim/work + @echo "libs done" + + +clean: + @rm -Rf modelsim + @rm -Rf modelsim.ini + @rm -Rf *~ + @rm -Rf transcript + @rm -Rf wlft* + @rm -Rf *.wlf + @rm -Rf vish_stacktrace.vstf + @rm -Rf libs.do + +vcom: vcom_grlib vcom_techmap vcom_tb + + +vcom_tb: + $(CMD_VCOM) work $(VHDLIB)/lib/lpp/./dsp/iir_filter/RAM_CEL.vhd + $(CMD_VCOM) work TB.vhd + +vcom_grlib: + $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/stdlib/version.vhd + $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/stdlib/config_types.vhd + $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/stdlib/config.vhd + $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/stdlib/stdlib.vhd + +vcom_techmap: + $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/gencomp/gencomp.vhd + $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/inferred/memory_inferred.vhd + $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/allmem.vhd + $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/syncram.vhd + $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/syncram_2p.vhd + + diff --git a/designs/Validation_RAM_CEL/TB.vhd b/designs/Validation_RAM_CEL/TB.vhd new file mode 100644 --- /dev/null +++ b/designs/Validation_RAM_CEL/TB.vhd @@ -0,0 +1,171 @@ +------------------------------------------------------------------------------ +-- This file is a part of the LPP VHDL IP LIBRARY +-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 3 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +------------------------------------------------------------------------------- +-- Author : Jean-christophe Pellion +-- Mail : jean-christophe.pellion@lpp.polytechnique.fr +------------------------------------------------------------------------------- + +LIBRARY IEEE; +USE IEEE.STD_LOGIC_1164.ALL; +USE IEEE.MATH_REAL.ALL; +USE IEEE.NUMERIC_STD.ALL; + +--LIBRARY lpp; +--USE lpp.iir_filter.ALL; + +LIBRARY techmap; +USE techmap.gencomp.ALL; + +ENTITY TB IS + + +END TB; + + +ARCHITECTURE beh OF TB IS + + COMPONENT RAM_CEL + GENERIC ( + DataSz : integer range 1 to 32; + abits : integer range 2 to 12); + PORT ( + WD : in std_logic_vector(DataSz-1 downto 0); + RD : out std_logic_vector(DataSz-1 downto 0); + WEN, REN : in std_logic; + WADDR : in std_logic_vector(abits-1 downto 0); + RADDR : in std_logic_vector(abits-1 downto 0); + RWCLK, RESET : in std_logic); + END COMPONENT; + + CONSTANT DATA_SIZE : INTEGER := 8; + CONSTANT ADDR_BIT_NUMBER : INTEGER := 8; + + ----------------------------------------------------------------------------- + SIGNAL clk : STD_LOGIC := '0'; + SIGNAL rstn : STD_LOGIC := '0'; + + ----------------------------------------------------------------------------- + SIGNAL write_data : STD_LOGIC_VECTOR(DATA_SIZE-1 DOWNTO 0); + SIGNAL write_addr : STD_LOGIC_VECTOR(ADDR_BIT_NUMBER-1 DOWNTO 0); + SIGNAL write_enable : STD_LOGIC; + SIGNAL write_enable_n : STD_LOGIC; + + SIGNAL read_data_ram : STD_LOGIC_VECTOR(DATA_SIZE-1 DOWNTO 0); + SIGNAL read_data_cel : STD_LOGIC_VECTOR(DATA_SIZE-1 DOWNTO 0); + SIGNAL read_addr : STD_LOGIC_VECTOR(ADDR_BIT_NUMBER-1 DOWNTO 0); + SIGNAL read_enable : STD_LOGIC; + SIGNAL read_enable_n : STD_LOGIC; + ----------------------------------------------------------------------------- + CONSTANT RANDOM_VECTOR_SIZE : INTEGER := DATA_SIZE + ADDR_BIT_NUMBER + ADDR_BIT_NUMBER + 2; + CONSTANT TWO_POWER_RANDOM_VECTOR_SIZE : real := (2**RANDOM_VECTOR_SIZE)*1.0; + SIGNAL random_vector : STD_LOGIC_VECTOR(RANDOM_VECTOR_SIZE-1 DOWNTO 0); + + ----------------------------------------------------------------------------- + SIGNAL error_value : STD_LOGIC; + SIGNAL warning_value : STD_LOGIC; + SIGNAL warning_value_clocked : STD_LOGIC; + + CONSTANT READ_DATA_ALL_X : STD_LOGIC_VECTOR(DATA_SIZE-1 DOWNTO 0) := (OTHERS => 'X'); + CONSTANT READ_DATA_ALL_U : STD_LOGIC_VECTOR(DATA_SIZE-1 DOWNTO 0) := (OTHERS => 'U'); + CONSTANT READ_DATA_ALL_0 : STD_LOGIC_VECTOR(DATA_SIZE-1 DOWNTO 0) := (OTHERS => '0'); + + + +BEGIN -- beh + + clk <= NOT clk AFTER 10 ns; + rstn <= '1' AFTER 30 ns; + ----------------------------------------------------------------------------- + + CEL: RAM_CEL + GENERIC MAP ( + DataSz => DATA_SIZE, + abits => ADDR_BIT_NUMBER) + PORT MAP ( + WD => write_data, + RD => read_data_cel, + WEN => write_enable_n, + REN => read_enable_n, + WADDR => write_addr, + RADDR => read_addr, + + RWCLK => clk, + RESET => rstn); + + RAM : syncram_2p + GENERIC MAP(tech => 0, abits => ADDR_BIT_NUMBER, dbits => DATA_SIZE) + PORT MAP(rclk => clk, renable => read_enable, raddress => read_addr, dataout => read_data_ram, + wclk => clk, write => write_enable, waddress => write_addr, datain => write_data); + + ----------------------------------------------------------------------------- + + PROCESS (clk, rstn) + VARIABLE seed1, seed2 : POSITIVE; + VARIABLE rand1 : REAL; + VARIABLE RANDOM_VECTOR_VAR : STD_LOGIC_VECTOR(RANDOM_VECTOR_SIZE-1 DOWNTO 0); + BEGIN -- PROCESS + IF rstn = '0' THEN -- asynchronous reset (active low) + random_vector <= (OTHERS => '0'); + ELSIF clk'event AND clk = '1' THEN -- rising clock edge + UNIFORM(seed1,seed2,rand1); + RANDOM_VECTOR_VAR := STD_LOGIC_VECTOR( + to_unsigned(INTEGER(TRUNC(rand1*TWO_POWER_RANDOM_VECTOR_SIZE)), + RANDOM_VECTOR_VAR'LENGTH) + ); + + random_vector <= RANDOM_VECTOR_VAR ; + + END IF; + END PROCESS; + + ----------------------------------------------------------------------------- + write_data <= random_vector(DATA_SIZE-1 DOWNTO 0); + write_addr <= random_vector(DATA_SIZE+ADDR_BIT_NUMBER-1 DOWNTO DATA_SIZE); + read_addr <= random_vector(DATA_SIZE+ADDR_BIT_NUMBER+ADDR_BIT_NUMBER-1 DOWNTO DATA_SIZE+ADDR_BIT_NUMBER); + read_enable <= random_vector(RANDOM_VECTOR_SIZE-2); + write_enable <= random_vector(RANDOM_VECTOR_SIZE-1); + + read_enable_n <= NOT read_enable; + write_enable_n <= NOT write_enable; + + ----------------------------------------------------------------------------- + warning_value <= '0' WHEN read_data_ram = read_data_cel ELSE + '1'; + + PROCESS (clk, rstn) + BEGIN -- PROCESS + IF rstn = '0' THEN -- asynchronous reset (active low) + error_value <= '0'; + warning_value_clocked <= '0'; + ELSIF clk'event AND clk = '1' THEN -- rising clock edge + IF read_data_ram = read_data_cel THEN + error_value <= '0'; + warning_value_clocked <= '0'; + ELSE + warning_value_clocked <= '1'; + IF read_data_ram = READ_DATA_ALL_U AND read_data_cel = READ_DATA_ALL_0 THEN + error_value <= '0'; + ELSE + error_value <= '1'; + END IF; + END IF; + END IF; + END PROCESS; + +END beh; + diff --git a/designs/Validation_RAM_CEL/run.do b/designs/Validation_RAM_CEL/run.do new file mode 100644 --- /dev/null +++ b/designs/Validation_RAM_CEL/run.do @@ -0,0 +1,3 @@ +log -R * +do wave.do +run 10 ms \ No newline at end of file diff --git a/designs/Validation_RAM_CEL/wave.do b/designs/Validation_RAM_CEL/wave.do new file mode 100644 --- /dev/null +++ b/designs/Validation_RAM_CEL/wave.do @@ -0,0 +1,34 @@ +onerror {resume} +quietly WaveActivateNextPane {} 0 +add wave -noupdate -expand -group COMMON /tb/clk +add wave -noupdate -expand -group COMMON /tb/rstn +add wave -noupdate -expand -group COMMON /tb/random_vector +add wave -noupdate -expand -group WRITE -radix hexadecimal /tb/write_data +add wave -noupdate -expand -group WRITE -radix hexadecimal /tb/write_addr +add wave -noupdate -expand -group WRITE -radix hexadecimal /tb/write_enable +add wave -noupdate -expand -group WRITE -radix hexadecimal /tb/write_enable_n +add wave -noupdate -expand -group READ -radix hexadecimal /tb/read_data_ram +add wave -noupdate -expand -group READ -radix hexadecimal /tb/read_data_cel +add wave -noupdate -expand -group READ -radix hexadecimal /tb/read_addr +add wave -noupdate -expand -group READ -radix hexadecimal /tb/read_enable +add wave -noupdate -expand -group READ -radix hexadecimal /tb/read_enable_n +add wave -noupdate -radix hexadecimal /tb/warning_value +add wave -noupdate -radix hexadecimal /tb/warning_value_clocked +add wave -noupdate -radix hexadecimal /tb/error_value +TreeUpdate [SetDefaultTree] +WaveRestoreCursors {{Cursor 1} {5926078 ps} 0} {{Cursor 2} {200000 ps} 0} +configure wave -namecolwidth 403 +configure wave -valuecolwidth 198 +configure wave -justifyvalue left +configure wave -signalnamewidth 0 +configure wave -snapdistance 10 +configure wave -datasetprefix 0 +configure wave -rowmargin 4 +configure wave -childrowmargin 2 +configure wave -gridoffset 0 +configure wave -gridperiod 1 +configure wave -griddelta 40 +configure wave -timeline 0 +configure wave -timelineunits ps +update +WaveRestoreZoom {0 ps} {25526182 ps}