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Update SOLO_LFR_LFR-EM timings constraints...
Update SOLO_LFR_LFR-EM timings constraints (due to the fact that we used a A3PE3000L FPGA on the LFR-EM board)
Alexis Jeandet -
r674:b0efa9138022 default
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/ designs / EGSE_ICI
.config Loading ...
DC_GATE_GEN.vhd Loading ...
EGSE_ICI.vhd Loading ...
ICI_EGSE_PROTOCOL.vhd Loading ...
ICI_EGSE_PROTOCOL2.vhd Loading ...
LF_GATE_GEN.vhd Loading ...
MajF_Gen.vhd Loading ...
Makefile Loading ...
MinF_Gen.vhd Loading ...
Serial_driver.vhd Loading ...
config.help Loading ...
config.in Loading ...
config.vhd Loading ...
config.vhd.h Loading ...
config.vhd.in Loading ...
defconfig Loading ...
indata Loading ...
lconfig.tk Loading ...
rhumc.dc Loading ...
testbench.vhd Loading ...
tkconfig.h Loading ...
top.qsf Loading ...
top.rc Loading ...
top.xise Loading ...
top_dc.tcl Loading ...
top_designer.tcl Loading ...
top_designer_act.tcl Loading ...
tsmc13.rc Loading ...
wave.do Loading ...