##// END OF EJS Templates
HG_REPOSITORIES » LPP » INSTRUMENTATION » USERS » PELLION » VHD_Lib
RSS

Clone from http://pc-instru.lpp.polytechnique.fr:5000/VHD_Lib

Update SOLO_LFR_LFR-EM timings constraints...
Update SOLO_LFR_LFR-EM timings constraints (due to the fact that we used a A3PE3000L FPGA on the LFR-EM board)
Alexis Jeandet - - Load All Authors

File last commit:

r217:13429b36c676 alexis
r674:b0efa9138022 default
Show More
top.rc
7 lines | 228 B | text/x-stsrc | TextLexer
/ designs / EGSE_ICI / top.rc
History | Annotation | Raw |Copy content |Copy permalink
set_attribute input_pragma_keyword "cadence synopsys get2chip g2c fast ambit pragma"
include compile.rc
read_hdl -vhdl -lib work config.vhd
read_hdl -vhdl -lib work ahbrom.vhd
read_hdl -vhdl -lib work leon3mp.vhd
elaborate top