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temp : update ADC driver...
temp : update ADC driver - conversion part clocked by clk_49 (49.152 MHz) - cnv_clk = clk_49.152/100 with duty cycle of 50% - 3 period for each Ren, - Data sampling during the 2nd cycle of Ren, - each 2 data input, 1 data output (@)
pellion - - Load All Authors

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r406:c218371d90d3 JC
r594:a9702b7364d2 simu_with_Leon3
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run.do
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log -R *
do wave.do
run 10 ms