temp : update ADC driver...
temp : update ADC driver
- conversion part clocked by clk_49 (49.152 MHz)
- cnv_clk = clk_49.152/100 with duty cycle of 50%
- 3 period for each Ren,
- Data sampling during the 2nd cycle of Ren,
- each 2 data input, 1 data output (@)