HG_REPOSITORIES/LPP/INSTRUMENTATION/USERS/PELLION/VHD_Lib Files · designs/EGSE_ICI/MinF_Gen.vhd

temp : update ADC driver...

temp : update ADC driver - conversion part clocked by clk_49 (49.152 MHz) - cnv_clk = clk_49.152/100 with duty cycle of 50% - 3 period for each Ren, - Data sampling during the 2nd cycle of Ren, - each 2 data input, 1 data output (@)

Alexis Jeandet - - Load All Authors

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             MinF_Gen.vhd
        
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      -- MinF_Gen.vhd

      library IEEE;

      use IEEE.std_logic_1164.all;

      use IEEE.numeric_std.all;

      entity MinF_Gen is 

      generic(WordCnt : integer :=144);

      port(

          clk         :   in  std_logic;

          reset       :   in  std_logic;

          WordCnt_in  :   in  integer range 0 to WordCnt-1;

          WordClk     :   in  std_logic;

          MinF_Clk    :   out std_logic

      );

      end entity;

      architecture arMinF_Gen of MinF_Gen is

      signal monostable : std_logic := '0';

      begin

      process(clk)

      begin

          if reset = '0' then

              MinF_Clk    <=  '0';

              monostable  <=  '1';

          elsif clk'event and clk = '0' then

              if WordCnt_in = 0 and WordClk = '1' and monostable = '1' then

                  MinF_Clk    <=  '1';

              else

                  MinF_Clk    <=  '0';

              end if;

              if WordCnt_in = 0 and WordClk = '1' and monostable = '1' then

                  monostable  <=  '0';

              elsif WordCnt_in /= 0  and monostable = '0' then

                  monostable  <=  '1';

              end if;

          end if;

      end process;

      end architecture;

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				-- MinF_Gen.vhd
				library IEEE;
				use IEEE.std_logic_1164.all;
				use IEEE.numeric_std.all;



				entity MinF_Gen is
				generic(WordCnt : integer :=144);
				port(
				clk : in std_logic;
				reset : in std_logic;
				WordCnt_in : in integer range 0 to WordCnt-1;
				WordClk : in std_logic;
				MinF_Clk : out std_logic
				);
				end entity;






				architecture arMinF_Gen of MinF_Gen is
				signal monostable : std_logic := '0';
				begin

				process(clk)
				begin
				if reset = '0' then
				MinF_Clk <= '0';
				monostable <= '1';
				elsif clk'event and clk = '0' then
				if WordCnt_in = 0 and WordClk = '1' and monostable = '1' then
				MinF_Clk <= '1';
				else
				MinF_Clk <= '0';
				end if;
				if WordCnt_in = 0 and WordClk = '1' and monostable = '1' then
				monostable <= '0';
				elsif WordCnt_in /= 0 and monostable = '0' then
				monostable <= '1';
				end if;
				end if;
				end process;

				end architecture;