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temp : update ADC driver...
temp : update ADC driver - conversion part clocked by clk_49 (49.152 MHz) - cnv_clk = clk_49.152/100 with duty cycle of 50% - 3 period for each Ren, - Data sampling during the 2nd cycle of Ren, - each 2 data input, 1 data output (@)
pellion -
r594:a9702b7364d2 simu_with_Leon3
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/ designs / EGSE_ICI
.config Loading ...
DC_GATE_GEN.vhd Loading ...
EGSE_ICI.vhd Loading ...
ICI_EGSE_PROTOCOL.vhd Loading ...
ICI_EGSE_PROTOCOL2.vhd Loading ...
LF_GATE_GEN.vhd Loading ...
MajF_Gen.vhd Loading ...
Makefile Loading ...
MinF_Gen.vhd Loading ...
Serial_driver.vhd Loading ...
config.help Loading ...
config.in Loading ...
config.vhd Loading ...
config.vhd.h Loading ...
config.vhd.in Loading ...
defconfig Loading ...
indata Loading ...
lconfig.tk Loading ...
rhumc.dc Loading ...
testbench.vhd Loading ...
tkconfig.h Loading ...
top.qsf Loading ...
top.rc Loading ...
top.xise Loading ...
top_dc.tcl Loading ...
top_designer.tcl Loading ...
top_designer_act.tcl Loading ...
tsmc13.rc Loading ...
wave.do Loading ...