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LIBRARY IEEE;
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USE IEEE.STD_LOGIC_1164.ALL;
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LIBRARY grlib;
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USE grlib.amba.ALL;
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USE grlib.stdlib.ALL;
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USE grlib.devices.ALL;
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USE GRLIB.DMA2AHB_Package.ALL;
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LIBRARY techmap;
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USE techmap.gencomp.ALL;
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PACKAGE lpp_waveform_pkg IS
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TYPE LPP_TYPE_ADDR_FIFO_WAVEFORM IS ARRAY (NATURAL RANGE <>) OF STD_LOGIC_VECTOR(6 DOWNTO 0);
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COMPONENT lpp_waveform_snapshot
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GENERIC (
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data_size : INTEGER;
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nb_snapshot_param_size : INTEGER);
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PORT (
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clk : IN STD_LOGIC;
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rstn : IN STD_LOGIC;
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enable : IN STD_LOGIC;
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burst_enable : IN STD_LOGIC;
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nb_snapshot_param : IN STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
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start_snapshot : IN STD_LOGIC;
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data_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
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data_in_valid : IN STD_LOGIC;
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data_out : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
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data_out_valid : OUT STD_LOGIC);
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END COMPONENT;
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COMPONENT lpp_waveform_burst
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GENERIC (
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data_size : INTEGER);
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PORT (
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clk : IN STD_LOGIC;
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rstn : IN STD_LOGIC;
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enable : IN STD_LOGIC;
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data_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
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data_in_valid : IN STD_LOGIC;
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data_out : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
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data_out_valid : OUT STD_LOGIC);
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END COMPONENT;
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COMPONENT lpp_waveform_snapshot_controler
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GENERIC (
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delta_snapshot_size : INTEGER;
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delta_f2_f0_size : INTEGER;
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delta_f2_f1_size : INTEGER);
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PORT (
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clk : IN STD_LOGIC;
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rstn : IN STD_LOGIC;
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delta_snapshot : IN STD_LOGIC_VECTOR(delta_snapshot_size-1 DOWNTO 0);
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delta_f2_f1 : IN STD_LOGIC_VECTOR(delta_f2_f1_size-1 DOWNTO 0);
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delta_f2_f0 : IN STD_LOGIC_VECTOR(delta_f2_f0_size-1 DOWNTO 0);
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coarse_time_0 : IN STD_LOGIC;
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data_f0_in_valid : IN STD_LOGIC;
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data_f2_in_valid : IN STD_LOGIC;
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start_snapshot_f0 : OUT STD_LOGIC;
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start_snapshot_f1 : OUT STD_LOGIC;
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start_snapshot_f2 : OUT STD_LOGIC);
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END COMPONENT;
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COMPONENT lpp_waveform
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GENERIC (
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hindex : INTEGER;
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tech : INTEGER;
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data_size : INTEGER;
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nb_burst_available_size : INTEGER;
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nb_snapshot_param_size : INTEGER;
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delta_snapshot_size : INTEGER;
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delta_f2_f0_size : INTEGER;
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delta_f2_f1_size : INTEGER);
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PORT (
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clk : IN STD_LOGIC;
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rstn : IN STD_LOGIC;
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AHB_Master_In : IN AHB_Mst_In_Type;
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AHB_Master_Out : OUT AHB_Mst_Out_Type;
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coarse_time_0 : IN STD_LOGIC;
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delta_snapshot : IN STD_LOGIC_VECTOR(delta_snapshot_size-1 DOWNTO 0);
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delta_f2_f1 : IN STD_LOGIC_VECTOR(delta_f2_f1_size-1 DOWNTO 0);
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delta_f2_f0 : IN STD_LOGIC_VECTOR(delta_f2_f0_size-1 DOWNTO 0);
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enable_f0 : IN STD_LOGIC;
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enable_f1 : IN STD_LOGIC;
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enable_f2 : IN STD_LOGIC;
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enable_f3 : IN STD_LOGIC;
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burst_f0 : IN STD_LOGIC;
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burst_f1 : IN STD_LOGIC;
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burst_f2 : IN STD_LOGIC;
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nb_burst_available : IN STD_LOGIC_VECTOR(nb_burst_available_size-1 DOWNTO 0);
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nb_snapshot_param : IN STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
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status_full : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
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status_full_ack : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
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status_full_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
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status_new_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
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addr_data_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
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addr_data_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
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addr_data_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
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addr_data_f3 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
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data_f0_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
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data_f1_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
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data_f2_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
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data_f3_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
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data_f0_in_valid : IN STD_LOGIC;
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data_f1_in_valid : IN STD_LOGIC;
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data_f2_in_valid : IN STD_LOGIC;
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data_f3_in_valid : IN STD_LOGIC);
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END COMPONENT;
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COMPONENT lpp_waveform_dma_send_Nword
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PORT (
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HCLK : IN STD_ULOGIC;
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HRESETn : IN STD_ULOGIC;
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DMAIn : OUT DMA_In_Type;
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DMAOut : IN DMA_OUt_Type;
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Nb_word_less1 : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
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send : IN STD_LOGIC;
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address : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
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data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
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ren : OUT STD_LOGIC;
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send_ok : OUT STD_LOGIC;
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send_ko : OUT STD_LOGIC);
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END COMPONENT;
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COMPONENT lpp_waveform_dma_selectaddress
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GENERIC (
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nb_burst_available_size : INTEGER);
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PORT (
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HCLK : IN STD_ULOGIC;
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HRESETn : IN STD_ULOGIC;
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update : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
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nb_burst_available : IN STD_LOGIC_VECTOR(nb_burst_available_size-1 DOWNTO 0);
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addr_data_reg : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
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addr_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
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status_full : OUT STD_LOGIC;
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status_full_ack : IN STD_LOGIC;
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status_full_err : OUT STD_LOGIC);
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END COMPONENT;
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COMPONENT lpp_waveform_dma_gen_valid
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PORT (
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HCLK : IN STD_LOGIC;
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HRESETn : IN STD_LOGIC;
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valid_in : IN STD_LOGIC;
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ack_in : IN STD_LOGIC;
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valid_out : OUT STD_LOGIC;
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error : OUT STD_LOGIC);
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END COMPONENT;
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COMPONENT lpp_waveform_dma
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GENERIC (
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data_size : INTEGER;
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tech : INTEGER;
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hindex : INTEGER;
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nb_burst_available_size : INTEGER);
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PORT (
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HCLK : IN STD_ULOGIC;
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HRESETn : IN STD_ULOGIC;
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AHB_Master_In : IN AHB_Mst_In_Type;
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AHB_Master_Out : OUT AHB_Mst_Out_Type;
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data_ready : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
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data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
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data_data_ren : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
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data_time_ren : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
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--data_f0_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
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--data_f1_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
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--data_f2_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
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--data_f3_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
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--data_f0_in_valid : IN STD_LOGIC;
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--data_f1_in_valid : IN STD_LOGIC;
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--data_f2_in_valid : IN STD_LOGIC;
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--data_f3_in_valid : IN STD_LOGIC;
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nb_burst_available : IN STD_LOGIC_VECTOR(nb_burst_available_size-1 DOWNTO 0);
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status_full : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
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status_full_ack : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
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status_full_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
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-- status_new_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
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addr_data_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
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addr_data_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
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addr_data_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
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addr_data_f3 : IN STD_LOGIC_VECTOR(31 DOWNTO 0));
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END COMPONENT;
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COMPONENT lpp_waveform_fifo_ctrl
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GENERIC (
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offset : INTEGER;
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length : INTEGER;
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enable_ready : STD_LOGIC);
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PORT (
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clk : IN STD_LOGIC;
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rstn : IN STD_LOGIC;
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ren : IN STD_LOGIC;
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wen : IN STD_LOGIC;
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mem_re : OUT STD_LOGIC;
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mem_we : OUT STD_LOGIC;
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mem_addr_ren : out STD_LOGIC_VECTOR(6 DOWNTO 0);
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mem_addr_wen : out STD_LOGIC_VECTOR(6 DOWNTO 0);
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ready : OUT STD_LOGIC);
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END COMPONENT;
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COMPONENT lpp_waveform_fifo_arbiter
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GENERIC (
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tech : INTEGER);
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PORT (
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clk : IN STD_LOGIC;
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rstn : IN STD_LOGIC;
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data_f0_valid : IN STD_LOGIC;
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data_f1_valid : IN STD_LOGIC;
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data_f2_valid : IN STD_LOGIC;
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data_f3_valid : IN STD_LOGIC;
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data_valid_ack : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
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data_f0 : IN STD_LOGIC_VECTOR(159 DOWNTO 0);
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data_f1 : IN STD_LOGIC_VECTOR(159 DOWNTO 0);
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data_f2 : IN STD_LOGIC_VECTOR(159 DOWNTO 0);
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data_f3 : IN STD_LOGIC_VECTOR(159 DOWNTO 0);
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ready : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
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time_wen : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
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data_wen : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
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data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0));
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END COMPONENT;
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COMPONENT lpp_waveform_fifo
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GENERIC (
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tech : INTEGER);
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PORT (
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clk : IN STD_LOGIC;
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rstn : IN STD_LOGIC;
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ready : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
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time_ren : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
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data_ren : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
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rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
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time_wen : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
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data_wen : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
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wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0));
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END COMPONENT;
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END lpp_waveform_pkg;
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