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1 | ||||
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2 | vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/general_purpose.vhd | |||
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3 | vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/SYNC_FF.vhd | |||
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4 | vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/MUXN.vhd | |||
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5 | vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/MUX2.vhd | |||
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6 | vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/REG.vhd | |||
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7 | vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/MAC.vhd | |||
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8 | vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/MAC_CONTROLER.vhd | |||
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9 | vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/MAC_REG.vhd | |||
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10 | vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/MAC_MUX.vhd | |||
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11 | vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/MAC_MUX2.vhd | |||
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12 | vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/Shifter.vhd | |||
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13 | vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/MULTIPLIER.vhd | |||
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14 | vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/ADDER.vhd | |||
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15 | vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/ALU.vhd | |||
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16 | vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/ADDRcntr.vhd | |||
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17 | ||||
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18 | vcom -quiet -93 -work lpp ../../lib/lpp/dsp/iir_filter/iir_filter.vhd | |||
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19 | vcom -quiet -93 -work lpp ../../lib/lpp/dsp/iir_filter/FILTERcfg.vhd | |||
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20 | vcom -quiet -93 -work lpp ../../lib/lpp/dsp/iir_filter/RAM_CEL.vhd | |||
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21 | vcom -quiet -93 -work lpp ../../lib/lpp/dsp/iir_filter/RAM_CEL_N.vhd | |||
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22 | vcom -quiet -93 -work lpp ../../lib/lpp/dsp/iir_filter/RAM_CTRLR2.vhd | |||
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23 | #vcom -quiet -93 -work lpp ../../lib/lpp/dsp/iir_filter/IIR_CEL_CTRLR.vhd | |||
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24 | ||||
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25 | vcom -quiet -93 -work lpp ../../lib/lpp/dsp/iir_filter/RAM_CTRLR_v2.vhd | |||
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26 | vcom -quiet -93 -work lpp ../../lib/lpp/dsp/iir_filter/IIR_CEL_CTRLR_v2_DATAFLOW.vhd | |||
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27 | vcom -quiet -93 -work lpp ../../lib/lpp/dsp/iir_filter/IIR_CEL_CTRLR_v2_CONTROL.vhd | |||
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28 | vcom -quiet -93 -work lpp ../../lib/lpp/dsp/iir_filter/IIR_CEL_CTRLR_v2.vhd | |||
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29 | ||||
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30 | vcom -quiet -93 -work lpp ../../lib/lpp/lpp_memory/lpp_memory.vhd | |||
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31 | vcom -quiet -93 -work lpp ../../lib/lpp/lpp_memory/lpp_FIFO.vhd | |||
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32 | vcom -quiet -93 -work lpp ../../lib/lpp/lpp_memory/lppFIFOxN.vhd | |||
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33 | ||||
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34 | vcom -quiet -93 -work lpp ../../lib/lpp/dsp/lpp_downsampling/Downsampling.vhd | |||
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35 | ||||
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36 | vcom -quiet -93 -work lpp e:/opt/tortoiseHG_vhdlib/lib/lpp/lpp_top_lfr/lpp_top_lfr_pkg.vhd | |||
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37 | vcom -quiet -93 -work lpp e:/opt/tortoiseHG_vhdlib/lib/lpp/lpp_top_lfr/lpp_top_acq.vhd | |||
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38 | ||||
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39 | vcom -quiet -93 -work lpp ../../lib/lpp/lpp_ad_Conv/lpp_ad_conv.vhd | |||
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40 | vcom -quiet -93 -work lpp ../../lib/lpp/lpp_ad_Conv/AD7688_drvr.vhd | |||
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41 | vcom -quiet -93 -work lpp ../../lib/lpp/lpp_ad_Conv/TestModule_ADS7886.vhd | |||
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42 | ||||
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43 | ||||
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44 | vcom -quiet -93 -work lpp ../../lib/lpp/lpp_top_lfr/lpp_top_lfr_pkg.vhd | |||
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45 | vcom -quiet -93 -work lpp ../../lib/lpp/lpp_top_lfr/lpp_top_acq.vhd | |||
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46 | #vcom -quiet -93 -work lpp ../../lib/lpp/lpp_top_lfr/lpp_top_lfr.vhd | |||
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47 | ||||
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48 | vcom -quiet -93 -work lpp ../../lib/lpp/lfr_time_management/lpp_lfr_time_management.vhd | |||
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49 | vcom -quiet -93 -work lpp ../../lib/lpp/lfr_time_management/apb_lfr_time_management.vhd | |||
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50 | vcom -quiet -93 -work lpp ../../lib/lpp/lfr_time_management/lfr_time_management.vhd | |||
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51 | ||||
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52 | vcom -quiet -93 -work lpp ../../lib/lpp/lpp_dma/lpp_dma_pkg.vhd | |||
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53 | ||||
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54 | vcom -quiet -93 -work lpp ../../lib/lpp/lpp_waveform/lpp_waveform_pkg.vhd | |||
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55 | vcom -quiet -93 -work lpp ../../lib/lpp/lpp_waveform/lpp_waveform.vhd | |||
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56 | vcom -quiet -93 -work lpp ../../lib/lpp/lpp_waveform/lpp_waveform_snapshot_controler.vhd | |||
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57 | vcom -quiet -93 -work lpp ../../lib/lpp/lpp_waveform/lpp_waveform_snapshot.vhd | |||
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58 | vcom -quiet -93 -work lpp ../../lib/lpp/lpp_waveform/lpp_waveform_burst.vhd | |||
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59 | ||||
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60 | vcom -quiet -93 -work lpp ../../lib/lpp/lpp_waveform/lpp_waveform_fifo_arbiter.vhd | |||
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61 | vcom -quiet -93 -work lpp ../../lib/lpp/lpp_waveform/lpp_waveform_fifo_ctrl.vhd | |||
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62 | vcom -quiet -93 -work lpp ../../lib/lpp/lpp_waveform/lpp_waveform_fifo.vhd | |||
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63 | ||||
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64 | vcom -quiet -93 -work lpp ../../lib/lpp/lpp_waveform/lpp_waveform_dma.vhd | |||
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65 | vcom -quiet -93 -work lpp ../../lib/lpp/lpp_dma/lpp_dma_pkg.vhd | |||
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66 | vcom -quiet -93 -work lpp ../../lib/lpp/lpp_dma/lpp_dma_send_1word.vhd | |||
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67 | vcom -quiet -93 -work lpp ../../lib/lpp/lpp_dma/lpp_dma_send_16word.vhd | |||
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68 | #vcom -quiet -93 -work lpp ../../lib/lpp/lpp_waveform/lpp_waveform_dma_send_Nword.vhd | |||
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69 | vcom -quiet -93 -work lpp ../../lib/lpp/lpp_waveform/lpp_waveform_dma_selectaddress.vhd | |||
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70 | vcom -quiet -93 -work lpp ../../lib/lpp/lpp_waveform/lpp_waveform_dma_genvalid.vhd | |||
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71 | ||||
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72 | vcom -quiet -93 -work work Top_Data_Acquisition.vhd | |||
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73 | ||||
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74 | vcom -quiet -93 -work work TB_Data_Acquisition.vhd | |||
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75 | ||||
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76 | vsim work.TB_Data_Acquisition | |||
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77 | ||||
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78 | log -r * | |||
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79 | do wave_waveform_picker.do | |||
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80 | run 5 ms | |||
| @@ -0,0 +1,364 | |||||
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1 | onerror {resume} | |||
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2 | quietly WaveActivateNextPane {} 0 | |||
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3 | add wave -noupdate /tb_data_acquisition/sample_f0_wen | |||
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4 | add wave -noupdate /tb_data_acquisition/sample_f0_wdata | |||
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5 | add wave -noupdate /tb_data_acquisition/sample_f1_wen | |||
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6 | add wave -noupdate /tb_data_acquisition/sample_f1_wdata | |||
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7 | add wave -noupdate /tb_data_acquisition/sample_f2_wen | |||
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8 | add wave -noupdate /tb_data_acquisition/sample_f2_wdata | |||
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9 | add wave -noupdate /tb_data_acquisition/sample_f3_wen | |||
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10 | add wave -noupdate /tb_data_acquisition/sample_f3_wdata | |||
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11 | add wave -noupdate -group TOP /tb_data_acquisition/ahb_master_in | |||
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12 | add wave -noupdate -group TOP /tb_data_acquisition/ahb_master_out | |||
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13 | add wave -noupdate -group TOP /tb_data_acquisition/coarse_time_0 | |||
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14 | add wave -noupdate -group TOP /tb_data_acquisition/coarse_time_0_t | |||
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15 | add wave -noupdate -group TOP /tb_data_acquisition/coarse_time_0_t2 | |||
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16 | add wave -noupdate -group TOP /tb_data_acquisition/delta_snapshot | |||
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17 | add wave -noupdate -group TOP /tb_data_acquisition/delta_f2_f1 | |||
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18 | add wave -noupdate -group TOP /tb_data_acquisition/delta_f2_f0 | |||
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19 | add wave -noupdate -group TOP /tb_data_acquisition/enable_f0 | |||
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20 | add wave -noupdate -group TOP /tb_data_acquisition/enable_f1 | |||
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21 | add wave -noupdate -group TOP /tb_data_acquisition/enable_f2 | |||
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22 | add wave -noupdate -group TOP /tb_data_acquisition/enable_f3 | |||
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23 | add wave -noupdate -group TOP /tb_data_acquisition/burst_f0 | |||
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24 | add wave -noupdate -group TOP /tb_data_acquisition/burst_f1 | |||
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25 | add wave -noupdate -group TOP /tb_data_acquisition/burst_f2 | |||
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26 | add wave -noupdate -group TOP /tb_data_acquisition/nb_snapshot_param | |||
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27 | add wave -noupdate -group TOP /tb_data_acquisition/status_full | |||
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28 | add wave -noupdate -group TOP /tb_data_acquisition/status_full_ack | |||
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29 | add wave -noupdate -group TOP /tb_data_acquisition/status_full_err | |||
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30 | add wave -noupdate -group TOP /tb_data_acquisition/status_new_err | |||
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31 | add wave -noupdate -group TOP /tb_data_acquisition/addr_data_f0 | |||
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32 | add wave -noupdate -group TOP /tb_data_acquisition/addr_data_f1 | |||
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33 | add wave -noupdate -group TOP /tb_data_acquisition/addr_data_f2 | |||
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34 | add wave -noupdate -group TOP /tb_data_acquisition/addr_data_f3 | |||
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35 | add wave -noupdate -group waveform_picker /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/data_size | |||
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36 | add wave -noupdate -group waveform_picker /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/nb_snapshot_param_size | |||
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37 | add wave -noupdate -group waveform_picker /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/delta_snapshot_size | |||
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38 | add wave -noupdate -group waveform_picker /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/delta_f2_f0_size | |||
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39 | add wave -noupdate -group waveform_picker /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/delta_f2_f1_size | |||
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40 | add wave -noupdate -group waveform_picker /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/clk | |||
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41 | add wave -noupdate -group waveform_picker /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/rstn | |||
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42 | add wave -noupdate -group waveform_picker /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/ahb_master_in | |||
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43 | add wave -noupdate -group waveform_picker /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/ahb_master_out | |||
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44 | add wave -noupdate -group waveform_picker /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/coarse_time_0 | |||
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45 | add wave -noupdate -group waveform_picker /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/delta_snapshot | |||
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46 | add wave -noupdate -group waveform_picker /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/delta_f2_f1 | |||
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47 | add wave -noupdate -group waveform_picker /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/delta_f2_f0 | |||
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48 | add wave -noupdate -group waveform_picker /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/enable_f0 | |||
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49 | add wave -noupdate -group waveform_picker /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/enable_f1 | |||
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50 | add wave -noupdate -group waveform_picker /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/enable_f2 | |||
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51 | add wave -noupdate -group waveform_picker /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/enable_f3 | |||
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52 | add wave -noupdate -group waveform_picker /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/burst_f0 | |||
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53 | add wave -noupdate -group waveform_picker /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/burst_f1 | |||
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54 | add wave -noupdate -group waveform_picker /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/burst_f2 | |||
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55 | add wave -noupdate -group waveform_picker /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/nb_snapshot_param | |||
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56 | add wave -noupdate -group waveform_picker /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/status_full | |||
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57 | add wave -noupdate -group waveform_picker /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/status_full_ack | |||
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58 | add wave -noupdate -group waveform_picker /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/status_full_err | |||
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59 | add wave -noupdate -group waveform_picker /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/status_new_err | |||
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60 | add wave -noupdate -group waveform_picker /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/addr_data_f0 | |||
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61 | add wave -noupdate -group waveform_picker /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/addr_data_f1 | |||
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62 | add wave -noupdate -group waveform_picker /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/addr_data_f2 | |||
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63 | add wave -noupdate -group waveform_picker /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/addr_data_f3 | |||
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64 | add wave -noupdate -group waveform_picker /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/data_f0_in | |||
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65 | add wave -noupdate -group waveform_picker /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/data_f1_in | |||
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66 | add wave -noupdate -group waveform_picker /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/data_f2_in | |||
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67 | add wave -noupdate -group waveform_picker /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/data_f3_in | |||
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68 | add wave -noupdate -group waveform_picker /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/data_f0_in_valid | |||
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69 | add wave -noupdate -group waveform_picker /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/data_f1_in_valid | |||
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70 | add wave -noupdate -group waveform_picker /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/data_f2_in_valid | |||
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71 | add wave -noupdate -group waveform_picker /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/data_f3_in_valid | |||
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72 | add wave -noupdate -group waveform_picker /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/start_snapshot_f0 | |||
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73 | add wave -noupdate -group waveform_picker /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/start_snapshot_f1 | |||
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74 | add wave -noupdate -group waveform_picker /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/start_snapshot_f2 | |||
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75 | add wave -noupdate -group waveform_picker /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/data_f0_out | |||
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76 | add wave -noupdate -group waveform_picker /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/data_f1_out | |||
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77 | add wave -noupdate -group waveform_picker /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/data_f2_out | |||
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78 | add wave -noupdate -group waveform_picker /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/data_f3_out | |||
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79 | add wave -noupdate -group waveform_picker /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/data_f0_out_valid | |||
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80 | add wave -noupdate -group waveform_picker /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/data_f1_out_valid | |||
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81 | add wave -noupdate -group waveform_picker /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/data_f2_out_valid | |||
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82 | add wave -noupdate -group waveform_picker /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/data_f3_out_valid | |||
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83 | add wave -noupdate -group waveform_controler /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_snapshot_controler_1/clk | |||
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84 | add wave -noupdate -group waveform_controler /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_snapshot_controler_1/rstn | |||
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85 | add wave -noupdate -group waveform_controler /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_snapshot_controler_1/delta_snapshot | |||
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86 | add wave -noupdate -group waveform_controler /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_snapshot_controler_1/delta_f2_f1 | |||
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87 | add wave -noupdate -group waveform_controler /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_snapshot_controler_1/delta_f2_f0 | |||
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88 | add wave -noupdate -group waveform_controler /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_snapshot_controler_1/coarse_time_0 | |||
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89 | add wave -noupdate -group waveform_controler /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_snapshot_controler_1/data_f2_in_valid | |||
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90 | add wave -noupdate -group waveform_controler /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_snapshot_controler_1/start_snapshot_f0 | |||
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91 | add wave -noupdate -group waveform_controler /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_snapshot_controler_1/start_snapshot_f1 | |||
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92 | add wave -noupdate -group waveform_controler /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_snapshot_controler_1/start_snapshot_f2 | |||
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93 | add wave -noupdate -group waveform_controler /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_snapshot_controler_1/counter_delta_snapshot | |||
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94 | add wave -noupdate -group waveform_controler /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_snapshot_controler_1/coarse_time_0_r | |||
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95 | add wave -noupdate -group waveform_snapshot_f0 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_snapshot_f0/clk | |||
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96 | add wave -noupdate -group waveform_snapshot_f0 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_snapshot_f0/rstn | |||
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97 | add wave -noupdate -group waveform_snapshot_f0 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_snapshot_f0/enable | |||
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98 | add wave -noupdate -group waveform_snapshot_f0 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_snapshot_f0/burst_enable | |||
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99 | add wave -noupdate -group waveform_snapshot_f0 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_snapshot_f0/nb_snapshot_param | |||
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100 | add wave -noupdate -group waveform_snapshot_f0 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_snapshot_f0/start_snapshot | |||
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101 | add wave -noupdate -group waveform_snapshot_f0 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_snapshot_f0/data_in | |||
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102 | add wave -noupdate -group waveform_snapshot_f0 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_snapshot_f0/data_in_valid | |||
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103 | add wave -noupdate -group waveform_snapshot_f0 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_snapshot_f0/data_out | |||
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104 | add wave -noupdate -group waveform_snapshot_f0 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_snapshot_f0/data_out_valid | |||
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105 | add wave -noupdate -group waveform_snapshot_f0 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_snapshot_f0/counter_points_snapshot | |||
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106 | add wave -noupdate -group waveform_snapshot_f1 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_snapshot_f1/clk | |||
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107 | add wave -noupdate -group waveform_snapshot_f1 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_snapshot_f1/rstn | |||
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108 | add wave -noupdate -group waveform_snapshot_f1 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_snapshot_f1/enable | |||
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109 | add wave -noupdate -group waveform_snapshot_f1 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_snapshot_f1/burst_enable | |||
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110 | add wave -noupdate -group waveform_snapshot_f1 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_snapshot_f1/nb_snapshot_param | |||
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111 | add wave -noupdate -group waveform_snapshot_f1 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_snapshot_f1/start_snapshot | |||
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112 | add wave -noupdate -group waveform_snapshot_f1 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_snapshot_f1/data_in | |||
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113 | add wave -noupdate -group waveform_snapshot_f1 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_snapshot_f1/data_in_valid | |||
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114 | add wave -noupdate -group waveform_snapshot_f1 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_snapshot_f1/data_out | |||
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115 | add wave -noupdate -group waveform_snapshot_f1 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_snapshot_f1/data_out_valid | |||
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116 | add wave -noupdate -group waveform_snapshot_f1 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_snapshot_f1/counter_points_snapshot | |||
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117 | add wave -noupdate -group waveform_snapshot_f2 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_snapshot_f2/clk | |||
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118 | add wave -noupdate -group waveform_snapshot_f2 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_snapshot_f2/rstn | |||
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119 | add wave -noupdate -group waveform_snapshot_f2 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_snapshot_f2/enable | |||
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120 | add wave -noupdate -group waveform_snapshot_f2 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_snapshot_f2/burst_enable | |||
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121 | add wave -noupdate -group waveform_snapshot_f2 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_snapshot_f2/nb_snapshot_param | |||
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122 | add wave -noupdate -group waveform_snapshot_f2 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_snapshot_f2/start_snapshot | |||
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123 | add wave -noupdate -group waveform_snapshot_f2 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_snapshot_f2/data_in | |||
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124 | add wave -noupdate -group waveform_snapshot_f2 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_snapshot_f2/data_in_valid | |||
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125 | add wave -noupdate -group waveform_snapshot_f2 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_snapshot_f2/data_out | |||
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126 | add wave -noupdate -group waveform_snapshot_f2 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_snapshot_f2/data_out_valid | |||
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127 | add wave -noupdate -group waveform_snapshot_f2 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_snapshot_f2/counter_points_snapshot | |||
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128 | add wave -noupdate -group waveform_burst____f3 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_burst_f3/clk | |||
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129 | add wave -noupdate -group waveform_burst____f3 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_burst_f3/rstn | |||
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130 | add wave -noupdate -group waveform_burst____f3 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_burst_f3/enable | |||
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131 | add wave -noupdate -group waveform_burst____f3 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_burst_f3/data_in | |||
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132 | add wave -noupdate -group waveform_burst____f3 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_burst_f3/data_in_valid | |||
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133 | add wave -noupdate -group waveform_burst____f3 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_burst_f3/data_out | |||
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134 | add wave -noupdate -group waveform_burst____f3 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_burst_f3/data_out_valid | |||
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135 | add wave -noupdate -group GEN_VALID_F0 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/all_input_valid(0)/lpp_waveform_dma_gen_valid_i/hclk | |||
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136 | add wave -noupdate -group GEN_VALID_F0 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/all_input_valid(0)/lpp_waveform_dma_gen_valid_i/hresetn | |||
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137 | add wave -noupdate -group GEN_VALID_F0 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/all_input_valid(0)/lpp_waveform_dma_gen_valid_i/valid_in | |||
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138 | add wave -noupdate -group GEN_VALID_F0 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/all_input_valid(0)/lpp_waveform_dma_gen_valid_i/ack_in | |||
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139 | add wave -noupdate -group GEN_VALID_F0 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/all_input_valid(0)/lpp_waveform_dma_gen_valid_i/valid_out | |||
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140 | add wave -noupdate -group GEN_VALID_F0 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/all_input_valid(0)/lpp_waveform_dma_gen_valid_i/error | |||
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141 | add wave -noupdate -group GEN_VALID_F1 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/all_input_valid(1)/lpp_waveform_dma_gen_valid_i/hclk | |||
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142 | add wave -noupdate -group GEN_VALID_F1 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/all_input_valid(1)/lpp_waveform_dma_gen_valid_i/hresetn | |||
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143 | add wave -noupdate -group GEN_VALID_F1 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/all_input_valid(1)/lpp_waveform_dma_gen_valid_i/valid_in | |||
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144 | add wave -noupdate -group GEN_VALID_F1 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/all_input_valid(1)/lpp_waveform_dma_gen_valid_i/ack_in | |||
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145 | add wave -noupdate -group GEN_VALID_F1 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/all_input_valid(1)/lpp_waveform_dma_gen_valid_i/valid_out | |||
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146 | add wave -noupdate -group GEN_VALID_F1 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/all_input_valid(1)/lpp_waveform_dma_gen_valid_i/error | |||
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147 | add wave -noupdate -group GEN_VALID_F1 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/all_input_valid(1)/lpp_waveform_dma_gen_valid_i/state | |||
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148 | add wave -noupdate -group GEN_VALID_F2 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/all_input_valid(2)/lpp_waveform_dma_gen_valid_i/hclk | |||
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149 | add wave -noupdate -group GEN_VALID_F2 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/all_input_valid(2)/lpp_waveform_dma_gen_valid_i/hresetn | |||
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150 | add wave -noupdate -group GEN_VALID_F2 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/all_input_valid(2)/lpp_waveform_dma_gen_valid_i/valid_in | |||
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151 | add wave -noupdate -group GEN_VALID_F2 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/all_input_valid(2)/lpp_waveform_dma_gen_valid_i/ack_in | |||
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152 | add wave -noupdate -group GEN_VALID_F2 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/all_input_valid(2)/lpp_waveform_dma_gen_valid_i/valid_out | |||
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153 | add wave -noupdate -group GEN_VALID_F2 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/all_input_valid(2)/lpp_waveform_dma_gen_valid_i/error | |||
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154 | add wave -noupdate -group GEN_VALID_F2 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/all_input_valid(2)/lpp_waveform_dma_gen_valid_i/state | |||
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155 | add wave -noupdate -group GEN_VALID_F3 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/all_input_valid(3)/lpp_waveform_dma_gen_valid_i/hclk | |||
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156 | add wave -noupdate -group GEN_VALID_F3 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/all_input_valid(3)/lpp_waveform_dma_gen_valid_i/hresetn | |||
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157 | add wave -noupdate -group GEN_VALID_F3 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/all_input_valid(3)/lpp_waveform_dma_gen_valid_i/valid_in | |||
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158 | add wave -noupdate -group GEN_VALID_F3 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/all_input_valid(3)/lpp_waveform_dma_gen_valid_i/ack_in | |||
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159 | add wave -noupdate -group GEN_VALID_F3 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/all_input_valid(3)/lpp_waveform_dma_gen_valid_i/valid_out | |||
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160 | add wave -noupdate -group GEN_VALID_F3 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/all_input_valid(3)/lpp_waveform_dma_gen_valid_i/error | |||
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161 | add wave -noupdate -group GEN_VALID_F3 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/all_input_valid(3)/lpp_waveform_dma_gen_valid_i/state | |||
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162 | add wave -noupdate /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/valid_in | |||
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163 | add wave -noupdate /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/valid_out | |||
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164 | add wave -noupdate /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/valid_ack | |||
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165 | add wave -noupdate /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/status_new_err | |||
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166 | add wave -noupdate -group FIFO_ARB /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_arbiter_1/clk | |||
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167 | add wave -noupdate -group FIFO_ARB /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_arbiter_1/rstn | |||
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168 | add wave -noupdate -group FIFO_ARB /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_arbiter_1/state | |||
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169 | add wave -noupdate -group FIFO_ARB /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_arbiter_1/data_f0_valid | |||
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170 | add wave -noupdate -group FIFO_ARB /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_arbiter_1/data_f1_valid | |||
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171 | add wave -noupdate -group FIFO_ARB /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_arbiter_1/data_f2_valid | |||
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172 | add wave -noupdate -group FIFO_ARB /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_arbiter_1/data_f3_valid | |||
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173 | add wave -noupdate -group FIFO_ARB /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_arbiter_1/data_valid_ack | |||
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174 | add wave -noupdate -group FIFO_ARB -radix hexadecimal /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_arbiter_1/data_f0 | |||
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175 | add wave -noupdate -group FIFO_ARB -radix hexadecimal /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_arbiter_1/data_f1 | |||
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176 | add wave -noupdate -group FIFO_ARB -radix hexadecimal /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_arbiter_1/data_f2 | |||
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177 | add wave -noupdate -group FIFO_ARB -radix hexadecimal /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_arbiter_1/data_f3 | |||
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178 | add wave -noupdate -group FIFO_ARB /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_arbiter_1/ready | |||
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179 | add wave -noupdate -group FIFO_ARB /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_arbiter_1/time_wen | |||
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180 | add wave -noupdate -group FIFO_ARB /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_arbiter_1/data_wen | |||
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181 | add wave -noupdate -group FIFO_ARB -radix hexadecimal /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_arbiter_1/data | |||
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182 | add wave -noupdate -group FIFO_ARB /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_arbiter_1/data_valid_and_ready | |||
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183 | add wave -noupdate -group FIFO_ARB -radix hexadecimal /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_arbiter_1/data_selected | |||
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184 | add wave -noupdate -group FIFO_ARB /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_arbiter_1/data_valid_selected | |||
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185 | add wave -noupdate -group FIFO_ARB /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_arbiter_1/data_ready_to_go | |||
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186 | add wave -noupdate -group FIFO_ARB -radix hexadecimal /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_arbiter_1/data_temp | |||
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187 | add wave -noupdate -group FIFO_ARB /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_arbiter_1/time_en_temp | |||
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188 | add wave -noupdate -expand -group FIFO -expand -group {IN - OUT} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/rstn | |||
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189 | add wave -noupdate -expand -group FIFO -expand -group {IN - OUT} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/ready | |||
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190 | add wave -noupdate -expand -group FIFO -expand -group {IN - OUT} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/time_ren | |||
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191 | add wave -noupdate -expand -group FIFO -expand -group {IN - OUT} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/data_ren | |||
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192 | add wave -noupdate -expand -group FIFO -expand -group {IN - OUT} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/rdata | |||
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193 | add wave -noupdate -expand -group FIFO -expand -group {IN - OUT} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/time_wen | |||
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194 | add wave -noupdate -expand -group FIFO -expand -group {IN - OUT} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/data_wen | |||
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195 | add wave -noupdate -expand -group FIFO -expand -group {IN - OUT} -radix hexadecimal /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/wdata | |||
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196 | add wave -noupdate -expand -group FIFO -expand -group read -radix hexadecimal -subitemconfig {/tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/time_mem_addr_r(3) {-radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/time_mem_addr_r(2) {-radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/time_mem_addr_r(1) {-radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/time_mem_addr_r(0) {-radix hexadecimal}} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/time_mem_addr_r | |||
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197 | add wave -noupdate -expand -group FIFO -expand -group read /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/data_mem_addr_r | |||
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198 | add wave -noupdate -expand -group FIFO -expand -group read /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/time_mem_ren | |||
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199 | add wave -noupdate -expand -group FIFO -expand -group read /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/data_mem_ren | |||
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200 | add wave -noupdate -expand -group FIFO -expand -group read /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/data_addr_r | |||
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201 | add wave -noupdate -expand -group FIFO -expand -group read /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/ren | |||
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202 | add wave -noupdate -expand -group FIFO -group write /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/data_mem_addr_w | |||
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203 | add wave -noupdate -expand -group FIFO -group write /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/time_mem_addr_w | |||
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204 | add wave -noupdate -expand -group FIFO -group write /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/data_mem_wen | |||
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205 | add wave -noupdate -expand -group FIFO -group write /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/time_mem_wen | |||
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206 | add wave -noupdate -expand -group FIFO -group write -radix unsigned /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/data_addr_w | |||
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207 | add wave -noupdate -expand -group FIFO -group write /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/wen | |||
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|
208 | add wave -noupdate -radix hexadecimal -subitemconfig {/tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(0) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(1) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(2) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(3) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(4) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(5) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(6) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(7) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(8) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(9) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(10) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(11) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(12) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(13) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(14) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(15) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(16) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(17) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(18) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(19) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(20) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(21) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(22) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(23) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(24) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(25) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(26) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(27) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(28) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(29) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(30) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(31) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(32) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(33) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(34) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(35) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(36) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(37) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(38) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(39) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(40) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(41) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(42) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(43) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(44) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(45) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(46) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(47) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(48) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(49) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(50) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(51) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(52) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(53) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(54) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(55) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(56) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(57) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(58) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(59) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(60) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(61) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(62) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(63) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(64) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(65) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(66) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(67) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(68) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(69) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(70) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(71) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(72) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(73) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(74) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(75) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(76) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(77) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(78) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(79) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(80) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(81) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(82) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(83) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(84) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(85) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(86) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(87) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(88) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(89) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(90) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(91) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(92) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(93) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(94) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(95) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(96) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(97) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(98) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(99) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(100) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(101) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(102) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(103) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(104) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(105) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(106) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(107) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(108) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(109) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(110) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(111) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(112) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(113) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(114) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(115) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(116) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(117) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(118) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(119) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(120) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(121) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(122) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(123) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(124) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(125) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(126) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(127) {-height 15 -radix hexadecimal}} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd | |||
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209 | add wave -noupdate -expand -group DMA -expand -group INOUT /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/pp_waveform_dma_1/hclk | |||
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210 | add wave -noupdate -expand -group DMA -expand -group INOUT /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/pp_waveform_dma_1/hresetn | |||
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211 | add wave -noupdate -expand -group DMA -expand -group INOUT /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/pp_waveform_dma_1/ahb_master_in | |||
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212 | add wave -noupdate -expand -group DMA -expand -group INOUT -subitemconfig {/tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/pp_waveform_dma_1/ahb_master_out.haddr {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/pp_waveform_dma_1/ahb_master_out.hwdata {-height 15 -radix hexadecimal}} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/pp_waveform_dma_1/ahb_master_out | |||
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213 | add wave -noupdate -expand -group DMA -expand -group INOUT -expand -group FIFO_interface /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/pp_waveform_dma_1/data_ready | |||
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214 | add wave -noupdate -expand -group DMA -expand -group INOUT -expand -group FIFO_interface /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/pp_waveform_dma_1/data | |||
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215 | add wave -noupdate -expand -group DMA -expand -group INOUT -expand -group FIFO_interface /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/pp_waveform_dma_1/data_data_ren | |||
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216 | add wave -noupdate -expand -group DMA -expand -group INOUT -expand -group FIFO_interface /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/pp_waveform_dma_1/data_time_ren | |||
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217 | add wave -noupdate -expand -group DMA -expand -group INOUT -expand -group REG_CONFIG -radix unsigned /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/pp_waveform_dma_1/nb_burst_available | |||
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218 | add wave -noupdate -expand -group DMA -expand -group INOUT -expand -group REG_CONFIG /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/pp_waveform_dma_1/addr_data_f0 | |||
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219 | add wave -noupdate -expand -group DMA -expand -group INOUT -expand -group REG_CONFIG /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/pp_waveform_dma_1/addr_data_f1 | |||
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220 | add wave -noupdate -expand -group DMA -expand -group INOUT -expand -group REG_CONFIG /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/pp_waveform_dma_1/addr_data_f2 | |||
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221 | add wave -noupdate -expand -group DMA -expand -group INOUT -expand -group REG_CONFIG /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/pp_waveform_dma_1/addr_data_f3 | |||
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222 | add wave -noupdate -expand -group DMA -expand -group INOUT /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/pp_waveform_dma_1/status_full | |||
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223 | add wave -noupdate -expand -group DMA -expand -group INOUT /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/pp_waveform_dma_1/status_full_ack | |||
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224 | add wave -noupdate -expand -group DMA -expand -group INOUT /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/pp_waveform_dma_1/status_full_err | |||
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225 | add wave -noupdate -expand -group DMA /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/pp_waveform_dma_1/dmain | |||
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226 | add wave -noupdate -expand -group DMA /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/pp_waveform_dma_1/dmaout | |||
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227 | add wave -noupdate -expand -group DMA /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/pp_waveform_dma_1/state | |||
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228 | add wave -noupdate -expand -group DMA /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/pp_waveform_dma_1/sel_data_s | |||
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229 | add wave -noupdate -expand -group DMA /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/pp_waveform_dma_1/sel_data | |||
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230 | add wave -noupdate -expand -group DMA /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/pp_waveform_dma_1/update | |||
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231 | add wave -noupdate -expand -group DMA /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/pp_waveform_dma_1/time_select | |||
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232 | add wave -noupdate -expand -group DMA /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/pp_waveform_dma_1/time_write | |||
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233 | add wave -noupdate -expand -group DMA /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/pp_waveform_dma_1/time_already_send | |||
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234 | add wave -noupdate -expand -group DMA /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/pp_waveform_dma_1/time_already_send_s | |||
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235 | add wave -noupdate -expand -group DMA /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/pp_waveform_dma_1/time_dmai | |||
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236 | add wave -noupdate -expand -group DMA /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/pp_waveform_dma_1/time_send | |||
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237 | add wave -noupdate -expand -group DMA /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/pp_waveform_dma_1/time_send_ok | |||
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238 | add wave -noupdate -expand -group DMA /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/pp_waveform_dma_1/time_send_ko | |||
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239 | add wave -noupdate -expand -group DMA /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/pp_waveform_dma_1/time_fifo_ren | |||
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240 | add wave -noupdate -expand -group DMA /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/pp_waveform_dma_1/time_ren | |||
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241 | add wave -noupdate -expand -group DMA /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/pp_waveform_dma_1/data_dmai | |||
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242 | add wave -noupdate -expand -group DMA /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/pp_waveform_dma_1/data_send | |||
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243 | add wave -noupdate -expand -group DMA /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/pp_waveform_dma_1/data_send_ok | |||
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244 | add wave -noupdate -expand -group DMA /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/pp_waveform_dma_1/data_send_ko | |||
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245 | add wave -noupdate -expand -group DMA /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/pp_waveform_dma_1/data_fifo_ren | |||
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246 | add wave -noupdate -expand -group DMA /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/pp_waveform_dma_1/data_ren | |||
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247 | add wave -noupdate -expand -group DMA /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/pp_waveform_dma_1/data_address | |||
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248 | add wave -noupdate -expand -group DMA /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/pp_waveform_dma_1/update_and_sel | |||
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249 | add wave -noupdate -expand -group DMA /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/pp_waveform_dma_1/addr_data_reg_vector | |||
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250 | add wave -noupdate -expand -group DMA /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/pp_waveform_dma_1/addr_data_vector | |||
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251 | add wave -noupdate -expand -group DMA /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/pp_waveform_dma_1/send_16_3_time | |||
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252 | add wave -noupdate -expand -group DMA /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/pp_waveform_dma_1/count_send_time | |||
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253 | add wave -noupdate /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/ren | |||
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254 | add wave -noupdate /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/wen | |||
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255 | add wave -noupdate -group fifo_ctrl_time_3 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_time(3)/lpp_waveform_fifo_ctrl_time/clk | |||
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256 | add wave -noupdate -group fifo_ctrl_time_3 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_time(3)/lpp_waveform_fifo_ctrl_time/rstn | |||
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257 | add wave -noupdate -group fifo_ctrl_time_3 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_time(3)/lpp_waveform_fifo_ctrl_time/ren | |||
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258 | add wave -noupdate -group fifo_ctrl_time_3 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_time(3)/lpp_waveform_fifo_ctrl_time/wen | |||
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259 | add wave -noupdate -group fifo_ctrl_time_3 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_time(3)/lpp_waveform_fifo_ctrl_time/mem_re | |||
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260 | add wave -noupdate -group fifo_ctrl_time_3 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_time(3)/lpp_waveform_fifo_ctrl_time/mem_we | |||
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261 | add wave -noupdate -group fifo_ctrl_time_3 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_time(3)/lpp_waveform_fifo_ctrl_time/mem_addr_ren | |||
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262 | add wave -noupdate -group fifo_ctrl_time_3 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_time(3)/lpp_waveform_fifo_ctrl_time/mem_addr_wen | |||
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263 | add wave -noupdate -group fifo_ctrl_time_3 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_time(3)/lpp_waveform_fifo_ctrl_time/ready | |||
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264 | add wave -noupdate -expand -group fifo_ctrl_time_2 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_time(2)/lpp_waveform_fifo_ctrl_time/clk | |||
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265 | add wave -noupdate -expand -group fifo_ctrl_time_2 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_time(2)/lpp_waveform_fifo_ctrl_time/rstn | |||
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266 | add wave -noupdate -expand -group fifo_ctrl_time_2 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_time(2)/lpp_waveform_fifo_ctrl_time/ren | |||
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267 | add wave -noupdate -expand -group fifo_ctrl_time_2 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_time(2)/lpp_waveform_fifo_ctrl_time/wen | |||
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268 | add wave -noupdate -expand -group fifo_ctrl_time_2 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_time(2)/lpp_waveform_fifo_ctrl_time/mem_re | |||
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269 | add wave -noupdate -expand -group fifo_ctrl_time_2 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_time(2)/lpp_waveform_fifo_ctrl_time/mem_we | |||
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270 | add wave -noupdate -expand -group fifo_ctrl_time_2 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_time(2)/lpp_waveform_fifo_ctrl_time/mem_addr_ren | |||
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271 | add wave -noupdate -expand -group fifo_ctrl_time_2 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_time(2)/lpp_waveform_fifo_ctrl_time/mem_addr_wen | |||
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272 | add wave -noupdate -expand -group fifo_ctrl_time_2 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_time(2)/lpp_waveform_fifo_ctrl_time/ready | |||
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273 | add wave -noupdate -expand -group fifo_ctrl_time_1 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_time(1)/lpp_waveform_fifo_ctrl_time/clk | |||
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274 | add wave -noupdate -expand -group fifo_ctrl_time_1 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_time(1)/lpp_waveform_fifo_ctrl_time/rstn | |||
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275 | add wave -noupdate -expand -group fifo_ctrl_time_1 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_time(1)/lpp_waveform_fifo_ctrl_time/ren | |||
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276 | add wave -noupdate -expand -group fifo_ctrl_time_1 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_time(1)/lpp_waveform_fifo_ctrl_time/wen | |||
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277 | add wave -noupdate -expand -group fifo_ctrl_time_1 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_time(1)/lpp_waveform_fifo_ctrl_time/mem_re | |||
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278 | add wave -noupdate -expand -group fifo_ctrl_time_1 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_time(1)/lpp_waveform_fifo_ctrl_time/mem_we | |||
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279 | add wave -noupdate -expand -group fifo_ctrl_time_1 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_time(1)/lpp_waveform_fifo_ctrl_time/mem_addr_ren | |||
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280 | add wave -noupdate -expand -group fifo_ctrl_time_1 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_time(1)/lpp_waveform_fifo_ctrl_time/mem_addr_wen | |||
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281 | add wave -noupdate -expand -group fifo_ctrl_time_1 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_time(1)/lpp_waveform_fifo_ctrl_time/ready | |||
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282 | add wave -noupdate -group fifo_ctrl_time_0 -group IN /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_time(0)/lpp_waveform_fifo_ctrl_time/clk | |||
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283 | add wave -noupdate -group fifo_ctrl_time_0 -group IN /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_time(0)/lpp_waveform_fifo_ctrl_time/rstn | |||
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284 | add wave -noupdate -group fifo_ctrl_time_0 -group IN /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_time(0)/lpp_waveform_fifo_ctrl_time/ren | |||
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285 | add wave -noupdate -group fifo_ctrl_time_0 -group IN /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_time(0)/lpp_waveform_fifo_ctrl_time/wen | |||
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286 | add wave -noupdate -group fifo_ctrl_time_0 -group OUT /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_time(0)/lpp_waveform_fifo_ctrl_time/mem_re | |||
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287 | add wave -noupdate -group fifo_ctrl_time_0 -group OUT /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_time(0)/lpp_waveform_fifo_ctrl_time/mem_we | |||
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288 | add wave -noupdate -group fifo_ctrl_time_0 -group OUT /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_time(0)/lpp_waveform_fifo_ctrl_time/mem_addr_ren | |||
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289 | add wave -noupdate -group fifo_ctrl_time_0 -group OUT /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_time(0)/lpp_waveform_fifo_ctrl_time/mem_addr_wen | |||
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290 | add wave -noupdate -group fifo_ctrl_time_0 -group OUT /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_time(0)/lpp_waveform_fifo_ctrl_time/ready | |||
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291 | add wave -noupdate -group fifo_ctrl_time_0 -group internal /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_time(0)/lpp_waveform_fifo_ctrl_time/sfull | |||
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292 | add wave -noupdate -group fifo_ctrl_time_0 -group internal /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_time(0)/lpp_waveform_fifo_ctrl_time/sfull_s | |||
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293 | add wave -noupdate -group fifo_ctrl_time_0 -group internal /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_time(0)/lpp_waveform_fifo_ctrl_time/sempty_s | |||
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294 | add wave -noupdate -group fifo_ctrl_time_0 -group internal /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_time(0)/lpp_waveform_fifo_ctrl_time/sempty | |||
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295 | add wave -noupdate -group fifo_ctrl_time_0 -group internal /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_time(0)/lpp_waveform_fifo_ctrl_time/sren | |||
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296 | add wave -noupdate -group fifo_ctrl_time_0 -group internal /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_time(0)/lpp_waveform_fifo_ctrl_time/swen | |||
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297 | add wave -noupdate -group fifo_ctrl_time_0 -group internal /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_time(0)/lpp_waveform_fifo_ctrl_time/sre | |||
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298 | add wave -noupdate -group fifo_ctrl_time_0 -group internal /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_time(0)/lpp_waveform_fifo_ctrl_time/swe | |||
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299 | add wave -noupdate -group fifo_ctrl_time_0 -group internal /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_time(0)/lpp_waveform_fifo_ctrl_time/waddr_vect | |||
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300 | add wave -noupdate -group fifo_ctrl_time_0 -group internal /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_time(0)/lpp_waveform_fifo_ctrl_time/raddr_vect | |||
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301 | add wave -noupdate -group fifo_ctrl_time_0 -group internal /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_time(0)/lpp_waveform_fifo_ctrl_time/waddr_vect_s | |||
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302 | add wave -noupdate -group fifo_ctrl_time_0 -group internal /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_time(0)/lpp_waveform_fifo_ctrl_time/raddr_vect_s | |||
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303 | add wave -noupdate -group fifo_ctrl_time_0 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_time(0)/lpp_waveform_fifo_ctrl_time/clk | |||
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304 | add wave -noupdate -group fifo_ctrl_time_0 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_time(0)/lpp_waveform_fifo_ctrl_time/rstn | |||
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305 | add wave -noupdate -group fifo_ctrl_time_0 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_time(0)/lpp_waveform_fifo_ctrl_time/ren | |||
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306 | add wave -noupdate -group fifo_ctrl_time_0 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_time(0)/lpp_waveform_fifo_ctrl_time/wen | |||
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307 | add wave -noupdate -group fifo_ctrl_time_0 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_time(0)/lpp_waveform_fifo_ctrl_time/mem_re | |||
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308 | add wave -noupdate -group fifo_ctrl_time_0 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_time(0)/lpp_waveform_fifo_ctrl_time/mem_we | |||
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309 | add wave -noupdate -group fifo_ctrl_time_0 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_time(0)/lpp_waveform_fifo_ctrl_time/mem_addr_ren | |||
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310 | add wave -noupdate -group fifo_ctrl_time_0 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_time(0)/lpp_waveform_fifo_ctrl_time/mem_addr_wen | |||
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311 | add wave -noupdate -group fifo_ctrl_time_0 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_time(0)/lpp_waveform_fifo_ctrl_time/ready | |||
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312 | add wave -noupdate -group fifo_ctrl_data_3 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_data(3)/lpp_waveform_fifo_ctrl_data/clk | |||
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313 | add wave -noupdate -group fifo_ctrl_data_3 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_data(3)/lpp_waveform_fifo_ctrl_data/rstn | |||
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314 | add wave -noupdate -group fifo_ctrl_data_3 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_data(3)/lpp_waveform_fifo_ctrl_data/ren | |||
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315 | add wave -noupdate -group fifo_ctrl_data_3 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_data(3)/lpp_waveform_fifo_ctrl_data/wen | |||
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316 | add wave -noupdate -group fifo_ctrl_data_3 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_data(3)/lpp_waveform_fifo_ctrl_data/mem_re | |||
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317 | add wave -noupdate -group fifo_ctrl_data_3 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_data(3)/lpp_waveform_fifo_ctrl_data/mem_we | |||
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318 | add wave -noupdate -group fifo_ctrl_data_3 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_data(3)/lpp_waveform_fifo_ctrl_data/mem_addr_ren | |||
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319 | add wave -noupdate -group fifo_ctrl_data_3 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_data(3)/lpp_waveform_fifo_ctrl_data/mem_addr_wen | |||
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320 | add wave -noupdate -group fifo_ctrl_data_3 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_data(3)/lpp_waveform_fifo_ctrl_data/ready | |||
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321 | add wave -noupdate -expand -group fifo_ctrl_data_2 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_data(2)/lpp_waveform_fifo_ctrl_data/clk | |||
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322 | add wave -noupdate -expand -group fifo_ctrl_data_2 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_data(2)/lpp_waveform_fifo_ctrl_data/rstn | |||
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323 | add wave -noupdate -expand -group fifo_ctrl_data_2 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_data(2)/lpp_waveform_fifo_ctrl_data/ren | |||
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324 | add wave -noupdate -expand -group fifo_ctrl_data_2 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_data(2)/lpp_waveform_fifo_ctrl_data/wen | |||
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325 | add wave -noupdate -expand -group fifo_ctrl_data_2 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_data(2)/lpp_waveform_fifo_ctrl_data/mem_re | |||
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326 | add wave -noupdate -expand -group fifo_ctrl_data_2 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_data(2)/lpp_waveform_fifo_ctrl_data/mem_we | |||
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327 | add wave -noupdate -expand -group fifo_ctrl_data_2 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_data(2)/lpp_waveform_fifo_ctrl_data/mem_addr_ren | |||
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328 | add wave -noupdate -expand -group fifo_ctrl_data_2 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_data(2)/lpp_waveform_fifo_ctrl_data/mem_addr_wen | |||
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329 | add wave -noupdate -expand -group fifo_ctrl_data_2 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_data(2)/lpp_waveform_fifo_ctrl_data/ready | |||
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330 | add wave -noupdate -group fifo_ctrl_data_1 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_data(1)/lpp_waveform_fifo_ctrl_data/clk | |||
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331 | add wave -noupdate -group fifo_ctrl_data_1 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_data(1)/lpp_waveform_fifo_ctrl_data/rstn | |||
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332 | add wave -noupdate -group fifo_ctrl_data_1 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_data(1)/lpp_waveform_fifo_ctrl_data/ren | |||
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333 | add wave -noupdate -group fifo_ctrl_data_1 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_data(1)/lpp_waveform_fifo_ctrl_data/wen | |||
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334 | add wave -noupdate -group fifo_ctrl_data_1 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_data(1)/lpp_waveform_fifo_ctrl_data/mem_re | |||
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335 | add wave -noupdate -group fifo_ctrl_data_1 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_data(1)/lpp_waveform_fifo_ctrl_data/mem_we | |||
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336 | add wave -noupdate -group fifo_ctrl_data_1 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_data(1)/lpp_waveform_fifo_ctrl_data/mem_addr_ren | |||
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337 | add wave -noupdate -group fifo_ctrl_data_1 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_data(1)/lpp_waveform_fifo_ctrl_data/mem_addr_wen | |||
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338 | add wave -noupdate -group fifo_ctrl_data_1 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_data(1)/lpp_waveform_fifo_ctrl_data/ready | |||
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339 | add wave -noupdate -group fifo_ctrl_data_0 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_data(0)/lpp_waveform_fifo_ctrl_data/clk | |||
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340 | add wave -noupdate -group fifo_ctrl_data_0 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_data(0)/lpp_waveform_fifo_ctrl_data/rstn | |||
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341 | add wave -noupdate -group fifo_ctrl_data_0 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_data(0)/lpp_waveform_fifo_ctrl_data/ren | |||
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342 | add wave -noupdate -group fifo_ctrl_data_0 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_data(0)/lpp_waveform_fifo_ctrl_data/wen | |||
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343 | add wave -noupdate -group fifo_ctrl_data_0 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_data(0)/lpp_waveform_fifo_ctrl_data/mem_re | |||
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344 | add wave -noupdate -group fifo_ctrl_data_0 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_data(0)/lpp_waveform_fifo_ctrl_data/mem_we | |||
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345 | add wave -noupdate -group fifo_ctrl_data_0 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_data(0)/lpp_waveform_fifo_ctrl_data/mem_addr_ren | |||
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346 | add wave -noupdate -group fifo_ctrl_data_0 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_data(0)/lpp_waveform_fifo_ctrl_data/mem_addr_wen | |||
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347 | add wave -noupdate -group fifo_ctrl_data_0 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_data(0)/lpp_waveform_fifo_ctrl_data/ready | |||
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348 | TreeUpdate [SetDefaultTree] | |||
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349 | WaveRestoreCursors {{Cursor 1} {70458134452 ps} 0} | |||
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350 | configure wave -namecolwidth 842 | |||
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351 | configure wave -valuecolwidth 100 | |||
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352 | configure wave -justifyvalue left | |||
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353 | configure wave -signalnamewidth 0 | |||
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354 | configure wave -snapdistance 10 | |||
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355 | configure wave -datasetprefix 0 | |||
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356 | configure wave -rowmargin 4 | |||
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357 | configure wave -childrowmargin 2 | |||
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358 | configure wave -gridoffset 0 | |||
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359 | configure wave -gridperiod 1 | |||
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360 | configure wave -griddelta 40 | |||
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361 | configure wave -timeline 0 | |||
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362 | configure wave -timelineunits ns | |||
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363 | update | |||
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364 | WaveRestoreZoom {70455153866 ps} {70464281299 ps} | |||
| @@ -0,0 +1,277 | |||||
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1 | LIBRARY IEEE; | |||
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2 | USE IEEE.STD_LOGIC_1164.ALL; | |||
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3 | USE ieee.numeric_std.ALL; | |||
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4 | ||||
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5 | LIBRARY grlib; | |||
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6 | USE grlib.amba.ALL; | |||
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7 | USE grlib.stdlib.ALL; | |||
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8 | USE grlib.devices.ALL; | |||
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9 | USE GRLIB.DMA2AHB_Package.ALL; | |||
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10 | ||||
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11 | LIBRARY lpp; | |||
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12 | USE lpp.lpp_waveform_pkg.ALL; | |||
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13 | ||||
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14 | LIBRARY techmap; | |||
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15 | USE techmap.gencomp.ALL; | |||
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16 | ||||
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17 | ENTITY lpp_waveform IS | |||
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18 | ||||
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19 | GENERIC ( | |||
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20 | hindex : INTEGER := 2; | |||
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21 | tech : INTEGER := inferred; | |||
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22 | data_size : INTEGER := 160; | |||
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23 | nb_burst_available_size : INTEGER := 11; | |||
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24 | nb_snapshot_param_size : INTEGER := 11; | |||
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25 | delta_snapshot_size : INTEGER := 16; | |||
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26 | delta_f2_f0_size : INTEGER := 10; | |||
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27 | delta_f2_f1_size : INTEGER := 10); | |||
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28 | ||||
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29 | PORT ( | |||
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30 | clk : IN STD_LOGIC; | |||
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31 | rstn : IN STD_LOGIC; | |||
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32 | ||||
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33 | -- AMBA AHB Master Interface | |||
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34 | AHB_Master_In : IN AHB_Mst_In_Type; | |||
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35 | AHB_Master_Out : OUT AHB_Mst_Out_Type; | |||
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36 | ||||
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37 | coarse_time_0 : IN STD_LOGIC; | |||
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38 | ||||
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39 | --config | |||
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40 | delta_snapshot : IN STD_LOGIC_VECTOR(delta_snapshot_size-1 DOWNTO 0); | |||
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41 | delta_f2_f1 : IN STD_LOGIC_VECTOR(delta_f2_f1_size-1 DOWNTO 0); | |||
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42 | delta_f2_f0 : IN STD_LOGIC_VECTOR(delta_f2_f0_size-1 DOWNTO 0); | |||
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43 | ||||
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44 | enable_f0 : IN STD_LOGIC; | |||
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45 | enable_f1 : IN STD_LOGIC; | |||
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46 | enable_f2 : IN STD_LOGIC; | |||
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47 | enable_f3 : IN STD_LOGIC; | |||
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48 | ||||
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49 | burst_f0 : IN STD_LOGIC; | |||
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50 | burst_f1 : IN STD_LOGIC; | |||
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51 | burst_f2 : IN STD_LOGIC; | |||
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52 | ||||
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53 | nb_burst_available : IN STD_LOGIC_VECTOR(nb_burst_available_size-1 DOWNTO 0); | |||
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54 | nb_snapshot_param : IN STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0); | |||
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55 | status_full : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); | |||
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56 | status_full_ack : IN STD_LOGIC_VECTOR(3 DOWNTO 0); | |||
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57 | status_full_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); | |||
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58 | status_new_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); -- New data f(i) before the current data is write by dma | |||
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59 | addr_data_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
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60 | addr_data_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
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61 | addr_data_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
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62 | addr_data_f3 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
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63 | ||||
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64 | data_f0_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); | |||
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65 | data_f1_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); | |||
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66 | data_f2_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); | |||
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67 | data_f3_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); | |||
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68 | ||||
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69 | data_f0_in_valid : IN STD_LOGIC; | |||
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70 | data_f1_in_valid : IN STD_LOGIC; | |||
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71 | data_f2_in_valid : IN STD_LOGIC; | |||
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72 | data_f3_in_valid : IN STD_LOGIC | |||
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73 | ); | |||
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74 | ||||
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75 | END lpp_waveform; | |||
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76 | ||||
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77 | ARCHITECTURE beh OF lpp_waveform IS | |||
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78 | SIGNAL start_snapshot_f0 : STD_LOGIC; | |||
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79 | SIGNAL start_snapshot_f1 : STD_LOGIC; | |||
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80 | SIGNAL start_snapshot_f2 : STD_LOGIC; | |||
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81 | ||||
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82 | SIGNAL data_f0_out : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); | |||
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83 | SIGNAL data_f1_out : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); | |||
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84 | SIGNAL data_f2_out : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); | |||
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85 | SIGNAL data_f3_out : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); | |||
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86 | ||||
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87 | SIGNAL data_f0_out_valid : STD_LOGIC; | |||
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88 | SIGNAL data_f1_out_valid : STD_LOGIC; | |||
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89 | SIGNAL data_f2_out_valid : STD_LOGIC; | |||
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90 | SIGNAL data_f3_out_valid : STD_LOGIC; | |||
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91 | SIGNAL nb_snapshot_param_more_one : STD_LOGIC_VECTOR(nb_snapshot_param_size DOWNTO 0); | |||
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92 | ||||
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93 | -- | |||
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94 | SIGNAL valid_in : STD_LOGIC_VECTOR(3 DOWNTO 0); | |||
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95 | SIGNAL valid_out : STD_LOGIC_VECTOR(3 DOWNTO 0); | |||
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96 | SIGNAL valid_ack : STD_LOGIC_VECTOR(3 DOWNTO 0); | |||
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97 | SIGNAL ready : STD_LOGIC_VECTOR(3 DOWNTO 0); | |||
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98 | SIGNAL ready_arb : STD_LOGIC_VECTOR(3 DOWNTO 0); | |||
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99 | SIGNAL data_wen : STD_LOGIC_VECTOR(3 DOWNTO 0); | |||
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100 | SIGNAL time_wen : STD_LOGIC_VECTOR(3 DOWNTO 0); | |||
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101 | SIGNAL wdata : STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
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102 | -- | |||
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103 | SIGNAL data_ren : STD_LOGIC_VECTOR(3 DOWNTO 0); | |||
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104 | SIGNAL time_ren : STD_LOGIC_VECTOR(3 DOWNTO 0); | |||
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105 | SIGNAL rdata : STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
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106 | ||||
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107 | BEGIN -- beh | |||
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108 | ||||
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109 | lpp_waveform_snapshot_controler_1: lpp_waveform_snapshot_controler | |||
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110 | GENERIC MAP ( | |||
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111 | delta_snapshot_size => delta_snapshot_size, | |||
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112 | delta_f2_f0_size => delta_f2_f0_size, | |||
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113 | delta_f2_f1_size => delta_f2_f1_size) | |||
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114 | PORT MAP ( | |||
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115 | clk => clk, | |||
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116 | rstn => rstn, | |||
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117 | delta_snapshot => delta_snapshot, | |||
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118 | delta_f2_f1 => delta_f2_f1, | |||
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119 | delta_f2_f0 => delta_f2_f0, | |||
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120 | coarse_time_0 => coarse_time_0, | |||
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121 | data_f0_in_valid => data_f0_in_valid, | |||
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122 | data_f2_in_valid => data_f2_in_valid, | |||
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123 | start_snapshot_f0 => start_snapshot_f0, | |||
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124 | start_snapshot_f1 => start_snapshot_f1, | |||
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125 | start_snapshot_f2 => start_snapshot_f2); | |||
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126 | ||||
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127 | lpp_waveform_snapshot_f0 : lpp_waveform_snapshot | |||
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128 | GENERIC MAP ( | |||
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129 | data_size => data_size, | |||
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130 | nb_snapshot_param_size => nb_snapshot_param_size) | |||
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131 | PORT MAP ( | |||
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132 | clk => clk, | |||
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133 | rstn => rstn, | |||
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134 | enable => enable_f0, | |||
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135 | burst_enable => burst_f0, | |||
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136 | nb_snapshot_param => nb_snapshot_param, | |||
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137 | start_snapshot => start_snapshot_f0, | |||
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138 | data_in => data_f0_in, | |||
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139 | data_in_valid => data_f0_in_valid, | |||
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140 | data_out => data_f0_out, | |||
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141 | data_out_valid => data_f0_out_valid); | |||
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142 | ||||
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143 | nb_snapshot_param_more_one <= ('0' & nb_snapshot_param) + 1; | |||
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144 | ||||
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145 | lpp_waveform_snapshot_f1 : lpp_waveform_snapshot | |||
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146 | GENERIC MAP ( | |||
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147 | data_size => data_size, | |||
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148 | nb_snapshot_param_size => nb_snapshot_param_size+1) | |||
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149 | PORT MAP ( | |||
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150 | clk => clk, | |||
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151 | rstn => rstn, | |||
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152 | enable => enable_f1, | |||
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153 | burst_enable => burst_f1, | |||
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154 | nb_snapshot_param => nb_snapshot_param_more_one, | |||
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155 | start_snapshot => start_snapshot_f1, | |||
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156 | data_in => data_f1_in, | |||
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157 | data_in_valid => data_f1_in_valid, | |||
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158 | data_out => data_f1_out, | |||
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159 | data_out_valid => data_f1_out_valid); | |||
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160 | ||||
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161 | lpp_waveform_snapshot_f2 : lpp_waveform_snapshot | |||
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162 | GENERIC MAP ( | |||
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163 | data_size => data_size, | |||
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164 | nb_snapshot_param_size => nb_snapshot_param_size+1) | |||
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165 | PORT MAP ( | |||
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166 | clk => clk, | |||
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167 | rstn => rstn, | |||
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168 | enable => enable_f2, | |||
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169 | burst_enable => burst_f2, | |||
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170 | nb_snapshot_param => nb_snapshot_param_more_one, | |||
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171 | start_snapshot => start_snapshot_f2, | |||
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172 | data_in => data_f2_in, | |||
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173 | data_in_valid => data_f2_in_valid, | |||
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174 | data_out => data_f2_out, | |||
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175 | data_out_valid => data_f2_out_valid); | |||
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176 | ||||
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177 | lpp_waveform_burst_f3: lpp_waveform_burst | |||
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178 | GENERIC MAP ( | |||
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179 | data_size => data_size) | |||
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180 | PORT MAP ( | |||
|
|
181 | clk => clk, | |||
|
|
182 | rstn => rstn, | |||
|
|
183 | enable => enable_f3, | |||
|
|
184 | data_in => data_f3_in, | |||
|
|
185 | data_in_valid => data_f3_in_valid, | |||
|
|
186 | data_out => data_f3_out, | |||
|
|
187 | data_out_valid => data_f3_out_valid); | |||
|
|
188 | ||||
|
|
189 | ||||
|
|
190 | valid_in <= data_f3_out_valid & data_f2_out_valid & data_f1_out_valid & data_f0_out_valid; | |||
|
|
191 | ||||
|
|
192 | all_input_valid: FOR i IN 3 DOWNTO 0 GENERATE | |||
|
|
193 | lpp_waveform_dma_gen_valid_I: lpp_waveform_dma_gen_valid | |||
|
|
194 | PORT MAP ( | |||
|
|
195 | HCLK => clk, | |||
|
|
196 | HRESETn => rstn, | |||
|
|
197 | valid_in => valid_in(I), | |||
|
|
198 | ack_in => valid_ack(I), | |||
|
|
199 | valid_out => valid_out(I), | |||
|
|
200 | error => status_new_err(I)); | |||
|
|
201 | END GENERATE all_input_valid; | |||
|
|
202 | ||||
|
|
203 | lpp_waveform_fifo_arbiter_1: lpp_waveform_fifo_arbiter | |||
|
|
204 | GENERIC MAP (tech => tech) | |||
|
|
205 | PORT MAP ( | |||
|
|
206 | clk => clk, | |||
|
|
207 | rstn => rstn, | |||
|
|
208 | data_f0_valid => valid_out(0), | |||
|
|
209 | data_f1_valid => valid_out(1), | |||
|
|
210 | data_f2_valid => valid_out(2), | |||
|
|
211 | data_f3_valid => valid_out(3), | |||
|
|
212 | ||||
|
|
213 | data_valid_ack => valid_ack, | |||
|
|
214 | ||||
|
|
215 | data_f0 => data_f0_out, | |||
|
|
216 | data_f1 => data_f1_out, | |||
|
|
217 | data_f2 => data_f2_out, | |||
|
|
218 | data_f3 => data_f3_out, | |||
|
|
219 | ||||
|
|
220 | ready => ready_arb, | |||
|
|
221 | time_wen => time_wen, | |||
|
|
222 | data_wen => data_wen, | |||
|
|
223 | data => wdata); | |||
|
|
224 | ||||
|
|
225 | ready_arb <= NOT ready; | |||
|
|
226 | ||||
|
|
227 | lpp_waveform_fifo_1: lpp_waveform_fifo | |||
|
|
228 | GENERIC MAP (tech => tech) | |||
|
|
229 | PORT MAP ( | |||
|
|
230 | clk => clk, | |||
|
|
231 | rstn => rstn, | |||
|
|
232 | ready => ready, | |||
|
|
233 | time_ren => time_ren, -- todo | |||
|
|
234 | data_ren => data_ren, -- todo | |||
|
|
235 | rdata => rdata, -- todo | |||
|
|
236 | ||||
|
|
237 | time_wen => time_wen, | |||
|
|
238 | data_wen => data_wen, | |||
|
|
239 | wdata => wdata); | |||
|
|
240 | ||||
|
|
241 | --time_ren <= (OTHERS => '1'); | |||
|
|
242 | --data_ren <= (OTHERS => '1'); | |||
|
|
243 | ||||
|
|
244 | pp_waveform_dma_1: lpp_waveform_dma | |||
|
|
245 | GENERIC MAP ( | |||
|
|
246 | data_size => data_size, | |||
|
|
247 | tech => tech, | |||
|
|
248 | hindex => hindex, | |||
|
|
249 | nb_burst_available_size => nb_burst_available_size) | |||
|
|
250 | PORT MAP ( | |||
|
|
251 | HCLK => clk, | |||
|
|
252 | HRESETn => rstn, | |||
|
|
253 | AHB_Master_In => AHB_Master_In, | |||
|
|
254 | AHB_Master_Out => AHB_Master_Out, | |||
|
|
255 | data_ready => ready, | |||
|
|
256 | data => rdata, | |||
|
|
257 | data_data_ren => data_ren, | |||
|
|
258 | data_time_ren => time_ren, | |||
|
|
259 | --data_f0_in => data_f0_out, | |||
|
|
260 | --data_f1_in => data_f1_out, | |||
|
|
261 | --data_f2_in => data_f2_out, | |||
|
|
262 | --data_f3_in => data_f3_out, | |||
|
|
263 | --data_f0_in_valid => data_f0_out_valid, | |||
|
|
264 | --data_f1_in_valid => data_f1_out_valid, | |||
|
|
265 | --data_f2_in_valid => data_f2_out_valid, | |||
|
|
266 | --data_f3_in_valid => data_f3_out_valid, | |||
|
|
267 | nb_burst_available => nb_burst_available, | |||
|
|
268 | status_full => status_full, | |||
|
|
269 | status_full_ack => status_full_ack, | |||
|
|
270 | status_full_err => status_full_err, | |||
|
|
271 | -- status_new_err => status_new_err, | |||
|
|
272 | addr_data_f0 => addr_data_f0, | |||
|
|
273 | addr_data_f1 => addr_data_f1, | |||
|
|
274 | addr_data_f2 => addr_data_f2, | |||
|
|
275 | addr_data_f3 => addr_data_f3); | |||
|
|
276 | ||||
|
|
277 | END beh; | |||
| @@ -0,0 +1,42 | |||||
|
|
1 | LIBRARY IEEE; | |||
|
|
2 | USE IEEE.STD_LOGIC_1164.ALL; | |||
|
|
3 | ||||
|
|
4 | ENTITY lpp_waveform_burst IS | |||
|
|
5 | ||||
|
|
6 | GENERIC ( | |||
|
|
7 | data_size : INTEGER := 16); | |||
|
|
8 | ||||
|
|
9 | PORT ( | |||
|
|
10 | clk : IN STD_LOGIC; | |||
|
|
11 | rstn : IN STD_LOGIC; | |||
|
|
12 | ||||
|
|
13 | enable : IN STD_LOGIC; | |||
|
|
14 | ||||
|
|
15 | data_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); | |||
|
|
16 | data_in_valid : IN STD_LOGIC; | |||
|
|
17 | ||||
|
|
18 | data_out : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); | |||
|
|
19 | data_out_valid : OUT STD_LOGIC | |||
|
|
20 | ); | |||
|
|
21 | ||||
|
|
22 | END lpp_waveform_burst; | |||
|
|
23 | ||||
|
|
24 | ARCHITECTURE beh OF lpp_waveform_burst IS | |||
|
|
25 | BEGIN -- beh | |||
|
|
26 | ||||
|
|
27 | PROCESS (clk, rstn) | |||
|
|
28 | BEGIN | |||
|
|
29 | IF rstn = '0' THEN | |||
|
|
30 | data_out <= (OTHERS => '0'); | |||
|
|
31 | data_out_valid <= '0'; | |||
|
|
32 | ELSIF clk'EVENT AND clk = '1' THEN | |||
|
|
33 | data_out <= data_in; | |||
|
|
34 | IF enable = '0' THEN | |||
|
|
35 | data_out_valid <= '0'; | |||
|
|
36 | ELSE | |||
|
|
37 | data_out_valid <= data_in_valid; | |||
|
|
38 | END IF; | |||
|
|
39 | END IF; | |||
|
|
40 | END PROCESS; | |||
|
|
41 | ||||
|
|
42 | END beh; | |||
| @@ -0,0 +1,363 | |||||
|
|
1 | ||||
|
|
2 | ------------------------------------------------------------------------------ | |||
|
|
3 | -- This file is a part of the LPP VHDL IP LIBRARY | |||
|
|
4 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS | |||
|
|
5 | -- | |||
|
|
6 | -- This program is free software; you can redistribute it and/or modify | |||
|
|
7 | -- it under the terms of the GNU General Public License as published by | |||
|
|
8 | -- the Free Software Foundation; either version 3 of the License, or | |||
|
|
9 | -- (at your option) any later version. | |||
|
|
10 | -- | |||
|
|
11 | -- This program is distributed in the hope that it will be useful, | |||
|
|
12 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of | |||
|
|
13 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |||
|
|
14 | -- GNU General Public License for more details. | |||
|
|
15 | -- | |||
|
|
16 | -- You should have received a copy of the GNU General Public License | |||
|
|
17 | -- along with this program; if not, write to the Free Software | |||
|
|
18 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |||
|
|
19 | ------------------------------------------------------------------------------- | |||
|
|
20 | -- Author : Jean-christophe Pellion | |||
|
|
21 | -- Mail : jean-christophe.pellion@lpp.polytechnique.fr | |||
|
|
22 | -- jean-christophe.pellion@easii-ic.com | |||
|
|
23 | ------------------------------------------------------------------------------- | |||
|
|
24 | -- 1.0 - initial version | |||
|
|
25 | -- 1.1 - (01/11/2013) FIX boundary error (1kB address should not be crossed by BURSTS) | |||
|
|
26 | ------------------------------------------------------------------------------- | |||
|
|
27 | LIBRARY ieee; | |||
|
|
28 | USE ieee.std_logic_1164.ALL; | |||
|
|
29 | USE ieee.numeric_std.ALL; | |||
|
|
30 | LIBRARY grlib; | |||
|
|
31 | USE grlib.amba.ALL; | |||
|
|
32 | USE grlib.stdlib.ALL; | |||
|
|
33 | USE grlib.devices.ALL; | |||
|
|
34 | USE GRLIB.DMA2AHB_Package.ALL; | |||
|
|
35 | LIBRARY lpp; | |||
|
|
36 | USE lpp.lpp_amba.ALL; | |||
|
|
37 | USE lpp.apb_devices_list.ALL; | |||
|
|
38 | USE lpp.lpp_memory.ALL; | |||
|
|
39 | USE lpp.lpp_dma_pkg.ALL; | |||
|
|
40 | USE lpp.lpp_waveform_pkg.ALL; | |||
|
|
41 | LIBRARY techmap; | |||
|
|
42 | USE techmap.gencomp.ALL; | |||
|
|
43 | ||||
|
|
44 | ||||
|
|
45 | ENTITY lpp_waveform_dma IS | |||
|
|
46 | GENERIC ( | |||
|
|
47 | data_size : INTEGER := 160; | |||
|
|
48 | tech : INTEGER := inferred; | |||
|
|
49 | hindex : INTEGER := 2; | |||
|
|
50 | nb_burst_available_size : INTEGER := 11 | |||
|
|
51 | ); | |||
|
|
52 | PORT ( | |||
|
|
53 | -- AMBA AHB system signals | |||
|
|
54 | HCLK : IN STD_ULOGIC; | |||
|
|
55 | HRESETn : IN STD_ULOGIC; | |||
|
|
56 | -- AMBA AHB Master Interface | |||
|
|
57 | AHB_Master_In : IN AHB_Mst_In_Type; | |||
|
|
58 | AHB_Master_Out : OUT AHB_Mst_Out_Type; | |||
|
|
59 | -- | |||
|
|
60 | data_ready : IN STD_LOGIC_VECTOR(3 DOWNTO 0); -- todo | |||
|
|
61 | data : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- todo | |||
|
|
62 | data_data_ren : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); -- todo | |||
|
|
63 | data_time_ren : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); -- todo | |||
|
|
64 | -- Reg | |||
|
|
65 | nb_burst_available : IN STD_LOGIC_VECTOR(nb_burst_available_size-1 DOWNTO 0); | |||
|
|
66 | status_full : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); | |||
|
|
67 | status_full_ack : IN STD_LOGIC_VECTOR(3 DOWNTO 0); | |||
|
|
68 | status_full_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); | |||
|
|
69 | -- status_new_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); -- New data f(i) before the current data is write by dma | |||
|
|
70 | addr_data_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
|
|
71 | addr_data_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
|
|
72 | addr_data_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
|
|
73 | addr_data_f3 : IN STD_LOGIC_VECTOR(31 DOWNTO 0) | |||
|
|
74 | ); | |||
|
|
75 | END; | |||
|
|
76 | ||||
|
|
77 | ARCHITECTURE Behavioral OF lpp_waveform_dma IS | |||
|
|
78 | ----------------------------------------------------------------------------- | |||
|
|
79 | SIGNAL DMAIn : DMA_In_Type; | |||
|
|
80 | SIGNAL DMAOut : DMA_OUt_Type; | |||
|
|
81 | ----------------------------------------------------------------------------- | |||
|
|
82 | TYPE state_DMAWriteBurst IS (IDLE, | |||
|
|
83 | SEND_TIME_0, WAIT_TIME_0, | |||
|
|
84 | SEND_TIME_1, WAIT_TIME_1, | |||
|
|
85 | SEND_5_TIME, | |||
|
|
86 | SEND_DATA, WAIT_DATA); | |||
|
|
87 | SIGNAL state : state_DMAWriteBurst := IDLE; | |||
|
|
88 | ----------------------------------------------------------------------------- | |||
|
|
89 | -- CONTROL | |||
|
|
90 | SIGNAL sel_data_s : STD_LOGIC_VECTOR(1 DOWNTO 0); | |||
|
|
91 | SIGNAL sel_data : STD_LOGIC_VECTOR(1 DOWNTO 0); | |||
|
|
92 | SIGNAL update : STD_LOGIC_VECTOR(1 DOWNTO 0); | |||
|
|
93 | SIGNAL time_select : STD_LOGIC; | |||
|
|
94 | SIGNAL time_write : STD_LOGIC; | |||
|
|
95 | SIGNAL time_already_send : STD_LOGIC_VECTOR(3 DOWNTO 0); | |||
|
|
96 | SIGNAL time_already_send_s : STD_LOGIC; | |||
|
|
97 | ----------------------------------------------------------------------------- | |||
|
|
98 | -- SEND TIME MODULE | |||
|
|
99 | SIGNAL time_dmai : DMA_In_Type; | |||
|
|
100 | SIGNAL time_send : STD_LOGIC; | |||
|
|
101 | SIGNAL time_send_ok : STD_LOGIC; | |||
|
|
102 | SIGNAL time_send_ko : STD_LOGIC; | |||
|
|
103 | SIGNAL time_fifo_ren : STD_LOGIC; | |||
|
|
104 | SIGNAL time_ren : STD_LOGIC; | |||
|
|
105 | ----------------------------------------------------------------------------- | |||
|
|
106 | -- SEND DATA MODULE | |||
|
|
107 | SIGNAL data_dmai : DMA_In_Type; | |||
|
|
108 | SIGNAL data_send : STD_LOGIC; | |||
|
|
109 | SIGNAL data_send_ok : STD_LOGIC; | |||
|
|
110 | SIGNAL data_send_ko : STD_LOGIC; | |||
|
|
111 | SIGNAL data_fifo_ren : STD_LOGIC; | |||
|
|
112 | SIGNAL data_ren : STD_LOGIC; | |||
|
|
113 | ----------------------------------------------------------------------------- | |||
|
|
114 | -- SELECT ADDRESS | |||
|
|
115 | SIGNAL data_address : STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
|
|
116 | SIGNAL update_and_sel : STD_LOGIC_VECTOR(7 DOWNTO 0); | |||
|
|
117 | SIGNAL addr_data_reg_vector : STD_LOGIC_VECTOR(32*4-1 DOWNTO 0); | |||
|
|
118 | SIGNAL addr_data_vector : STD_LOGIC_VECTOR(32*4-1 DOWNTO 0); | |||
|
|
119 | ----------------------------------------------------------------------------- | |||
|
|
120 | SIGNAL send_16_3_time : STD_LOGIC_VECTOR(2 DOWNTO 0); | |||
|
|
121 | SIGNAL count_send_time : INTEGER; | |||
|
|
122 | BEGIN | |||
|
|
123 | ||||
|
|
124 | ----------------------------------------------------------------------------- | |||
|
|
125 | -- DMA to AHB interface | |||
|
|
126 | DMA2AHB_1 : DMA2AHB | |||
|
|
127 | GENERIC MAP ( | |||
|
|
128 | hindex => hindex, | |||
|
|
129 | vendorid => VENDOR_LPP, | |||
|
|
130 | deviceid => 0, | |||
|
|
131 | version => 0, | |||
|
|
132 | syncrst => 1, | |||
|
|
133 | boundary => 1) -- FIX 11/01/2013 | |||
|
|
134 | PORT MAP ( | |||
|
|
135 | HCLK => HCLK, | |||
|
|
136 | HRESETn => HRESETn, | |||
|
|
137 | DMAIn => DMAIn, | |||
|
|
138 | DMAOut => DMAOut, | |||
|
|
139 | AHBIn => AHB_Master_In, | |||
|
|
140 | AHBOut => AHB_Master_Out); | |||
|
|
141 | ----------------------------------------------------------------------------- | |||
|
|
142 | ||||
|
|
143 | ----------------------------------------------------------------------------- | |||
|
|
144 | -- This module memorises when the Times info are write. When FSM send | |||
|
|
145 | -- the Times info, the "reg" is set and when a full_ack is received the "reg" is reset. | |||
|
|
146 | all_time_write: FOR I IN 3 DOWNTO 0 GENERATE | |||
|
|
147 | PROCESS (HCLK, HRESETn) | |||
|
|
148 | BEGIN -- PROCESS | |||
|
|
149 | IF HRESETn = '0' THEN -- asynchronous reset (active low) | |||
|
|
150 | time_already_send(I) <= '0'; | |||
|
|
151 | ELSIF HCLK'EVENT AND HCLK = '1' THEN -- rising clock edge | |||
|
|
152 | IF time_write = '1' AND UNSIGNED(sel_data) = I THEN | |||
|
|
153 | time_already_send(I) <= '1'; | |||
|
|
154 | ELSIF status_full_ack(I) = '1' THEN | |||
|
|
155 | time_already_send(I) <= '0'; | |||
|
|
156 | END IF; | |||
|
|
157 | END IF; | |||
|
|
158 | END PROCESS; | |||
|
|
159 | END GENERATE all_time_write; | |||
|
|
160 | ||||
|
|
161 | ----------------------------------------------------------------------------- | |||
|
|
162 | sel_data_s <= "00" WHEN data_ready(0) = '1' ELSE | |||
|
|
163 | "01" WHEN data_ready(1) = '1' ELSE | |||
|
|
164 | "10" WHEN data_ready(2) = '1' ELSE | |||
|
|
165 | "11"; | |||
|
|
166 | ||||
|
|
167 | time_already_send_s <= time_already_send(0) WHEN data_ready(0) = '1' ELSE | |||
|
|
168 | time_already_send(1) WHEN data_ready(1) = '1' ELSE | |||
|
|
169 | time_already_send(2) WHEN data_ready(2) = '1' ELSE | |||
|
|
170 | time_already_send(3); | |||
|
|
171 | ||||
|
|
172 | -- DMA control | |||
|
|
173 | DMAWriteFSM_p : PROCESS (HCLK, HRESETn) | |||
|
|
174 | BEGIN -- PROCESS DMAWriteBurst_p | |||
|
|
175 | IF HRESETn = '0' THEN | |||
|
|
176 | state <= IDLE; | |||
|
|
177 | ||||
|
|
178 | sel_data <= "00"; | |||
|
|
179 | update <= "00"; | |||
|
|
180 | time_select <= '0'; | |||
|
|
181 | time_fifo_ren <= '1'; | |||
|
|
182 | data_send <= '0'; | |||
|
|
183 | time_send <= '0'; | |||
|
|
184 | time_write <= '0'; | |||
|
|
185 | send_16_3_time <= "001"; | |||
|
|
186 | ||||
|
|
187 | ELSIF HCLK'EVENT AND HCLK = '1' THEN | |||
|
|
188 | ||||
|
|
189 | CASE state IS | |||
|
|
190 | WHEN IDLE => | |||
|
|
191 | count_send_time <= 0; | |||
|
|
192 | sel_data <= "00"; | |||
|
|
193 | update <= "00"; | |||
|
|
194 | time_select <= '0'; | |||
|
|
195 | time_fifo_ren <= '1'; | |||
|
|
196 | data_send <= '0'; | |||
|
|
197 | time_send <= '0'; | |||
|
|
198 | time_write <= '0'; | |||
|
|
199 | ||||
|
|
200 | IF data_ready = "0000" THEN | |||
|
|
201 | state <= IDLE; | |||
|
|
202 | ELSE | |||
|
|
203 | sel_data <= sel_data_s; | |||
|
|
204 | send_16_3_time <= send_16_3_time(1 DOWNTO 0) & send_16_3_time(2); | |||
|
|
205 | IF send_16_3_time(0) = '1' THEN | |||
|
|
206 | state <= SEND_TIME_0; | |||
|
|
207 | ELSE | |||
|
|
208 | state <= SEND_5_TIME; | |||
|
|
209 | END IF; | |||
|
|
210 | END IF; | |||
|
|
211 | ||||
|
|
212 | WHEN SEND_TIME_0 => | |||
|
|
213 | time_select <= '1'; | |||
|
|
214 | IF time_already_send_s = '0' THEN | |||
|
|
215 | time_send <= '1'; | |||
|
|
216 | state <= WAIT_TIME_0; | |||
|
|
217 | ELSE | |||
|
|
218 | time_send <= '0'; | |||
|
|
219 | state <= SEND_TIME_1; | |||
|
|
220 | END IF; | |||
|
|
221 | time_fifo_ren <= '0'; | |||
|
|
222 | ||||
|
|
223 | WHEN WAIT_TIME_0 => | |||
|
|
224 | time_fifo_ren <= '1'; | |||
|
|
225 | update <= "00"; | |||
|
|
226 | time_send <= '0'; | |||
|
|
227 | IF time_send_ok = '1' OR time_send_ko = '1' THEN | |||
|
|
228 | update <= "01"; | |||
|
|
229 | state <= SEND_TIME_1; | |||
|
|
230 | END IF; | |||
|
|
231 | ||||
|
|
232 | WHEN SEND_TIME_1 => | |||
|
|
233 | time_select <= '1'; | |||
|
|
234 | IF time_already_send_s = '0' THEN | |||
|
|
235 | time_send <= '1'; | |||
|
|
236 | state <= WAIT_TIME_1; | |||
|
|
237 | ELSE | |||
|
|
238 | time_send <= '0'; | |||
|
|
239 | state <= SEND_5_TIME; | |||
|
|
240 | END IF; | |||
|
|
241 | time_fifo_ren <= '0'; | |||
|
|
242 | ||||
|
|
243 | WHEN WAIT_TIME_1 => | |||
|
|
244 | time_fifo_ren <= '1'; | |||
|
|
245 | update <= "00"; | |||
|
|
246 | time_send <= '0'; | |||
|
|
247 | IF time_send_ok = '1' OR time_send_ko = '1' THEN | |||
|
|
248 | time_write <= '1'; | |||
|
|
249 | update <= "01"; | |||
|
|
250 | state <= SEND_5_TIME; | |||
|
|
251 | END IF; | |||
|
|
252 | ||||
|
|
253 | WHEN SEND_5_TIME => | |||
|
|
254 | update <= "00"; | |||
|
|
255 | time_select <= '1'; | |||
|
|
256 | time_fifo_ren <= '0'; | |||
|
|
257 | count_send_time <= count_send_time + 1; | |||
|
|
258 | IF count_send_time = 10 THEN | |||
|
|
259 | state <= SEND_DATA; | |||
|
|
260 | END IF; | |||
|
|
261 | ||||
|
|
262 | WHEN SEND_DATA => | |||
|
|
263 | time_fifo_ren <= '1'; | |||
|
|
264 | time_write <= '0'; | |||
|
|
265 | time_send <= '0'; | |||
|
|
266 | ||||
|
|
267 | time_select <= '0'; | |||
|
|
268 | data_send <= '1'; | |||
|
|
269 | update <= "00"; | |||
|
|
270 | state <= WAIT_DATA; | |||
|
|
271 | ||||
|
|
272 | WHEN WAIT_DATA => | |||
|
|
273 | data_send <= '0'; | |||
|
|
274 | ||||
|
|
275 | IF data_send_ok = '1' OR data_send_ko = '1' THEN | |||
|
|
276 | state <= IDLE; | |||
|
|
277 | update <= "10"; | |||
|
|
278 | END IF; | |||
|
|
279 | ||||
|
|
280 | WHEN OTHERS => NULL; | |||
|
|
281 | END CASE; | |||
|
|
282 | ||||
|
|
283 | END IF; | |||
|
|
284 | END PROCESS DMAWriteFSM_p; | |||
|
|
285 | ----------------------------------------------------------------------------- | |||
|
|
286 | ||||
|
|
287 | ||||
|
|
288 | ||||
|
|
289 | ----------------------------------------------------------------------------- | |||
|
|
290 | -- SEND 1 word by DMA | |||
|
|
291 | ----------------------------------------------------------------------------- | |||
|
|
292 | lpp_dma_send_1word_1 : lpp_dma_send_1word | |||
|
|
293 | PORT MAP ( | |||
|
|
294 | HCLK => HCLK, | |||
|
|
295 | HRESETn => HRESETn, | |||
|
|
296 | DMAIn => time_dmai, | |||
|
|
297 | DMAOut => DMAOut, | |||
|
|
298 | ||||
|
|
299 | send => time_send, | |||
|
|
300 | address => data_address, | |||
|
|
301 | data => data, | |||
|
|
302 | send_ok => time_send_ok, | |||
|
|
303 | send_ko => time_send_ko | |||
|
|
304 | ); | |||
|
|
305 | ||||
|
|
306 | ----------------------------------------------------------------------------- | |||
|
|
307 | -- SEND 16 word by DMA (in burst mode) | |||
|
|
308 | ----------------------------------------------------------------------------- | |||
|
|
309 | lpp_dma_send_16word_1 : lpp_dma_send_16word | |||
|
|
310 | PORT MAP ( | |||
|
|
311 | HCLK => HCLK, | |||
|
|
312 | HRESETn => HRESETn, | |||
|
|
313 | DMAIn => data_dmai, | |||
|
|
314 | DMAOut => DMAOut, | |||
|
|
315 | ||||
|
|
316 | send => data_send, | |||
|
|
317 | address => data_address, | |||
|
|
318 | data => data, | |||
|
|
319 | ren => data_fifo_ren, | |||
|
|
320 | send_ok => data_send_ok, | |||
|
|
321 | send_ko => data_send_ko); | |||
|
|
322 | ||||
|
|
323 | DMAIn <= time_dmai WHEN time_select = '1' ELSE data_dmai; | |||
|
|
324 | data_ren <= '1' WHEN time_select = '1' ELSE data_fifo_ren; | |||
|
|
325 | time_ren <= time_fifo_ren WHEN time_select = '1' ELSE '1'; | |||
|
|
326 | ||||
|
|
327 | all_data_ren : FOR I IN 3 DOWNTO 0 GENERATE | |||
|
|
328 | data_data_ren(I) <= data_ren WHEN UNSIGNED(sel_data) = I ELSE '1'; | |||
|
|
329 | data_time_ren(I) <= time_ren WHEN UNSIGNED(sel_data) = I ELSE '1'; | |||
|
|
330 | END GENERATE all_data_ren; | |||
|
|
331 | ||||
|
|
332 | ----------------------------------------------------------------------------- | |||
|
|
333 | -- SELECT ADDRESS | |||
|
|
334 | addr_data_reg_vector <= addr_data_f3 & addr_data_f2 & addr_data_f1 & addr_data_f0; | |||
|
|
335 | ||||
|
|
336 | gen_select_address : FOR I IN 3 DOWNTO 0 GENERATE | |||
|
|
337 | ||||
|
|
338 | update_and_sel((2*I)+1 DOWNTO 2*I) <= update WHEN UNSIGNED(sel_data) = I ELSE "00"; | |||
|
|
339 | ||||
|
|
340 | lpp_waveform_dma_selectaddress_I : lpp_waveform_dma_selectaddress | |||
|
|
341 | GENERIC MAP ( | |||
|
|
342 | nb_burst_available_size => nb_burst_available_size) | |||
|
|
343 | PORT MAP ( | |||
|
|
344 | HCLK => HCLK, | |||
|
|
345 | HRESETn => HRESETn, | |||
|
|
346 | update => update_and_sel((2*I)+1 DOWNTO 2*I), | |||
|
|
347 | nb_burst_available => nb_burst_available, | |||
|
|
348 | addr_data_reg => addr_data_reg_vector(32*I+31 DOWNTO 32*I), | |||
|
|
349 | addr_data => addr_data_vector(32*I+31 DOWNTO 32*I), | |||
|
|
350 | status_full => status_full(I), | |||
|
|
351 | status_full_ack => status_full_ack(I), | |||
|
|
352 | status_full_err => status_full_err(I)); | |||
|
|
353 | ||||
|
|
354 | END GENERATE gen_select_address; | |||
|
|
355 | ||||
|
|
356 | data_address <= addr_data_vector(31 DOWNTO 0) WHEN UNSIGNED(sel_data) = 0 ELSE | |||
|
|
357 | addr_data_vector(32*1+31 DOWNTO 32*1) WHEN UNSIGNED(sel_data) = 1 ELSE | |||
|
|
358 | addr_data_vector(32*2+31 DOWNTO 32*2) WHEN UNSIGNED(sel_data) = 2 ELSE | |||
|
|
359 | addr_data_vector(32*3+31 DOWNTO 32*3); | |||
|
|
360 | ----------------------------------------------------------------------------- | |||
|
|
361 | ||||
|
|
362 | ||||
|
|
363 | END Behavioral; | |||
| @@ -0,0 +1,88 | |||||
|
|
1 | ||||
|
|
2 | ------------------------------------------------------------------------------ | |||
|
|
3 | -- This file is a part of the LPP VHDL IP LIBRARY | |||
|
|
4 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS | |||
|
|
5 | -- | |||
|
|
6 | -- This program is free software; you can redistribute it and/or modify | |||
|
|
7 | -- it under the terms of the GNU General Public License as published by | |||
|
|
8 | -- the Free Software Foundation; either version 3 of the License, or | |||
|
|
9 | -- (at your option) any later version. | |||
|
|
10 | -- | |||
|
|
11 | -- This program is distributed in the hope that it will be useful, | |||
|
|
12 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of | |||
|
|
13 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |||
|
|
14 | -- GNU General Public License for more details. | |||
|
|
15 | -- | |||
|
|
16 | -- You should have received a copy of the GNU General Public License | |||
|
|
17 | -- along with this program; if not, write to the Free Software | |||
|
|
18 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |||
|
|
19 | ------------------------------------------------------------------------------- | |||
|
|
20 | -- Author : Jean-christophe Pellion | |||
|
|
21 | -- Mail : jean-christophe.pellion@lpp.polytechnique.fr | |||
|
|
22 | -- jean-christophe.pellion@easii-ic.com | |||
|
|
23 | ------------------------------------------------------------------------------- | |||
|
|
24 | -- 1.0 - initial version | |||
|
|
25 | ------------------------------------------------------------------------------- | |||
|
|
26 | ||||
|
|
27 | LIBRARY ieee; | |||
|
|
28 | USE ieee.std_logic_1164.ALL; | |||
|
|
29 | USE ieee.numeric_std.ALL; | |||
|
|
30 | ||||
|
|
31 | ||||
|
|
32 | ENTITY lpp_waveform_dma_gen_valid IS | |||
|
|
33 | PORT ( | |||
|
|
34 | HCLK : IN STD_LOGIC; | |||
|
|
35 | HRESETn : IN STD_LOGIC; | |||
|
|
36 | ||||
|
|
37 | valid_in : IN STD_LOGIC; | |||
|
|
38 | ack_in : IN STD_LOGIC; | |||
|
|
39 | ||||
|
|
40 | valid_out : OUT STD_LOGIC; | |||
|
|
41 | error : OUT STD_LOGIC | |||
|
|
42 | ); | |||
|
|
43 | END; | |||
|
|
44 | ||||
|
|
45 | ARCHITECTURE Behavioral OF lpp_waveform_dma_gen_valid IS | |||
|
|
46 | TYPE state_fsm IS (IDLE, VALID); | |||
|
|
47 | SIGNAL state : state_fsm; | |||
|
|
48 | BEGIN | |||
|
|
49 | ||||
|
|
50 | FSM_SELECT_ADDRESS : PROCESS (HCLK, HRESETn) | |||
|
|
51 | BEGIN | |||
|
|
52 | IF HRESETn = '0' THEN | |||
|
|
53 | state <= IDLE; | |||
|
|
54 | valid_out <= '0'; | |||
|
|
55 | error <= '0'; | |||
|
|
56 | ELSIF HCLK'EVENT AND HCLK = '1' THEN | |||
|
|
57 | CASE state IS | |||
|
|
58 | WHEN IDLE => | |||
|
|
59 | valid_out <= '0'; | |||
|
|
60 | error <= '0'; | |||
|
|
61 | IF valid_in = '1' THEN | |||
|
|
62 | state <= VALID; | |||
|
|
63 | valid_out <= '1'; | |||
|
|
64 | END IF; | |||
|
|
65 | ||||
|
|
66 | WHEN VALID => | |||
|
|
67 | valid_out <= '1'; | |||
|
|
68 | error <= '0'; | |||
|
|
69 | IF valid_in = '1' THEN | |||
|
|
70 | IF ack_in = '1' THEN | |||
|
|
71 | state <= VALID; | |||
|
|
72 | valid_out <= '1'; | |||
|
|
73 | ELSE | |||
|
|
74 | state <= IDLE; | |||
|
|
75 | error <= '1'; | |||
|
|
76 | valid_out <= '0'; | |||
|
|
77 | END IF; | |||
|
|
78 | ELSIF ack_in = '1' THEN | |||
|
|
79 | state <= IDLE; | |||
|
|
80 | valid_out <= '0'; | |||
|
|
81 | END IF; | |||
|
|
82 | ||||
|
|
83 | WHEN OTHERS => NULL; | |||
|
|
84 | END CASE; | |||
|
|
85 | END IF; | |||
|
|
86 | END PROCESS FSM_SELECT_ADDRESS; | |||
|
|
87 | ||||
|
|
88 | END Behavioral; | |||
| @@ -0,0 +1,129 | |||||
|
|
1 | ||||
|
|
2 | ------------------------------------------------------------------------------ | |||
|
|
3 | -- This file is a part of the LPP VHDL IP LIBRARY | |||
|
|
4 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS | |||
|
|
5 | -- | |||
|
|
6 | -- This program is free software; you can redistribute it and/or modify | |||
|
|
7 | -- it under the terms of the GNU General Public License as published by | |||
|
|
8 | -- the Free Software Foundation; either version 3 of the License, or | |||
|
|
9 | -- (at your option) any later version. | |||
|
|
10 | -- | |||
|
|
11 | -- This program is distributed in the hope that it will be useful, | |||
|
|
12 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of | |||
|
|
13 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |||
|
|
14 | -- GNU General Public License for more details. | |||
|
|
15 | -- | |||
|
|
16 | -- You should have received a copy of the GNU General Public License | |||
|
|
17 | -- along with this program; if not, write to the Free Software | |||
|
|
18 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |||
|
|
19 | ------------------------------------------------------------------------------- | |||
|
|
20 | -- Author : Jean-christophe Pellion | |||
|
|
21 | -- Mail : jean-christophe.pellion@lpp.polytechnique.fr | |||
|
|
22 | -- jean-christophe.pellion@easii-ic.com | |||
|
|
23 | ------------------------------------------------------------------------------- | |||
|
|
24 | -- 1.0 - initial version | |||
|
|
25 | ------------------------------------------------------------------------------- | |||
|
|
26 | ||||
|
|
27 | LIBRARY ieee; | |||
|
|
28 | USE ieee.std_logic_1164.ALL; | |||
|
|
29 | USE ieee.numeric_std.ALL; | |||
|
|
30 | ||||
|
|
31 | ||||
|
|
32 | ENTITY lpp_waveform_dma_selectaddress IS | |||
|
|
33 | GENERIC ( | |||
|
|
34 | nb_burst_available_size : INTEGER := 11 | |||
|
|
35 | ); | |||
|
|
36 | PORT ( | |||
|
|
37 | HCLK : IN STD_ULOGIC; | |||
|
|
38 | HRESETn : IN STD_ULOGIC; | |||
|
|
39 | ||||
|
|
40 | update : IN STD_LOGIC_VECTOR(1 DOWNTO 0); | |||
|
|
41 | ||||
|
|
42 | nb_burst_available : IN STD_LOGIC_VECTOR(nb_burst_available_size-1 DOWNTO 0); | |||
|
|
43 | addr_data_reg : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
|
|
44 | ||||
|
|
45 | addr_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
|
|
46 | ||||
|
|
47 | status_full : OUT STD_LOGIC; | |||
|
|
48 | status_full_ack : IN STD_LOGIC; | |||
|
|
49 | status_full_err : OUT STD_LOGIC | |||
|
|
50 | ); | |||
|
|
51 | END; | |||
|
|
52 | ||||
|
|
53 | ARCHITECTURE Behavioral OF lpp_waveform_dma_selectaddress IS | |||
|
|
54 | TYPE state_fsm_select_data IS (IDLE, ADD, FULL, ERR, UPDATED); | |||
|
|
55 | SIGNAL state : state_fsm_select_data; | |||
|
|
56 | ||||
|
|
57 | SIGNAL address : STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
|
|
58 | SIGNAL nb_send : STD_LOGIC_VECTOR(nb_burst_available_size-1 DOWNTO 0); | |||
|
|
59 | SIGNAL nb_send_next : STD_LOGIC_VECTOR(nb_burst_available_size-1 DOWNTO 0); | |||
|
|
60 | ||||
|
|
61 | SIGNAL update_s : STD_LOGIC; | |||
|
|
62 | BEGIN | |||
|
|
63 | ||||
|
|
64 | update_s <= update(0) OR update(1); | |||
|
|
65 | ||||
|
|
66 | addr_data <= address; | |||
|
|
67 | nb_send_next <= std_logic_vector(unsigned(nb_send) + 1); | |||
|
|
68 | ||||
|
|
69 | FSM_SELECT_ADDRESS : PROCESS (HCLK, HRESETn) | |||
|
|
70 | BEGIN | |||
|
|
71 | IF HRESETn = '0' THEN | |||
|
|
72 | state <= IDLE; | |||
|
|
73 | address <= (OTHERS => '0'); | |||
|
|
74 | nb_send <= (OTHERS => '0'); | |||
|
|
75 | status_full <= '0'; | |||
|
|
76 | status_full_err <= '0'; | |||
|
|
77 | ELSIF HCLK'EVENT AND HCLK = '1' THEN | |||
|
|
78 | CASE state IS | |||
|
|
79 | WHEN IDLE => | |||
|
|
80 | IF update_s = '1' THEN | |||
|
|
81 | state <= ADD; | |||
|
|
82 | END IF; | |||
|
|
83 | ||||
|
|
84 | WHEN ADD => | |||
|
|
85 | IF UNSIGNED(nb_send_next) < UNSIGNED(nb_burst_available) THEN | |||
|
|
86 | state <= IDLE; | |||
|
|
87 | IF update = "10" THEN | |||
|
|
88 | address <= std_logic_vector(unsigned(address) + 16); | |||
|
|
89 | nb_send <= nb_send_next; | |||
|
|
90 | ELSIF update = "01" THEN | |||
|
|
91 | address <= std_logic_vector(unsigned(address) + 1); | |||
|
|
92 | END IF; | |||
|
|
93 | ELSE | |||
|
|
94 | state <= FULL; | |||
|
|
95 | nb_send <= (OTHERS => '0'); | |||
|
|
96 | status_full <= '1'; | |||
|
|
97 | END IF; | |||
|
|
98 | ||||
|
|
99 | WHEN FULL => | |||
|
|
100 | status_full <= '0'; | |||
|
|
101 | IF status_full_ack = '1' THEN | |||
|
|
102 | IF update_s = '1' THEN | |||
|
|
103 | status_full_err <= '1'; | |||
|
|
104 | END IF; | |||
|
|
105 | state <= UPDATED; | |||
|
|
106 | ELSE | |||
|
|
107 | IF update_s = '1' THEN | |||
|
|
108 | status_full_err <= '1'; | |||
|
|
109 | state <= ERR; | |||
|
|
110 | END IF; | |||
|
|
111 | END IF; | |||
|
|
112 | ||||
|
|
113 | WHEN ERR => | |||
|
|
114 | status_full_err <= '0'; | |||
|
|
115 | IF status_full_ack = '1' THEN | |||
|
|
116 | state <= UPDATED; | |||
|
|
117 | END IF; | |||
|
|
118 | ||||
|
|
119 | WHEN UPDATED => | |||
|
|
120 | status_full_err <= '0'; | |||
|
|
121 | state <= IDLE; | |||
|
|
122 | address <= addr_data_reg; | |||
|
|
123 | ||||
|
|
124 | WHEN OTHERS => NULL; | |||
|
|
125 | END CASE; | |||
|
|
126 | END IF; | |||
|
|
127 | END PROCESS FSM_SELECT_ADDRESS; | |||
|
|
128 | ||||
|
|
129 | END Behavioral; | |||
| @@ -0,0 +1,173 | |||||
|
|
1 | ------------------------------------------------------------------------------ | |||
|
|
2 | -- This file is a part of the LPP VHDL IP LIBRARY | |||
|
|
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS | |||
|
|
4 | -- | |||
|
|
5 | -- This program is free software; you can redistribute it and/or modify | |||
|
|
6 | -- it under the terms of the GNU General Public License as published by | |||
|
|
7 | -- the Free Software Foundation; either version 3 of the License, or | |||
|
|
8 | -- (at your option) any later version. | |||
|
|
9 | -- | |||
|
|
10 | -- This program is distributed in the hope that it will be useful, | |||
|
|
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of | |||
|
|
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |||
|
|
13 | -- GNU General Public License for more details. | |||
|
|
14 | -- | |||
|
|
15 | -- You should have received a copy of the GNU General Public License | |||
|
|
16 | -- along with this program; if not, write to the Free Software | |||
|
|
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |||
|
|
18 | ------------------------------------------------------------------------------- | |||
|
|
19 | -- Author : Jean-christophe Pellion | |||
|
|
20 | -- Mail : jean-christophe.pellion@lpp.polytechnique.fr | |||
|
|
21 | -- jean-christophe.pellion@easii-ic.com | |||
|
|
22 | ---------------------------------------------------------------------------- | |||
|
|
23 | ||||
|
|
24 | LIBRARY ieee; | |||
|
|
25 | USE ieee.std_logic_1164.ALL; | |||
|
|
26 | USE ieee.numeric_std.ALL; | |||
|
|
27 | LIBRARY grlib; | |||
|
|
28 | USE grlib.amba.ALL; | |||
|
|
29 | USE grlib.stdlib.ALL; | |||
|
|
30 | USE grlib.devices.ALL; | |||
|
|
31 | USE GRLIB.DMA2AHB_Package.ALL; | |||
|
|
32 | LIBRARY lpp; | |||
|
|
33 | USE lpp.lpp_amba.ALL; | |||
|
|
34 | USE lpp.apb_devices_list.ALL; | |||
|
|
35 | USE lpp.lpp_memory.ALL; | |||
|
|
36 | LIBRARY techmap; | |||
|
|
37 | USE techmap.gencomp.ALL; | |||
|
|
38 | ||||
|
|
39 | ENTITY lpp_waveform_dma_send_Nword IS | |||
|
|
40 | PORT ( | |||
|
|
41 | -- AMBA AHB system signals | |||
|
|
42 | HCLK : IN STD_ULOGIC; | |||
|
|
43 | HRESETn : IN STD_ULOGIC; | |||
|
|
44 | ||||
|
|
45 | -- DMA | |||
|
|
46 | DMAIn : OUT DMA_In_Type; | |||
|
|
47 | DMAOut : IN DMA_OUt_Type; | |||
|
|
48 | ||||
|
|
49 | -- | |||
|
|
50 | Nb_word_less1 : IN STD_LOGIC_VECTOR(3 DOWNTO 0); | |||
|
|
51 | -- | |||
|
|
52 | send : IN STD_LOGIC; | |||
|
|
53 | address : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
|
|
54 | data : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
|
|
55 | ren : OUT STD_LOGIC; | |||
|
|
56 | -- | |||
|
|
57 | send_ok : OUT STD_LOGIC; | |||
|
|
58 | send_ko : OUT STD_LOGIC | |||
|
|
59 | ); | |||
|
|
60 | END lpp_waveform_dma_send_Nword; | |||
|
|
61 | ||||
|
|
62 | ARCHITECTURE beh OF lpp_waveform_dma_send_Nword IS | |||
|
|
63 | ||||
|
|
64 | TYPE state_fsm_send_Nword IS (IDLE, REQUEST_BUS, SEND_DATA, ERROR0, ERROR1, WAIT_LAST_READY); | |||
|
|
65 | SIGNAL state : state_fsm_send_Nword; | |||
|
|
66 | ||||
|
|
67 | SIGNAL data_counter : INTEGER; | |||
|
|
68 | SIGNAL grant_counter : INTEGER; | |||
|
|
69 | ||||
|
|
70 | BEGIN -- beh | |||
|
|
71 | ||||
|
|
72 | DMAIn.Beat <= HINCR16; | |||
|
|
73 | DMAIn.Size <= HSIZE32; | |||
|
|
74 | ||||
|
|
75 | PROCESS (HCLK, HRESETn) | |||
|
|
76 | BEGIN -- PROCESS | |||
|
|
77 | IF HRESETn = '0' THEN -- asynchronous reset (active low) | |||
|
|
78 | state <= IDLE; | |||
|
|
79 | send_ok <= '0'; | |||
|
|
80 | send_ko <= '0'; | |||
|
|
81 | ||||
|
|
82 | DMAIn.Reset <= '0'; | |||
|
|
83 | DMAIn.Address <= (OTHERS => '0'); | |||
|
|
84 | DMAIn.Request <= '0'; | |||
|
|
85 | DMAIn.Store <= '0'; | |||
|
|
86 | DMAIn.Burst <= '1'; | |||
|
|
87 | DMAIn.Lock <= '0'; | |||
|
|
88 | data_counter <= 0; | |||
|
|
89 | ELSIF HCLK'EVENT AND HCLK = '1' THEN -- rising clock edge | |||
|
|
90 | ||||
|
|
91 | CASE state IS | |||
|
|
92 | WHEN IDLE => | |||
|
|
93 | DMAIn.Store <= '1'; | |||
|
|
94 | DMAIn.Request <= '0'; | |||
|
|
95 | send_ok <= '0'; | |||
|
|
96 | send_ko <= '0'; | |||
|
|
97 | DMAIn.Address <= address; | |||
|
|
98 | data_counter <= 0; | |||
|
|
99 | DMAIn.Lock <= '0'; -- FIX test | |||
|
|
100 | IF send = '1' THEN | |||
|
|
101 | state <= REQUEST_BUS; | |||
|
|
102 | DMAIn.Request <= '1'; | |||
|
|
103 | DMAIn.Lock <= '1'; -- FIX test | |||
|
|
104 | DMAIn.Store <= '1'; | |||
|
|
105 | END IF; | |||
|
|
106 | WHEN REQUEST_BUS => | |||
|
|
107 | IF DMAOut.Grant = '1' THEN | |||
|
|
108 | data_counter <= 1; | |||
|
|
109 | grant_counter <= 1; | |||
|
|
110 | state <= SEND_DATA; | |||
|
|
111 | END IF; | |||
|
|
112 | WHEN SEND_DATA => | |||
|
|
113 | ||||
|
|
114 | IF DMAOut.Fault = '1' THEN | |||
|
|
115 | DMAIn.Reset <= '0'; | |||
|
|
116 | DMAIn.Address <= (OTHERS => '0'); | |||
|
|
117 | DMAIn.Request <= '0'; | |||
|
|
118 | DMAIn.Store <= '0'; | |||
|
|
119 | DMAIn.Burst <= '0'; | |||
|
|
120 | state <= ERROR0; | |||
|
|
121 | ELSE | |||
|
|
122 | ||||
|
|
123 | IF DMAOut.Grant = '1' THEN | |||
|
|
124 | IF grant_counter = UNSIGNED(Nb_word_less1) THEN -- | |||
|
|
125 | DMAIn.Reset <= '0'; | |||
|
|
126 | DMAIn.Request <= '0'; | |||
|
|
127 | DMAIn.Store <= '0'; | |||
|
|
128 | DMAIn.Burst <= '0'; | |||
|
|
129 | ELSE | |||
|
|
130 | grant_counter <= grant_counter+1; | |||
|
|
131 | END IF; | |||
|
|
132 | END IF; | |||
|
|
133 | ||||
|
|
134 | IF DMAOut.OKAY = '1' THEN | |||
|
|
135 | IF data_counter = UNSIGNED(Nb_word_less1) THEN | |||
|
|
136 | DMAIn.Address <= (OTHERS => '0'); | |||
|
|
137 | state <= WAIT_LAST_READY; | |||
|
|
138 | ELSE | |||
|
|
139 | data_counter <= data_counter + 1; | |||
|
|
140 | END IF; | |||
|
|
141 | END IF; | |||
|
|
142 | END IF; | |||
|
|
143 | ||||
|
|
144 | ||||
|
|
145 | WHEN WAIT_LAST_READY => | |||
|
|
146 | IF DMAOut.Ready = '1' THEN | |||
|
|
147 | IF grant_counter = UNSIGNED(Nb_word_less1) THEN | |||
|
|
148 | state <= IDLE; | |||
|
|
149 | send_ok <= '1'; | |||
|
|
150 | send_ko <= '0'; | |||
|
|
151 | ELSE | |||
|
|
152 | state <= ERROR0; | |||
|
|
153 | END IF; | |||
|
|
154 | END IF; | |||
|
|
155 | ||||
|
|
156 | WHEN ERROR0 => | |||
|
|
157 | state <= ERROR1; | |||
|
|
158 | WHEN ERROR1 => | |||
|
|
159 | send_ok <= '0'; | |||
|
|
160 | send_ko <= '1'; | |||
|
|
161 | state <= IDLE; | |||
|
|
162 | WHEN OTHERS => NULL; | |||
|
|
163 | END CASE; | |||
|
|
164 | END IF; | |||
|
|
165 | END PROCESS; | |||
|
|
166 | ||||
|
|
167 | DMAIn.Data <= data; | |||
|
|
168 | ||||
|
|
169 | ren <= '0' WHEN DMAOut.OKAY = '1' AND state = SEND_DATA ELSE | |||
|
|
170 | '0' WHEN state = REQUEST_BUS AND DMAOut.Grant = '1' ELSE | |||
|
|
171 | '1'; | |||
|
|
172 | ||||
|
|
173 | END beh; | |||
| @@ -0,0 +1,176 | |||||
|
|
1 | ------------------------------------------------------------------------------ | |||
|
|
2 | -- This file is a part of the LPP VHDL IP LIBRARY | |||
|
|
3 | -- Copyright (C) 2009 - 2012, Laboratory of Plasmas Physic - CNRS | |||
|
|
4 | -- | |||
|
|
5 | -- This program is free software; you can redistribute it and/or modify | |||
|
|
6 | -- it under the terms of the GNU General Public License as published by | |||
|
|
7 | -- the Free Software Foundation; either version 3 of the License, or | |||
|
|
8 | -- (at your option) any later version. | |||
|
|
9 | -- | |||
|
|
10 | -- This program is distributed in the hope that it will be useful, | |||
|
|
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of | |||
|
|
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |||
|
|
13 | -- GNU General Public License for more details. | |||
|
|
14 | -- | |||
|
|
15 | -- You should have received a copy of the GNU General Public License | |||
|
|
16 | -- along with this program; if not, write to the Free Software | |||
|
|
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |||
|
|
18 | ------------------------------------------------------------------------------ | |||
|
|
19 | -- Author : Jean-christophe PELLION | |||
|
|
20 | -- Mail : jean-christophe.pellion@lpp.polytechnique.fr | |||
|
|
21 | ------------------------------------------------------------------------------ | |||
|
|
22 | LIBRARY IEEE; | |||
|
|
23 | USE IEEE.std_logic_1164.ALL; | |||
|
|
24 | USE IEEE.numeric_std.ALL; | |||
|
|
25 | LIBRARY lpp; | |||
|
|
26 | USE lpp.lpp_memory.ALL; | |||
|
|
27 | USE lpp.iir_filter.ALL; | |||
|
|
28 | USE lpp.lpp_waveform_pkg.ALL; | |||
|
|
29 | ||||
|
|
30 | LIBRARY techmap; | |||
|
|
31 | USE techmap.gencomp.ALL; | |||
|
|
32 | ||||
|
|
33 | ENTITY lpp_waveform_fifo IS | |||
|
|
34 | GENERIC( | |||
|
|
35 | tech : INTEGER := 0 | |||
|
|
36 | ); | |||
|
|
37 | PORT( | |||
|
|
38 | clk : IN STD_LOGIC; | |||
|
|
39 | rstn : IN STD_LOGIC; | |||
|
|
40 | ||||
|
|
41 | --------------------------------------------------------------------------- | |||
|
|
42 | ready : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); -- FIFO_DATA occupancy is greater than 16 * 32b | |||
|
|
43 | ||||
|
|
44 | --------------------------------------------------------------------------- | |||
|
|
45 | time_ren : IN STD_LOGIC_VECTOR(3 DOWNTO 0); | |||
|
|
46 | data_ren : IN STD_LOGIC_VECTOR(3 DOWNTO 0); | |||
|
|
47 | ||||
|
|
48 | rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
|
|
49 | ||||
|
|
50 | --------------------------------------------------------------------------- | |||
|
|
51 | time_wen : IN STD_LOGIC_VECTOR(3 DOWNTO 0); | |||
|
|
52 | data_wen : IN STD_LOGIC_VECTOR(3 DOWNTO 0); | |||
|
|
53 | ||||
|
|
54 | wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0) | |||
|
|
55 | ); | |||
|
|
56 | END ENTITY; | |||
|
|
57 | ||||
|
|
58 | ||||
|
|
59 | ARCHITECTURE ar_lpp_waveform_fifo OF lpp_waveform_fifo IS | |||
|
|
60 | ||||
|
|
61 | ||||
|
|
62 | SIGNAL time_mem_addr_r : LPP_TYPE_ADDR_FIFO_WAVEFORM(3 DOWNTO 0); | |||
|
|
63 | SIGNAL time_mem_addr_w : LPP_TYPE_ADDR_FIFO_WAVEFORM(3 DOWNTO 0); | |||
|
|
64 | SIGNAL time_mem_ren : STD_LOGIC_VECTOR(3 DOWNTO 0); | |||
|
|
65 | SIGNAL time_mem_wen : STD_LOGIC_VECTOR(3 DOWNTO 0); | |||
|
|
66 | ||||
|
|
67 | SIGNAL data_mem_addr_r : LPP_TYPE_ADDR_FIFO_WAVEFORM(3 DOWNTO 0); | |||
|
|
68 | SIGNAL data_mem_addr_w : LPP_TYPE_ADDR_FIFO_WAVEFORM(3 DOWNTO 0); | |||
|
|
69 | SIGNAL data_mem_ren : STD_LOGIC_VECTOR(3 DOWNTO 0); | |||
|
|
70 | SIGNAL data_mem_wen : STD_LOGIC_VECTOR(3 DOWNTO 0); | |||
|
|
71 | ||||
|
|
72 | SIGNAL data_addr_r : STD_LOGIC_VECTOR(6 DOWNTO 0); | |||
|
|
73 | SIGNAL data_addr_w : STD_LOGIC_VECTOR(6 DOWNTO 0); | |||
|
|
74 | SIGNAL ren : STD_LOGIC; | |||
|
|
75 | SIGNAL wen : STD_LOGIC; | |||
|
|
76 | ||||
|
|
77 | BEGIN | |||
|
|
78 | ||||
|
|
79 | SRAM : syncram_2p | |||
|
|
80 | GENERIC MAP(tech, 7, 32) | |||
|
|
81 | PORT MAP(clk, ren, data_addr_r, rdata, | |||
|
|
82 | clk, wen, data_addr_w, wdata); | |||
|
|
83 | ||||
|
|
84 | ||||
|
|
85 | ren <= time_mem_ren(3) OR data_mem_ren(3) OR | |||
|
|
86 | time_mem_ren(2) OR data_mem_ren(2) OR | |||
|
|
87 | time_mem_ren(1) OR data_mem_ren(1) OR | |||
|
|
88 | time_mem_ren(0) OR data_mem_ren(0); | |||
|
|
89 | ||||
|
|
90 | wen <= time_mem_wen(3) OR data_mem_wen(3) OR | |||
|
|
91 | time_mem_wen(2) OR data_mem_wen(2) OR | |||
|
|
92 | time_mem_wen(1) OR data_mem_wen(1) OR | |||
|
|
93 | time_mem_wen(0) OR data_mem_wen(0); | |||
|
|
94 | ||||
|
|
95 | data_addr_r <= time_mem_addr_r(0) WHEN time_mem_ren(0) = '1' ELSE | |||
|
|
96 | time_mem_addr_r(1) WHEN time_mem_ren(1) = '1' ELSE | |||
|
|
97 | time_mem_addr_r(2) WHEN time_mem_ren(2) = '1' ELSE | |||
|
|
98 | time_mem_addr_r(3) WHEN time_mem_ren(3) = '1' ELSE | |||
|
|
99 | data_mem_addr_r(0) WHEN data_mem_ren(0) = '1' ELSE | |||
|
|
100 | data_mem_addr_r(1) WHEN data_mem_ren(1) = '1' ELSE | |||
|
|
101 | data_mem_addr_r(2) WHEN data_mem_ren(2) = '1' ELSE | |||
|
|
102 | data_mem_addr_r(3); | |||
|
|
103 | ||||
|
|
104 | data_addr_w <= time_mem_addr_w(0) WHEN time_mem_wen(0) = '1' ELSE | |||
|
|
105 | time_mem_addr_w(1) WHEN time_mem_wen(1) = '1' ELSE | |||
|
|
106 | time_mem_addr_w(2) WHEN time_mem_wen(2) = '1' ELSE | |||
|
|
107 | time_mem_addr_w(3) WHEN time_mem_wen(3) = '1' ELSE | |||
|
|
108 | data_mem_addr_w(0) WHEN data_mem_wen(0) = '1' ELSE | |||
|
|
109 | data_mem_addr_w(1) WHEN data_mem_wen(1) = '1' ELSE | |||
|
|
110 | data_mem_addr_w(2) WHEN data_mem_wen(2) = '1' ELSE | |||
|
|
111 | data_mem_addr_w(3); | |||
|
|
112 | ||||
|
|
113 | gen_fifo_ctrl_time: FOR I IN 3 DOWNTO 0 GENERATE | |||
|
|
114 | lpp_waveform_fifo_ctrl_time: lpp_waveform_fifo_ctrl | |||
|
|
115 | GENERIC MAP ( | |||
|
|
116 | offset => 32*I + 20, | |||
|
|
117 | length => 10, | |||
|
|
118 | enable_ready => '0') | |||
|
|
119 | PORT MAP ( | |||
|
|
120 | clk => clk, | |||
|
|
121 | rstn => rstn, | |||
|
|
122 | ren => time_ren(I), | |||
|
|
123 | wen => time_wen(I), | |||
|
|
124 | mem_re => time_mem_ren(I), | |||
|
|
125 | mem_we => time_mem_wen(I), | |||
|
|
126 | mem_addr_ren => time_mem_addr_r(I), | |||
|
|
127 | mem_addr_wen => time_mem_addr_w(I), | |||
|
|
128 | ready => OPEN); | |||
|
|
129 | END GENERATE gen_fifo_ctrl_time; | |||
|
|
130 | ||||
|
|
131 | gen_fifo_ctrl_data: FOR I IN 3 DOWNTO 0 GENERATE | |||
|
|
132 | lpp_waveform_fifo_ctrl_data: lpp_waveform_fifo_ctrl | |||
|
|
133 | GENERIC MAP ( | |||
|
|
134 | offset => 32*I, | |||
|
|
135 | length => 20, | |||
|
|
136 | enable_ready => '1') | |||
|
|
137 | PORT MAP ( | |||
|
|
138 | clk => clk, | |||
|
|
139 | rstn => rstn, | |||
|
|
140 | ren => data_ren(I), | |||
|
|
141 | wen => data_wen(I), | |||
|
|
142 | mem_re => data_mem_ren(I), | |||
|
|
143 | mem_we => data_mem_wen(I), | |||
|
|
144 | mem_addr_ren => data_mem_addr_r(I), | |||
|
|
145 | mem_addr_wen => data_mem_addr_w(I), | |||
|
|
146 | ready => ready(I)); | |||
|
|
147 | END GENERATE gen_fifo_ctrl_data; | |||
|
|
148 | ||||
|
|
149 | ||||
|
|
150 | END ARCHITECTURE; | |||
|
|
151 | ||||
|
|
152 | ||||
|
|
153 | ||||
|
|
154 | ||||
|
|
155 | ||||
|
|
156 | ||||
|
|
157 | ||||
|
|
158 | ||||
|
|
159 | ||||
|
|
160 | ||||
|
|
161 | ||||
|
|
162 | ||||
|
|
163 | ||||
|
|
164 | ||||
|
|
165 | ||||
|
|
166 | ||||
|
|
167 | ||||
|
|
168 | ||||
|
|
169 | ||||
|
|
170 | ||||
|
|
171 | ||||
|
|
172 | ||||
|
|
173 | ||||
|
|
174 | ||||
|
|
175 | ||||
|
|
176 | ||||
| @@ -0,0 +1,177 | |||||
|
|
1 | ------------------------------------------------------------------------------ | |||
|
|
2 | -- This file is a part of the LPP VHDL IP LIBRARY | |||
|
|
3 | -- Copyright (C) 2009 - 2012, Laboratory of Plasmas Physic - CNRS | |||
|
|
4 | -- | |||
|
|
5 | -- This program is free software; you can redistribute it and/or modify | |||
|
|
6 | -- it under the terms of the GNU General Public License as published by | |||
|
|
7 | -- the Free Software Foundation; either version 3 of the License, or | |||
|
|
8 | -- (at your option) any later version. | |||
|
|
9 | -- | |||
|
|
10 | -- This program is distributed in the hope that it will be useful, | |||
|
|
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of | |||
|
|
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |||
|
|
13 | -- GNU General Public License for more details. | |||
|
|
14 | -- | |||
|
|
15 | -- You should have received a copy of the GNU General Public License | |||
|
|
16 | -- along with this program; if not, write to the Free Software | |||
|
|
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |||
|
|
18 | ------------------------------------------------------------------------------ | |||
|
|
19 | -- Author : Jean-christophe PELLION | |||
|
|
20 | -- Mail : jean-christophe.pellion@lpp.polytechnique.fr | |||
|
|
21 | ------------------------------------------------------------------------------ | |||
|
|
22 | LIBRARY IEEE; | |||
|
|
23 | USE IEEE.std_logic_1164.ALL; | |||
|
|
24 | USE IEEE.numeric_std.ALL; | |||
|
|
25 | ||||
|
|
26 | LIBRARY lpp; | |||
|
|
27 | USE lpp.lpp_waveform_pkg.ALL; | |||
|
|
28 | ||||
|
|
29 | ENTITY lpp_waveform_fifo_arbiter IS | |||
|
|
30 | GENERIC( | |||
|
|
31 | tech : INTEGER := 0 | |||
|
|
32 | ); | |||
|
|
33 | PORT( | |||
|
|
34 | clk : IN STD_LOGIC; | |||
|
|
35 | rstn : IN STD_LOGIC; | |||
|
|
36 | ||||
|
|
37 | --------------------------------------------------------------------------- | |||
|
|
38 | data_f0_valid : IN STD_LOGIC; | |||
|
|
39 | data_f1_valid : IN STD_LOGIC; | |||
|
|
40 | data_f2_valid : IN STD_LOGIC; | |||
|
|
41 | data_f3_valid : IN STD_LOGIC; | |||
|
|
42 | ||||
|
|
43 | data_valid_ack : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); | |||
|
|
44 | ||||
|
|
45 | data_f0 : IN STD_LOGIC_VECTOR(159 DOWNTO 0); | |||
|
|
46 | data_f1 : IN STD_LOGIC_VECTOR(159 DOWNTO 0); | |||
|
|
47 | data_f2 : IN STD_LOGIC_VECTOR(159 DOWNTO 0); | |||
|
|
48 | data_f3 : IN STD_LOGIC_VECTOR(159 DOWNTO 0); | |||
|
|
49 | ||||
|
|
50 | --------------------------------------------------------------------------- | |||
|
|
51 | ready : IN STD_LOGIC_VECTOR(3 DOWNTO 0); | |||
|
|
52 | ||||
|
|
53 | --------------------------------------------------------------------------- | |||
|
|
54 | time_wen : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); | |||
|
|
55 | data_wen : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); | |||
|
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56 | data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) | |||
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57 | ||||
|
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58 | ); | |||
|
|
59 | END ENTITY; | |||
|
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60 | ||||
|
|
61 | ||||
|
|
62 | ARCHITECTURE ar_lpp_waveform_fifo_arbiter OF lpp_waveform_fifo_arbiter IS | |||
|
|
63 | TYPE state_fsm IS (IDLE, T1, T2, D1, D2); | |||
|
|
64 | SIGNAL state : state_fsm; | |||
|
|
65 | ||||
|
|
66 | SIGNAL data_valid_and_ready : STD_LOGIC_VECTOR(3 DOWNTO 0); | |||
|
|
67 | SIGNAL data_selected : STD_LOGIC_VECTOR(159 DOWNTO 0); | |||
|
|
68 | SIGNAL data_valid_selected : STD_LOGIC_VECTOR(3 DOWNTO 0); | |||
|
|
69 | SIGNAL data_ready_to_go : STD_LOGIC; | |||
|
|
70 | ||||
|
|
71 | SIGNAL data_temp : STD_LOGIC_VECTOR(32*4-1 DOWNTO 0); | |||
|
|
72 | SIGNAL time_en_temp : STD_LOGIC_VECTOR(3 DOWNTO 0); | |||
|
|
73 | BEGIN | |||
|
|
74 | ||||
|
|
75 | data_valid_and_ready(0) <= ready(0) AND data_f0_valid; | |||
|
|
76 | data_valid_and_ready(1) <= ready(1) AND data_f1_valid; | |||
|
|
77 | data_valid_and_ready(2) <= ready(2) AND data_f2_valid; | |||
|
|
78 | data_valid_and_ready(3) <= ready(3) AND data_f3_valid; | |||
|
|
79 | ||||
|
|
80 | data_selected <= data_f0 WHEN data_valid_and_ready(0) = '1' ELSE | |||
|
|
81 | data_f1 WHEN data_valid_and_ready(1) = '1' ELSE | |||
|
|
82 | data_f2 WHEN data_valid_and_ready(2) = '1' ELSE | |||
|
|
83 | data_f3; | |||
|
|
84 | ||||
|
|
85 | data_valid_selected <= "0001" WHEN data_valid_and_ready(0) = '1' ELSE | |||
|
|
86 | "0010" WHEN data_valid_and_ready(1) = '1' ELSE | |||
|
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87 | "0100" WHEN data_valid_and_ready(2) = '1' ELSE | |||
|
|
88 | "1000" WHEN data_valid_and_ready(3) = '1' ELSE | |||
|
|
89 | "0000"; | |||
|
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90 | ||||
|
|
91 | data_ready_to_go <= data_valid_and_ready(0) OR | |||
|
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92 | data_valid_and_ready(1) OR | |||
|
|
93 | data_valid_and_ready(2) OR | |||
|
|
94 | data_valid_and_ready(3); | |||
|
|
95 | ||||
|
|
96 | PROCESS (clk, rstn) | |||
|
|
97 | BEGIN | |||
|
|
98 | IF rstn = '0' THEN | |||
|
|
99 | state <= IDLE; | |||
|
|
100 | data_valid_ack <= (OTHERS => '0'); | |||
|
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101 | data_wen <= (OTHERS => '1'); | |||
|
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102 | time_wen <= (OTHERS => '1'); | |||
|
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103 | data <= (OTHERS => '0'); | |||
|
|
104 | data_temp <= (OTHERS => '0'); | |||
|
|
105 | time_en_temp <= (OTHERS => '0'); | |||
|
|
106 | ELSIF clk'EVENT AND clk = '1' THEN | |||
|
|
107 | CASE state IS | |||
|
|
108 | WHEN IDLE => | |||
|
|
109 | data_valid_ack <= (OTHERS => '0'); | |||
|
|
110 | time_wen <= (OTHERS => '1'); | |||
|
|
111 | data_wen <= (OTHERS => '1'); | |||
|
|
112 | data <= (OTHERS => '0'); | |||
|
|
113 | data_temp <= (OTHERS => '0'); | |||
|
|
114 | IF data_ready_to_go = '1' THEN | |||
|
|
115 | state <= T1; | |||
|
|
116 | data_valid_ack <= data_valid_selected; | |||
|
|
117 | time_wen <= NOT data_valid_selected; | |||
|
|
118 | time_en_temp <= NOT data_valid_selected; | |||
|
|
119 | data <= data_selected(31 DOWNTO 0); | |||
|
|
120 | data_temp <= data_selected(159 DOWNTO 32); | |||
|
|
121 | END IF; | |||
|
|
122 | WHEN T1 => | |||
|
|
123 | state <= T2; | |||
|
|
124 | data_valid_ack <= (OTHERS => '0'); | |||
|
|
125 | data <= data_temp(31 DOWNTO 0); | |||
|
|
126 | data_temp(32*3-1 DOWNTO 0) <= data_temp(32*4-1 DOWNTO 32); | |||
|
|
127 | ||||
|
|
128 | WHEN T2 => | |||
|
|
129 | state <= D1; | |||
|
|
130 | time_wen <= (OTHERS => '1'); | |||
|
|
131 | data_wen <= time_en_temp; | |||
|
|
132 | data <= data_temp(31 DOWNTO 0); | |||
|
|
133 | data_temp(32*3-1 DOWNTO 0) <= data_temp(32*4-1 DOWNTO 32); | |||
|
|
134 | ||||
|
|
135 | WHEN D1 => | |||
|
|
136 | state <= D2; | |||
|
|
137 | data <= data_temp(31 DOWNTO 0); | |||
|
|
138 | data_temp(32*3-1 DOWNTO 0) <= data_temp(32*4-1 DOWNTO 32); | |||
|
|
139 | ||||
|
|
140 | WHEN D2 => | |||
|
|
141 | state <= IDLE; | |||
|
|
142 | data <= data_temp(31 DOWNTO 0); | |||
|
|
143 | data_temp(32*3-1 DOWNTO 0) <= data_temp(32*4-1 DOWNTO 32); | |||
|
|
144 | ||||
|
|
145 | WHEN OTHERS => NULL; | |||
|
|
146 | END CASE; | |||
|
|
147 | ||||
|
|
148 | END IF; | |||
|
|
149 | END PROCESS; | |||
|
|
150 | ||||
|
|
151 | END ARCHITECTURE; | |||
|
|
152 | ||||
|
|
153 | ||||
|
|
154 | ||||
|
|
155 | ||||
|
|
156 | ||||
|
|
157 | ||||
|
|
158 | ||||
|
|
159 | ||||
|
|
160 | ||||
|
|
161 | ||||
|
|
162 | ||||
|
|
163 | ||||
|
|
164 | ||||
|
|
165 | ||||
|
|
166 | ||||
|
|
167 | ||||
|
|
168 | ||||
|
|
169 | ||||
|
|
170 | ||||
|
|
171 | ||||
|
|
172 | ||||
|
|
173 | ||||
|
|
174 | ||||
|
|
175 | ||||
|
|
176 | ||||
|
|
177 | ||||
| @@ -0,0 +1,171 | |||||
|
|
1 | ------------------------------------------------------------------------------ | |||
|
|
2 | -- This file is a part of the LPP VHDL IP LIBRARY | |||
|
|
3 | -- Copyright (C) 2009 - 2012, Laboratory of Plasmas Physic - CNRS | |||
|
|
4 | -- | |||
|
|
5 | -- This program is free software; you can redistribute it and/or modify | |||
|
|
6 | -- it under the terms of the GNU General Public License as published by | |||
|
|
7 | -- the Free Software Foundation; either version 3 of the License, or | |||
|
|
8 | -- (at your option) any later version. | |||
|
|
9 | -- | |||
|
|
10 | -- This program is distributed in the hope that it will be useful, | |||
|
|
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of | |||
|
|
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |||
|
|
13 | -- GNU General Public License for more details. | |||
|
|
14 | -- | |||
|
|
15 | -- You should have received a copy of the GNU General Public License | |||
|
|
16 | -- along with this program; if not, write to the Free Software | |||
|
|
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |||
|
|
18 | ------------------------------------------------------------------------------ | |||
|
|
19 | -- Author : Jean-christophe PELLION | |||
|
|
20 | -- Mail : jean-christophe.pellion@lpp.polytechnique.fr | |||
|
|
21 | ------------------------------------------------------------------------------ | |||
|
|
22 | LIBRARY IEEE; | |||
|
|
23 | USE IEEE.std_logic_1164.ALL; | |||
|
|
24 | USE IEEE.numeric_std.ALL; | |||
|
|
25 | LIBRARY lpp; | |||
|
|
26 | USE lpp.lpp_memory.ALL; | |||
|
|
27 | USE lpp.iir_filter.ALL; | |||
|
|
28 | USE lpp.lpp_waveform_pkg.ALL; | |||
|
|
29 | ||||
|
|
30 | LIBRARY techmap; | |||
|
|
31 | USE techmap.gencomp.ALL; | |||
|
|
32 | ||||
|
|
33 | ENTITY lpp_waveform_fifo_ctrl IS | |||
|
|
34 | generic( | |||
|
|
35 | offset : INTEGER := 0; | |||
|
|
36 | length : INTEGER := 20; | |||
|
|
37 | enable_ready : STD_LOGIC := '1' | |||
|
|
38 | ); | |||
|
|
39 | PORT( | |||
|
|
40 | clk : IN STD_LOGIC; | |||
|
|
41 | rstn : IN STD_LOGIC; | |||
|
|
42 | ||||
|
|
43 | ren : IN STD_LOGIC; | |||
|
|
44 | wen : IN STD_LOGIC; | |||
|
|
45 | ||||
|
|
46 | mem_re : OUT STD_LOGIC; | |||
|
|
47 | mem_we : OUT STD_LOGIC; | |||
|
|
48 | ||||
|
|
49 | mem_addr_ren : out STD_LOGIC_VECTOR(6 DOWNTO 0); | |||
|
|
50 | mem_addr_wen : out STD_LOGIC_VECTOR(6 DOWNTO 0); | |||
|
|
51 | ||||
|
|
52 | ready : OUT STD_LOGIC | |||
|
|
53 | ); | |||
|
|
54 | END ENTITY; | |||
|
|
55 | ||||
|
|
56 | ||||
|
|
57 | ARCHITECTURE ar_lpp_waveform_fifo_ctrl OF lpp_waveform_fifo_ctrl IS | |||
|
|
58 | ||||
|
|
59 | SIGNAL sFull : STD_LOGIC; | |||
|
|
60 | SIGNAL sFull_s : STD_LOGIC; | |||
|
|
61 | SIGNAL sEmpty_s : STD_LOGIC; | |||
|
|
62 | ||||
|
|
63 | SIGNAL sEmpty : STD_LOGIC; | |||
|
|
64 | SIGNAL sREN : STD_LOGIC; | |||
|
|
65 | SIGNAL sWEN : STD_LOGIC; | |||
|
|
66 | SIGNAL sRE : STD_LOGIC; | |||
|
|
67 | SIGNAL sWE : STD_LOGIC; | |||
|
|
68 | ||||
|
|
69 | SIGNAL Waddr_vect : INTEGER RANGE 0 TO length := 0; | |||
|
|
70 | SIGNAL Raddr_vect : INTEGER RANGE 0 TO length := 0; | |||
|
|
71 | SIGNAL Waddr_vect_s : INTEGER RANGE 0 TO length := 0; | |||
|
|
72 | SIGNAL Raddr_vect_s : INTEGER RANGE 0 TO length := 0; | |||
|
|
73 | ||||
|
|
74 | BEGIN | |||
|
|
75 | mem_re <= sRE; | |||
|
|
76 | mem_we <= sWE; | |||
|
|
77 | --============================= | |||
|
|
78 | -- Read section | |||
|
|
79 | --============================= | |||
|
|
80 | sREN <= REN OR sEmpty; | |||
|
|
81 | sRE <= NOT sREN; | |||
|
|
82 | ||||
|
|
83 | sEmpty_s <= '1' WHEN sEmpty = '1' AND Wen = '1' ELSE | |||
|
|
84 | '1' WHEN sEmpty = '0' AND (Wen = '1' AND Ren = '0' AND Raddr_vect_s = Waddr_vect) ELSE | |||
|
|
85 | '0'; | |||
|
|
86 | ||||
|
|
87 | Raddr_vect_s <= Raddr_vect +1 WHEN Raddr_vect < length -1 ELSE 0 ; | |||
|
|
88 | ||||
|
|
89 | PROCESS (clk, rstn) | |||
|
|
90 | BEGIN | |||
|
|
91 | IF(rstn = '0')then | |||
|
|
92 | Raddr_vect <= 0; | |||
|
|
93 | sempty <= '1'; | |||
|
|
94 | ELSIF(clk'EVENT AND clk = '1')then | |||
|
|
95 | sEmpty <= sempty_s; | |||
|
|
96 | ||||
|
|
97 | IF(sREN = '0' and sempty = '0')then | |||
|
|
98 | Raddr_vect <= Raddr_vect_s; | |||
|
|
99 | END IF; | |||
|
|
100 | ||||
|
|
101 | END IF; | |||
|
|
102 | END PROCESS; | |||
|
|
103 | ||||
|
|
104 | --============================= | |||
|
|
105 | -- Write section | |||
|
|
106 | --============================= | |||
|
|
107 | sWEN <= WEN OR sFull; | |||
|
|
108 | sWE <= NOT sWEN; | |||
|
|
109 | ||||
|
|
110 | sFull_s <= '1' WHEN Waddr_vect_s = Raddr_vect AND REN = '1' AND WEN = '0' ELSE | |||
|
|
111 | '1' WHEN sFull = '1' AND REN = '1' ELSE | |||
|
|
112 | '0'; | |||
|
|
113 | ||||
|
|
114 | Waddr_vect_s <= Waddr_vect +1 WHEN Waddr_vect < length -1 ELSE 0 ; | |||
|
|
115 | ||||
|
|
116 | PROCESS (clk, rstn) | |||
|
|
117 | BEGIN | |||
|
|
118 | IF(rstn = '0')then | |||
|
|
119 | Waddr_vect <= 0; | |||
|
|
120 | sfull <= '0'; | |||
|
|
121 | ELSIF(clk'EVENT AND clk = '1')then | |||
|
|
122 | sfull <= sfull_s; | |||
|
|
123 | ||||
|
|
124 | IF(sWEN = '0' and sfull = '0')THEN | |||
|
|
125 | Waddr_vect <= Waddr_vect_s; | |||
|
|
126 | END IF; | |||
|
|
127 | ||||
|
|
128 | END IF; | |||
|
|
129 | END PROCESS; | |||
|
|
130 | ||||
|
|
131 | ||||
|
|
132 | mem_addr_wen <= std_logic_vector(to_unsigned((Waddr_vect + offset), mem_addr_wen'length)); | |||
|
|
133 | mem_addr_ren <= std_logic_vector(to_unsigned((Raddr_vect + offset), mem_addr_ren'length)); | |||
|
|
134 | ||||
|
|
135 | ready_gen: IF enable_ready = '1' GENERATE | |||
|
|
136 | ready <= '1' WHEN Waddr_vect > Raddr_vect AND (Waddr_vect - Raddr_vect) > 15 ELSE | |||
|
|
137 | '1' WHEN Waddr_vect < Raddr_vect AND (length + Waddr_vect - Raddr_vect) > 15 ELSE | |||
|
|
138 | '0'; | |||
|
|
139 | END GENERATE ready_gen; | |||
|
|
140 | ||||
|
|
141 | ready_not_gen: IF enable_ready = '0' GENERATE | |||
|
|
142 | ready <= '0'; | |||
|
|
143 | END GENERATE ready_not_gen; | |||
|
|
144 | ||||
|
|
145 | END ARCHITECTURE; | |||
|
|
146 | ||||
|
|
147 | ||||
|
|
148 | ||||
|
|
149 | ||||
|
|
150 | ||||
|
|
151 | ||||
|
|
152 | ||||
|
|
153 | ||||
|
|
154 | ||||
|
|
155 | ||||
|
|
156 | ||||
|
|
157 | ||||
|
|
158 | ||||
|
|
159 | ||||
|
|
160 | ||||
|
|
161 | ||||
|
|
162 | ||||
|
|
163 | ||||
|
|
164 | ||||
|
|
165 | ||||
|
|
166 | ||||
|
|
167 | ||||
|
|
168 | ||||
|
|
169 | ||||
|
|
170 | ||||
|
|
171 | ||||
| @@ -0,0 +1,243 | |||||
|
|
1 | LIBRARY IEEE; | |||
|
|
2 | USE IEEE.STD_LOGIC_1164.ALL; | |||
|
|
3 | ||||
|
|
4 | LIBRARY grlib; | |||
|
|
5 | USE grlib.amba.ALL; | |||
|
|
6 | USE grlib.stdlib.ALL; | |||
|
|
7 | USE grlib.devices.ALL; | |||
|
|
8 | USE GRLIB.DMA2AHB_Package.ALL; | |||
|
|
9 | ||||
|
|
10 | LIBRARY techmap; | |||
|
|
11 | USE techmap.gencomp.ALL; | |||
|
|
12 | ||||
|
|
13 | PACKAGE lpp_waveform_pkg IS | |||
|
|
14 | ||||
|
|
15 | TYPE LPP_TYPE_ADDR_FIFO_WAVEFORM IS ARRAY (NATURAL RANGE <>) OF STD_LOGIC_VECTOR(6 DOWNTO 0); | |||
|
|
16 | ||||
|
|
17 | COMPONENT lpp_waveform_snapshot | |||
|
|
18 | GENERIC ( | |||
|
|
19 | data_size : INTEGER; | |||
|
|
20 | nb_snapshot_param_size : INTEGER); | |||
|
|
21 | PORT ( | |||
|
|
22 | clk : IN STD_LOGIC; | |||
|
|
23 | rstn : IN STD_LOGIC; | |||
|
|
24 | enable : IN STD_LOGIC; | |||
|
|
25 | burst_enable : IN STD_LOGIC; | |||
|
|
26 | nb_snapshot_param : IN STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0); | |||
|
|
27 | start_snapshot : IN STD_LOGIC; | |||
|
|
28 | data_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); | |||
|
|
29 | data_in_valid : IN STD_LOGIC; | |||
|
|
30 | data_out : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); | |||
|
|
31 | data_out_valid : OUT STD_LOGIC); | |||
|
|
32 | END COMPONENT; | |||
|
|
33 | ||||
|
|
34 | COMPONENT lpp_waveform_burst | |||
|
|
35 | GENERIC ( | |||
|
|
36 | data_size : INTEGER); | |||
|
|
37 | PORT ( | |||
|
|
38 | clk : IN STD_LOGIC; | |||
|
|
39 | rstn : IN STD_LOGIC; | |||
|
|
40 | enable : IN STD_LOGIC; | |||
|
|
41 | data_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); | |||
|
|
42 | data_in_valid : IN STD_LOGIC; | |||
|
|
43 | data_out : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); | |||
|
|
44 | data_out_valid : OUT STD_LOGIC); | |||
|
|
45 | END COMPONENT; | |||
|
|
46 | ||||
|
|
47 | COMPONENT lpp_waveform_snapshot_controler | |||
|
|
48 | GENERIC ( | |||
|
|
49 | delta_snapshot_size : INTEGER; | |||
|
|
50 | delta_f2_f0_size : INTEGER; | |||
|
|
51 | delta_f2_f1_size : INTEGER); | |||
|
|
52 | PORT ( | |||
|
|
53 | clk : IN STD_LOGIC; | |||
|
|
54 | rstn : IN STD_LOGIC; | |||
|
|
55 | delta_snapshot : IN STD_LOGIC_VECTOR(delta_snapshot_size-1 DOWNTO 0); | |||
|
|
56 | delta_f2_f1 : IN STD_LOGIC_VECTOR(delta_f2_f1_size-1 DOWNTO 0); | |||
|
|
57 | delta_f2_f0 : IN STD_LOGIC_VECTOR(delta_f2_f0_size-1 DOWNTO 0); | |||
|
|
58 | coarse_time_0 : IN STD_LOGIC; | |||
|
|
59 | data_f0_in_valid : IN STD_LOGIC; | |||
|
|
60 | data_f2_in_valid : IN STD_LOGIC; | |||
|
|
61 | start_snapshot_f0 : OUT STD_LOGIC; | |||
|
|
62 | start_snapshot_f1 : OUT STD_LOGIC; | |||
|
|
63 | start_snapshot_f2 : OUT STD_LOGIC); | |||
|
|
64 | END COMPONENT; | |||
|
|
65 | ||||
|
|
66 | ||||
|
|
67 | ||||
|
|
68 | COMPONENT lpp_waveform | |||
|
|
69 | GENERIC ( | |||
|
|
70 | hindex : INTEGER; | |||
|
|
71 | tech : INTEGER; | |||
|
|
72 | data_size : INTEGER; | |||
|
|
73 | nb_burst_available_size : INTEGER; | |||
|
|
74 | nb_snapshot_param_size : INTEGER; | |||
|
|
75 | delta_snapshot_size : INTEGER; | |||
|
|
76 | delta_f2_f0_size : INTEGER; | |||
|
|
77 | delta_f2_f1_size : INTEGER); | |||
|
|
78 | PORT ( | |||
|
|
79 | clk : IN STD_LOGIC; | |||
|
|
80 | rstn : IN STD_LOGIC; | |||
|
|
81 | AHB_Master_In : IN AHB_Mst_In_Type; | |||
|
|
82 | AHB_Master_Out : OUT AHB_Mst_Out_Type; | |||
|
|
83 | coarse_time_0 : IN STD_LOGIC; | |||
|
|
84 | delta_snapshot : IN STD_LOGIC_VECTOR(delta_snapshot_size-1 DOWNTO 0); | |||
|
|
85 | delta_f2_f1 : IN STD_LOGIC_VECTOR(delta_f2_f1_size-1 DOWNTO 0); | |||
|
|
86 | delta_f2_f0 : IN STD_LOGIC_VECTOR(delta_f2_f0_size-1 DOWNTO 0); | |||
|
|
87 | enable_f0 : IN STD_LOGIC; | |||
|
|
88 | enable_f1 : IN STD_LOGIC; | |||
|
|
89 | enable_f2 : IN STD_LOGIC; | |||
|
|
90 | enable_f3 : IN STD_LOGIC; | |||
|
|
91 | burst_f0 : IN STD_LOGIC; | |||
|
|
92 | burst_f1 : IN STD_LOGIC; | |||
|
|
93 | burst_f2 : IN STD_LOGIC; | |||
|
|
94 | nb_burst_available : IN STD_LOGIC_VECTOR(nb_burst_available_size-1 DOWNTO 0); | |||
|
|
95 | nb_snapshot_param : IN STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0); | |||
|
|
96 | status_full : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); | |||
|
|
97 | status_full_ack : IN STD_LOGIC_VECTOR(3 DOWNTO 0); | |||
|
|
98 | status_full_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); | |||
|
|
99 | status_new_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); | |||
|
|
100 | addr_data_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
|
|
101 | addr_data_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
|
|
102 | addr_data_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
|
|
103 | addr_data_f3 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
|
|
104 | data_f0_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); | |||
|
|
105 | data_f1_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); | |||
|
|
106 | data_f2_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); | |||
|
|
107 | data_f3_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); | |||
|
|
108 | data_f0_in_valid : IN STD_LOGIC; | |||
|
|
109 | data_f1_in_valid : IN STD_LOGIC; | |||
|
|
110 | data_f2_in_valid : IN STD_LOGIC; | |||
|
|
111 | data_f3_in_valid : IN STD_LOGIC); | |||
|
|
112 | END COMPONENT; | |||
|
|
113 | ||||
|
|
114 | COMPONENT lpp_waveform_dma_send_Nword | |||
|
|
115 | PORT ( | |||
|
|
116 | HCLK : IN STD_ULOGIC; | |||
|
|
117 | HRESETn : IN STD_ULOGIC; | |||
|
|
118 | DMAIn : OUT DMA_In_Type; | |||
|
|
119 | DMAOut : IN DMA_OUt_Type; | |||
|
|
120 | Nb_word_less1 : IN STD_LOGIC_VECTOR(3 DOWNTO 0); | |||
|
|
121 | send : IN STD_LOGIC; | |||
|
|
122 | address : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
|
|
123 | data : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
|
|
124 | ren : OUT STD_LOGIC; | |||
|
|
125 | send_ok : OUT STD_LOGIC; | |||
|
|
126 | send_ko : OUT STD_LOGIC); | |||
|
|
127 | END COMPONENT; | |||
|
|
128 | ||||
|
|
129 | COMPONENT lpp_waveform_dma_selectaddress | |||
|
|
130 | GENERIC ( | |||
|
|
131 | nb_burst_available_size : INTEGER); | |||
|
|
132 | PORT ( | |||
|
|
133 | HCLK : IN STD_ULOGIC; | |||
|
|
134 | HRESETn : IN STD_ULOGIC; | |||
|
|
135 | update : IN STD_LOGIC_VECTOR(1 DOWNTO 0); | |||
|
|
136 | nb_burst_available : IN STD_LOGIC_VECTOR(nb_burst_available_size-1 DOWNTO 0); | |||
|
|
137 | addr_data_reg : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
|
|
138 | addr_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
|
|
139 | status_full : OUT STD_LOGIC; | |||
|
|
140 | status_full_ack : IN STD_LOGIC; | |||
|
|
141 | status_full_err : OUT STD_LOGIC); | |||
|
|
142 | END COMPONENT; | |||
|
|
143 | ||||
|
|
144 | COMPONENT lpp_waveform_dma_gen_valid | |||
|
|
145 | PORT ( | |||
|
|
146 | HCLK : IN STD_LOGIC; | |||
|
|
147 | HRESETn : IN STD_LOGIC; | |||
|
|
148 | valid_in : IN STD_LOGIC; | |||
|
|
149 | ack_in : IN STD_LOGIC; | |||
|
|
150 | valid_out : OUT STD_LOGIC; | |||
|
|
151 | error : OUT STD_LOGIC); | |||
|
|
152 | END COMPONENT; | |||
|
|
153 | ||||
|
|
154 | COMPONENT lpp_waveform_dma | |||
|
|
155 | GENERIC ( | |||
|
|
156 | data_size : INTEGER; | |||
|
|
157 | tech : INTEGER; | |||
|
|
158 | hindex : INTEGER; | |||
|
|
159 | nb_burst_available_size : INTEGER); | |||
|
|
160 | PORT ( | |||
|
|
161 | HCLK : IN STD_ULOGIC; | |||
|
|
162 | HRESETn : IN STD_ULOGIC; | |||
|
|
163 | AHB_Master_In : IN AHB_Mst_In_Type; | |||
|
|
164 | AHB_Master_Out : OUT AHB_Mst_Out_Type; | |||
|
|
165 | data_ready : IN STD_LOGIC_VECTOR(3 DOWNTO 0); | |||
|
|
166 | data : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
|
|
167 | data_data_ren : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); | |||
|
|
168 | data_time_ren : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); | |||
|
|
169 | --data_f0_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); | |||
|
|
170 | --data_f1_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); | |||
|
|
171 | --data_f2_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); | |||
|
|
172 | --data_f3_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); | |||
|
|
173 | --data_f0_in_valid : IN STD_LOGIC; | |||
|
|
174 | --data_f1_in_valid : IN STD_LOGIC; | |||
|
|
175 | --data_f2_in_valid : IN STD_LOGIC; | |||
|
|
176 | --data_f3_in_valid : IN STD_LOGIC; | |||
|
|
177 | nb_burst_available : IN STD_LOGIC_VECTOR(nb_burst_available_size-1 DOWNTO 0); | |||
|
|
178 | status_full : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); | |||
|
|
179 | status_full_ack : IN STD_LOGIC_VECTOR(3 DOWNTO 0); | |||
|
|
180 | status_full_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); | |||
|
|
181 | -- status_new_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); | |||
|
|
182 | addr_data_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
|
|
183 | addr_data_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
|
|
184 | addr_data_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
|
|
185 | addr_data_f3 : IN STD_LOGIC_VECTOR(31 DOWNTO 0)); | |||
|
|
186 | END COMPONENT; | |||
|
|
187 | ||||
|
|
188 | COMPONENT lpp_waveform_fifo_ctrl | |||
|
|
189 | GENERIC ( | |||
|
|
190 | offset : INTEGER; | |||
|
|
191 | length : INTEGER; | |||
|
|
192 | enable_ready : STD_LOGIC); | |||
|
|
193 | PORT ( | |||
|
|
194 | clk : IN STD_LOGIC; | |||
|
|
195 | rstn : IN STD_LOGIC; | |||
|
|
196 | ren : IN STD_LOGIC; | |||
|
|
197 | wen : IN STD_LOGIC; | |||
|
|
198 | mem_re : OUT STD_LOGIC; | |||
|
|
199 | mem_we : OUT STD_LOGIC; | |||
|
|
200 | mem_addr_ren : out STD_LOGIC_VECTOR(6 DOWNTO 0); | |||
|
|
201 | mem_addr_wen : out STD_LOGIC_VECTOR(6 DOWNTO 0); | |||
|
|
202 | ready : OUT STD_LOGIC); | |||
|
|
203 | END COMPONENT; | |||
|
|
204 | ||||
|
|
205 | COMPONENT lpp_waveform_fifo_arbiter | |||
|
|
206 | GENERIC ( | |||
|
|
207 | tech : INTEGER); | |||
|
|
208 | PORT ( | |||
|
|
209 | clk : IN STD_LOGIC; | |||
|
|
210 | rstn : IN STD_LOGIC; | |||
|
|
211 | data_f0_valid : IN STD_LOGIC; | |||
|
|
212 | data_f1_valid : IN STD_LOGIC; | |||
|
|
213 | data_f2_valid : IN STD_LOGIC; | |||
|
|
214 | data_f3_valid : IN STD_LOGIC; | |||
|
|
215 | data_valid_ack : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); | |||
|
|
216 | data_f0 : IN STD_LOGIC_VECTOR(159 DOWNTO 0); | |||
|
|
217 | data_f1 : IN STD_LOGIC_VECTOR(159 DOWNTO 0); | |||
|
|
218 | data_f2 : IN STD_LOGIC_VECTOR(159 DOWNTO 0); | |||
|
|
219 | data_f3 : IN STD_LOGIC_VECTOR(159 DOWNTO 0); | |||
|
|
220 | ready : IN STD_LOGIC_VECTOR(3 DOWNTO 0); | |||
|
|
221 | time_wen : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); | |||
|
|
222 | data_wen : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); | |||
|
|
223 | data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)); | |||
|
|
224 | END COMPONENT; | |||
|
|
225 | ||||
|
|
226 | COMPONENT lpp_waveform_fifo | |||
|
|
227 | GENERIC ( | |||
|
|
228 | tech : INTEGER); | |||
|
|
229 | PORT ( | |||
|
|
230 | clk : IN STD_LOGIC; | |||
|
|
231 | rstn : IN STD_LOGIC; | |||
|
|
232 | ready : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); | |||
|
|
233 | time_ren : IN STD_LOGIC_VECTOR(3 DOWNTO 0); | |||
|
|
234 | data_ren : IN STD_LOGIC_VECTOR(3 DOWNTO 0); | |||
|
|
235 | rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
|
|
236 | time_wen : IN STD_LOGIC_VECTOR(3 DOWNTO 0); | |||
|
|
237 | data_wen : IN STD_LOGIC_VECTOR(3 DOWNTO 0); | |||
|
|
238 | wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0)); | |||
|
|
239 | END COMPONENT; | |||
|
|
240 | ||||
|
|
241 | ||||
|
|
242 | ||||
|
|
243 | END lpp_waveform_pkg; | |||
| @@ -0,0 +1,80 | |||||
|
|
1 | LIBRARY IEEE; | |||
|
|
2 | USE IEEE.STD_LOGIC_1164.ALL; | |||
|
|
3 | USE ieee.numeric_std.ALL; | |||
|
|
4 | ||||
|
|
5 | ENTITY lpp_waveform_snapshot IS | |||
|
|
6 | ||||
|
|
7 | GENERIC ( | |||
|
|
8 | data_size : INTEGER := 16; | |||
|
|
9 | nb_snapshot_param_size : INTEGER := 11); | |||
|
|
10 | ||||
|
|
11 | PORT ( | |||
|
|
12 | clk : IN STD_LOGIC; | |||
|
|
13 | rstn : IN STD_LOGIC; | |||
|
|
14 | ||||
|
|
15 | enable : IN STD_LOGIC; | |||
|
|
16 | burst_enable : IN STD_LOGIC; | |||
|
|
17 | nb_snapshot_param : IN STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0); | |||
|
|
18 | ||||
|
|
19 | start_snapshot : IN STD_LOGIC; | |||
|
|
20 | ||||
|
|
21 | data_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); | |||
|
|
22 | data_in_valid : IN STD_LOGIC; | |||
|
|
23 | ||||
|
|
24 | data_out : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); | |||
|
|
25 | data_out_valid : OUT STD_LOGIC | |||
|
|
26 | ); | |||
|
|
27 | ||||
|
|
28 | END lpp_waveform_snapshot; | |||
|
|
29 | ||||
|
|
30 | ARCHITECTURE beh OF lpp_waveform_snapshot IS | |||
|
|
31 | SIGNAL counter_points_snapshot : INTEGER; | |||
|
|
32 | BEGIN -- beh | |||
|
|
33 | ||||
|
|
34 | PROCESS (clk, rstn) | |||
|
|
35 | BEGIN | |||
|
|
36 | IF rstn = '0' THEN | |||
|
|
37 | data_out <= (OTHERS => '0'); | |||
|
|
38 | data_out_valid <= '0'; | |||
|
|
39 | counter_points_snapshot <= 0; | |||
|
|
40 | ELSIF clk'EVENT AND clk = '1' THEN | |||
|
|
41 | data_out <= data_in; | |||
|
|
42 | IF enable = '0' THEN | |||
|
|
43 | data_out_valid <= '0'; | |||
|
|
44 | counter_points_snapshot <= 0; | |||
|
|
45 | ELSE | |||
|
|
46 | IF burst_enable = '1' THEN | |||
|
|
47 | -- BURST ModE -- | |||
|
|
48 | data_out_valid <= data_in_valid; | |||
|
|
49 | counter_points_snapshot <= 0; | |||
|
|
50 | ELSE | |||
|
|
51 | -- SNAPShOT MODE -- | |||
|
|
52 | IF start_snapshot = '1' THEN | |||
|
|
53 | IF data_in_valid = '1' THEN | |||
|
|
54 | counter_points_snapshot <= to_integer(unsigned(nb_snapshot_param)) - 1; | |||
|
|
55 | data_out_valid <= '1'; | |||
|
|
56 | ELSE | |||
|
|
57 | counter_points_snapshot <= to_integer(unsigned(nb_snapshot_param)); | |||
|
|
58 | data_out_valid <= '0'; | |||
|
|
59 | END IF; | |||
|
|
60 | ELSE | |||
|
|
61 | IF data_in_valid = '1' THEN | |||
|
|
62 | IF counter_points_snapshot > 0 THEN | |||
|
|
63 | counter_points_snapshot <= counter_points_snapshot - 1; | |||
|
|
64 | data_out_valid <= '1'; | |||
|
|
65 | ELSE | |||
|
|
66 | counter_points_snapshot <= counter_points_snapshot; | |||
|
|
67 | data_out_valid <= '0'; | |||
|
|
68 | END IF; | |||
|
|
69 | ELSE | |||
|
|
70 | counter_points_snapshot <= counter_points_snapshot; | |||
|
|
71 | data_out_valid <= '0'; | |||
|
|
72 | END IF; | |||
|
|
73 | END IF; | |||
|
|
74 | ||||
|
|
75 | END IF; | |||
|
|
76 | END IF; | |||
|
|
77 | END IF; | |||
|
|
78 | END PROCESS; | |||
|
|
79 | ||||
|
|
80 | END beh; | |||
| @@ -0,0 +1,116 | |||||
|
|
1 | LIBRARY IEEE; | |||
|
|
2 | USE IEEE.STD_LOGIC_1164.ALL; | |||
|
|
3 | USE ieee.numeric_std.ALL; | |||
|
|
4 | ||||
|
|
5 | ENTITY lpp_waveform_snapshot_controler IS | |||
|
|
6 | ||||
|
|
7 | GENERIC ( | |||
|
|
8 | delta_snapshot_size : INTEGER := 16; | |||
|
|
9 | delta_f2_f0_size : INTEGER := 10; | |||
|
|
10 | delta_f2_f1_size : INTEGER := 10); | |||
|
|
11 | ||||
|
|
12 | PORT ( | |||
|
|
13 | clk : IN STD_LOGIC; | |||
|
|
14 | rstn : IN STD_LOGIC; | |||
|
|
15 | --config | |||
|
|
16 | delta_snapshot : IN STD_LOGIC_VECTOR(delta_snapshot_size-1 DOWNTO 0); | |||
|
|
17 | delta_f2_f1 : IN STD_LOGIC_VECTOR(delta_f2_f1_size-1 DOWNTO 0); | |||
|
|
18 | delta_f2_f0 : IN STD_LOGIC_VECTOR(delta_f2_f0_size-1 DOWNTO 0); | |||
|
|
19 | ||||
|
|
20 | --input | |||
|
|
21 | coarse_time_0 : IN STD_LOGIC; | |||
|
|
22 | data_f0_in_valid : IN STD_LOGIC; | |||
|
|
23 | data_f2_in_valid : IN STD_LOGIC; | |||
|
|
24 | --output | |||
|
|
25 | start_snapshot_f0 : OUT STD_LOGIC; | |||
|
|
26 | start_snapshot_f1 : OUT STD_LOGIC; | |||
|
|
27 | start_snapshot_f2 : OUT STD_LOGIC | |||
|
|
28 | ); | |||
|
|
29 | ||||
|
|
30 | END lpp_waveform_snapshot_controler; | |||
|
|
31 | ||||
|
|
32 | ARCHITECTURE beh OF lpp_waveform_snapshot_controler IS | |||
|
|
33 | SIGNAL counter_delta_snapshot : INTEGER; | |||
|
|
34 | SIGNAL counter_delta_f0 : INTEGER; | |||
|
|
35 | ||||
|
|
36 | SIGNAL coarse_time_0_r : STD_LOGIC; | |||
|
|
37 | SIGNAL start_snapshot_f2_temp : STD_LOGIC; | |||
|
|
38 | SIGNAL start_snapshot_fothers_temp : STD_LOGIC; | |||
|
|
39 | SIGNAL start_snapshot_fothers_temp2 : STD_LOGIC; | |||
|
|
40 | BEGIN -- beh | |||
|
|
41 | ||||
|
|
42 | PROCESS (clk, rstn) | |||
|
|
43 | BEGIN | |||
|
|
44 | IF rstn = '0' THEN | |||
|
|
45 | start_snapshot_f0 <= '0'; | |||
|
|
46 | start_snapshot_f1 <= '0'; | |||
|
|
47 | start_snapshot_f2 <= '0'; | |||
|
|
48 | counter_delta_snapshot <= 0; | |||
|
|
49 | counter_delta_f0 <= 0; | |||
|
|
50 | coarse_time_0_r <= '0'; | |||
|
|
51 | start_snapshot_f2_temp <= '0'; | |||
|
|
52 | start_snapshot_fothers_temp <= '0'; | |||
|
|
53 | start_snapshot_fothers_temp2 <= '0'; | |||
|
|
54 | ELSIF clk'EVENT AND clk = '1' THEN | |||
|
|
55 | IF counter_delta_snapshot = UNSIGNED(delta_snapshot) THEN | |||
|
|
56 | start_snapshot_f2_temp <= '1'; | |||
|
|
57 | ELSE | |||
|
|
58 | start_snapshot_f2_temp <= '0'; | |||
|
|
59 | END IF; | |||
|
|
60 | ------------------------------------------------------------------------- | |||
|
|
61 | IF counter_delta_snapshot = UNSIGNED(delta_snapshot) AND start_snapshot_f2_temp = '0' THEN | |||
|
|
62 | start_snapshot_f2 <= '1'; | |||
|
|
63 | ELSE | |||
|
|
64 | start_snapshot_f2 <= '0'; | |||
|
|
65 | END IF; | |||
|
|
66 | ------------------------------------------------------------------------- | |||
|
|
67 | coarse_time_0_r <= coarse_time_0; | |||
|
|
68 | IF coarse_time_0 = NOT coarse_time_0_r AND coarse_time_0 = '1' THEN | |||
|
|
69 | IF counter_delta_snapshot = 0 THEN | |||
|
|
70 | counter_delta_snapshot <= to_integer(UNSIGNED(delta_snapshot)); | |||
|
|
71 | ELSE | |||
|
|
72 | counter_delta_snapshot <= counter_delta_snapshot - 1; | |||
|
|
73 | END IF; | |||
|
|
74 | END IF; | |||
|
|
75 | ||||
|
|
76 | ||||
|
|
77 | ------------------------------------------------------------------------- | |||
|
|
78 | ||||
|
|
79 | ||||
|
|
80 | ||||
|
|
81 | IF counter_delta_f0 = UNSIGNED(delta_f2_f1) THEN | |||
|
|
82 | start_snapshot_f1 <= '1'; | |||
|
|
83 | ELSE | |||
|
|
84 | start_snapshot_f1 <= '0'; | |||
|
|
85 | END IF; | |||
|
|
86 | ||||
|
|
87 | IF counter_delta_f0 = 1 THEN --UNSIGNED(delta_f2_f0) THEN | |||
|
|
88 | start_snapshot_f0 <= '1'; | |||
|
|
89 | ELSE | |||
|
|
90 | start_snapshot_f0 <= '0'; | |||
|
|
91 | END IF; | |||
|
|
92 | ||||
|
|
93 | IF counter_delta_snapshot = UNSIGNED(delta_snapshot) | |||
|
|
94 | AND start_snapshot_f2_temp = '0' | |||
|
|
95 | THEN -- | |||
|
|
96 | start_snapshot_fothers_temp <= '1'; | |||
|
|
97 | ELSIF counter_delta_f0 > 0 THEN | |||
|
|
98 | start_snapshot_fothers_temp <= '0'; | |||
|
|
99 | END IF; | |||
|
|
100 | ||||
|
|
101 | ||||
|
|
102 | ------------------------------------------------------------------------- | |||
|
|
103 | IF (start_snapshot_fothers_temp = '1' OR (counter_delta_snapshot = UNSIGNED(delta_snapshot) AND start_snapshot_f2_temp = '0')) AND data_f2_in_valid = '1' THEN | |||
|
|
104 | --counter_delta_snapshot = UNSIGNED(delta_snapshot) AND start_snapshot_f2_temp = '0' THEN -- | |||
|
|
105 | --counter_delta_snapshot = UNSIGNED(delta_snapshot) THEN | |||
|
|
106 | counter_delta_f0 <= to_integer(UNSIGNED(delta_f2_f0)); --0; | |||
|
|
107 | ELSE | |||
|
|
108 | IF (( counter_delta_f0 > 0 ) AND ( data_f0_in_valid = '1' )) THEN --<= UNSIGNED(delta_f2_f0) THEN | |||
|
|
109 | counter_delta_f0 <= counter_delta_f0 - 1;--counter_delta_f0 + 1; | |||
|
|
110 | END IF; | |||
|
|
111 | END IF; | |||
|
|
112 | ------------------------------------------------------------------------- | |||
|
|
113 | END IF; | |||
|
|
114 | END PROCESS; | |||
|
|
115 | ||||
|
|
116 | END beh; | |||
| @@ -0,0 +1,88 | |||||
|
|
1 | ------------------------------------------------------------------------------ | |||
|
|
2 | -- This file is a part of the LPP VHDL IP LIBRARY | |||
|
|
3 | -- Copyright (C) 2009 - 2012, Laboratory of Plasmas Physic - CNRS | |||
|
|
4 | -- | |||
|
|
5 | -- This program is free software; you can redistribute it and/or modify | |||
|
|
6 | -- it under the terms of the GNU General Public License as published by | |||
|
|
7 | -- the Free Software Foundation; either version 3 of the License, or | |||
|
|
8 | -- (at your option) any later version. | |||
|
|
9 | -- | |||
|
|
10 | -- This program is distributed in the hope that it will be useful, | |||
|
|
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of | |||
|
|
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |||
|
|
13 | -- GNU General Public License for more details. | |||
|
|
14 | -- | |||
|
|
15 | -- You should have received a copy of the GNU General Public License | |||
|
|
16 | -- along with this program; if not, write to the Free Software | |||
|
|
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |||
|
|
18 | ------------------------------------------------------------------------------ | |||
|
|
19 | -- Author : Jean-christophe PELLION | |||
|
|
20 | -- Mail : jean-christophe.pellion@lpp.polytechnique.fr | |||
|
|
21 | ------------------------------------------------------------------------------ | |||
|
|
22 | LIBRARY IEEE; | |||
|
|
23 | USE IEEE.std_logic_1164.ALL; | |||
|
|
24 | USE IEEE.numeric_std.ALL; | |||
|
|
25 | ||||
|
|
26 | LIBRARY lpp; | |||
|
|
27 | USE lpp.lpp_waveform_pkg.ALL; | |||
|
|
28 | ||||
|
|
29 | ENTITY lpp_waveform_valid_ack IS | |||
|
|
30 | PORT( | |||
|
|
31 | clk : IN STD_LOGIC; | |||
|
|
32 | rstn : IN STD_LOGIC; | |||
|
|
33 | ||||
|
|
34 | data_valid_in : IN STD_LOGIC_VECTOR(3 DOWNTO 0); | |||
|
|
35 | data_valid_out : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); | |||
|
|
36 | error_valid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0) | |||
|
|
37 | ); | |||
|
|
38 | END ENTITY; | |||
|
|
39 | ||||
|
|
40 | ||||
|
|
41 | ARCHITECTURE ar_lpp_waveform_valid_ack OF lpp_waveform_valid_ack IS | |||
|
|
42 | ||||
|
|
43 | SIGNAL data_valid_temp : STD_LOGIC_VECTOR(3 DOWNTO 0); | |||
|
|
44 | ||||
|
|
45 | BEGIN | |||
|
|
46 | ||||
|
|
47 | all_input: FOR I IN 3 DOWNTO 0 GENERATE | |||
|
|
48 | ||||
|
|
49 | PROCESS (clk, rstn) | |||
|
|
50 | BEGIN | |||
|
|
51 | IF rstn = '0' THEN | |||
|
|
52 | data_valid_temp(I) <= '0'; | |||
|
|
53 | ELSIF clk'event AND clk = '1' THEN | |||
|
|
54 | data_valid_temp(I) <= data_valid_in(I); | |||
|
|
55 | data_valid_out(I) <= data_valid_in(I) AND ; | |||
|
|
56 | ||||
|
|
57 | END IF; | |||
|
|
58 | END PROCESS; | |||
|
|
59 | ||||
|
|
60 | END GENERATE all_input; | |||
|
|
61 | ||||
|
|
62 | END ARCHITECTURE; | |||
|
|
63 | ||||
|
|
64 | ||||
|
|
65 | ||||
|
|
66 | ||||
|
|
67 | ||||
|
|
68 | ||||
|
|
69 | ||||
|
|
70 | ||||
|
|
71 | ||||
|
|
72 | ||||
|
|
73 | ||||
|
|
74 | ||||
|
|
75 | ||||
|
|
76 | ||||
|
|
77 | ||||
|
|
78 | ||||
|
|
79 | ||||
|
|
80 | ||||
|
|
81 | ||||
|
|
82 | ||||
|
|
83 | ||||
|
|
84 | ||||
|
|
85 | ||||
|
|
86 | ||||
|
|
87 | ||||
|
|
88 | ||||
| @@ -0,0 +1,9 | |||||
|
|
1 | lpp_waveform_pkg.vhd | |||
|
|
2 | lpp_waveform.vhd | |||
|
|
3 | lpp_waveform_snapshot_controler.vhd | |||
|
|
4 | lpp_waveform_snapshot.vhd | |||
|
|
5 | lpp_waveform_burst.vhd | |||
|
|
6 | lpp_waveform_dma.vhd | |||
|
|
7 | lpp_waveform_dma_send_Nword.vhd | |||
|
|
8 | lpp_waveform_dma_selectaddress.vhd | |||
|
|
9 | lpp_waveform_dma_genvalid.vhd | |||
| @@ -1,8 +1,19 | |||||
| 1 | LIBRARY ieee; |
|
1 | LIBRARY ieee; | |
| 2 | USE ieee.std_logic_1164.ALL; |
|
2 | USE ieee.std_logic_1164.ALL; | |
|
|
3 | ||||
| 3 | LIBRARY lpp; |
|
4 | LIBRARY lpp; | |
| 4 | USE lpp.lpp_ad_conv.ALL; |
|
5 | USE lpp.lpp_ad_conv.ALL; | |
| 5 | USE lpp.lpp_top_lfr_pkg.ALL; |
|
6 | USE lpp.lpp_top_lfr_pkg.ALL; | |
|
|
7 | USE lpp.lpp_waveform_pkg.ALL; | |||
|
|
8 | ||||
|
|
9 | LIBRARY grlib; | |||
|
|
10 | USE grlib.amba.ALL; | |||
|
|
11 | USE grlib.stdlib.ALL; | |||
|
|
12 | USE grlib.devices.ALL; | |||
|
|
13 | USE GRLIB.DMA2AHB_Package.ALL; | |||
|
|
14 | ||||
|
|
15 | LIBRARY techmap; | |||
|
|
16 | USE techmap.gencomp.ALL; | |||
| 6 |
|
17 | |||
| 7 | ------------------------------------------------------------------------------- |
|
18 | ------------------------------------------------------------------------------- | |
| 8 |
|
19 | |||
| @@ -25,6 +36,57 ARCHITECTURE tb OF TB_Data_Acquisition I | |||||
| 25 | sck : IN STD_LOGIC; |
|
36 | sck : IN STD_LOGIC; | |
| 26 | sdo : OUT STD_LOGIC); |
|
37 | sdo : OUT STD_LOGIC); | |
| 27 | END COMPONENT; |
|
38 | END COMPONENT; | |
|
|
39 | ||||
|
|
40 | COMPONENT Top_Data_Acquisition | |||
|
|
41 | GENERIC ( | |||
|
|
42 | hindex : INTEGER; | |||
|
|
43 | nb_burst_available_size : INTEGER := 11; | |||
|
|
44 | nb_snapshot_param_size : INTEGER := 11; | |||
|
|
45 | delta_snapshot_size : INTEGER := 16; | |||
|
|
46 | delta_f2_f0_size : INTEGER := 10; | |||
|
|
47 | delta_f2_f1_size : INTEGER := 10; | |||
|
|
48 | tech : integer); | |||
|
|
49 | PORT ( | |||
|
|
50 | cnv_run : IN STD_LOGIC; | |||
|
|
51 | cnv : OUT STD_LOGIC; | |||
|
|
52 | sck : OUT STD_LOGIC; | |||
|
|
53 | sdo : IN STD_LOGIC_VECTOR(7 DOWNTO 0); | |||
|
|
54 | cnv_clk : IN STD_LOGIC; | |||
|
|
55 | cnv_rstn : IN STD_LOGIC; | |||
|
|
56 | clk : IN STD_LOGIC; | |||
|
|
57 | rstn : IN STD_LOGIC; | |||
|
|
58 | sample_f0_wen : out STD_LOGIC_VECTOR(5 DOWNTO 0); | |||
|
|
59 | sample_f0_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); | |||
|
|
60 | sample_f1_wen : out STD_LOGIC_VECTOR(5 DOWNTO 0); | |||
|
|
61 | sample_f1_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); | |||
|
|
62 | sample_f2_wen : out STD_LOGIC_VECTOR(5 DOWNTO 0); | |||
|
|
63 | sample_f2_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); | |||
|
|
64 | sample_f3_wen : out STD_LOGIC_VECTOR(5 DOWNTO 0); | |||
|
|
65 | sample_f3_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); | |||
|
|
66 | AHB_Master_In : IN AHB_Mst_In_Type; | |||
|
|
67 | AHB_Master_Out : OUT AHB_Mst_Out_Type; | |||
|
|
68 | coarse_time_0 : IN STD_LOGIC; | |||
|
|
69 | delta_snapshot : IN STD_LOGIC_VECTOR(delta_snapshot_size-1 DOWNTO 0); | |||
|
|
70 | delta_f2_f1 : IN STD_LOGIC_VECTOR(delta_f2_f1_size-1 DOWNTO 0); | |||
|
|
71 | delta_f2_f0 : IN STD_LOGIC_VECTOR(delta_f2_f0_size-1 DOWNTO 0); | |||
|
|
72 | enable_f0 : IN STD_LOGIC; | |||
|
|
73 | enable_f1 : IN STD_LOGIC; | |||
|
|
74 | enable_f2 : IN STD_LOGIC; | |||
|
|
75 | enable_f3 : IN STD_LOGIC; | |||
|
|
76 | burst_f0 : IN STD_LOGIC; | |||
|
|
77 | burst_f1 : IN STD_LOGIC; | |||
|
|
78 | burst_f2 : IN STD_LOGIC; | |||
|
|
79 | nb_burst_available : IN STD_LOGIC_VECTOR(nb_burst_available_size-1 DOWNTO 0); | |||
|
|
80 | nb_snapshot_param : IN STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0); | |||
|
|
81 | status_full : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); | |||
|
|
82 | status_full_ack : IN STD_LOGIC_VECTOR(3 DOWNTO 0); | |||
|
|
83 | status_full_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); | |||
|
|
84 | status_new_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); | |||
|
|
85 | addr_data_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
|
|
86 | addr_data_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
|
|
87 | addr_data_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
|
|
88 | addr_data_f3 : IN STD_LOGIC_VECTOR(31 DOWNTO 0)); | |||
|
|
89 | END COMPONENT; | |||
| 28 |
|
90 | |||
| 29 | -- component ports |
|
91 | -- component ports | |
| 30 | SIGNAL cnv_rstn : STD_LOGIC; |
|
92 | SIGNAL cnv_rstn : STD_LOGIC; | |
| @@ -40,17 +102,57 ARCHITECTURE tb OF TB_Data_Acquisition I | |||||
| 40 | SIGNAL cnv_clk : STD_LOGIC := '1'; |
|
102 | SIGNAL cnv_clk : STD_LOGIC := '1'; | |
| 41 |
|
103 | |||
| 42 | ----------------------------------------------------------------------------- |
|
104 | ----------------------------------------------------------------------------- | |
| 43 |
SIGNAL sample_f0_wen : STD_LOGIC_VECTOR( |
|
105 | SIGNAL sample_f0_wen : STD_LOGIC_VECTOR(5 DOWNTO 0); | |
| 44 |
SIGNAL sample_f0_wdata : STD_LOGIC_VECTOR(( |
|
106 | SIGNAL sample_f0_wdata : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); | |
|
|
107 | ----------------------------------------------------------------------------- | |||
|
|
108 | SIGNAL sample_f1_wen : STD_LOGIC_VECTOR(5 DOWNTO 0); | |||
|
|
109 | SIGNAL sample_f1_wdata : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); | |||
| 45 | ----------------------------------------------------------------------------- |
|
110 | ----------------------------------------------------------------------------- | |
| 46 |
SIGNAL sample_f |
|
111 | SIGNAL sample_f2_wen : STD_LOGIC_VECTOR(5 DOWNTO 0); | |
| 47 |
SIGNAL sample_f |
|
112 | SIGNAL sample_f2_wdata : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); | |
|
|
113 | ----------------------------------------------------------------------------- | |||
|
|
114 | SIGNAL sample_f3_wen : STD_LOGIC_VECTOR(5 DOWNTO 0); | |||
|
|
115 | SIGNAL sample_f3_wdata : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); | |||
|
|
116 | ||||
| 48 | ----------------------------------------------------------------------------- |
|
117 | ----------------------------------------------------------------------------- | |
| 49 | SIGNAL sample_f2_wen : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
118 | CONSTANT nb_burst_available_size : INTEGER := 11; | |
| 50 | SIGNAL sample_f2_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); |
|
119 | CONSTANT nb_snapshot_param_size : INTEGER := 11; | |
| 51 | ----------------------------------------------------------------------------- |
|
120 | CONSTANT delta_snapshot_size : INTEGER := 16; | |
| 52 | SIGNAL sample_f3_wen : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
121 | CONSTANT delta_f2_f0_size : INTEGER := 10; | |
| 53 | SIGNAL sample_f3_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); |
|
122 | CONSTANT delta_f2_f1_size : INTEGER := 10; | |
|
|
123 | ||||
|
|
124 | SIGNAL AHB_Master_In : AHB_Mst_In_Type; | |||
|
|
125 | SIGNAL AHB_Master_Out : AHB_Mst_Out_Type; | |||
|
|
126 | ||||
|
|
127 | SIGNAL coarse_time_0 : STD_LOGIC; | |||
|
|
128 | SIGNAL coarse_time_0_t : STD_LOGIC := '0'; | |||
|
|
129 | SIGNAL coarse_time_0_t2 : STD_LOGIC := '0'; | |||
|
|
130 | ||||
|
|
131 | SIGNAL delta_snapshot : STD_LOGIC_VECTOR(delta_snapshot_size-1 DOWNTO 0); | |||
|
|
132 | SIGNAL delta_f2_f1 : STD_LOGIC_VECTOR(delta_f2_f1_size-1 DOWNTO 0); | |||
|
|
133 | SIGNAL delta_f2_f0 : STD_LOGIC_VECTOR(delta_f2_f0_size-1 DOWNTO 0); | |||
|
|
134 | ||||
|
|
135 | SIGNAL enable_f0 : STD_LOGIC; | |||
|
|
136 | SIGNAL enable_f1 : STD_LOGIC; | |||
|
|
137 | SIGNAL enable_f2 : STD_LOGIC; | |||
|
|
138 | SIGNAL enable_f3 : STD_LOGIC; | |||
|
|
139 | ||||
|
|
140 | SIGNAL burst_f0 : STD_LOGIC; | |||
|
|
141 | SIGNAL burst_f1 : STD_LOGIC; | |||
|
|
142 | SIGNAL burst_f2 : STD_LOGIC; | |||
|
|
143 | ||||
|
|
144 | SIGNAL nb_burst_available : STD_LOGIC_VECTOR(nb_burst_available_size-1 DOWNTO 0); | |||
|
|
145 | SIGNAL nb_snapshot_param : STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0); | |||
|
|
146 | ||||
|
|
147 | SIGNAL status_full : STD_LOGIC_VECTOR(3 DOWNTO 0); | |||
|
|
148 | SIGNAL status_full_ack : STD_LOGIC_VECTOR(3 DOWNTO 0); | |||
|
|
149 | SIGNAL status_full_err : STD_LOGIC_VECTOR(3 DOWNTO 0); | |||
|
|
150 | SIGNAL status_new_err : STD_LOGIC_VECTOR(3 DOWNTO 0); | |||
|
|
151 | ||||
|
|
152 | SIGNAL addr_data_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
|
|
153 | SIGNAL addr_data_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
|
|
154 | SIGNAL addr_data_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
|
|
155 | SIGNAL addr_data_f3 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
| 54 |
|
156 | |||
| 55 | BEGIN -- tb |
|
157 | BEGIN -- tb | |
| 56 |
|
158 | |||
| @@ -108,33 +210,119 BEGIN -- tb | |||||
| 108 | end process WaveGen_Proc; |
|
210 | end process WaveGen_Proc; | |
| 109 |
|
211 | |||
| 110 | ----------------------------------------------------------------------------- |
|
212 | ----------------------------------------------------------------------------- | |
| 111 |
|
213 | |||
| 112 |
Top_Data_Acquisition_ |
|
214 | Top_Data_Acquisition_2: Top_Data_Acquisition | |
|
|
215 | GENERIC MAP ( | |||
|
|
216 | hindex => 2, | |||
|
|
217 | nb_burst_available_size => nb_burst_available_size, | |||
|
|
218 | nb_snapshot_param_size => nb_snapshot_param_size, | |||
|
|
219 | tech => 0) | |||
| 113 | PORT MAP ( |
|
220 | PORT MAP ( | |
| 114 | cnv_run => run_cnv, |
|
221 | cnv_run => run_cnv, | |
| 115 | cnv => cnv, |
|
222 | cnv => cnv, | |
| 116 | sck => sck, |
|
223 | sck => sck, | |
| 117 | sdo => sdo, |
|
224 | sdo => sdo, | |
| 118 | cnv_clk => cnv_clk, |
|
225 | cnv_clk => cnv_clk, | |
| 119 | cnv_rstn => cnv_rstn, |
|
226 | cnv_rstn => cnv_rstn, | |
| 120 | clk => clk, |
|
227 | clk => clk, | |
| 121 | rstn => rstn, |
|
228 | rstn => rstn, | |
| 122 | -- |
|
229 | sample_f0_wen => sample_f0_wen, | |
| 123 |
sample_f0_w |
|
230 | sample_f0_wdata => sample_f0_wdata, | |
| 124 |
sample_f |
|
231 | sample_f1_wen => sample_f1_wen, | |
| 125 | -- |
|
232 | sample_f1_wdata => sample_f1_wdata, | |
| 126 |
sample_f |
|
233 | sample_f2_wen => sample_f2_wen, | |
| 127 |
sample_f |
|
234 | sample_f2_wdata => sample_f2_wdata, | |
| 128 | -- |
|
235 | sample_f3_wen => sample_f3_wen, | |
| 129 |
sample_f |
|
236 | sample_f3_wdata => sample_f3_wdata, | |
| 130 | sample_f2_wdata => sample_f2_wdata, |
|
237 | AHB_Master_In => AHB_Master_In, | |
| 131 | -- |
|
238 | AHB_Master_Out => AHB_Master_Out, | |
| 132 | sample_f3_wen => sample_f3_wen, |
|
239 | coarse_time_0 => coarse_time_0, | |
| 133 | sample_f3_wdata => sample_f3_wdata |
|
240 | delta_snapshot => delta_snapshot, | |
| 134 | ); |
|
241 | delta_f2_f1 => delta_f2_f1, | |
|
|
242 | delta_f2_f0 => delta_f2_f0, | |||
|
|
243 | enable_f0 => enable_f0, | |||
|
|
244 | enable_f1 => enable_f1, | |||
|
|
245 | enable_f2 => enable_f2, | |||
|
|
246 | enable_f3 => enable_f3, | |||
|
|
247 | burst_f0 => burst_f0, | |||
|
|
248 | burst_f1 => burst_f1, | |||
|
|
249 | burst_f2 => burst_f2, | |||
|
|
250 | nb_burst_available => nb_burst_available, | |||
|
|
251 | nb_snapshot_param => nb_snapshot_param, | |||
|
|
252 | status_full => status_full, | |||
|
|
253 | status_full_ack => status_full_ack, | |||
|
|
254 | status_full_err => status_full_err, | |||
|
|
255 | status_new_err => status_new_err, | |||
|
|
256 | addr_data_f0 => addr_data_f0, | |||
|
|
257 | addr_data_f1 => addr_data_f1, | |||
|
|
258 | addr_data_f2 => addr_data_f2, | |||
|
|
259 | addr_data_f3 => addr_data_f3); | |||
|
|
260 | ||||
|
|
261 | PROCESS (clk, rstn) | |||
|
|
262 | BEGIN -- PROCESS | |||
|
|
263 | IF rstn = '0' THEN -- asynchronous reset (active low) | |||
|
|
264 | enable_f0 <= '0'; | |||
|
|
265 | enable_f1 <= '0'; | |||
|
|
266 | enable_f2 <= '0'; | |||
|
|
267 | enable_f3 <= '0'; | |||
|
|
268 | ELSIF clk'event AND clk = '1' THEN -- rising clock edge | |||
|
|
269 | enable_f0 <= '1'; --TODO test | |||
|
|
270 | enable_f1 <= '1'; | |||
|
|
271 | enable_f2 <= '1'; | |||
|
|
272 | enable_f3 <= '1'; | |||
|
|
273 | END IF; | |||
|
|
274 | END PROCESS; | |||
|
|
275 | ||||
|
|
276 | burst_f0 <= '0'; --TODO test | |||
|
|
277 | burst_f1 <= '0'; --TODO test | |||
|
|
278 | burst_f2 <= '0'; | |||
|
|
279 | ||||
|
|
280 | ||||
|
|
281 | delta_snapshot <= "0000000000000001"; | |||
|
|
282 | --nb_snapshot_param <= "00000001110"; -- 14+1 = 15 | |||
|
|
283 | --delta_f2_f0 <= "1010011001";--665 = 14/2*96 -14/2 | |||
|
|
284 | --delta_f2_f1 <= "0000100110";-- 38 = 14/2*6 - 14/4 | |||
|
|
285 | ||||
|
|
286 | -- A redefinir car ca ne tombe pas correctement ... ??? | |||
|
|
287 | nb_burst_available <= "00000110010"; -- 3*16 + 2 = 34 | |||
|
|
288 | nb_snapshot_param <= "00000001111"; -- x+1 = 16 | |||
|
|
289 | delta_f2_f0 <= "1011001000";--712 = x/2*96 -x/2 | |||
|
|
290 | delta_f2_f1 <= "0000101001";-- 41 = x/2*6 - x/4 | |||
|
|
291 | ||||
|
|
292 | addr_data_f0 <= "00000000000000000000000000000000"; | |||
|
|
293 | addr_data_f1 <= "00010000000000000000000000000000"; | |||
|
|
294 | addr_data_f2 <= "00100000000000000000000000000000"; | |||
|
|
295 | addr_data_f3 <= "00110000000000000000000000000000"; | |||
|
|
296 | ||||
|
|
297 | PROCESS (clk, rstn) | |||
|
|
298 | BEGIN -- PROCESS | |||
|
|
299 | IF rstn = '0' THEN -- asynchronous reset (active low) | |||
|
|
300 | status_full_ack <= (OTHERS => '0'); | |||
|
|
301 | ELSIF clk'event AND clk = '1' THEN -- rising clock edge | |||
|
|
302 | status_full_ack <= status_full; | |||
|
|
303 | END IF; | |||
|
|
304 | END PROCESS; | |||
|
|
305 | ||||
|
|
306 | ||||
|
|
307 | coarse_time_0_t <= not coarse_time_0_t after 50 ms; | |||
|
|
308 | ||||
|
|
309 | PROCESS (clk, rstn) | |||
|
|
310 | BEGIN -- PROCESS | |||
|
|
311 | IF rstn = '0' THEN -- asynchronous reset (active low) | |||
|
|
312 | coarse_time_0_t2 <= '0'; | |||
|
|
313 | coarse_time_0 <= '0'; | |||
|
|
314 | ELSIF clk'event AND clk = '1' THEN -- rising clock edge | |||
|
|
315 | coarse_time_0_t2 <= coarse_time_0_t; | |||
|
|
316 | coarse_time_0 <= coarse_time_0_t AND (NOT coarse_time_0_t2); | |||
|
|
317 | END IF; | |||
|
|
318 | END PROCESS; | |||
|
|
319 | ||||
|
|
320 | ||||
|
|
321 | AHB_Master_In.HGRANT(2) <= '1'; | |||
|
|
322 | AHB_Master_In.HREADY <= '1'; | |||
| 135 |
|
323 | |||
| 136 |
|
324 | |||
| 137 |
|
325 | AHB_Master_In.HRESP <= HRESP_OKAY; | ||
| 138 |
|
326 | |||
| 139 |
|
327 | |||
| 140 | END tb; |
|
328 | END tb; | |
| This diff has been collapsed as it changes many lines, (526 lines changed) Show them Hide them | |||||
| @@ -1,50 +1,88 | |||||
| 1 | LIBRARY ieee; |
|
1 | LIBRARY ieee; | |
| 2 | USE ieee.std_logic_1164.ALL; |
|
2 | USE ieee.std_logic_1164.ALL; | |
|
|
3 | ||||
| 3 | LIBRARY lpp; |
|
4 | LIBRARY lpp; | |
| 4 | USE lpp.lpp_ad_conv.ALL; |
|
5 | USE lpp.lpp_ad_conv.ALL; | |
| 5 | USE lpp.iir_filter.ALL; |
|
6 | USE lpp.iir_filter.ALL; | |
| 6 | USE lpp.FILTERcfg.ALL; |
|
7 | USE lpp.FILTERcfg.ALL; | |
| 7 | USE lpp.lpp_memory.ALL; |
|
8 | USE lpp.lpp_memory.ALL; | |
|
|
9 | USE lpp.lpp_waveform_pkg.ALL; | |||
|
|
10 | ||||
| 8 | LIBRARY techmap; |
|
11 | LIBRARY techmap; | |
| 9 | USE techmap.gencomp.ALL; |
|
12 | USE techmap.gencomp.ALL; | |
| 10 | --USE lpp.ALL; |
|
13 | ||
|
|
14 | LIBRARY grlib; | |||
|
|
15 | USE grlib.amba.ALL; | |||
|
|
16 | USE grlib.stdlib.ALL; | |||
|
|
17 | USE grlib.devices.ALL; | |||
|
|
18 | USE GRLIB.DMA2AHB_Package.ALL; | |||
| 11 |
|
19 | |||
| 12 | ENTITY Top_Data_Acquisition IS |
|
20 | ENTITY Top_Data_Acquisition IS | |
| 13 | generic( |
|
21 | GENERIC( | |
| 14 | tech : integer := 0 |
|
22 | hindex : INTEGER := 2; | |
|
|
23 | nb_burst_available_size : INTEGER := 11; | |||
|
|
24 | nb_snapshot_param_size : INTEGER := 11; | |||
|
|
25 | delta_snapshot_size : INTEGER := 16; | |||
|
|
26 | delta_f2_f0_size : INTEGER := 10; | |||
|
|
27 | delta_f2_f1_size : INTEGER := 10; | |||
|
|
28 | tech : INTEGER := 0 | |||
| 15 | ); |
|
29 | ); | |
| 16 | PORT ( |
|
30 | PORT ( | |
| 17 | -- ADS7886 |
|
31 | -- ADS7886 | |
| 18 | cnv_run : IN STD_LOGIC; |
|
32 | cnv_run : IN STD_LOGIC; | |
| 19 | cnv : OUT STD_LOGIC; |
|
33 | cnv : OUT STD_LOGIC; | |
| 20 | sck : OUT STD_LOGIC; |
|
34 | sck : OUT STD_LOGIC; | |
| 21 | sdo : IN STD_LOGIC_VECTOR(7 DOWNTO 0); |
|
35 | sdo : IN STD_LOGIC_VECTOR(7 DOWNTO 0); | |
|
|
36 | -- | |||
|
|
37 | cnv_clk : IN STD_LOGIC; | |||
|
|
38 | cnv_rstn : IN STD_LOGIC; | |||
| 22 | -- |
|
39 | -- | |
| 23 |
|
|
40 | clk : IN STD_LOGIC; | |
| 24 |
|
|
41 | rstn : IN STD_LOGIC; | |
|
|
42 | -- | |||
|
|
43 | sample_f0_wen : OUT STD_LOGIC_VECTOR(5 DOWNTO 0); | |||
|
|
44 | sample_f0_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); | |||
| 25 | -- |
|
45 | -- | |
| 26 | clk : IN STD_LOGIC; |
|
46 | sample_f1_wen : OUT STD_LOGIC_VECTOR(5 DOWNTO 0); | |
| 27 | rstn : IN STD_LOGIC; |
|
47 | sample_f1_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); | |
|
|
48 | -- | |||
|
|
49 | sample_f2_wen : OUT STD_LOGIC_VECTOR(5 DOWNTO 0); | |||
|
|
50 | sample_f2_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); | |||
| 28 | -- |
|
51 | -- | |
| 29 |
sample_f |
|
52 | sample_f3_wen : OUT STD_LOGIC_VECTOR(5 DOWNTO 0); | |
| 30 |
sample_f |
|
53 | sample_f3_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); | |
| 31 | sample_f0_0_full : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
54 | ||
| 32 | sample_f0_0_empty : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
55 | -- AMBA AHB Master Interface | |
| 33 | -- |
|
56 | AHB_Master_In : IN AHB_Mst_In_Type; | |
| 34 | sample_f0_1_ren : IN STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
57 | AHB_Master_Out : OUT AHB_Mst_Out_Type; | |
| 35 | sample_f0_1_rdata : OUT STD_LOGIC_VECTOR((5*18)-1 DOWNTO 0); |
|
58 | ||
| 36 | sample_f0_1_full : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
59 | coarse_time_0 : IN STD_LOGIC; | |
| 37 | sample_f0_1_empty : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
60 | ||
| 38 | -- |
|
61 | --config | |
| 39 |
|
|
62 | delta_snapshot : IN STD_LOGIC_VECTOR(delta_snapshot_size-1 DOWNTO 0); | |
| 40 |
|
|
63 | delta_f2_f1 : IN STD_LOGIC_VECTOR(delta_f2_f1_size-1 DOWNTO 0); | |
| 41 |
|
|
64 | delta_f2_f0 : IN STD_LOGIC_VECTOR(delta_f2_f0_size-1 DOWNTO 0); | |
| 42 | sample_f1_empty : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
65 | ||
| 43 | -- |
|
66 | enable_f0 : IN STD_LOGIC; | |
| 44 | sample_f3_ren : IN STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
67 | enable_f1 : IN STD_LOGIC; | |
| 45 | sample_f3_rdata : OUT STD_LOGIC_VECTOR((5*18)-1 DOWNTO 0); |
|
68 | enable_f2 : IN STD_LOGIC; | |
| 46 | sample_f3_full : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
69 | enable_f3 : IN STD_LOGIC; | |
| 47 | sample_f3_empty : OUT STD_LOGIC_VECTOR(4 DOWNTO 0) |
|
70 | ||
|
|
71 | burst_f0 : IN STD_LOGIC; | |||
|
|
72 | burst_f1 : IN STD_LOGIC; | |||
|
|
73 | burst_f2 : IN STD_LOGIC; | |||
|
|
74 | ||||
|
|
75 | nb_burst_available : IN STD_LOGIC_VECTOR(nb_burst_available_size-1 DOWNTO 0); | |||
|
|
76 | nb_snapshot_param : IN STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0); | |||
|
|
77 | status_full : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); | |||
|
|
78 | status_full_ack : IN STD_LOGIC_VECTOR(3 DOWNTO 0); | |||
|
|
79 | status_full_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); | |||
|
|
80 | status_new_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); -- New data f(i) before the current data is write by dma | |||
|
|
81 | ||||
|
|
82 | addr_data_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
|
|
83 | addr_data_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
|
|
84 | addr_data_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
|
|
85 | addr_data_f3 : IN STD_LOGIC_VECTOR(31 DOWNTO 0) | |||
| 48 | ); |
|
86 | ); | |
| 49 | END Top_Data_Acquisition; |
|
87 | END Top_Data_Acquisition; | |
| 50 |
|
88 | |||
| @@ -79,49 +117,43 ARCHITECTURE tb OF Top_Data_Acquisition | |||||
| 79 | CONSTANT CoefPerCel : INTEGER := 5; |
|
117 | CONSTANT CoefPerCel : INTEGER := 5; | |
| 80 | CONSTANT Cels_count : INTEGER := 5; |
|
118 | CONSTANT Cels_count : INTEGER := 5; | |
| 81 |
|
119 | |||
| 82 |
SIGNAL coefs |
|
120 | SIGNAL coefs : STD_LOGIC_VECTOR((Coef_SZ*CoefCntPerCel*Cels_count)-1 DOWNTO 0); | |
| 83 |
SIGNAL coefs_ |
|
121 | SIGNAL coefs_v2 : STD_LOGIC_VECTOR((Coef_SZ*CoefPerCel*Cels_count)-1 DOWNTO 0); | |
| 84 |
SIGNAL sample_filter_in |
|
122 | SIGNAL sample_filter_in : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0); | |
| 85 |
SIGNAL sample_filter_out |
|
123 | SIGNAL sample_filter_out : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0); | |
| 86 | -- |
|
124 | -- | |
| 87 |
SIGNAL sample_filter_ |
|
125 | SIGNAL sample_filter_v2_out_val : STD_LOGIC; | |
| 88 |
SIGNAL sample_filter_ |
|
126 | SIGNAL sample_filter_v2_out : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0); | |
|
|
127 | SIGNAL sample_filter_v2_out_s : samplT(5 DOWNTO 0, 15 DOWNTO 0); | |||
|
|
128 | ----------------------------------------------------------------------------- | |||
|
|
129 | SIGNAL sample_f0_val : STD_LOGIC; | |||
|
|
130 | SIGNAL sample_f0 : samplT(5 DOWNTO 0, 15 DOWNTO 0); | |||
| 89 | -- |
|
131 | -- | |
| 90 |
SIGNAL sample_f |
|
132 | SIGNAL sample_f1_val : STD_LOGIC; | |
| 91 |
SIGNAL sample_f |
|
133 | SIGNAL sample_f1 : samplT(5 DOWNTO 0, 15 DOWNTO 0); | |
| 92 | ----------------------------------------------------------------------------- |
|
|||
| 93 | SIGNAL downsampling_cnt : STD_LOGIC_VECTOR(1 DOWNTO 0); |
|
|||
| 94 | SIGNAL sample_downsampling_out_val : STD_LOGIC; |
|
|||
| 95 | SIGNAL sample_downsampling_out : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0); |
|
|||
| 96 | -- |
|
134 | -- | |
| 97 |
SIGNAL sample_f |
|
135 | SIGNAL sample_f2_val : STD_LOGIC; | |
| 98 |
SIGNAL sample_f |
|
136 | SIGNAL sample_f2 : samplT(5 DOWNTO 0, 15 DOWNTO 0); | |
| 99 | SIGNAL sample_f0_0_wen : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
137 | -- | |
| 100 |
SIGNAL sample_f |
|
138 | SIGNAL sample_f3_val : STD_LOGIC; | |
| 101 |
SIGNAL sample_f |
|
139 | SIGNAL sample_f3 : samplT(5 DOWNTO 0, 15 DOWNTO 0); | |
| 102 | -- |
|
140 | ||
| 103 | SIGNAL sample_f0_0_val : STD_LOGIC; |
|
|||
| 104 | SIGNAL sample_f0_1_val : STD_LOGIC; |
|
|||
| 105 | SIGNAL counter_f0 : INTEGER; |
|
|||
| 106 | ----------------------------------------------------------------------------- |
|
141 | ----------------------------------------------------------------------------- | |
| 107 | SIGNAL sample_f1_val : STD_LOGIC; |
|
142 | SIGNAL data_f0_in_valid : STD_LOGIC_VECTOR(159 DOWNTO 0) := (OTHERS => '0'); | |
| 108 | SIGNAL sample_f1 : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0); |
|
143 | SIGNAL data_f1_in_valid : STD_LOGIC_VECTOR(159 DOWNTO 0) := (OTHERS => '0'); | |
| 109 |
SIGNAL |
|
144 | SIGNAL data_f2_in_valid : STD_LOGIC_VECTOR(159 DOWNTO 0) := (OTHERS => '0'); | |
| 110 | SIGNAL sample_f1_wdata : STD_LOGIC_VECTOR((5*18)-1 DOWNTO 0); |
|
145 | SIGNAL data_f3_in_valid : STD_LOGIC_VECTOR(159 DOWNTO 0) := (OTHERS => '0'); | |
| 111 | -- |
|
146 | ----------------------------------------------------------------------------- | |
| 112 | SIGNAL sample_f2_val : STD_LOGIC; |
|
|||
| 113 | SIGNAL sample_f2 : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0); |
|
|||
| 114 | -- |
|
|||
| 115 | SIGNAL sample_f3_val : STD_LOGIC; |
|
|||
| 116 | SIGNAL sample_f3 : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0); |
|
|||
| 117 | SIGNAL sample_f3_wen : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
|||
| 118 | SIGNAL sample_f3_wdata : STD_LOGIC_VECTOR((5*18)-1 DOWNTO 0); |
|
|||
| 119 |
|
147 | |||
|
|
148 | SIGNAL sample_f0_wdata_s : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); | |||
|
|
149 | SIGNAL sample_f1_wdata_s : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); | |||
|
|
150 | SIGNAL sample_f2_wdata_s : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); | |||
|
|
151 | SIGNAL sample_f3_wdata_s : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); | |||
| 120 | BEGIN |
|
152 | BEGIN | |
| 121 |
|
153 | |||
| 122 | -- component instantiation |
|
154 | -- component instantiation | |
| 123 | ----------------------------------------------------------------------------- |
|
155 | ----------------------------------------------------------------------------- | |
| 124 |
DIGITAL_acquisition : AD |
|
156 | DIGITAL_acquisition : AD7688_drvr | |
| 125 | GENERIC MAP ( |
|
157 | GENERIC MAP ( | |
| 126 | ChanelCount => ChanelCount, |
|
158 | ChanelCount => ChanelCount, | |
| 127 | ncycle_cnv_high => ncycle_cnv_high, |
|
159 | ncycle_cnv_high => ncycle_cnv_high, | |
| @@ -159,166 +191,75 BEGIN | |||||
| 159 | sample_filter_in(i, 17) <= sample(i)(15); |
|
191 | sample_filter_in(i, 17) <= sample(i)(15); | |
| 160 | END GENERATE; |
|
192 | END GENERATE; | |
| 161 |
|
193 | |||
| 162 |
--coefs |
|
194 | --coefs_v2 <= CoefsInitValCst_v2; | |
| 163 | coefs_JC <= CoefsInitValCst_v2; |
|
|||
| 164 |
|
||||
| 165 | --FILTER : IIR_CEL_CTRLR |
|
|||
| 166 | -- GENERIC MAP ( |
|
|||
| 167 | -- tech => 0, |
|
|||
| 168 | -- Sample_SZ => 18, |
|
|||
| 169 | -- ChanelsCount => ChanelCount, |
|
|||
| 170 | -- Coef_SZ => Coef_SZ, |
|
|||
| 171 | -- CoefCntPerCel => CoefCntPerCel, |
|
|||
| 172 | -- Cels_count => Cels_count, |
|
|||
| 173 | -- Mem_use => use_CEL) -- use_CEL for SIMU, use_RAM for synthesis |
|
|||
| 174 | -- PORT MAP ( |
|
|||
| 175 | -- reset => rstn, |
|
|||
| 176 | -- clk => clk, |
|
|||
| 177 | -- sample_clk => sample_val_delay, |
|
|||
| 178 | -- sample_in => sample_filter_in, |
|
|||
| 179 | -- sample_out => sample_filter_out, |
|
|||
| 180 | -- virg_pos => 7, |
|
|||
| 181 | -- GOtest => OPEN, |
|
|||
| 182 | -- coefs => coefs); |
|
|||
| 183 |
|
195 | |||
| 184 | IIR_CEL_CTRLR_v2_1 : IIR_CEL_CTRLR_v2 |
|
196 | --IIR_CEL_CTRLR_v2_1 : IIR_CEL_CTRLR_v2 | |
| 185 | GENERIC MAP ( |
|
197 | -- GENERIC MAP ( | |
| 186 | tech => 0, |
|
198 | -- tech => 0, | |
| 187 | Mem_use => use_RAM, |
|
199 | -- Mem_use => use_RAM, | |
| 188 | Sample_SZ => 18, |
|
200 | -- Sample_SZ => 18, | |
| 189 | Coef_SZ => Coef_SZ, |
|
201 | -- Coef_SZ => Coef_SZ, | |
| 190 |
Coef_Nb => 25, |
|
202 | -- Coef_Nb => 25, | |
| 191 |
|
|
203 | -- Coef_sel_SZ => 5, | |
| 192 | Cels_count => Cels_count, |
|
204 | -- Cels_count => Cels_count, | |
| 193 | ChanelsCount => ChanelCount) |
|
205 | -- ChanelsCount => ChanelCount) | |
| 194 | PORT MAP ( |
|
206 | -- PORT MAP ( | |
| 195 | rstn => rstn, |
|
207 | -- rstn => rstn, | |
| 196 | clk => clk, |
|
208 | -- clk => clk, | |
| 197 | virg_pos => 7, |
|
209 | -- virg_pos => 7, | |
| 198 |
coefs => coefs_ |
|
210 | -- coefs => coefs_v2, | |
| 199 |
|
|
211 | -- sample_in_val => sample_val_delay, | |
| 200 | sample_in => sample_filter_in, |
|
212 | -- sample_in => sample_filter_in, | |
| 201 |
sample_out_val => sample_filter_ |
|
213 | -- sample_out_val => sample_filter_v2_out_val, | |
| 202 |
sample_out => sample_filter_ |
|
214 | -- sample_out => sample_filter_v2_out); | |
| 203 |
|
215 | |||
| 204 | ----------------------------------------------------------------------------- |
|
216 | sample_filter_v2_out_val <= sample_val_delay; | |
| 205 | PROCESS (clk, rstn) |
|
217 | ||
| 206 | BEGIN -- PROCESS |
|
218 | ChanelLoopOut : FOR i IN 0 TO 5 GENERATE | |
| 207 | IF rstn = '0' THEN -- asynchronous reset (active low) |
|
219 | SampleLoopOut : FOR j IN 0 TO 15 GENERATE | |
| 208 | sample_filter_JC_out_r_val <= '0'; |
|
220 | --sample_filter_v2_out_s(i, j) <= sample_filter_v2_out(i, j); | |
| 209 | rst_all_chanel : FOR I IN ChanelCount-1 DOWNTO 0 LOOP |
|
221 | sample_filter_v2_out_s(i, j) <= sample_filter_in(i, j); | |
| 210 | rst_all_bits : FOR J IN 17 DOWNTO 0 LOOP |
|
222 | END GENERATE; | |
| 211 | sample_filter_JC_out_r(I, J) <= '0'; |
|
223 | END GENERATE; | |
| 212 | END LOOP rst_all_bits; |
|
|||
| 213 | END LOOP rst_all_chanel; |
|
|||
| 214 | ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge |
|
|||
| 215 | sample_filter_JC_out_r_val <= sample_filter_JC_out_val; |
|
|||
| 216 | IF sample_filter_JC_out_val = '1' THEN |
|
|||
| 217 | sample_filter_JC_out_r <= sample_filter_JC_out; |
|
|||
| 218 | END IF; |
|
|||
| 219 | END IF; |
|
|||
| 220 | END PROCESS; |
|
|||
| 221 |
|
||||
| 222 | ----------------------------------------------------------------------------- |
|
224 | ----------------------------------------------------------------------------- | |
| 223 | -- F0 -- @24.576 kHz |
|
225 | -- F0 -- @24.576 kHz | |
| 224 | ----------------------------------------------------------------------------- |
|
226 | ----------------------------------------------------------------------------- | |
| 225 | Downsampling_f0 : Downsampling |
|
227 | Downsampling_f0 : Downsampling | |
| 226 | GENERIC MAP ( |
|
228 | GENERIC MAP ( | |
| 227 |
ChanelCount => |
|
229 | ChanelCount => 6, | |
| 228 |
SampleSize => 1 |
|
230 | SampleSize => 16, | |
| 229 | DivideParam => 4) |
|
231 | DivideParam => 4) | |
| 230 | PORT MAP ( |
|
232 | PORT MAP ( | |
| 231 | clk => clk, |
|
233 | clk => clk, | |
| 232 | rstn => rstn, |
|
234 | rstn => rstn, | |
| 233 |
sample_in_val => sample_filter_ |
|
235 | sample_in_val => sample_filter_v2_out_val, | |
| 234 |
sample_in => sample_filter_ |
|
236 | sample_in => sample_filter_v2_out_s, | |
| 235 | sample_out_val => sample_f0_val, |
|
237 | sample_out_val => sample_f0_val, | |
| 236 | sample_out => sample_f0); |
|
238 | sample_out => sample_f0); | |
| 237 |
|
239 | |||
| 238 |
all_bit_sample_f0: FOR I IN 1 |
|
240 | all_bit_sample_f0 : FOR I IN 15 DOWNTO 0 GENERATE | |
| 239 |
sample_f0_wdata( |
|
241 | sample_f0_wdata_s(I) <= sample_f0(0, I); | |
| 240 |
sample_f0_wdata(1 |
|
242 | sample_f0_wdata_s(16*1+I) <= sample_f0(1, I); | |
| 241 |
sample_f0_wdata(1 |
|
243 | sample_f0_wdata_s(16*2+I) <= sample_f0(2, I); | |
| 242 |
sample_f0_wdata(1 |
|
244 | sample_f0_wdata_s(16*3+I) <= sample_f0(3, I); | |
| 243 |
sample_f0_wdata(1 |
|
245 | sample_f0_wdata_s(16*4+I) <= sample_f0(4, I); | |
|
|
246 | sample_f0_wdata_s(16*5+I) <= sample_f0(5, I); | |||
| 244 | END GENERATE all_bit_sample_f0; |
|
247 | END GENERATE all_bit_sample_f0; | |
| 245 |
|
248 | |||
| 246 | PROCESS (clk, rstn) |
|
249 | sample_f0_wen <= NOT(sample_f0_val) & | |
| 247 | BEGIN -- PROCESS |
|
250 | NOT(sample_f0_val) & | |
| 248 | IF rstn = '0' THEN -- asynchronous reset (active low) |
|
251 | NOT(sample_f0_val) & | |
| 249 | counter_f0 <= 0; |
|
252 | NOT(sample_f0_val) & | |
| 250 | ELSIF clk'event AND clk = '1' THEN -- rising clock edge |
|
253 | NOT(sample_f0_val) & | |
| 251 | IF sample_f0_val = '1' THEN |
|
254 | NOT(sample_f0_val); | |
| 252 | IF counter_f0 = 511 THEN |
|
|||
| 253 | counter_f0 <= 0; |
|
|||
| 254 | ELSE |
|
|||
| 255 | counter_f0 <= counter_f0 + 1; |
|
|||
| 256 | END IF; |
|
|||
| 257 | END IF; |
|
|||
| 258 | END IF; |
|
|||
| 259 | END PROCESS; |
|
|||
| 260 |
|
||||
| 261 | sample_f0_0_val <= sample_f0_val WHEN counter_f0 < 256 ELSE '0'; |
|
|||
| 262 | sample_f0_0_wen <= NOT(sample_f0_0_val) & |
|
|||
| 263 | NOT(sample_f0_0_val) & |
|
|||
| 264 | NOT(sample_f0_0_val) & |
|
|||
| 265 | NOT(sample_f0_0_val) & |
|
|||
| 266 | NOT(sample_f0_0_val); |
|
|||
| 267 |
|
||||
| 268 | lppFIFO_f0_0: lppFIFOxN |
|
|||
| 269 | GENERIC MAP ( |
|
|||
| 270 | tech => tech, |
|
|||
| 271 | Data_sz => 18, |
|
|||
| 272 | FifoCnt => 5, |
|
|||
| 273 | Enable_ReUse => '0') |
|
|||
| 274 | PORT MAP ( |
|
|||
| 275 | rst => rstn, |
|
|||
| 276 | wclk => clk, |
|
|||
| 277 | rclk => clk, |
|
|||
| 278 | ReUse => (OTHERS => '0'), |
|
|||
| 279 |
|
||||
| 280 | wen => sample_f0_0_wen, |
|
|||
| 281 | ren => sample_f0_0_ren, |
|
|||
| 282 | wdata => sample_f0_wdata, |
|
|||
| 283 | rdata => sample_f0_0_rdata, |
|
|||
| 284 | full => sample_f0_0_full, |
|
|||
| 285 | empty => sample_f0_0_empty); |
|
|||
| 286 |
|
||||
| 287 | sample_f0_1_val <= sample_f0_val WHEN counter_f0 > 255 ELSE '0'; |
|
|||
| 288 | sample_f0_1_wen <= NOT(sample_f0_1_val) & |
|
|||
| 289 | NOT(sample_f0_1_val) & |
|
|||
| 290 | NOT(sample_f0_1_val) & |
|
|||
| 291 | NOT(sample_f0_1_val) & |
|
|||
| 292 | NOT(sample_f0_1_val); |
|
|||
| 293 |
|
||||
| 294 | lppFIFO_f0_1: lppFIFOxN |
|
|||
| 295 | GENERIC MAP ( |
|
|||
| 296 | tech => tech, |
|
|||
| 297 | Data_sz => 18, |
|
|||
| 298 | FifoCnt => 5, |
|
|||
| 299 | Enable_ReUse => '0') |
|
|||
| 300 | PORT MAP ( |
|
|||
| 301 | rst => rstn, |
|
|||
| 302 | wclk => clk, |
|
|||
| 303 | rclk => clk, |
|
|||
| 304 | ReUse => (OTHERS => '0'), |
|
|||
| 305 |
|
||||
| 306 | wen => sample_f0_1_wen, |
|
|||
| 307 | ren => sample_f0_1_ren, |
|
|||
| 308 | wdata => sample_f0_wdata, |
|
|||
| 309 | rdata => sample_f0_1_rdata, |
|
|||
| 310 | full => sample_f0_1_full, |
|
|||
| 311 | empty => sample_f0_1_empty); |
|
|||
| 312 |
|
255 | |||
| 313 |
|
||||
| 314 |
|
||||
| 315 | ----------------------------------------------------------------------------- |
|
256 | ----------------------------------------------------------------------------- | |
| 316 | -- F1 -- @4096 Hz |
|
257 | -- F1 -- @4096 Hz | |
| 317 | ----------------------------------------------------------------------------- |
|
258 | ----------------------------------------------------------------------------- | |
| 318 | Downsampling_f1 : Downsampling |
|
259 | Downsampling_f1 : Downsampling | |
| 319 | GENERIC MAP ( |
|
260 | GENERIC MAP ( | |
| 320 |
ChanelCount => |
|
261 | ChanelCount => 6, | |
| 321 |
SampleSize => 1 |
|
262 | SampleSize => 16, | |
| 322 | DivideParam => 6) |
|
263 | DivideParam => 6) | |
| 323 | PORT MAP ( |
|
264 | PORT MAP ( | |
| 324 | clk => clk, |
|
265 | clk => clk, | |
| @@ -328,104 +269,143 BEGIN | |||||
| 328 | sample_out_val => sample_f1_val, |
|
269 | sample_out_val => sample_f1_val, | |
| 329 | sample_out => sample_f1); |
|
270 | sample_out => sample_f1); | |
| 330 |
|
271 | |||
| 331 |
sample_f1_wen |
|
272 | sample_f1_wen <= NOT(sample_f1_val) & | |
|
|
273 | NOT(sample_f1_val) & | |||
| 332 | NOT(sample_f1_val) & |
|
274 | NOT(sample_f1_val) & | |
| 333 | NOT(sample_f1_val) & |
|
275 | NOT(sample_f1_val) & | |
| 334 | NOT(sample_f1_val) & |
|
276 | NOT(sample_f1_val) & | |
| 335 | NOT(sample_f1_val); |
|
277 | NOT(sample_f1_val); | |
| 336 |
|
278 | |||
| 337 |
all_bit_sample_f1: FOR I IN 1 |
|
279 | all_bit_sample_f1 : FOR I IN 15 DOWNTO 0 GENERATE | |
| 338 |
sample_f1_wdata( |
|
280 | sample_f1_wdata_s(I) <= sample_f1(0, I); | |
| 339 |
sample_f1_wdata(1 |
|
281 | sample_f1_wdata_s(16*1+I) <= sample_f1(1, I); | |
| 340 |
sample_f1_wdata(1 |
|
282 | sample_f1_wdata_s(16*2+I) <= sample_f1(2, I); | |
| 341 |
sample_f1_wdata(1 |
|
283 | sample_f1_wdata_s(16*3+I) <= sample_f1(3, I); | |
| 342 |
sample_f1_wdata(1 |
|
284 | sample_f1_wdata_s(16*4+I) <= sample_f1(4, I); | |
|
|
285 | sample_f1_wdata_s(16*5+I) <= sample_f1(5, I); | |||
| 343 | END GENERATE all_bit_sample_f1; |
|
286 | END GENERATE all_bit_sample_f1; | |
| 344 |
|
||||
| 345 | lppFIFO_f1: lppFIFOxN |
|
|||
| 346 | GENERIC MAP ( |
|
|||
| 347 | tech => tech, |
|
|||
| 348 | Data_sz => 18, |
|
|||
| 349 | FifoCnt => 5, |
|
|||
| 350 | Enable_ReUse => '0') |
|
|||
| 351 | PORT MAP ( |
|
|||
| 352 | rst => rstn, |
|
|||
| 353 | wclk => clk, |
|
|||
| 354 | rclk => clk, |
|
|||
| 355 | ReUse => (OTHERS => '0'), |
|
|||
| 356 |
|
||||
| 357 | wen => sample_f1_wen, |
|
|||
| 358 | ren => sample_f1_ren, |
|
|||
| 359 | wdata => sample_f1_wdata, |
|
|||
| 360 | rdata => sample_f1_rdata, |
|
|||
| 361 | full => sample_f1_full, |
|
|||
| 362 | empty => sample_f1_empty); |
|
|||
| 363 |
|
287 | |||
| 364 | ----------------------------------------------------------------------------- |
|
288 | ----------------------------------------------------------------------------- | |
| 365 |
-- F2 -- @ |
|
289 | -- F2 -- @256 Hz | |
| 366 | ----------------------------------------------------------------------------- |
|
290 | ----------------------------------------------------------------------------- | |
| 367 | Downsampling_f2 : Downsampling |
|
291 | Downsampling_f2 : Downsampling | |
| 368 | GENERIC MAP ( |
|
292 | GENERIC MAP ( | |
| 369 |
ChanelCount => |
|
293 | ChanelCount => 6, | |
| 370 |
SampleSize => 1 |
|
294 | SampleSize => 16, | |
|
|
295 | DivideParam => 96) | |||
|
|
296 | PORT MAP ( | |||
|
|
297 | clk => clk, | |||
|
|
298 | rstn => rstn, | |||
|
|
299 | sample_in_val => sample_f0_val , | |||
|
|
300 | sample_in => sample_f0, | |||
|
|
301 | sample_out_val => sample_f2_val, | |||
|
|
302 | sample_out => sample_f2); | |||
|
|
303 | ||||
|
|
304 | sample_f2_wen <= NOT(sample_f2_val) & | |||
|
|
305 | NOT(sample_f2_val) & | |||
|
|
306 | NOT(sample_f2_val) & | |||
|
|
307 | NOT(sample_f2_val) & | |||
|
|
308 | NOT(sample_f2_val) & | |||
|
|
309 | NOT(sample_f2_val); | |||
|
|
310 | ||||
|
|
311 | all_bit_sample_f2 : FOR I IN 15 DOWNTO 0 GENERATE | |||
|
|
312 | sample_f2_wdata_s(I) <= sample_f2(0, I); | |||
|
|
313 | sample_f2_wdata_s(16*1+I) <= sample_f2(1, I); | |||
|
|
314 | sample_f2_wdata_s(16*2+I) <= sample_f2(2, I); | |||
|
|
315 | sample_f2_wdata_s(16*3+I) <= sample_f2(3, I); | |||
|
|
316 | sample_f2_wdata_s(16*4+I) <= sample_f2(4, I); | |||
|
|
317 | sample_f2_wdata_s(16*5+I) <= sample_f2(5, I); | |||
|
|
318 | END GENERATE all_bit_sample_f2; | |||
|
|
319 | ||||
|
|
320 | ----------------------------------------------------------------------------- | |||
|
|
321 | -- F3 -- @16 Hz | |||
|
|
322 | ----------------------------------------------------------------------------- | |||
|
|
323 | Downsampling_f3 : Downsampling | |||
|
|
324 | GENERIC MAP ( | |||
|
|
325 | ChanelCount => 6, | |||
|
|
326 | SampleSize => 16, | |||
| 371 | DivideParam => 256) |
|
327 | DivideParam => 256) | |
| 372 | PORT MAP ( |
|
328 | PORT MAP ( | |
| 373 | clk => clk, |
|
329 | clk => clk, | |
| 374 | rstn => rstn, |
|
330 | rstn => rstn, | |
| 375 | sample_in_val => sample_f1_val , |
|
331 | sample_in_val => sample_f1_val , | |
| 376 | sample_in => sample_f1, |
|
332 | sample_in => sample_f1, | |
| 377 | sample_out_val => sample_f2_val, |
|
|||
| 378 | sample_out => sample_f2); |
|
|||
| 379 |
|
||||
| 380 | ----------------------------------------------------------------------------- |
|
|||
| 381 | -- F3 -- @256 Hz |
|
|||
| 382 | ----------------------------------------------------------------------------- |
|
|||
| 383 | Downsampling_f3 : Downsampling |
|
|||
| 384 | GENERIC MAP ( |
|
|||
| 385 | ChanelCount => ChanelCount, |
|
|||
| 386 | SampleSize => 18, |
|
|||
| 387 | DivideParam => 96) |
|
|||
| 388 | PORT MAP ( |
|
|||
| 389 | clk => clk, |
|
|||
| 390 | rstn => rstn, |
|
|||
| 391 | sample_in_val => sample_f0_val , |
|
|||
| 392 | sample_in => sample_f0, |
|
|||
| 393 | sample_out_val => sample_f3_val, |
|
333 | sample_out_val => sample_f3_val, | |
| 394 | sample_out => sample_f3); |
|
334 | sample_out => sample_f3); | |
| 395 |
|
335 | |||
| 396 |
sample_f3_wen |
|
336 | sample_f3_wen <= (NOT sample_f3_val) & | |
|
|
337 | (NOT sample_f3_val) & | |||
| 397 | (NOT sample_f3_val) & |
|
338 | (NOT sample_f3_val) & | |
| 398 | (NOT sample_f3_val) & |
|
339 | (NOT sample_f3_val) & | |
| 399 | (NOT sample_f3_val) & |
|
340 | (NOT sample_f3_val) & | |
| 400 | (NOT sample_f3_val); |
|
341 | (NOT sample_f3_val); | |
| 401 |
|
342 | |||
| 402 |
all_bit_sample_f3: FOR I IN 1 |
|
343 | all_bit_sample_f3 : FOR I IN 15 DOWNTO 0 GENERATE | |
| 403 |
sample_f3_wdata( |
|
344 | sample_f3_wdata_s(I) <= sample_f3(0, I); | |
| 404 |
sample_f3_wdata(1 |
|
345 | sample_f3_wdata_s(16*1+I) <= sample_f3(1, I); | |
| 405 |
sample_f3_wdata(1 |
|
346 | sample_f3_wdata_s(16*2+I) <= sample_f3(2, I); | |
| 406 |
sample_f3_wdata(1 |
|
347 | sample_f3_wdata_s(16*3+I) <= sample_f3(3, I); | |
| 407 |
sample_f3_wdata(1 |
|
348 | sample_f3_wdata_s(16*4+I) <= sample_f3(4, I); | |
|
|
349 | sample_f3_wdata_s(16*5+I) <= sample_f3(5, I); | |||
| 408 | END GENERATE all_bit_sample_f3; |
|
350 | END GENERATE all_bit_sample_f3; | |
| 409 |
|
351 | |||
| 410 | lppFIFO_f3: lppFIFOxN |
|
352 | lpp_waveform_1 : lpp_waveform | |
| 411 | GENERIC MAP ( |
|
353 | GENERIC MAP ( | |
| 412 |
|
|
354 | hindex => hindex, | |
| 413 | Data_sz => 18, |
|
355 | tech => tech, | |
| 414 | FifoCnt => 5, |
|
356 | data_size => 160, | |
| 415 | Enable_ReUse => '0') |
|
357 | nb_burst_available_size => nb_burst_available_size, | |
|
|
358 | nb_snapshot_param_size => nb_snapshot_param_size, | |||
|
|
359 | delta_snapshot_size => delta_snapshot_size, | |||
|
|
360 | delta_f2_f0_size => delta_f2_f0_size, | |||
|
|
361 | delta_f2_f1_size => delta_f2_f1_size) | |||
| 416 | PORT MAP ( |
|
362 | PORT MAP ( | |
| 417 |
|
|
363 | clk => clk, | |
| 418 | wclk => clk, |
|
364 | rstn => rstn, | |
| 419 | rclk => clk, |
|
365 | ||
| 420 | ReUse => (OTHERS => '0'), |
|
366 | AHB_Master_In => AHB_Master_In, | |
| 421 |
|
367 | AHB_Master_Out => AHB_Master_Out, | ||
| 422 | wen => sample_f3_wen, |
|
368 | ||
| 423 | ren => sample_f3_ren, |
|
369 | coarse_time_0 => coarse_time_0, -- IN | |
| 424 | wdata => sample_f3_wdata, |
|
370 | delta_snapshot => delta_snapshot, -- IN | |
| 425 | rdata => sample_f3_rdata, |
|
371 | delta_f2_f1 => delta_f2_f1, -- IN | |
| 426 | full => sample_f3_full, |
|
372 | delta_f2_f0 => delta_f2_f0, -- IN | |
| 427 | empty => sample_f3_empty); |
|
373 | enable_f0 => enable_f0, -- IN | |
|
|
374 | enable_f1 => enable_f1, -- IN | |||
|
|
375 | enable_f2 => enable_f2, -- IN | |||
|
|
376 | enable_f3 => enable_f3, -- IN | |||
|
|
377 | burst_f0 => burst_f0, -- IN | |||
|
|
378 | burst_f1 => burst_f1, -- IN | |||
|
|
379 | burst_f2 => burst_f2, -- IN | |||
|
|
380 | nb_burst_available => nb_burst_available, | |||
|
|
381 | nb_snapshot_param => nb_snapshot_param, | |||
|
|
382 | status_full => status_full, | |||
|
|
383 | status_full_ack => status_full_ack, -- IN | |||
|
|
384 | status_full_err => status_full_err, | |||
|
|
385 | status_new_err => status_new_err, | |||
| 428 |
|
386 | |||
| 429 |
|
387 | addr_data_f0 => addr_data_f0, -- IN | ||
|
|
388 | addr_data_f1 => addr_data_f1, -- IN | |||
|
|
389 | addr_data_f2 => addr_data_f2, -- IN | |||
|
|
390 | addr_data_f3 => addr_data_f3, -- IN | |||
|
|
391 | ||||
|
|
392 | data_f0_in => data_f0_in_valid, | |||
|
|
393 | data_f1_in => data_f1_in_valid, | |||
|
|
394 | data_f2_in => data_f2_in_valid, | |||
|
|
395 | data_f3_in => data_f3_in_valid, | |||
|
|
396 | data_f0_in_valid => sample_f0_val, | |||
|
|
397 | data_f1_in_valid => sample_f1_val, | |||
|
|
398 | data_f2_in_valid => sample_f2_val, | |||
|
|
399 | data_f3_in_valid => sample_f3_val); | |||
|
|
400 | ||||
|
|
401 | data_f0_in_valid((10*16)-1 DOWNTO (4*16)) <= sample_f0_wdata_s; | |||
|
|
402 | data_f1_in_valid((10*16)-1 DOWNTO (4*16)) <= sample_f1_wdata_s; | |||
|
|
403 | data_f2_in_valid((10*16)-1 DOWNTO (4*16)) <= sample_f2_wdata_s; | |||
|
|
404 | data_f3_in_valid((10*16)-1 DOWNTO (4*16)) <= sample_f3_wdata_s; | |||
|
|
405 | ||||
|
|
406 | sample_f0_wdata <= sample_f0_wdata_s; | |||
|
|
407 | sample_f1_wdata <= sample_f1_wdata_s; | |||
|
|
408 | sample_f2_wdata <= sample_f2_wdata_s; | |||
|
|
409 | sample_f3_wdata <= sample_f3_wdata_s; | |||
| 430 |
|
410 | |||
| 431 | END tb; |
|
411 | END tb; | |
| @@ -45,9 +45,27 vcom -quiet -93 -work lpp ../../lib/lpp/ | |||||
| 45 | vcom -quiet -93 -work lpp ../../lib/lpp/lpp_top_lfr/lpp_top_acq.vhd |
|
45 | vcom -quiet -93 -work lpp ../../lib/lpp/lpp_top_lfr/lpp_top_acq.vhd | |
| 46 | #vcom -quiet -93 -work lpp ../../lib/lpp/lpp_top_lfr/lpp_top_lfr.vhd |
|
46 | #vcom -quiet -93 -work lpp ../../lib/lpp/lpp_top_lfr/lpp_top_lfr.vhd | |
| 47 |
|
47 | |||
|
|
48 | vcom -quiet -93 -work lpp ../../lib/lpp/lfr_time_management/lpp_lfr_time_management.vhd | |||
|
|
49 | vcom -quiet -93 -work lpp ../../lib/lpp/lfr_time_management/apb_lfr_time_management.vhd | |||
|
|
50 | vcom -quiet -93 -work lpp ../../lib/lpp/lfr_time_management/lfr_time_management.vhd | |||
|
|
51 | ||||
|
|
52 | vcom -quiet -93 -work lpp ../../lib/lpp/lpp_dma/lpp_dma_pkg.vhd | |||
|
|
53 | ||||
|
|
54 | vcom -quiet -93 -work lpp ../../lib/lpp/lpp_waveform/lpp_waveform_pkg.vhd | |||
|
|
55 | vcom -quiet -93 -work lpp ../../lib/lpp/lpp_waveform/lpp_waveform.vhd | |||
|
|
56 | vcom -quiet -93 -work lpp ../../lib/lpp/lpp_waveform/lpp_waveform_snapshot_controler.vhd | |||
|
|
57 | vcom -quiet -93 -work lpp ../../lib/lpp/lpp_waveform/lpp_waveform_snapshot.vhd | |||
|
|
58 | vcom -quiet -93 -work lpp ../../lib/lpp/lpp_waveform/lpp_waveform_burst.vhd | |||
|
|
59 | vcom -quiet -93 -work lpp ../../lib/lpp/lpp_waveform/lpp_waveform_dma.vhd | |||
|
|
60 | vcom -quiet -93 -work lpp ../../lib/lpp/lpp_waveform/lpp_waveform_dma_send_Nword.vhd | |||
|
|
61 | vcom -quiet -93 -work lpp ../../lib/lpp/lpp_waveform/lpp_waveform_dma_selectaddress.vhd | |||
|
|
62 | vcom -quiet -93 -work lpp ../../lib/lpp/lpp_waveform/lpp_waveform_dma_genvalid.vhd | |||
|
|
63 | ||||
|
|
64 | vcom -quiet -93 -work work Top_Data_Acquisition.vhd | |||
|
|
65 | ||||
| 48 | vcom -quiet -93 -work work TB_Data_Acquisition.vhd |
|
66 | vcom -quiet -93 -work work TB_Data_Acquisition.vhd | |
| 49 |
|
67 | |||
| 50 | vsim work.TB_Data_Acquisition |
|
68 | #vsim work.TB_Data_Acquisition | |
| 51 |
|
69 | |||
| 52 | #log -r * |
|
70 | #log -r * | |
| 53 | #do wave_data_acquisition.do |
|
71 | #do wave_data_acquisition.do | |
| @@ -17,158 +17,158 | |||||
| 17 | -- Additional Comments: |
|
17 | -- Additional Comments: | |
| 18 | -- |
|
18 | -- | |
| 19 | ---------------------------------------------------------------------------------- |
|
19 | ---------------------------------------------------------------------------------- | |
| 20 | library IEEE; |
|
20 | LIBRARY IEEE; | |
| 21 |
|
|
21 | USE IEEE.STD_LOGIC_1164.ALL; | |
| 22 |
|
|
22 | USE IEEE.NUMERIC_STD.ALL; | |
| 23 | library grlib; |
|
23 | LIBRARY grlib; | |
| 24 |
|
|
24 | USE grlib.amba.ALL; | |
| 25 |
|
|
25 | USE grlib.stdlib.ALL; | |
| 26 |
|
|
26 | USE grlib.devices.ALL; | |
| 27 | library lpp; |
|
27 | LIBRARY lpp; | |
| 28 |
|
|
28 | USE lpp.apb_devices_list.ALL; | |
| 29 |
|
|
29 | USE lpp.lpp_lfr_time_management.ALL; | |
| 30 |
|
30 | |||
| 31 |
|
|
31 | ENTITY apb_lfr_time_management IS | |
| 32 |
|
32 | |||
| 33 | generic( |
|
33 | GENERIC( | |
| 34 |
|
|
34 | pindex : INTEGER := 0; --! APB slave index | |
| 35 |
|
|
35 | paddr : INTEGER := 0; --! ADDR field of the APB BAR | |
| 36 |
|
|
36 | pmask : INTEGER := 16#fff#; --! MASK field of the APB BAR | |
| 37 |
|
|
37 | pirq : INTEGER := 0; --! 2 consecutive IRQ lines are used | |
| 38 |
|
|
38 | masterclk : INTEGER := 25000000; --! master clock in Hz | |
| 39 |
|
|
39 | otherclk : INTEGER := 49152000; --! other clock in Hz | |
| 40 |
|
|
40 | finetimeclk : INTEGER := 65536 --! divided clock used for the fine time counter | |
| 41 | ); |
|
41 | ); | |
| 42 |
|
42 | |||
| 43 | Port ( |
|
43 | PORT ( | |
| 44 |
|
|
44 | clk25MHz : IN STD_LOGIC; --! Clock | |
| 45 |
|
|
45 | clk49_152MHz : IN STD_LOGIC; --! secondary clock | |
| 46 |
|
|
46 | resetn : IN STD_LOGIC; --! Reset | |
| 47 |
|
|
47 | grspw_tick : IN STD_LOGIC; --! grspw signal asserted when a valid time-code is received | |
| 48 |
|
|
48 | apbi : IN apb_slv_in_type; --! APB slave input signals | |
| 49 |
|
|
49 | apbo : OUT apb_slv_out_type; --! APB slave output signals | |
| 50 | coarse_time : out std_logic_vector(31 downto 0); --! coarse time |
|
50 | coarse_time : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); --! coarse time | |
| 51 | fine_time : out std_logic_vector(31 downto 0) --! fine time |
|
51 | fine_time : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) --! fine time | |
| 52 | ); |
|
52 | ); | |
| 53 |
|
||||
| 54 | end apb_lfr_time_management; |
|
|||
| 55 |
|
53 | |||
| 56 | architecture Behavioral of apb_lfr_time_management is |
|
54 | END apb_lfr_time_management; | |
| 57 |
|
55 | |||
| 58 | constant REVISION : integer := 1; |
|
56 | ARCHITECTURE Behavioral OF apb_lfr_time_management IS | |
|
|
57 | ||||
|
|
58 | CONSTANT REVISION : INTEGER := 1; | |||
| 59 |
|
59 | |||
| 60 | --! the following types are defined in the grlib amba package |
|
60 | --! the following types are defined in the grlib amba package | |
| 61 | --! subtype amba_config_word is std_logic_vector(31 downto 0); |
|
61 | --! subtype amba_config_word is std_logic_vector(31 downto 0); | |
| 62 | --! type apb_config_type is array (0 to NAPBCFG-1) of amba_config_word; |
|
62 | --! type apb_config_type is array (0 to NAPBCFG-1) of amba_config_word; | |
| 63 |
|
|
63 | CONSTANT pconfig : apb_config_type := ( | |
| 64 | --! 0 => ahb_device_reg (VENDOR_LPP, LPP_ROTARY, 0, REVISION, 0), |
|
64 | --! 0 => ahb_device_reg (VENDOR_LPP, LPP_ROTARY, 0, REVISION, 0), | |
| 65 |
|
|
65 | 0 => ahb_device_reg (19, 14, 0, REVISION, pirq), | |
| 66 |
|
|
66 | 1 => apb_iobar(paddr, pmask)); | |
| 67 |
|
67 | |||
| 68 |
|
|
68 | TYPE apb_lfr_time_management_Reg IS RECORD | |
| 69 | ctrl : std_logic_vector(31 downto 0); |
|
69 | ctrl : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
| 70 | coarse_time_load : std_logic_vector(31 downto 0); |
|
70 | coarse_time_load : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
| 71 | coarse_time : std_logic_vector(31 downto 0); |
|
71 | coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
| 72 | fine_time : std_logic_vector(31 downto 0); |
|
72 | fine_time : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
| 73 |
next_commutation |
|
73 | next_commutation : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
| 74 | end record; |
|
74 | END RECORD; | |
| 75 |
|
75 | |||
| 76 |
|
|
76 | SIGNAL r : apb_lfr_time_management_Reg; | |
| 77 | signal Rdata : std_logic_vector(31 downto 0); |
|
77 | SIGNAL Rdata : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
| 78 | signal force_tick : std_logic; |
|
78 | SIGNAL force_tick : STD_LOGIC; | |
| 79 |
|
|
79 | SIGNAL previous_force_tick : STD_LOGIC; | |
| 80 | signal soft_tick : std_logic; |
|
80 | SIGNAL soft_tick : STD_LOGIC; | |
| 81 |
|
|
81 | SIGNAL reset_next_commutation : STD_LOGIC; | |
| 82 |
|
82 | |||
| 83 | begin |
|
83 | BEGIN | |
| 84 |
|
84 | |||
| 85 | lfrtimemanagement0: lfr_time_management |
|
85 | lfrtimemanagement0 : lfr_time_management | |
| 86 |
|
|
86 | GENERIC MAP(masterclk => masterclk, timeclk => otherclk, finetimeclk => finetimeclk) | |
| 87 |
|
|
87 | PORT MAP(master_clock => clk25MHz, time_clock => clk49_152MHz, resetn => resetn, | |
| 88 |
|
|
88 | grspw_tick => grspw_tick, soft_tick => soft_tick, | |
| 89 |
|
|
89 | coarse_time_load => r.coarse_time_load, coarse_time => r.coarse_time, fine_time => r.fine_time, | |
| 90 |
|
|
90 | next_commutation => r.next_commutation, reset_next_commutation => reset_next_commutation, | |
| 91 |
|
|
91 | irq1 => apbo.pirq(pirq), irq2 => apbo.pirq(pirq+1)); | |
| 92 |
|
92 | |||
| 93 |
|
|
93 | PROCESS(resetn, clk25MHz, reset_next_commutation) | |
| 94 | begin |
|
94 | BEGIN | |
| 95 |
|
95 | |||
| 96 |
|
|
96 | IF resetn = '0' THEN | |
| 97 |
|
|
97 | r.coarse_time_load <= x"80000000"; | |
| 98 |
|
|
98 | r.ctrl <= x"00000000"; | |
| 99 |
|
|
99 | r.next_commutation <= x"ffffffff"; | |
| 100 |
|
|
100 | force_tick <= '0'; | |
| 101 |
|
|
101 | previous_force_tick <= '0'; | |
| 102 | soft_tick <= '0'; |
|
102 | soft_tick <= '0'; | |
| 103 |
|
103 | |||
| 104 |
|
|
104 | ELSIF reset_next_commutation = '1' THEN | |
| 105 |
|
|
105 | r.next_commutation <= x"ffffffff"; | |
| 106 |
|
106 | |||
| 107 | elsif clk25MHz'event and clk25MHz = '1' then |
|
107 | ELSIF clk25MHz'EVENT AND clk25MHz = '1' THEN | |
| 108 |
|
108 | |||
| 109 |
|
|
109 | previous_force_tick <= force_tick; | |
| 110 |
|
|
110 | force_tick <= r.ctrl(0); | |
| 111 |
|
|
111 | IF (previous_force_tick = '0') AND (force_tick = '1') THEN | |
| 112 |
|
|
112 | soft_tick <= '1'; | |
| 113 | else |
|
113 | ELSE | |
| 114 |
|
|
114 | soft_tick <= '0'; | |
| 115 | end if; |
|
115 | END IF; | |
| 116 |
|
116 | |||
| 117 | --APB Write OP |
|
117 | --APB Write OP | |
| 118 |
|
|
118 | IF (apbi.psel(pindex) AND apbi.penable AND apbi.pwrite) = '1' THEN | |
| 119 | case apbi.paddr(7 downto 2) is |
|
119 | CASE apbi.paddr(7 DOWNTO 2) IS | |
| 120 | when "000000" => |
|
120 | WHEN "000000" => | |
| 121 |
|
|
121 | r.ctrl <= apbi.pwdata(31 DOWNTO 0); | |
| 122 | when "000001" => |
|
122 | WHEN "000001" => | |
| 123 |
|
|
123 | r.coarse_time_load <= apbi.pwdata(31 DOWNTO 0); | |
| 124 |
|
|
124 | WHEN "000100" => | |
| 125 |
|
|
125 | r.next_commutation <= apbi.pwdata(31 DOWNTO 0); | |
| 126 | when others => |
|
126 | WHEN OTHERS => | |
| 127 |
|
|
127 | r.coarse_time_load <= x"00000000"; | |
| 128 | end case; |
|
128 | END CASE; | |
| 129 | elsif r.ctrl(0) = '1' then |
|
129 | ELSIF r.ctrl(0) = '1' THEN | |
| 130 |
|
|
130 | r.ctrl(0) <= '0'; | |
| 131 | end if; |
|
131 | END IF; | |
| 132 |
|
132 | |||
| 133 | --APB READ OP |
|
133 | --APB READ OP | |
| 134 |
|
|
134 | IF (apbi.psel(pindex) AND (NOT apbi.pwrite)) = '1' THEN | |
| 135 | case apbi.paddr(7 downto 2) is |
|
135 | CASE apbi.paddr(7 DOWNTO 2) IS | |
| 136 | when "000000" => |
|
136 | WHEN "000000" => | |
| 137 | Rdata(31 downto 24) <= r.ctrl(31 downto 24); |
|
137 | Rdata(31 DOWNTO 24) <= r.ctrl(31 DOWNTO 24); | |
| 138 | Rdata(23 downto 16) <= r.ctrl(23 downto 16); |
|
138 | Rdata(23 DOWNTO 16) <= r.ctrl(23 DOWNTO 16); | |
| 139 | Rdata(15 downto 8) <= r.ctrl(15 downto 8); |
|
139 | Rdata(15 DOWNTO 8) <= r.ctrl(15 DOWNTO 8); | |
| 140 | Rdata(7 downto 0) <= r.ctrl(7 downto 0); |
|
140 | Rdata(7 DOWNTO 0) <= r.ctrl(7 DOWNTO 0); | |
| 141 | when "000001" => |
|
141 | WHEN "000001" => | |
| 142 |
|
|
142 | Rdata(31 DOWNTO 24) <= r.coarse_time_load(31 DOWNTO 24); | |
| 143 |
|
|
143 | Rdata(23 DOWNTO 16) <= r.coarse_time_load(23 DOWNTO 16); | |
| 144 |
|
|
144 | Rdata(15 DOWNTO 8) <= r.coarse_time_load(15 DOWNTO 8); | |
| 145 |
|
|
145 | Rdata(7 DOWNTO 0) <= r.coarse_time_load(7 DOWNTO 0); | |
| 146 | when "000010" => |
|
146 | WHEN "000010" => | |
| 147 |
|
|
147 | Rdata(31 DOWNTO 24) <= r.coarse_time(31 DOWNTO 24); | |
| 148 |
|
|
148 | Rdata(23 DOWNTO 16) <= r.coarse_time(23 DOWNTO 16); | |
| 149 |
|
|
149 | Rdata(15 DOWNTO 8) <= r.coarse_time(15 DOWNTO 8); | |
| 150 |
|
|
150 | Rdata(7 DOWNTO 0) <= r.coarse_time(7 DOWNTO 0); | |
| 151 | when "000011" => |
|
151 | WHEN "000011" => | |
| 152 |
|
|
152 | Rdata(31 DOWNTO 24) <= r.fine_time(31 DOWNTO 24); | |
| 153 |
|
|
153 | Rdata(23 DOWNTO 16) <= r.fine_time(23 DOWNTO 16); | |
| 154 |
|
|
154 | Rdata(15 DOWNTO 8) <= r.fine_time(15 DOWNTO 8); | |
| 155 | Rdata(7 downto 0) <= r.fine_time(7 downto 0); |
|
155 | Rdata(7 DOWNTO 0) <= r.fine_time(7 DOWNTO 0); | |
| 156 |
|
|
156 | WHEN "000100" => | |
| 157 |
|
|
157 | Rdata(31 DOWNTO 24) <= r.next_commutation(31 DOWNTO 24); | |
| 158 |
|
|
158 | Rdata(23 DOWNTO 16) <= r.next_commutation(23 DOWNTO 16); | |
| 159 |
|
|
159 | Rdata(15 DOWNTO 8) <= r.next_commutation(15 DOWNTO 8); | |
| 160 |
|
|
160 | Rdata(7 DOWNTO 0) <= r.next_commutation(7 DOWNTO 0); | |
| 161 | when others => |
|
161 | WHEN OTHERS => | |
| 162 |
|
|
162 | Rdata(31 DOWNTO 0) <= x"00000000"; | |
| 163 | end case; |
|
163 | END CASE; | |
| 164 | end if; |
|
164 | END IF; | |
| 165 |
|
165 | |||
| 166 | end if; |
|
166 | END IF; | |
| 167 |
|
|
167 | apbo.pconfig <= pconfig; | |
| 168 | end process; |
|
168 | END PROCESS; | |
| 169 |
|
169 | |||
| 170 |
apbo.prdata <= |
|
170 | apbo.prdata <= Rdata WHEN apbi.penable = '1'; | |
| 171 | coarse_time <= r.coarse_time; |
|
171 | coarse_time <= r.coarse_time; | |
| 172 | fine_time <= r.fine_time; |
|
172 | fine_time <= r.fine_time; | |
| 173 |
|
173 | |||
| 174 |
|
|
174 | END Behavioral; | |
| @@ -245,7 +245,7 BEGIN | |||||
| 245 | GENERIC MAP ( |
|
245 | GENERIC MAP ( | |
| 246 | ChanelCount => ChanelCount, |
|
246 | ChanelCount => ChanelCount, | |
| 247 | SampleSize => 18, |
|
247 | SampleSize => 18, | |
| 248 |
DivideParam => |
|
248 | DivideParam => 96) | |
| 249 | PORT MAP ( |
|
249 | PORT MAP ( | |
| 250 | clk => clk, |
|
250 | clk => clk, | |
| 251 | rstn => rstn, |
|
251 | rstn => rstn, | |
| @@ -275,7 +275,7 BEGIN | |||||
| 275 | GENERIC MAP ( |
|
275 | GENERIC MAP ( | |
| 276 | ChanelCount => ChanelCount, |
|
276 | ChanelCount => ChanelCount, | |
| 277 | SampleSize => 18, |
|
277 | SampleSize => 18, | |
| 278 |
DivideParam => |
|
278 | DivideParam => 256) | |
| 279 | PORT MAP ( |
|
279 | PORT MAP ( | |
| 280 | clk => clk, |
|
280 | clk => clk, | |
| 281 | rstn => rstn, |
|
281 | rstn => rstn, | |
| @@ -14,7 +14,8 USE lpp.lpp_top_lfr_pkg.ALL; | |||||
| 14 | USE lpp.lpp_dma_pkg.ALL; |
|
14 | USE lpp.lpp_dma_pkg.ALL; | |
| 15 | USE lpp.lpp_demux.ALL; |
|
15 | USE lpp.lpp_demux.ALL; | |
| 16 | USE lpp.lpp_fft.ALL; |
|
16 | USE lpp.lpp_fft.ALL; | |
| 17 |
|
|
17 | USE lpp.lpp_matrix.ALL; | |
|
|
18 | USE lpp.lpp_waveform_pkg.ALL; | |||
| 18 | LIBRARY techmap; |
|
19 | LIBRARY techmap; | |
| 19 | USE techmap.gencomp.ALL; |
|
20 | USE techmap.gencomp.ALL; | |
| 20 |
|
21 | |||
| @@ -46,6 +47,10 ENTITY lpp_top_lfr IS | |||||
| 46 | -- AMBA AHB Master Interface |
|
47 | -- AMBA AHB Master Interface | |
| 47 | AHB_DMA_SpectralMatrix_In : IN AHB_Mst_In_Type; |
|
48 | AHB_DMA_SpectralMatrix_In : IN AHB_Mst_In_Type; | |
| 48 | AHB_DMA_SpectralMatrix_Out : OUT AHB_Mst_Out_Type |
|
49 | AHB_DMA_SpectralMatrix_Out : OUT AHB_Mst_Out_Type | |
|
|
50 | ||||
|
|
51 | -- Time | |||
|
|
52 | coarse_time : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); --! coarse time | |||
|
|
53 | fine_time : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) --! fine time | |||
| 49 | ); |
|
54 | ); | |
| 50 | END lpp_top_lfr; |
|
55 | END lpp_top_lfr; | |
| 51 |
|
56 | |||
| @@ -53,8 +58,7 ARCHITECTURE tb OF lpp_top_lfr IS | |||||
| 53 |
|
58 | |||
| 54 | ----------------------------------------------------------------------------- |
|
59 | ----------------------------------------------------------------------------- | |
| 55 | -- f0 |
|
60 | -- f0 | |
| 56 |
SIGNAL sample_f0_ |
|
61 | SIGNAL sample_f0_wen : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
| 57 | SIGNAL sample_f0_1_wen : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
|||
| 58 | SIGNAL sample_f0_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); |
|
62 | SIGNAL sample_f0_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); | |
| 59 | -- |
|
63 | -- | |
| 60 | SIGNAL sample_f0_0_ren : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
64 | SIGNAL sample_f0_0_ren : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
| @@ -104,9 +108,9 ARCHITECTURE tb OF lpp_top_lfr IS | |||||
| 104 | SIGNAL fft_fifo_wen : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
108 | SIGNAL fft_fifo_wen : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
| 105 | SIGNAL fft_fifo_reuse : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
109 | SIGNAL fft_fifo_reuse : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
| 106 |
|
110 | |||
| 107 |
SIGNAL SP_fifo_data |
|
111 | SIGNAL SP_fifo_data : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); | |
| 108 | SIGNAL SP_fifo_ren : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
112 | SIGNAL SP_fifo_ren : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
| 109 |
|
113 | |||
| 110 | SIGNAL fifo_data : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
114 | SIGNAL fifo_data : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
| 111 | SIGNAL fifo_empty : STD_LOGIC; |
|
115 | SIGNAL fifo_empty : STD_LOGIC; | |
| 112 | SIGNAL fifo_ren : STD_LOGIC; |
|
116 | SIGNAL fifo_ren : STD_LOGIC; | |
| @@ -136,6 +140,35 ARCHITECTURE tb OF lpp_top_lfr IS | |||||
| 136 | SIGNAL addr_matrix_f0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
140 | SIGNAL addr_matrix_f0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
| 137 | SIGNAL addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
141 | SIGNAL addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
| 138 | SIGNAL addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
142 | SIGNAL addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
|
143 | ||||
|
|
144 | ----------------------------------------------------------------------------- | |||
|
|
145 | -- | |||
|
|
146 | ----------------------------------------------------------------------------- | |||
|
|
147 | ||||
|
|
148 | CONSTANT nb_snapshot_param_size : INTEGER := 11; | |||
|
|
149 | CONSTANT delta_snapshot_size : INTEGER := 16; | |||
|
|
150 | CONSTANT delta_f2_f0_size : INTEGER := 10; | |||
|
|
151 | CONSTANT delta_f2_f1_size : INTEGER := 10; | |||
|
|
152 | ||||
|
|
153 | SIGNAL waveform_enable_f0 : STD_LOGIC; | |||
|
|
154 | SIGNAL waveform_enable_f1 : STD_LOGIC; | |||
|
|
155 | SIGNAL waveform_enable_f2 : STD_LOGIC; | |||
|
|
156 | SIGNAL waveform_enable_f3 : STD_LOGIC; | |||
|
|
157 | ||||
|
|
158 | SIGNAL waveform_burst_f0 : STD_LOGIC; | |||
|
|
159 | SIGNAL waveform_burst_f1 : STD_LOGIC; | |||
|
|
160 | SIGNAL waveform_burst_f2 : STD_LOGIC; | |||
|
|
161 | ||||
|
|
162 | SIGNAL waveform_nb_snapshot_param : STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0); | |||
|
|
163 | SIGNAL waveform_delta_snapshot : STD_LOGIC_VECTOR(delta_snapshot_size-1 DOWNTO 0); | |||
|
|
164 | SIGNAL waveform_delta_f2_f1 : STD_LOGIC_VECTOR(delta_f2_f1_size-1 DOWNTO 0); | |||
|
|
165 | SIGNAL waveform_delta_f2_f0 : STD_LOGIC_VECTOR(delta_f2_f0_size-1 DOWNTO 0); | |||
|
|
166 | ||||
|
|
167 | SIGNAL data_f0_in_valid : STD_LOGIC; | |||
|
|
168 | SIGNAL data_f0_in_valid_r : STD_LOGIC; | |||
|
|
169 | SIGNAL data_f1_in_valid : STD_LOGIC; | |||
|
|
170 | SIGNAL data_f2_in_valid : STD_LOGIC; | |||
|
|
171 | SIGNAL data_f3_in_valid : STD_LOGIC; | |||
| 139 |
|
172 | |||
| 140 | BEGIN |
|
173 | BEGIN | |
| 141 |
|
174 | |||
| @@ -155,8 +188,7 BEGIN | |||||
| 155 | clk => clk, |
|
188 | clk => clk, | |
| 156 | rstn => rstn, |
|
189 | rstn => rstn, | |
| 157 |
|
190 | |||
| 158 |
sample_f0_ |
|
191 | sample_f0_wen => sample_f0_wen, | |
| 159 | sample_f0_1_wen => sample_f0_1_wen, |
|
|||
| 160 | sample_f0_wdata => sample_f0_wdata, |
|
192 | sample_f0_wdata => sample_f0_wdata, | |
| 161 | sample_f1_wen => sample_f1_wen, |
|
193 | sample_f1_wen => sample_f1_wen, | |
| 162 | sample_f1_wdata => sample_f1_wdata, |
|
194 | sample_f1_wdata => sample_f1_wdata, | |
| @@ -169,7 +201,7 BEGIN | |||||
| 169 | -- FIFO |
|
201 | -- FIFO | |
| 170 | ----------------------------------------------------------------------------- |
|
202 | ----------------------------------------------------------------------------- | |
| 171 |
|
203 | |||
| 172 |
lppFIFO_f0 |
|
204 | lppFIFO_f0 : lppFIFOxN | |
| 173 | GENERIC MAP ( |
|
205 | GENERIC MAP ( | |
| 174 | tech => tech, |
|
206 | tech => tech, | |
| 175 | Data_sz => 16, |
|
207 | Data_sz => 16, | |
| @@ -181,31 +213,12 BEGIN | |||||
| 181 | rclk => clk, |
|
213 | rclk => clk, | |
| 182 | ReUse => (OTHERS => '0'), |
|
214 | ReUse => (OTHERS => '0'), | |
| 183 |
|
215 | |||
| 184 |
wen => sample_f0_ |
|
216 | wen => sample_f0_wen, | |
| 185 |
ren => sample_f0_ |
|
217 | ren => sample_f0_ren, | |
| 186 | wdata => sample_f0_wdata, |
|
218 | wdata => sample_f0_wdata, | |
| 187 |
rdata => sample_f0_ |
|
219 | rdata => sample_f0_rdata, | |
| 188 |
full => sample_f0_ |
|
220 | full => sample_f0_full, | |
| 189 |
empty => sample_f0_ |
|
221 | empty => sample_f0_empty); | |
| 190 |
|
||||
| 191 | lppFIFO_f0_1 : lppFIFOxN |
|
|||
| 192 | GENERIC MAP ( |
|
|||
| 193 | tech => tech, |
|
|||
| 194 | Data_sz => 16, |
|
|||
| 195 | FifoCnt => 5, |
|
|||
| 196 | Enable_ReUse => '0') |
|
|||
| 197 | PORT MAP ( |
|
|||
| 198 | rst => rstn, |
|
|||
| 199 | wclk => clk, |
|
|||
| 200 | rclk => clk, |
|
|||
| 201 | ReUse => (OTHERS => '0'), |
|
|||
| 202 |
|
||||
| 203 | wen => sample_f0_1_wen, |
|
|||
| 204 | ren => sample_f0_1_ren, |
|
|||
| 205 | wdata => sample_f0_wdata, |
|
|||
| 206 | rdata => sample_f0_1_rdata, |
|
|||
| 207 | full => sample_f0_1_full, |
|
|||
| 208 | empty => sample_f0_1_empty); |
|
|||
| 209 |
|
222 | |||
| 210 | lppFIFO_f1 : lppFIFOxN |
|
223 | lppFIFO_f1 : lppFIFOxN | |
| 211 | GENERIC MAP ( |
|
224 | GENERIC MAP ( | |
| @@ -226,7 +239,7 BEGIN | |||||
| 226 | full => sample_f1_full, |
|
239 | full => sample_f1_full, | |
| 227 | empty => sample_f1_empty); |
|
240 | empty => sample_f1_empty); | |
| 228 |
|
241 | |||
| 229 |
lppFIFO_f |
|
242 | lppFIFO_f2 : lppFIFOxN | |
| 230 | GENERIC MAP ( |
|
243 | GENERIC MAP ( | |
| 231 | tech => tech, |
|
244 | tech => tech, | |
| 232 | Data_sz => 16, |
|
245 | Data_sz => 16, | |
| @@ -238,92 +251,91 BEGIN | |||||
| 238 | rclk => clk, |
|
251 | rclk => clk, | |
| 239 | ReUse => (OTHERS => '0'), |
|
252 | ReUse => (OTHERS => '0'), | |
| 240 |
|
253 | |||
| 241 |
wen => sample_f |
|
254 | wen => sample_f2_wen, | |
| 242 |
ren => sample_f |
|
255 | ren => sample_f2_ren, | |
| 243 |
wdata => sample_f |
|
256 | wdata => sample_f2_wdata, | |
| 244 |
rdata => sample_f |
|
257 | rdata => sample_f2_rdata, | |
| 245 |
full => sample_f |
|
258 | full => sample_f2_full, | |
| 246 |
empty => sample_f |
|
259 | empty => sample_f2_empty); | |
| 247 |
|
260 | |||
| 248 | ----------------------------------------------------------------------------- |
|
261 | ----------------------------------------------------------------------------- | |
| 249 | -- SPECTRAL MATRIX |
|
262 | -- SPECTRAL MATRIX | |
| 250 | ----------------------------------------------------------------------------- |
|
263 | ----------------------------------------------------------------------------- | |
| 251 |
sample_f |
|
264 | --sample_f0_ren <= sample_ren(4 DOWNTO 0); | |
| 252 |
sample_f |
|
265 | --sample_f1_ren <= sample_ren(14 DOWNTO 10); | |
| 253 |
sample_f |
|
266 | --sample_f2_ren <= sample_ren(19 DOWNTO 15); | |
| 254 | sample_f3_ren <= sample_ren(19 DOWNTO 15); |
|
|||
| 255 |
|
267 | |||
| 256 | Demultiplex_1 : Demultiplex |
|
268 | --Demultiplex_1 : Demultiplex | |
| 257 | GENERIC MAP ( |
|
269 | -- GENERIC MAP ( | |
| 258 | Data_sz => 16) |
|
270 | -- Data_sz => 16) | |
| 259 | PORT MAP ( |
|
271 | -- PORT MAP ( | |
| 260 |
|
|
272 | -- clk => clk, | |
| 261 | rstn => rstn, |
|
273 | -- rstn => rstn, | |
| 262 |
|
274 | |||
| 263 | Read => demux_ren, |
|
275 | -- Read => demux_ren, | |
| 264 | EmptyF0a => sample_f0_0_empty, |
|
276 | -- EmptyF0a => sample_f0_0_empty, | |
| 265 | EmptyF0b => sample_f0_0_empty, |
|
277 | -- EmptyF0b => sample_f0_0_empty, | |
| 266 | EmptyF1 => sample_f1_empty, |
|
278 | -- EmptyF1 => sample_f1_empty, | |
| 267 | EmptyF2 => sample_f3_empty, |
|
279 | -- EmptyF2 => sample_f3_empty, | |
| 268 | DataF0a => sample_f0_0_rdata, |
|
280 | -- DataF0a => sample_f0_0_rdata, | |
| 269 | DataF0b => sample_f0_1_rdata, |
|
281 | -- DataF0b => sample_f0_1_rdata, | |
| 270 | DataF1 => sample_f1_rdata, |
|
282 | -- DataF1 => sample_f1_rdata, | |
| 271 | DataF2 => sample_f3_rdata, |
|
283 | -- DataF2 => sample_f3_rdata, | |
| 272 | Read_DEMUX => sample_ren, |
|
284 | -- Read_DEMUX => sample_ren, | |
| 273 | Empty => demux_empty, |
|
285 | -- Empty => demux_empty, | |
| 274 | Data => demux_data); |
|
286 | -- Data => demux_data); | |
| 275 |
|
287 | |||
| 276 | FFT_1 : FFT |
|
288 | --FFT_1 : FFT | |
| 277 | GENERIC MAP ( |
|
289 | -- GENERIC MAP ( | |
| 278 | Data_sz => 16, |
|
290 | -- Data_sz => 16, | |
| 279 |
|
|
291 | -- NbData => 256) | |
| 280 | PORT MAP ( |
|
292 | -- PORT MAP ( | |
| 281 | clkm => clk, |
|
293 | -- clkm => clk, | |
| 282 | rstn => rstn, |
|
294 | -- rstn => rstn, | |
| 283 | FifoIN_Empty => demux_empty, |
|
295 | -- FifoIN_Empty => demux_empty, | |
| 284 |
|
|
296 | -- FifoIN_Data => demux_data, | |
| 285 |
FifoOUT_Full => fft_fifo_full, |
|
297 | -- FifoOUT_Full => fft_fifo_full, | |
| 286 |
|
|
298 | -- Read => demux_ren, | |
| 287 |
Write => fft_fifo_wen, |
|
299 | -- Write => fft_fifo_wen, | |
| 288 |
ReUse => fft_fifo_reuse, |
|
300 | -- ReUse => fft_fifo_reuse, | |
| 289 | Data => fft_fifo_data); |
|
301 | -- Data => fft_fifo_data); | |
| 290 |
|
302 | |||
| 291 | lppFIFO_fft : lppFIFOxN |
|
303 | --lppFIFO_fft : lppFIFOxN | |
| 292 | GENERIC MAP ( |
|
304 | -- GENERIC MAP ( | |
| 293 | tech => tech, |
|
305 | -- tech => tech, | |
| 294 | Data_sz => 16, |
|
306 | -- Data_sz => 16, | |
| 295 | FifoCnt => 5, |
|
307 | -- FifoCnt => 5, | |
| 296 | Enable_ReUse => '1') |
|
308 | -- Enable_ReUse => '1') | |
| 297 | PORT MAP ( |
|
309 | -- PORT MAP ( | |
| 298 | rst => rstn, |
|
310 | -- rst => rstn, | |
| 299 |
|
|
311 | -- wclk => clk, | |
| 300 |
|
|
312 | -- rclk => clk, | |
| 301 | ReUse => fft_fifo_reuse, |
|
313 | -- ReUse => fft_fifo_reuse, | |
| 302 | wen => fft_fifo_wen, |
|
314 | -- wen => fft_fifo_wen, | |
| 303 | ren => SP_fifo_ren, |
|
315 | -- ren => SP_fifo_ren, | |
| 304 | wdata => fft_fifo_data, |
|
316 | -- wdata => fft_fifo_data, | |
| 305 | rdata => SP_fifo_data, |
|
317 | -- rdata => SP_fifo_data, | |
| 306 |
|
|
318 | -- full => fft_fifo_full, | |
| 307 | empty => OPEN); |
|
319 | -- empty => OPEN); | |
| 308 |
|
320 | |||
| 309 | MatriceSpectrale_1: MatriceSpectrale |
|
321 | --MatriceSpectrale_1 : MatriceSpectrale | |
| 310 | GENERIC MAP ( |
|
322 | -- GENERIC MAP ( | |
| 311 |
|
|
323 | -- Input_SZ => 16, | |
| 312 | Result_SZ => 32) |
|
324 | -- Result_SZ => 32) | |
| 313 | PORT MAP ( |
|
325 | -- PORT MAP ( | |
| 314 |
clkm |
|
326 | -- clkm => clk, | |
| 315 |
rstn |
|
327 | -- rstn => rstn, | |
| 316 |
|
328 | |||
| 317 |
|
|
329 | -- FifoIN_Full => fft_fifo_full, | |
| 318 | FifoOUT_Full => , -- TODO |
|
330 | -- FifoOUT_Full => , -- TODO | |
| 319 | Data_IN => SP_fifo_data, |
|
331 | -- Data_IN => SP_fifo_data, | |
| 320 | ACQ => , -- TODO |
|
332 | -- ACQ => , -- TODO | |
| 321 | FlagError => , -- TODO |
|
333 | -- FlagError => , -- TODO | |
| 322 | Pong => , -- TODO |
|
334 | -- Pong => , -- TODO | |
| 323 | Write => , -- TODO |
|
335 | -- Write => , -- TODO | |
| 324 | Read => SP_fifo_ren, |
|
336 | -- Read => SP_fifo_ren, | |
| 325 | Data_OUT => ); -- TODO |
|
337 | -- Data_OUT => ); -- TODO | |
| 326 |
|
338 | |||
| 327 |
|
339 | |||
| 328 | ----------------------------------------------------------------------------- |
|
340 | ----------------------------------------------------------------------------- | |
| 329 | -- DMA SPECTRAL MATRIX |
|
341 | -- DMA SPECTRAL MATRIX | |
| @@ -401,11 +413,73 BEGIN | |||||
| 401 | addr_matrix_f2 => addr_matrix_f2); |
|
413 | addr_matrix_f2 => addr_matrix_f2); | |
| 402 |
|
414 | |||
| 403 |
|
415 | |||
|
|
416 | ----------------------------------------------------------------------------- | |||
|
|
417 | -- WAVEFORM | |||
|
|
418 | ----------------------------------------------------------------------------- | |||
|
|
419 | ||||
|
|
420 | ----------------------------------------------------------------------------- | |||
|
|
421 | delay_valid_waveform : PROCESS (clk, rstn) | |||
|
|
422 | BEGIN | |||
|
|
423 | IF rstn = '0' THEN | |||
|
|
424 | data_f0_in_valid <= '0'; | |||
|
|
425 | data_f1_in_valid <= '0'; | |||
|
|
426 | ELSIF clk'EVENT AND clk = '1' THEN | |||
|
|
427 | data_f0_in_valid_r <= NOT sample_f0_wen; | |||
|
|
428 | data_f0_in_valid <= NOT data_f0_in_valid_r; | |||
|
|
429 | data_f1_in_valid <= NOT sample_f1_wen; | |||
|
|
430 | END IF; | |||
|
|
431 | END PROCESS delay_valid_waveform; | |||
|
|
432 | ||||
|
|
433 | data_f2_in_valid <= NOT sample_f2_wen; | |||
|
|
434 | data_f3_in_valid <= NOT sample_f3_wen; | |||
|
|
435 | ||||
|
|
436 | ----------------------------------------------------------------------------- | |||
|
|
437 | lpp_waveform_1 : lpp_waveform | |||
|
|
438 | GENERIC MAP ( | |||
|
|
439 | data_size => 16, | |||
|
|
440 | nb_snapshot_param_size => nb_snapshot_param_size, | |||
|
|
441 | delta_snapshot_size => delta_snapshot_size, | |||
|
|
442 | delta_f2_f0_size => delta_f2_f0_size, | |||
|
|
443 | delta_f2_f1_size => delta_f2_f1_size) | |||
|
|
444 | PORT MAP ( | |||
|
|
445 | clk => clk, | |||
|
|
446 | rstn => rstn, | |||
|
|
447 | ||||
|
|
448 | coarse_time_0 => coarse_time(0), | |||
|
|
449 | delta_snapshot => waveform_delta_snapshot, | |||
|
|
450 | delta_f2_f1 => waveform_delta_f2_f1, | |||
|
|
451 | delta_f2_f0 => waveform_delta_f2_f0, | |||
|
|
452 | ||||
|
|
453 | enable_f0 => waveform_enable_f0, | |||
|
|
454 | enable_f1 => waveform_enable_f1, | |||
|
|
455 | enable_f2 => waveform_enable_f2, | |||
|
|
456 | enable_f3 => waveform_enable_f3, | |||
|
|
457 | ||||
|
|
458 | burst_f0 => waveform_burst_f0, | |||
|
|
459 | burst_f1 => waveform_burst_f1, | |||
|
|
460 | burst_f2 => waveform_burst_f2, | |||
|
|
461 | ||||
|
|
462 | nb_snapshot_param => waveform_nb_snapshot_param, | |||
|
|
463 | ||||
|
|
464 | data_f0_in => sample_f0_wdata, | |||
|
|
465 | data_f1_in => sample_f1_wdata, | |||
|
|
466 | data_f2_in => sample_f2_wdata, | |||
|
|
467 | data_f3_in => sample_f3_wdata, | |||
|
|
468 | ||||
|
|
469 | data_f0_in_valid => data_f0_in_valid, | |||
|
|
470 | data_f1_in_valid => data_f1_in_valid, | |||
|
|
471 | data_f2_in_valid => data_f2_in_valid, | |||
|
|
472 | data_f3_in_valid => data_f3_in_valid); | |||
|
|
473 | ||||
|
|
474 | ----------------------------------------------------------------------------- | |||
|
|
475 | -- | |||
|
|
476 | ----------------------------------------------------------------------------- | |||
|
|
477 | ||||
| 404 | --DONE : add the irq alert for DMA matrix transfert ending |
|
478 | --DONE : add the irq alert for DMA matrix transfert ending | |
| 405 |
|
479 | |||
| 406 | --TODO : add 5 bit register into APB to control the DATA SHIPING |
|
480 | --TODO : add 5 bit register into APB to control the DATA SHIPING | |
| 407 | --TODO : data shiping |
|
481 | --TODO : data shiping | |
| 408 |
|
482 | |||
| 409 | --TODO : add Spectral Matrix (FFT + SP) |
|
483 | --TODO : add Spectral Matrix (FFT + SP) | |
| 410 | --TODO : add DMA for WaveForms Picker |
|
484 | --TODO : add DMA for WaveForms Picker | |
| 411 | --TODO : add APB Reg to control WaveForms Picker |
|
485 | --TODO : add APB Reg to control WaveForms Picker | |
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