diff --git a/designs/Projet-LeonLFR-A3P3K-Sheldon_sim-all/TB_Data_Acquisition.vhd b/designs/Projet-LeonLFR-A3P3K-Sheldon_sim-all/TB_Data_Acquisition.vhd --- a/designs/Projet-LeonLFR-A3P3K-Sheldon_sim-all/TB_Data_Acquisition.vhd +++ b/designs/Projet-LeonLFR-A3P3K-Sheldon_sim-all/TB_Data_Acquisition.vhd @@ -1,8 +1,19 @@ LIBRARY ieee; USE ieee.std_logic_1164.ALL; + LIBRARY lpp; USE lpp.lpp_ad_conv.ALL; USE lpp.lpp_top_lfr_pkg.ALL; +USE lpp.lpp_waveform_pkg.ALL; + +LIBRARY grlib; +USE grlib.amba.ALL; +USE grlib.stdlib.ALL; +USE grlib.devices.ALL; +USE GRLIB.DMA2AHB_Package.ALL; + +LIBRARY techmap; +USE techmap.gencomp.ALL; ------------------------------------------------------------------------------- @@ -25,6 +36,57 @@ ARCHITECTURE tb OF TB_Data_Acquisition I sck : IN STD_LOGIC; sdo : OUT STD_LOGIC); END COMPONENT; + + COMPONENT Top_Data_Acquisition + GENERIC ( + hindex : INTEGER; + nb_burst_available_size : INTEGER := 11; + nb_snapshot_param_size : INTEGER := 11; + delta_snapshot_size : INTEGER := 16; + delta_f2_f0_size : INTEGER := 10; + delta_f2_f1_size : INTEGER := 10; + tech : integer); + PORT ( + cnv_run : IN STD_LOGIC; + cnv : OUT STD_LOGIC; + sck : OUT STD_LOGIC; + sdo : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + cnv_clk : IN STD_LOGIC; + cnv_rstn : IN STD_LOGIC; + clk : IN STD_LOGIC; + rstn : IN STD_LOGIC; + sample_f0_wen : out STD_LOGIC_VECTOR(5 DOWNTO 0); + sample_f0_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); + sample_f1_wen : out STD_LOGIC_VECTOR(5 DOWNTO 0); + sample_f1_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); + sample_f2_wen : out STD_LOGIC_VECTOR(5 DOWNTO 0); + sample_f2_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); + sample_f3_wen : out STD_LOGIC_VECTOR(5 DOWNTO 0); + sample_f3_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); + AHB_Master_In : IN AHB_Mst_In_Type; + AHB_Master_Out : OUT AHB_Mst_Out_Type; + coarse_time_0 : IN STD_LOGIC; + delta_snapshot : IN STD_LOGIC_VECTOR(delta_snapshot_size-1 DOWNTO 0); + delta_f2_f1 : IN STD_LOGIC_VECTOR(delta_f2_f1_size-1 DOWNTO 0); + delta_f2_f0 : IN STD_LOGIC_VECTOR(delta_f2_f0_size-1 DOWNTO 0); + enable_f0 : IN STD_LOGIC; + enable_f1 : IN STD_LOGIC; + enable_f2 : IN STD_LOGIC; + enable_f3 : IN STD_LOGIC; + burst_f0 : IN STD_LOGIC; + burst_f1 : IN STD_LOGIC; + burst_f2 : IN STD_LOGIC; + nb_burst_available : IN STD_LOGIC_VECTOR(nb_burst_available_size-1 DOWNTO 0); + nb_snapshot_param : IN STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0); + status_full : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + status_full_ack : IN STD_LOGIC_VECTOR(3 DOWNTO 0); + status_full_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + status_new_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + addr_data_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + addr_data_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + addr_data_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + addr_data_f3 : IN STD_LOGIC_VECTOR(31 DOWNTO 0)); + END COMPONENT; -- component ports SIGNAL cnv_rstn : STD_LOGIC; @@ -40,17 +102,57 @@ ARCHITECTURE tb OF TB_Data_Acquisition I SIGNAL cnv_clk : STD_LOGIC := '1'; ----------------------------------------------------------------------------- - SIGNAL sample_f0_wen : STD_LOGIC_VECTOR(4 DOWNTO 0); - SIGNAL sample_f0_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); + SIGNAL sample_f0_wen : STD_LOGIC_VECTOR(5 DOWNTO 0); + SIGNAL sample_f0_wdata : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); + ----------------------------------------------------------------------------- + SIGNAL sample_f1_wen : STD_LOGIC_VECTOR(5 DOWNTO 0); + SIGNAL sample_f1_wdata : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); ----------------------------------------------------------------------------- - SIGNAL sample_f1_wen : STD_LOGIC_VECTOR(4 DOWNTO 0); - SIGNAL sample_f1_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); + SIGNAL sample_f2_wen : STD_LOGIC_VECTOR(5 DOWNTO 0); + SIGNAL sample_f2_wdata : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); + ----------------------------------------------------------------------------- + SIGNAL sample_f3_wen : STD_LOGIC_VECTOR(5 DOWNTO 0); + SIGNAL sample_f3_wdata : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); + ----------------------------------------------------------------------------- - SIGNAL sample_f2_wen : STD_LOGIC_VECTOR(4 DOWNTO 0); - SIGNAL sample_f2_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); - ----------------------------------------------------------------------------- - SIGNAL sample_f3_wen : STD_LOGIC_VECTOR(4 DOWNTO 0); - SIGNAL sample_f3_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); + CONSTANT nb_burst_available_size : INTEGER := 11; + CONSTANT nb_snapshot_param_size : INTEGER := 11; + CONSTANT delta_snapshot_size : INTEGER := 16; + CONSTANT delta_f2_f0_size : INTEGER := 10; + CONSTANT delta_f2_f1_size : INTEGER := 10; + + SIGNAL AHB_Master_In : AHB_Mst_In_Type; + SIGNAL AHB_Master_Out : AHB_Mst_Out_Type; + + SIGNAL coarse_time_0 : STD_LOGIC; + SIGNAL coarse_time_0_t : STD_LOGIC := '0'; + SIGNAL coarse_time_0_t2 : STD_LOGIC := '0'; + + SIGNAL delta_snapshot : STD_LOGIC_VECTOR(delta_snapshot_size-1 DOWNTO 0); + SIGNAL delta_f2_f1 : STD_LOGIC_VECTOR(delta_f2_f1_size-1 DOWNTO 0); + SIGNAL delta_f2_f0 : STD_LOGIC_VECTOR(delta_f2_f0_size-1 DOWNTO 0); + + SIGNAL enable_f0 : STD_LOGIC; + SIGNAL enable_f1 : STD_LOGIC; + SIGNAL enable_f2 : STD_LOGIC; + SIGNAL enable_f3 : STD_LOGIC; + + SIGNAL burst_f0 : STD_LOGIC; + SIGNAL burst_f1 : STD_LOGIC; + SIGNAL burst_f2 : STD_LOGIC; + + SIGNAL nb_burst_available : STD_LOGIC_VECTOR(nb_burst_available_size-1 DOWNTO 0); + SIGNAL nb_snapshot_param : STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0); + + SIGNAL status_full : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL status_full_ack : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL status_full_err : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL status_new_err : STD_LOGIC_VECTOR(3 DOWNTO 0); + + SIGNAL addr_data_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0); + SIGNAL addr_data_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0); + SIGNAL addr_data_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0); + SIGNAL addr_data_f3 : STD_LOGIC_VECTOR(31 DOWNTO 0); BEGIN -- tb @@ -108,33 +210,119 @@ BEGIN -- tb end process WaveGen_Proc; ----------------------------------------------------------------------------- - - Top_Data_Acquisition_1: lpp_top_acq + + Top_Data_Acquisition_2: Top_Data_Acquisition + GENERIC MAP ( + hindex => 2, + nb_burst_available_size => nb_burst_available_size, + nb_snapshot_param_size => nb_snapshot_param_size, + tech => 0) PORT MAP ( - cnv_run => run_cnv, - cnv => cnv, - sck => sck, - sdo => sdo, - cnv_clk => cnv_clk, - cnv_rstn => cnv_rstn, - clk => clk, - rstn => rstn, - -- - sample_f0_wen => sample_f0_wen, - sample_f0_wdata => sample_f0_wdata, - -- - sample_f1_wen => sample_f1_wen, - sample_f1_wdata => sample_f1_wdata, - -- - sample_f2_wen => sample_f2_wen, - sample_f2_wdata => sample_f2_wdata, - -- - sample_f3_wen => sample_f3_wen, - sample_f3_wdata => sample_f3_wdata - ); + cnv_run => run_cnv, + cnv => cnv, + sck => sck, + sdo => sdo, + cnv_clk => cnv_clk, + cnv_rstn => cnv_rstn, + clk => clk, + rstn => rstn, + sample_f0_wen => sample_f0_wen, + sample_f0_wdata => sample_f0_wdata, + sample_f1_wen => sample_f1_wen, + sample_f1_wdata => sample_f1_wdata, + sample_f2_wen => sample_f2_wen, + sample_f2_wdata => sample_f2_wdata, + sample_f3_wen => sample_f3_wen, + sample_f3_wdata => sample_f3_wdata, + AHB_Master_In => AHB_Master_In, + AHB_Master_Out => AHB_Master_Out, + coarse_time_0 => coarse_time_0, + delta_snapshot => delta_snapshot, + delta_f2_f1 => delta_f2_f1, + delta_f2_f0 => delta_f2_f0, + enable_f0 => enable_f0, + enable_f1 => enable_f1, + enable_f2 => enable_f2, + enable_f3 => enable_f3, + burst_f0 => burst_f0, + burst_f1 => burst_f1, + burst_f2 => burst_f2, + nb_burst_available => nb_burst_available, + nb_snapshot_param => nb_snapshot_param, + status_full => status_full, + status_full_ack => status_full_ack, + status_full_err => status_full_err, + status_new_err => status_new_err, + addr_data_f0 => addr_data_f0, + addr_data_f1 => addr_data_f1, + addr_data_f2 => addr_data_f2, + addr_data_f3 => addr_data_f3); + + PROCESS (clk, rstn) + BEGIN -- PROCESS + IF rstn = '0' THEN -- asynchronous reset (active low) + enable_f0 <= '0'; + enable_f1 <= '0'; + enable_f2 <= '0'; + enable_f3 <= '0'; + ELSIF clk'event AND clk = '1' THEN -- rising clock edge + enable_f0 <= '1'; --TODO test + enable_f1 <= '1'; + enable_f2 <= '1'; + enable_f3 <= '1'; + END IF; + END PROCESS; + + burst_f0 <= '0'; --TODO test + burst_f1 <= '0'; --TODO test + burst_f2 <= '0'; + + + delta_snapshot <= "0000000000000001"; + --nb_snapshot_param <= "00000001110"; -- 14+1 = 15 + --delta_f2_f0 <= "1010011001";--665 = 14/2*96 -14/2 + --delta_f2_f1 <= "0000100110";-- 38 = 14/2*6 - 14/4 + + -- A redefinir car ca ne tombe pas correctement ... ??? + nb_burst_available <= "00000110010"; -- 3*16 + 2 = 34 + nb_snapshot_param <= "00000001111"; -- x+1 = 16 + delta_f2_f0 <= "1011001000";--712 = x/2*96 -x/2 + delta_f2_f1 <= "0000101001";-- 41 = x/2*6 - x/4 + + addr_data_f0 <= "00000000000000000000000000000000"; + addr_data_f1 <= "00010000000000000000000000000000"; + addr_data_f2 <= "00100000000000000000000000000000"; + addr_data_f3 <= "00110000000000000000000000000000"; + + PROCESS (clk, rstn) + BEGIN -- PROCESS + IF rstn = '0' THEN -- asynchronous reset (active low) + status_full_ack <= (OTHERS => '0'); + ELSIF clk'event AND clk = '1' THEN -- rising clock edge + status_full_ack <= status_full; + END IF; + END PROCESS; + + + coarse_time_0_t <= not coarse_time_0_t after 50 ms; + + PROCESS (clk, rstn) + BEGIN -- PROCESS + IF rstn = '0' THEN -- asynchronous reset (active low) + coarse_time_0_t2 <= '0'; + coarse_time_0 <= '0'; + ELSIF clk'event AND clk = '1' THEN -- rising clock edge + coarse_time_0_t2 <= coarse_time_0_t; + coarse_time_0 <= coarse_time_0_t AND (NOT coarse_time_0_t2); + END IF; + END PROCESS; + + + AHB_Master_In.HGRANT(2) <= '1'; + AHB_Master_In.HREADY <= '1'; - - - + AHB_Master_In.HRESP <= HRESP_OKAY; + + END tb; diff --git a/designs/Projet-LeonLFR-A3P3K-Sheldon_sim-all/Top_Data_Acquisition.vhd b/designs/Projet-LeonLFR-A3P3K-Sheldon_sim-all/Top_Data_Acquisition.vhd --- a/designs/Projet-LeonLFR-A3P3K-Sheldon_sim-all/Top_Data_Acquisition.vhd +++ b/designs/Projet-LeonLFR-A3P3K-Sheldon_sim-all/Top_Data_Acquisition.vhd @@ -1,50 +1,88 @@ LIBRARY ieee; USE ieee.std_logic_1164.ALL; + LIBRARY lpp; USE lpp.lpp_ad_conv.ALL; USE lpp.iir_filter.ALL; USE lpp.FILTERcfg.ALL; USE lpp.lpp_memory.ALL; +USE lpp.lpp_waveform_pkg.ALL; + LIBRARY techmap; USE techmap.gencomp.ALL; ---USE lpp.ALL; + +LIBRARY grlib; +USE grlib.amba.ALL; +USE grlib.stdlib.ALL; +USE grlib.devices.ALL; +USE GRLIB.DMA2AHB_Package.ALL; ENTITY Top_Data_Acquisition IS - generic( - tech : integer := 0 + GENERIC( + hindex : INTEGER := 2; + nb_burst_available_size : INTEGER := 11; + nb_snapshot_param_size : INTEGER := 11; + delta_snapshot_size : INTEGER := 16; + delta_f2_f0_size : INTEGER := 10; + delta_f2_f1_size : INTEGER := 10; + tech : INTEGER := 0 ); PORT ( -- ADS7886 - cnv_run : IN STD_LOGIC; - cnv : OUT STD_LOGIC; - sck : OUT STD_LOGIC; - sdo : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + cnv_run : IN STD_LOGIC; + cnv : OUT STD_LOGIC; + sck : OUT STD_LOGIC; + sdo : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + -- + cnv_clk : IN STD_LOGIC; + cnv_rstn : IN STD_LOGIC; -- - cnv_clk : IN STD_LOGIC; - cnv_rstn : IN STD_LOGIC; + clk : IN STD_LOGIC; + rstn : IN STD_LOGIC; + -- + sample_f0_wen : OUT STD_LOGIC_VECTOR(5 DOWNTO 0); + sample_f0_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); -- - clk : IN STD_LOGIC; - rstn : IN STD_LOGIC; + sample_f1_wen : OUT STD_LOGIC_VECTOR(5 DOWNTO 0); + sample_f1_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); + -- + sample_f2_wen : OUT STD_LOGIC_VECTOR(5 DOWNTO 0); + sample_f2_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); -- - sample_f0_0_ren : IN STD_LOGIC_VECTOR(4 DOWNTO 0); - sample_f0_0_rdata : OUT STD_LOGIC_VECTOR((5*18)-1 DOWNTO 0); - sample_f0_0_full : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); - sample_f0_0_empty : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); - -- - sample_f0_1_ren : IN STD_LOGIC_VECTOR(4 DOWNTO 0); - sample_f0_1_rdata : OUT STD_LOGIC_VECTOR((5*18)-1 DOWNTO 0); - sample_f0_1_full : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); - sample_f0_1_empty : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); - -- - sample_f1_ren : IN STD_LOGIC_VECTOR(4 DOWNTO 0); - sample_f1_rdata : OUT STD_LOGIC_VECTOR((5*18)-1 DOWNTO 0); - sample_f1_full : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); - sample_f1_empty : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); - -- - sample_f3_ren : IN STD_LOGIC_VECTOR(4 DOWNTO 0); - sample_f3_rdata : OUT STD_LOGIC_VECTOR((5*18)-1 DOWNTO 0); - sample_f3_full : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); - sample_f3_empty : OUT STD_LOGIC_VECTOR(4 DOWNTO 0) + sample_f3_wen : OUT STD_LOGIC_VECTOR(5 DOWNTO 0); + sample_f3_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); + + -- AMBA AHB Master Interface + AHB_Master_In : IN AHB_Mst_In_Type; + AHB_Master_Out : OUT AHB_Mst_Out_Type; + + coarse_time_0 : IN STD_LOGIC; + + --config + delta_snapshot : IN STD_LOGIC_VECTOR(delta_snapshot_size-1 DOWNTO 0); + delta_f2_f1 : IN STD_LOGIC_VECTOR(delta_f2_f1_size-1 DOWNTO 0); + delta_f2_f0 : IN STD_LOGIC_VECTOR(delta_f2_f0_size-1 DOWNTO 0); + + enable_f0 : IN STD_LOGIC; + enable_f1 : IN STD_LOGIC; + enable_f2 : IN STD_LOGIC; + enable_f3 : IN STD_LOGIC; + + burst_f0 : IN STD_LOGIC; + burst_f1 : IN STD_LOGIC; + burst_f2 : IN STD_LOGIC; + + nb_burst_available : IN STD_LOGIC_VECTOR(nb_burst_available_size-1 DOWNTO 0); + nb_snapshot_param : IN STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0); + status_full : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + status_full_ack : IN STD_LOGIC_VECTOR(3 DOWNTO 0); + status_full_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + status_new_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); -- New data f(i) before the current data is write by dma + + addr_data_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + addr_data_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + addr_data_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + addr_data_f3 : IN STD_LOGIC_VECTOR(31 DOWNTO 0) ); END Top_Data_Acquisition; @@ -79,49 +117,43 @@ ARCHITECTURE tb OF Top_Data_Acquisition CONSTANT CoefPerCel : INTEGER := 5; CONSTANT Cels_count : INTEGER := 5; - SIGNAL coefs : STD_LOGIC_VECTOR((Coef_SZ*CoefCntPerCel*Cels_count)-1 DOWNTO 0); - SIGNAL coefs_JC : STD_LOGIC_VECTOR((Coef_SZ*CoefPerCel*Cels_count)-1 DOWNTO 0); - SIGNAL sample_filter_in : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0); - SIGNAL sample_filter_out : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0); + SIGNAL coefs : STD_LOGIC_VECTOR((Coef_SZ*CoefCntPerCel*Cels_count)-1 DOWNTO 0); + SIGNAL coefs_v2 : STD_LOGIC_VECTOR((Coef_SZ*CoefPerCel*Cels_count)-1 DOWNTO 0); + SIGNAL sample_filter_in : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0); + SIGNAL sample_filter_out : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0); -- - SIGNAL sample_filter_JC_out_val : STD_LOGIC; - SIGNAL sample_filter_JC_out : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0); + SIGNAL sample_filter_v2_out_val : STD_LOGIC; + SIGNAL sample_filter_v2_out : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0); + SIGNAL sample_filter_v2_out_s : samplT(5 DOWNTO 0, 15 DOWNTO 0); + ----------------------------------------------------------------------------- + SIGNAL sample_f0_val : STD_LOGIC; + SIGNAL sample_f0 : samplT(5 DOWNTO 0, 15 DOWNTO 0); -- - SIGNAL sample_filter_JC_out_r_val : STD_LOGIC; - SIGNAL sample_filter_JC_out_r : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0); - ----------------------------------------------------------------------------- - SIGNAL downsampling_cnt : STD_LOGIC_VECTOR(1 DOWNTO 0); - SIGNAL sample_downsampling_out_val : STD_LOGIC; - SIGNAL sample_downsampling_out : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0); + SIGNAL sample_f1_val : STD_LOGIC; + SIGNAL sample_f1 : samplT(5 DOWNTO 0, 15 DOWNTO 0); -- - SIGNAL sample_f0_val : STD_LOGIC; - SIGNAL sample_f0 : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0); - SIGNAL sample_f0_0_wen : STD_LOGIC_VECTOR(4 DOWNTO 0); - SIGNAL sample_f0_1_wen : STD_LOGIC_VECTOR(4 DOWNTO 0); - SIGNAL sample_f0_wdata : STD_LOGIC_VECTOR((5*18)-1 DOWNTO 0); - -- - SIGNAL sample_f0_0_val : STD_LOGIC; - SIGNAL sample_f0_1_val : STD_LOGIC; - SIGNAL counter_f0 : INTEGER; + SIGNAL sample_f2_val : STD_LOGIC; + SIGNAL sample_f2 : samplT(5 DOWNTO 0, 15 DOWNTO 0); + -- + SIGNAL sample_f3_val : STD_LOGIC; + SIGNAL sample_f3 : samplT(5 DOWNTO 0, 15 DOWNTO 0); + ----------------------------------------------------------------------------- - SIGNAL sample_f1_val : STD_LOGIC; - SIGNAL sample_f1 : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0); - SIGNAL sample_f1_wen : STD_LOGIC_VECTOR(4 DOWNTO 0); - SIGNAL sample_f1_wdata : STD_LOGIC_VECTOR((5*18)-1 DOWNTO 0); - -- - SIGNAL sample_f2_val : STD_LOGIC; - SIGNAL sample_f2 : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0); - -- - SIGNAL sample_f3_val : STD_LOGIC; - SIGNAL sample_f3 : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0); - SIGNAL sample_f3_wen : STD_LOGIC_VECTOR(4 DOWNTO 0); - SIGNAL sample_f3_wdata : STD_LOGIC_VECTOR((5*18)-1 DOWNTO 0); + SIGNAL data_f0_in_valid : STD_LOGIC_VECTOR(159 DOWNTO 0) := (OTHERS => '0'); + SIGNAL data_f1_in_valid : STD_LOGIC_VECTOR(159 DOWNTO 0) := (OTHERS => '0'); + SIGNAL data_f2_in_valid : STD_LOGIC_VECTOR(159 DOWNTO 0) := (OTHERS => '0'); + SIGNAL data_f3_in_valid : STD_LOGIC_VECTOR(159 DOWNTO 0) := (OTHERS => '0'); + ----------------------------------------------------------------------------- + SIGNAL sample_f0_wdata_s : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); + SIGNAL sample_f1_wdata_s : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); + SIGNAL sample_f2_wdata_s : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); + SIGNAL sample_f3_wdata_s : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); BEGIN -- component instantiation ----------------------------------------------------------------------------- - DIGITAL_acquisition : ADS7886_drvr + DIGITAL_acquisition : AD7688_drvr GENERIC MAP ( ChanelCount => ChanelCount, ncycle_cnv_high => ncycle_cnv_high, @@ -159,166 +191,75 @@ BEGIN sample_filter_in(i, 17) <= sample(i)(15); END GENERATE; - --coefs <= CoefsInitValCst; - coefs_JC <= CoefsInitValCst_v2; - - --FILTER : IIR_CEL_CTRLR - -- GENERIC MAP ( - -- tech => 0, - -- Sample_SZ => 18, - -- ChanelsCount => ChanelCount, - -- Coef_SZ => Coef_SZ, - -- CoefCntPerCel => CoefCntPerCel, - -- Cels_count => Cels_count, - -- Mem_use => use_CEL) -- use_CEL for SIMU, use_RAM for synthesis - -- PORT MAP ( - -- reset => rstn, - -- clk => clk, - -- sample_clk => sample_val_delay, - -- sample_in => sample_filter_in, - -- sample_out => sample_filter_out, - -- virg_pos => 7, - -- GOtest => OPEN, - -- coefs => coefs); + --coefs_v2 <= CoefsInitValCst_v2; - IIR_CEL_CTRLR_v2_1 : IIR_CEL_CTRLR_v2 - GENERIC MAP ( - tech => 0, - Mem_use => use_RAM, - Sample_SZ => 18, - Coef_SZ => Coef_SZ, - Coef_Nb => 25, -- TODO - Coef_sel_SZ => 5, -- TODO - Cels_count => Cels_count, - ChanelsCount => ChanelCount) - PORT MAP ( - rstn => rstn, - clk => clk, - virg_pos => 7, - coefs => coefs_JC, - sample_in_val => sample_val_delay, - sample_in => sample_filter_in, - sample_out_val => sample_filter_JC_out_val, - sample_out => sample_filter_JC_out); + --IIR_CEL_CTRLR_v2_1 : IIR_CEL_CTRLR_v2 + -- GENERIC MAP ( + -- tech => 0, + -- Mem_use => use_RAM, + -- Sample_SZ => 18, + -- Coef_SZ => Coef_SZ, + -- Coef_Nb => 25, + -- Coef_sel_SZ => 5, + -- Cels_count => Cels_count, + -- ChanelsCount => ChanelCount) + -- PORT MAP ( + -- rstn => rstn, + -- clk => clk, + -- virg_pos => 7, + -- coefs => coefs_v2, + -- sample_in_val => sample_val_delay, + -- sample_in => sample_filter_in, + -- sample_out_val => sample_filter_v2_out_val, + -- sample_out => sample_filter_v2_out); - ----------------------------------------------------------------------------- - PROCESS (clk, rstn) - BEGIN -- PROCESS - IF rstn = '0' THEN -- asynchronous reset (active low) - sample_filter_JC_out_r_val <= '0'; - rst_all_chanel : FOR I IN ChanelCount-1 DOWNTO 0 LOOP - rst_all_bits : FOR J IN 17 DOWNTO 0 LOOP - sample_filter_JC_out_r(I, J) <= '0'; - END LOOP rst_all_bits; - END LOOP rst_all_chanel; - ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge - sample_filter_JC_out_r_val <= sample_filter_JC_out_val; - IF sample_filter_JC_out_val = '1' THEN - sample_filter_JC_out_r <= sample_filter_JC_out; - END IF; - END IF; - END PROCESS; - + sample_filter_v2_out_val <= sample_val_delay; + + ChanelLoopOut : FOR i IN 0 TO 5 GENERATE + SampleLoopOut : FOR j IN 0 TO 15 GENERATE + --sample_filter_v2_out_s(i, j) <= sample_filter_v2_out(i, j); + sample_filter_v2_out_s(i, j) <= sample_filter_in(i, j); + END GENERATE; + END GENERATE; ----------------------------------------------------------------------------- -- F0 -- @24.576 kHz ----------------------------------------------------------------------------- Downsampling_f0 : Downsampling GENERIC MAP ( - ChanelCount => ChanelCount, - SampleSize => 18, + ChanelCount => 6, + SampleSize => 16, DivideParam => 4) PORT MAP ( clk => clk, rstn => rstn, - sample_in_val => sample_filter_JC_out_val , - sample_in => sample_filter_JC_out, + sample_in_val => sample_filter_v2_out_val, + sample_in => sample_filter_v2_out_s, sample_out_val => sample_f0_val, sample_out => sample_f0); - - all_bit_sample_f0: FOR I IN 17 DOWNTO 0 GENERATE - sample_f0_wdata( I) <= sample_f0(0,I); - sample_f0_wdata(18*1+I) <= sample_f0(1,I); - sample_f0_wdata(18*2+I) <= sample_f0(2,I); - sample_f0_wdata(18*3+I) <= sample_f0(6,I); - sample_f0_wdata(18*4+I) <= sample_f0(7,I); + + all_bit_sample_f0 : FOR I IN 15 DOWNTO 0 GENERATE + sample_f0_wdata_s(I) <= sample_f0(0, I); + sample_f0_wdata_s(16*1+I) <= sample_f0(1, I); + sample_f0_wdata_s(16*2+I) <= sample_f0(2, I); + sample_f0_wdata_s(16*3+I) <= sample_f0(3, I); + sample_f0_wdata_s(16*4+I) <= sample_f0(4, I); + sample_f0_wdata_s(16*5+I) <= sample_f0(5, I); END GENERATE all_bit_sample_f0; - PROCESS (clk, rstn) - BEGIN -- PROCESS - IF rstn = '0' THEN -- asynchronous reset (active low) - counter_f0 <= 0; - ELSIF clk'event AND clk = '1' THEN -- rising clock edge - IF sample_f0_val = '1' THEN - IF counter_f0 = 511 THEN - counter_f0 <= 0; - ELSE - counter_f0 <= counter_f0 + 1; - END IF; - END IF; - END IF; - END PROCESS; - - sample_f0_0_val <= sample_f0_val WHEN counter_f0 < 256 ELSE '0'; - sample_f0_0_wen <= NOT(sample_f0_0_val) & - NOT(sample_f0_0_val) & - NOT(sample_f0_0_val) & - NOT(sample_f0_0_val) & - NOT(sample_f0_0_val); - - lppFIFO_f0_0: lppFIFOxN - GENERIC MAP ( - tech => tech, - Data_sz => 18, - FifoCnt => 5, - Enable_ReUse => '0') - PORT MAP ( - rst => rstn, - wclk => clk, - rclk => clk, - ReUse => (OTHERS => '0'), - - wen => sample_f0_0_wen, - ren => sample_f0_0_ren, - wdata => sample_f0_wdata, - rdata => sample_f0_0_rdata, - full => sample_f0_0_full, - empty => sample_f0_0_empty); - - sample_f0_1_val <= sample_f0_val WHEN counter_f0 > 255 ELSE '0'; - sample_f0_1_wen <= NOT(sample_f0_1_val) & - NOT(sample_f0_1_val) & - NOT(sample_f0_1_val) & - NOT(sample_f0_1_val) & - NOT(sample_f0_1_val); - - lppFIFO_f0_1: lppFIFOxN - GENERIC MAP ( - tech => tech, - Data_sz => 18, - FifoCnt => 5, - Enable_ReUse => '0') - PORT MAP ( - rst => rstn, - wclk => clk, - rclk => clk, - ReUse => (OTHERS => '0'), - - wen => sample_f0_1_wen, - ren => sample_f0_1_ren, - wdata => sample_f0_wdata, - rdata => sample_f0_1_rdata, - full => sample_f0_1_full, - empty => sample_f0_1_empty); + sample_f0_wen <= NOT(sample_f0_val) & + NOT(sample_f0_val) & + NOT(sample_f0_val) & + NOT(sample_f0_val) & + NOT(sample_f0_val) & + NOT(sample_f0_val); - - ----------------------------------------------------------------------------- -- F1 -- @4096 Hz ----------------------------------------------------------------------------- Downsampling_f1 : Downsampling GENERIC MAP ( - ChanelCount => ChanelCount, - SampleSize => 18, + ChanelCount => 6, + SampleSize => 16, DivideParam => 6) PORT MAP ( clk => clk, @@ -328,104 +269,143 @@ BEGIN sample_out_val => sample_f1_val, sample_out => sample_f1); - sample_f1_wen <= NOT(sample_f1_val) & + sample_f1_wen <= NOT(sample_f1_val) & + NOT(sample_f1_val) & NOT(sample_f1_val) & NOT(sample_f1_val) & NOT(sample_f1_val) & NOT(sample_f1_val); - all_bit_sample_f1: FOR I IN 17 DOWNTO 0 GENERATE - sample_f1_wdata( I) <= sample_f1(0,I); - sample_f1_wdata(18*1+I) <= sample_f1(1,I); - sample_f1_wdata(18*2+I) <= sample_f1(2,I); - sample_f1_wdata(18*3+I) <= sample_f1(6,I); - sample_f1_wdata(18*4+I) <= sample_f1(7,I); + all_bit_sample_f1 : FOR I IN 15 DOWNTO 0 GENERATE + sample_f1_wdata_s(I) <= sample_f1(0, I); + sample_f1_wdata_s(16*1+I) <= sample_f1(1, I); + sample_f1_wdata_s(16*2+I) <= sample_f1(2, I); + sample_f1_wdata_s(16*3+I) <= sample_f1(3, I); + sample_f1_wdata_s(16*4+I) <= sample_f1(4, I); + sample_f1_wdata_s(16*5+I) <= sample_f1(5, I); END GENERATE all_bit_sample_f1; - - lppFIFO_f1: lppFIFOxN - GENERIC MAP ( - tech => tech, - Data_sz => 18, - FifoCnt => 5, - Enable_ReUse => '0') - PORT MAP ( - rst => rstn, - wclk => clk, - rclk => clk, - ReUse => (OTHERS => '0'), - - wen => sample_f1_wen, - ren => sample_f1_ren, - wdata => sample_f1_wdata, - rdata => sample_f1_rdata, - full => sample_f1_full, - empty => sample_f1_empty); ----------------------------------------------------------------------------- - -- F2 -- @16 Hz + -- F2 -- @256 Hz ----------------------------------------------------------------------------- Downsampling_f2 : Downsampling GENERIC MAP ( - ChanelCount => ChanelCount, - SampleSize => 18, + ChanelCount => 6, + SampleSize => 16, + DivideParam => 96) + PORT MAP ( + clk => clk, + rstn => rstn, + sample_in_val => sample_f0_val , + sample_in => sample_f0, + sample_out_val => sample_f2_val, + sample_out => sample_f2); + + sample_f2_wen <= NOT(sample_f2_val) & + NOT(sample_f2_val) & + NOT(sample_f2_val) & + NOT(sample_f2_val) & + NOT(sample_f2_val) & + NOT(sample_f2_val); + + all_bit_sample_f2 : FOR I IN 15 DOWNTO 0 GENERATE + sample_f2_wdata_s(I) <= sample_f2(0, I); + sample_f2_wdata_s(16*1+I) <= sample_f2(1, I); + sample_f2_wdata_s(16*2+I) <= sample_f2(2, I); + sample_f2_wdata_s(16*3+I) <= sample_f2(3, I); + sample_f2_wdata_s(16*4+I) <= sample_f2(4, I); + sample_f2_wdata_s(16*5+I) <= sample_f2(5, I); + END GENERATE all_bit_sample_f2; + + ----------------------------------------------------------------------------- + -- F3 -- @16 Hz + ----------------------------------------------------------------------------- + Downsampling_f3 : Downsampling + GENERIC MAP ( + ChanelCount => 6, + SampleSize => 16, DivideParam => 256) PORT MAP ( clk => clk, rstn => rstn, sample_in_val => sample_f1_val , sample_in => sample_f1, - sample_out_val => sample_f2_val, - sample_out => sample_f2); - - ----------------------------------------------------------------------------- - -- F3 -- @256 Hz - ----------------------------------------------------------------------------- - Downsampling_f3 : Downsampling - GENERIC MAP ( - ChanelCount => ChanelCount, - SampleSize => 18, - DivideParam => 96) - PORT MAP ( - clk => clk, - rstn => rstn, - sample_in_val => sample_f0_val , - sample_in => sample_f0, sample_out_val => sample_f3_val, sample_out => sample_f3); - sample_f3_wen <= (NOT sample_f3_val) & + sample_f3_wen <= (NOT sample_f3_val) & + (NOT sample_f3_val) & (NOT sample_f3_val) & (NOT sample_f3_val) & (NOT sample_f3_val) & (NOT sample_f3_val); - all_bit_sample_f3: FOR I IN 17 DOWNTO 0 GENERATE - sample_f3_wdata( I) <= sample_f3(0,I); - sample_f3_wdata(18*1+I) <= sample_f3(1,I); - sample_f3_wdata(18*2+I) <= sample_f3(2,I); - sample_f3_wdata(18*3+I) <= sample_f3(6,I); - sample_f3_wdata(18*4+I) <= sample_f3(7,I); + all_bit_sample_f3 : FOR I IN 15 DOWNTO 0 GENERATE + sample_f3_wdata_s(I) <= sample_f3(0, I); + sample_f3_wdata_s(16*1+I) <= sample_f3(1, I); + sample_f3_wdata_s(16*2+I) <= sample_f3(2, I); + sample_f3_wdata_s(16*3+I) <= sample_f3(3, I); + sample_f3_wdata_s(16*4+I) <= sample_f3(4, I); + sample_f3_wdata_s(16*5+I) <= sample_f3(5, I); END GENERATE all_bit_sample_f3; - - lppFIFO_f3: lppFIFOxN + + lpp_waveform_1 : lpp_waveform GENERIC MAP ( - tech => tech, - Data_sz => 18, - FifoCnt => 5, - Enable_ReUse => '0') + hindex => hindex, + tech => tech, + data_size => 160, + nb_burst_available_size => nb_burst_available_size, + nb_snapshot_param_size => nb_snapshot_param_size, + delta_snapshot_size => delta_snapshot_size, + delta_f2_f0_size => delta_f2_f0_size, + delta_f2_f1_size => delta_f2_f1_size) PORT MAP ( - rst => rstn, - wclk => clk, - rclk => clk, - ReUse => (OTHERS => '0'), - - wen => sample_f3_wen, - ren => sample_f3_ren, - wdata => sample_f3_wdata, - rdata => sample_f3_rdata, - full => sample_f3_full, - empty => sample_f3_empty); + clk => clk, + rstn => rstn, + + AHB_Master_In => AHB_Master_In, + AHB_Master_Out => AHB_Master_Out, + + coarse_time_0 => coarse_time_0, -- IN + delta_snapshot => delta_snapshot, -- IN + delta_f2_f1 => delta_f2_f1, -- IN + delta_f2_f0 => delta_f2_f0, -- IN + enable_f0 => enable_f0, -- IN + enable_f1 => enable_f1, -- IN + enable_f2 => enable_f2, -- IN + enable_f3 => enable_f3, -- IN + burst_f0 => burst_f0, -- IN + burst_f1 => burst_f1, -- IN + burst_f2 => burst_f2, -- IN + nb_burst_available => nb_burst_available, + nb_snapshot_param => nb_snapshot_param, + status_full => status_full, + status_full_ack => status_full_ack, -- IN + status_full_err => status_full_err, + status_new_err => status_new_err, - + addr_data_f0 => addr_data_f0, -- IN + addr_data_f1 => addr_data_f1, -- IN + addr_data_f2 => addr_data_f2, -- IN + addr_data_f3 => addr_data_f3, -- IN + + data_f0_in => data_f0_in_valid, + data_f1_in => data_f1_in_valid, + data_f2_in => data_f2_in_valid, + data_f3_in => data_f3_in_valid, + data_f0_in_valid => sample_f0_val, + data_f1_in_valid => sample_f1_val, + data_f2_in_valid => sample_f2_val, + data_f3_in_valid => sample_f3_val); + + data_f0_in_valid((10*16)-1 DOWNTO (4*16)) <= sample_f0_wdata_s; + data_f1_in_valid((10*16)-1 DOWNTO (4*16)) <= sample_f1_wdata_s; + data_f2_in_valid((10*16)-1 DOWNTO (4*16)) <= sample_f2_wdata_s; + data_f3_in_valid((10*16)-1 DOWNTO (4*16)) <= sample_f3_wdata_s; + + sample_f0_wdata <= sample_f0_wdata_s; + sample_f1_wdata <= sample_f1_wdata_s; + sample_f2_wdata <= sample_f2_wdata_s; + sample_f3_wdata <= sample_f3_wdata_s; END tb; diff --git a/designs/Projet-LeonLFR-A3P3K-Sheldon_sim-all/run_sim_data_acquisition.do b/designs/Projet-LeonLFR-A3P3K-Sheldon_sim-all/run_sim_data_acquisition.do --- a/designs/Projet-LeonLFR-A3P3K-Sheldon_sim-all/run_sim_data_acquisition.do +++ b/designs/Projet-LeonLFR-A3P3K-Sheldon_sim-all/run_sim_data_acquisition.do @@ -45,9 +45,27 @@ vcom -quiet -93 -work lpp ../../lib/lpp/ vcom -quiet -93 -work lpp ../../lib/lpp/lpp_top_lfr/lpp_top_acq.vhd #vcom -quiet -93 -work lpp ../../lib/lpp/lpp_top_lfr/lpp_top_lfr.vhd +vcom -quiet -93 -work lpp ../../lib/lpp/lfr_time_management/lpp_lfr_time_management.vhd +vcom -quiet -93 -work lpp ../../lib/lpp/lfr_time_management/apb_lfr_time_management.vhd +vcom -quiet -93 -work lpp ../../lib/lpp/lfr_time_management/lfr_time_management.vhd + +vcom -quiet -93 -work lpp ../../lib/lpp/lpp_dma/lpp_dma_pkg.vhd + +vcom -quiet -93 -work lpp ../../lib/lpp/lpp_waveform/lpp_waveform_pkg.vhd +vcom -quiet -93 -work lpp ../../lib/lpp/lpp_waveform/lpp_waveform.vhd +vcom -quiet -93 -work lpp ../../lib/lpp/lpp_waveform/lpp_waveform_snapshot_controler.vhd +vcom -quiet -93 -work lpp ../../lib/lpp/lpp_waveform/lpp_waveform_snapshot.vhd +vcom -quiet -93 -work lpp ../../lib/lpp/lpp_waveform/lpp_waveform_burst.vhd +vcom -quiet -93 -work lpp ../../lib/lpp/lpp_waveform/lpp_waveform_dma.vhd +vcom -quiet -93 -work lpp ../../lib/lpp/lpp_waveform/lpp_waveform_dma_send_Nword.vhd +vcom -quiet -93 -work lpp ../../lib/lpp/lpp_waveform/lpp_waveform_dma_selectaddress.vhd +vcom -quiet -93 -work lpp ../../lib/lpp/lpp_waveform/lpp_waveform_dma_genvalid.vhd + +vcom -quiet -93 -work work Top_Data_Acquisition.vhd + vcom -quiet -93 -work work TB_Data_Acquisition.vhd -vsim work.TB_Data_Acquisition +#vsim work.TB_Data_Acquisition #log -r * #do wave_data_acquisition.do diff --git a/designs/Projet-LeonLFR-A3P3K-Sheldon_sim-all/run_sim_waveform_picker.do b/designs/Projet-LeonLFR-A3P3K-Sheldon_sim-all/run_sim_waveform_picker.do new file mode 100644 --- /dev/null +++ b/designs/Projet-LeonLFR-A3P3K-Sheldon_sim-all/run_sim_waveform_picker.do @@ -0,0 +1,80 @@ + +vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/general_purpose.vhd +vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/SYNC_FF.vhd +vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/MUXN.vhd +vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/MUX2.vhd +vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/REG.vhd +vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/MAC.vhd +vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/MAC_CONTROLER.vhd +vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/MAC_REG.vhd +vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/MAC_MUX.vhd +vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/MAC_MUX2.vhd +vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/Shifter.vhd +vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/MULTIPLIER.vhd +vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/ADDER.vhd +vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/ALU.vhd +vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/ADDRcntr.vhd + +vcom -quiet -93 -work lpp ../../lib/lpp/dsp/iir_filter/iir_filter.vhd +vcom -quiet -93 -work lpp ../../lib/lpp/dsp/iir_filter/FILTERcfg.vhd +vcom -quiet -93 -work lpp ../../lib/lpp/dsp/iir_filter/RAM_CEL.vhd +vcom -quiet -93 -work lpp ../../lib/lpp/dsp/iir_filter/RAM_CEL_N.vhd +vcom -quiet -93 -work lpp ../../lib/lpp/dsp/iir_filter/RAM_CTRLR2.vhd +#vcom -quiet -93 -work lpp ../../lib/lpp/dsp/iir_filter/IIR_CEL_CTRLR.vhd + +vcom -quiet -93 -work lpp ../../lib/lpp/dsp/iir_filter/RAM_CTRLR_v2.vhd +vcom -quiet -93 -work lpp ../../lib/lpp/dsp/iir_filter/IIR_CEL_CTRLR_v2_DATAFLOW.vhd +vcom -quiet -93 -work lpp ../../lib/lpp/dsp/iir_filter/IIR_CEL_CTRLR_v2_CONTROL.vhd +vcom -quiet -93 -work lpp ../../lib/lpp/dsp/iir_filter/IIR_CEL_CTRLR_v2.vhd + +vcom -quiet -93 -work lpp ../../lib/lpp/lpp_memory/lpp_memory.vhd +vcom -quiet -93 -work lpp ../../lib/lpp/lpp_memory/lpp_FIFO.vhd +vcom -quiet -93 -work lpp ../../lib/lpp/lpp_memory/lppFIFOxN.vhd + +vcom -quiet -93 -work lpp ../../lib/lpp/dsp/lpp_downsampling/Downsampling.vhd + +vcom -quiet -93 -work lpp e:/opt/tortoiseHG_vhdlib/lib/lpp/lpp_top_lfr/lpp_top_lfr_pkg.vhd +vcom -quiet -93 -work lpp e:/opt/tortoiseHG_vhdlib/lib/lpp/lpp_top_lfr/lpp_top_acq.vhd + +vcom -quiet -93 -work lpp ../../lib/lpp/lpp_ad_Conv/lpp_ad_conv.vhd +vcom -quiet -93 -work lpp ../../lib/lpp/lpp_ad_Conv/AD7688_drvr.vhd +vcom -quiet -93 -work lpp ../../lib/lpp/lpp_ad_Conv/TestModule_ADS7886.vhd + + +vcom -quiet -93 -work lpp ../../lib/lpp/lpp_top_lfr/lpp_top_lfr_pkg.vhd +vcom -quiet -93 -work lpp ../../lib/lpp/lpp_top_lfr/lpp_top_acq.vhd +#vcom -quiet -93 -work lpp ../../lib/lpp/lpp_top_lfr/lpp_top_lfr.vhd + +vcom -quiet -93 -work lpp ../../lib/lpp/lfr_time_management/lpp_lfr_time_management.vhd +vcom -quiet -93 -work lpp ../../lib/lpp/lfr_time_management/apb_lfr_time_management.vhd +vcom -quiet -93 -work lpp ../../lib/lpp/lfr_time_management/lfr_time_management.vhd + +vcom -quiet -93 -work lpp ../../lib/lpp/lpp_dma/lpp_dma_pkg.vhd + +vcom -quiet -93 -work lpp ../../lib/lpp/lpp_waveform/lpp_waveform_pkg.vhd +vcom -quiet -93 -work lpp ../../lib/lpp/lpp_waveform/lpp_waveform.vhd +vcom -quiet -93 -work lpp ../../lib/lpp/lpp_waveform/lpp_waveform_snapshot_controler.vhd +vcom -quiet -93 -work lpp ../../lib/lpp/lpp_waveform/lpp_waveform_snapshot.vhd +vcom -quiet -93 -work lpp ../../lib/lpp/lpp_waveform/lpp_waveform_burst.vhd + +vcom -quiet -93 -work lpp ../../lib/lpp/lpp_waveform/lpp_waveform_fifo_arbiter.vhd +vcom -quiet -93 -work lpp ../../lib/lpp/lpp_waveform/lpp_waveform_fifo_ctrl.vhd +vcom -quiet -93 -work lpp ../../lib/lpp/lpp_waveform/lpp_waveform_fifo.vhd + +vcom -quiet -93 -work lpp ../../lib/lpp/lpp_waveform/lpp_waveform_dma.vhd +vcom -quiet -93 -work lpp ../../lib/lpp/lpp_dma/lpp_dma_pkg.vhd +vcom -quiet -93 -work lpp ../../lib/lpp/lpp_dma/lpp_dma_send_1word.vhd +vcom -quiet -93 -work lpp ../../lib/lpp/lpp_dma/lpp_dma_send_16word.vhd +#vcom -quiet -93 -work lpp ../../lib/lpp/lpp_waveform/lpp_waveform_dma_send_Nword.vhd +vcom -quiet -93 -work lpp ../../lib/lpp/lpp_waveform/lpp_waveform_dma_selectaddress.vhd +vcom -quiet -93 -work lpp ../../lib/lpp/lpp_waveform/lpp_waveform_dma_genvalid.vhd + +vcom -quiet -93 -work work Top_Data_Acquisition.vhd + +vcom -quiet -93 -work work TB_Data_Acquisition.vhd + +vsim work.TB_Data_Acquisition + +log -r * +do wave_waveform_picker.do +run 5 ms diff --git a/designs/Projet-LeonLFR-A3P3K-Sheldon_sim-all/wave_waveform_picker.do b/designs/Projet-LeonLFR-A3P3K-Sheldon_sim-all/wave_waveform_picker.do new file mode 100644 --- /dev/null +++ b/designs/Projet-LeonLFR-A3P3K-Sheldon_sim-all/wave_waveform_picker.do @@ -0,0 +1,364 @@ +onerror {resume} +quietly WaveActivateNextPane {} 0 +add wave -noupdate /tb_data_acquisition/sample_f0_wen +add wave -noupdate /tb_data_acquisition/sample_f0_wdata +add wave -noupdate /tb_data_acquisition/sample_f1_wen +add wave -noupdate /tb_data_acquisition/sample_f1_wdata +add wave -noupdate /tb_data_acquisition/sample_f2_wen +add wave -noupdate /tb_data_acquisition/sample_f2_wdata +add wave -noupdate /tb_data_acquisition/sample_f3_wen +add wave -noupdate /tb_data_acquisition/sample_f3_wdata +add wave -noupdate -group TOP /tb_data_acquisition/ahb_master_in +add wave -noupdate -group TOP /tb_data_acquisition/ahb_master_out +add wave -noupdate -group TOP /tb_data_acquisition/coarse_time_0 +add wave -noupdate -group TOP /tb_data_acquisition/coarse_time_0_t +add wave -noupdate -group TOP /tb_data_acquisition/coarse_time_0_t2 +add wave -noupdate -group TOP /tb_data_acquisition/delta_snapshot +add wave -noupdate -group TOP /tb_data_acquisition/delta_f2_f1 +add wave -noupdate -group TOP /tb_data_acquisition/delta_f2_f0 +add wave -noupdate -group TOP /tb_data_acquisition/enable_f0 +add wave -noupdate -group TOP /tb_data_acquisition/enable_f1 +add wave -noupdate -group TOP /tb_data_acquisition/enable_f2 +add wave -noupdate -group TOP /tb_data_acquisition/enable_f3 +add wave -noupdate -group TOP /tb_data_acquisition/burst_f0 +add wave -noupdate -group TOP /tb_data_acquisition/burst_f1 +add wave -noupdate -group TOP /tb_data_acquisition/burst_f2 +add wave -noupdate -group TOP /tb_data_acquisition/nb_snapshot_param +add wave -noupdate -group TOP /tb_data_acquisition/status_full +add wave -noupdate -group TOP /tb_data_acquisition/status_full_ack +add wave -noupdate -group TOP /tb_data_acquisition/status_full_err +add wave -noupdate -group TOP /tb_data_acquisition/status_new_err +add wave -noupdate -group TOP /tb_data_acquisition/addr_data_f0 +add wave -noupdate -group TOP /tb_data_acquisition/addr_data_f1 +add wave -noupdate -group TOP /tb_data_acquisition/addr_data_f2 +add wave -noupdate -group TOP /tb_data_acquisition/addr_data_f3 +add wave -noupdate -group waveform_picker /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/data_size +add wave -noupdate -group waveform_picker /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/nb_snapshot_param_size +add wave -noupdate -group waveform_picker /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/delta_snapshot_size +add wave -noupdate -group waveform_picker /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/delta_f2_f0_size +add wave -noupdate -group waveform_picker /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/delta_f2_f1_size +add wave -noupdate -group waveform_picker /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/clk +add wave -noupdate -group waveform_picker /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/rstn +add wave -noupdate -group waveform_picker /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/ahb_master_in +add wave -noupdate -group waveform_picker /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/ahb_master_out +add wave -noupdate -group waveform_picker /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/coarse_time_0 +add wave -noupdate -group waveform_picker /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/delta_snapshot +add wave -noupdate -group waveform_picker /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/delta_f2_f1 +add wave -noupdate -group waveform_picker /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/delta_f2_f0 +add wave -noupdate -group waveform_picker /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/enable_f0 +add wave -noupdate -group waveform_picker /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/enable_f1 +add wave -noupdate -group waveform_picker /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/enable_f2 +add wave -noupdate -group waveform_picker /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/enable_f3 +add wave -noupdate -group waveform_picker /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/burst_f0 +add wave -noupdate -group waveform_picker /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/burst_f1 +add wave -noupdate -group waveform_picker /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/burst_f2 +add wave -noupdate -group waveform_picker /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/nb_snapshot_param +add wave -noupdate -group waveform_picker /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/status_full +add wave -noupdate -group waveform_picker /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/status_full_ack +add wave -noupdate -group waveform_picker /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/status_full_err +add wave -noupdate -group waveform_picker /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/status_new_err +add wave -noupdate -group waveform_picker /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/addr_data_f0 +add wave -noupdate -group waveform_picker /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/addr_data_f1 +add wave -noupdate -group waveform_picker /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/addr_data_f2 +add wave -noupdate -group waveform_picker /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/addr_data_f3 +add wave -noupdate -group waveform_picker /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/data_f0_in +add wave -noupdate -group waveform_picker /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/data_f1_in +add wave -noupdate -group waveform_picker /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/data_f2_in +add wave -noupdate -group waveform_picker /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/data_f3_in +add wave -noupdate -group waveform_picker /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/data_f0_in_valid +add wave -noupdate -group waveform_picker /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/data_f1_in_valid +add wave -noupdate -group waveform_picker /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/data_f2_in_valid +add wave -noupdate -group waveform_picker /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/data_f3_in_valid +add wave -noupdate -group waveform_picker /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/start_snapshot_f0 +add wave -noupdate -group waveform_picker /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/start_snapshot_f1 +add wave -noupdate -group waveform_picker /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/start_snapshot_f2 +add wave -noupdate -group waveform_picker /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/data_f0_out +add wave -noupdate -group waveform_picker /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/data_f1_out +add wave -noupdate -group waveform_picker /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/data_f2_out +add wave -noupdate -group waveform_picker /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/data_f3_out +add wave -noupdate -group waveform_picker /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/data_f0_out_valid +add wave -noupdate -group waveform_picker /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/data_f1_out_valid +add wave -noupdate -group waveform_picker /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/data_f2_out_valid +add wave -noupdate -group waveform_picker /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/data_f3_out_valid +add wave -noupdate -group waveform_controler /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_snapshot_controler_1/clk +add wave -noupdate -group waveform_controler /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_snapshot_controler_1/rstn +add wave -noupdate -group waveform_controler /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_snapshot_controler_1/delta_snapshot +add wave -noupdate -group waveform_controler /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_snapshot_controler_1/delta_f2_f1 +add wave -noupdate -group waveform_controler /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_snapshot_controler_1/delta_f2_f0 +add wave -noupdate -group waveform_controler /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_snapshot_controler_1/coarse_time_0 +add wave -noupdate -group waveform_controler /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_snapshot_controler_1/data_f2_in_valid +add wave -noupdate -group waveform_controler /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_snapshot_controler_1/start_snapshot_f0 +add wave -noupdate -group waveform_controler /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_snapshot_controler_1/start_snapshot_f1 +add wave -noupdate -group waveform_controler /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_snapshot_controler_1/start_snapshot_f2 +add wave -noupdate -group waveform_controler /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_snapshot_controler_1/counter_delta_snapshot +add wave -noupdate -group waveform_controler /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_snapshot_controler_1/coarse_time_0_r +add wave -noupdate -group waveform_snapshot_f0 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_snapshot_f0/clk +add wave -noupdate -group waveform_snapshot_f0 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_snapshot_f0/rstn +add wave -noupdate -group waveform_snapshot_f0 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_snapshot_f0/enable +add wave -noupdate -group waveform_snapshot_f0 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_snapshot_f0/burst_enable +add wave -noupdate -group waveform_snapshot_f0 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_snapshot_f0/nb_snapshot_param +add wave -noupdate -group waveform_snapshot_f0 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_snapshot_f0/start_snapshot +add wave -noupdate -group waveform_snapshot_f0 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_snapshot_f0/data_in +add wave -noupdate -group waveform_snapshot_f0 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_snapshot_f0/data_in_valid +add wave -noupdate -group waveform_snapshot_f0 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_snapshot_f0/data_out +add wave -noupdate -group waveform_snapshot_f0 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_snapshot_f0/data_out_valid +add wave -noupdate -group waveform_snapshot_f0 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_snapshot_f0/counter_points_snapshot +add wave -noupdate -group waveform_snapshot_f1 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_snapshot_f1/clk +add wave -noupdate -group waveform_snapshot_f1 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_snapshot_f1/rstn +add wave -noupdate -group waveform_snapshot_f1 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_snapshot_f1/enable +add wave -noupdate -group waveform_snapshot_f1 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_snapshot_f1/burst_enable +add wave -noupdate -group waveform_snapshot_f1 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_snapshot_f1/nb_snapshot_param +add wave -noupdate -group waveform_snapshot_f1 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_snapshot_f1/start_snapshot +add wave -noupdate -group waveform_snapshot_f1 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_snapshot_f1/data_in +add wave -noupdate -group waveform_snapshot_f1 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_snapshot_f1/data_in_valid +add wave -noupdate -group waveform_snapshot_f1 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_snapshot_f1/data_out +add wave -noupdate -group waveform_snapshot_f1 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_snapshot_f1/data_out_valid +add wave -noupdate -group waveform_snapshot_f1 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_snapshot_f1/counter_points_snapshot +add wave -noupdate -group waveform_snapshot_f2 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_snapshot_f2/clk +add wave -noupdate -group waveform_snapshot_f2 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_snapshot_f2/rstn +add wave -noupdate -group waveform_snapshot_f2 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_snapshot_f2/enable +add wave -noupdate -group waveform_snapshot_f2 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_snapshot_f2/burst_enable +add wave -noupdate -group waveform_snapshot_f2 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_snapshot_f2/nb_snapshot_param +add wave -noupdate -group waveform_snapshot_f2 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_snapshot_f2/start_snapshot +add wave -noupdate -group waveform_snapshot_f2 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_snapshot_f2/data_in +add wave -noupdate -group waveform_snapshot_f2 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_snapshot_f2/data_in_valid +add wave -noupdate -group waveform_snapshot_f2 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_snapshot_f2/data_out +add wave -noupdate -group waveform_snapshot_f2 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_snapshot_f2/data_out_valid +add wave -noupdate -group waveform_snapshot_f2 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_snapshot_f2/counter_points_snapshot +add wave -noupdate -group waveform_burst____f3 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_burst_f3/clk +add wave -noupdate -group waveform_burst____f3 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_burst_f3/rstn +add wave -noupdate -group waveform_burst____f3 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_burst_f3/enable +add wave -noupdate -group waveform_burst____f3 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_burst_f3/data_in +add wave -noupdate -group waveform_burst____f3 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_burst_f3/data_in_valid +add wave -noupdate -group waveform_burst____f3 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_burst_f3/data_out +add wave -noupdate -group waveform_burst____f3 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_burst_f3/data_out_valid +add wave -noupdate -group GEN_VALID_F0 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/all_input_valid(0)/lpp_waveform_dma_gen_valid_i/hclk +add wave -noupdate -group GEN_VALID_F0 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/all_input_valid(0)/lpp_waveform_dma_gen_valid_i/hresetn +add wave -noupdate -group GEN_VALID_F0 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/all_input_valid(0)/lpp_waveform_dma_gen_valid_i/valid_in +add wave -noupdate -group GEN_VALID_F0 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/all_input_valid(0)/lpp_waveform_dma_gen_valid_i/ack_in +add wave -noupdate -group GEN_VALID_F0 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/all_input_valid(0)/lpp_waveform_dma_gen_valid_i/valid_out +add wave -noupdate -group GEN_VALID_F0 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/all_input_valid(0)/lpp_waveform_dma_gen_valid_i/error +add wave -noupdate -group GEN_VALID_F1 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/all_input_valid(1)/lpp_waveform_dma_gen_valid_i/hclk +add wave -noupdate -group GEN_VALID_F1 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/all_input_valid(1)/lpp_waveform_dma_gen_valid_i/hresetn +add wave -noupdate -group GEN_VALID_F1 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/all_input_valid(1)/lpp_waveform_dma_gen_valid_i/valid_in +add wave -noupdate -group GEN_VALID_F1 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/all_input_valid(1)/lpp_waveform_dma_gen_valid_i/ack_in +add wave -noupdate -group GEN_VALID_F1 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/all_input_valid(1)/lpp_waveform_dma_gen_valid_i/valid_out +add wave -noupdate -group GEN_VALID_F1 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/all_input_valid(1)/lpp_waveform_dma_gen_valid_i/error +add wave -noupdate -group GEN_VALID_F1 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/all_input_valid(1)/lpp_waveform_dma_gen_valid_i/state +add wave -noupdate -group GEN_VALID_F2 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/all_input_valid(2)/lpp_waveform_dma_gen_valid_i/hclk +add wave -noupdate -group GEN_VALID_F2 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/all_input_valid(2)/lpp_waveform_dma_gen_valid_i/hresetn +add wave -noupdate -group GEN_VALID_F2 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/all_input_valid(2)/lpp_waveform_dma_gen_valid_i/valid_in +add wave -noupdate -group GEN_VALID_F2 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/all_input_valid(2)/lpp_waveform_dma_gen_valid_i/ack_in +add wave -noupdate -group GEN_VALID_F2 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/all_input_valid(2)/lpp_waveform_dma_gen_valid_i/valid_out +add wave -noupdate -group GEN_VALID_F2 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/all_input_valid(2)/lpp_waveform_dma_gen_valid_i/error +add wave -noupdate -group GEN_VALID_F2 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/all_input_valid(2)/lpp_waveform_dma_gen_valid_i/state +add wave -noupdate -group GEN_VALID_F3 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/all_input_valid(3)/lpp_waveform_dma_gen_valid_i/hclk +add wave -noupdate -group GEN_VALID_F3 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/all_input_valid(3)/lpp_waveform_dma_gen_valid_i/hresetn +add wave -noupdate -group GEN_VALID_F3 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/all_input_valid(3)/lpp_waveform_dma_gen_valid_i/valid_in +add wave -noupdate -group GEN_VALID_F3 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/all_input_valid(3)/lpp_waveform_dma_gen_valid_i/ack_in +add wave -noupdate -group GEN_VALID_F3 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/all_input_valid(3)/lpp_waveform_dma_gen_valid_i/valid_out +add wave -noupdate -group GEN_VALID_F3 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/all_input_valid(3)/lpp_waveform_dma_gen_valid_i/error +add wave -noupdate -group GEN_VALID_F3 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/all_input_valid(3)/lpp_waveform_dma_gen_valid_i/state +add wave -noupdate /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/valid_in +add wave -noupdate /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/valid_out +add wave -noupdate /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/valid_ack +add wave -noupdate /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/status_new_err +add wave -noupdate -group FIFO_ARB /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_arbiter_1/clk +add wave -noupdate -group FIFO_ARB /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_arbiter_1/rstn +add wave -noupdate -group FIFO_ARB /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_arbiter_1/state +add wave -noupdate -group FIFO_ARB /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_arbiter_1/data_f0_valid +add wave -noupdate -group FIFO_ARB /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_arbiter_1/data_f1_valid +add wave -noupdate -group FIFO_ARB /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_arbiter_1/data_f2_valid +add wave -noupdate -group FIFO_ARB /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_arbiter_1/data_f3_valid +add wave -noupdate -group FIFO_ARB /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_arbiter_1/data_valid_ack +add wave -noupdate -group FIFO_ARB -radix hexadecimal /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_arbiter_1/data_f0 +add wave -noupdate -group FIFO_ARB -radix hexadecimal /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_arbiter_1/data_f1 +add wave -noupdate -group FIFO_ARB -radix hexadecimal /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_arbiter_1/data_f2 +add wave -noupdate -group FIFO_ARB -radix hexadecimal /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_arbiter_1/data_f3 +add wave -noupdate -group FIFO_ARB /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_arbiter_1/ready +add wave -noupdate -group FIFO_ARB /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_arbiter_1/time_wen +add wave -noupdate -group FIFO_ARB /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_arbiter_1/data_wen +add wave -noupdate -group FIFO_ARB -radix hexadecimal /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_arbiter_1/data +add wave -noupdate -group FIFO_ARB /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_arbiter_1/data_valid_and_ready +add wave -noupdate -group FIFO_ARB -radix hexadecimal /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_arbiter_1/data_selected +add wave -noupdate -group FIFO_ARB /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_arbiter_1/data_valid_selected +add wave -noupdate -group FIFO_ARB /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_arbiter_1/data_ready_to_go +add wave -noupdate -group FIFO_ARB -radix hexadecimal /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_arbiter_1/data_temp +add wave -noupdate -group FIFO_ARB /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_arbiter_1/time_en_temp +add wave -noupdate -expand -group FIFO -expand -group {IN - OUT} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/rstn +add wave -noupdate -expand -group FIFO -expand -group {IN - OUT} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/ready +add wave -noupdate -expand -group FIFO -expand -group {IN - OUT} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/time_ren +add wave -noupdate -expand -group FIFO -expand -group {IN - OUT} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/data_ren +add wave -noupdate -expand -group FIFO -expand -group {IN - OUT} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/rdata +add wave -noupdate -expand -group FIFO -expand -group {IN - OUT} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/time_wen +add wave -noupdate -expand -group FIFO -expand -group {IN - OUT} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/data_wen +add wave -noupdate -expand -group FIFO -expand -group {IN - OUT} -radix hexadecimal /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/wdata +add wave -noupdate -expand -group FIFO -expand -group read -radix hexadecimal -subitemconfig {/tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/time_mem_addr_r(3) {-radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/time_mem_addr_r(2) {-radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/time_mem_addr_r(1) {-radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/time_mem_addr_r(0) {-radix hexadecimal}} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/time_mem_addr_r +add wave -noupdate -expand -group FIFO -expand -group read /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/data_mem_addr_r +add wave -noupdate -expand -group FIFO -expand -group read /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/time_mem_ren +add wave -noupdate -expand -group FIFO -expand -group read /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/data_mem_ren +add wave -noupdate -expand -group FIFO -expand -group read /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/data_addr_r +add wave -noupdate -expand -group FIFO -expand -group read /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/ren +add wave -noupdate -expand -group FIFO -group write /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/data_mem_addr_w +add wave -noupdate -expand -group FIFO -group write /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/time_mem_addr_w +add wave -noupdate -expand -group FIFO -group write /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/data_mem_wen +add wave -noupdate -expand -group FIFO -group write /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/time_mem_wen +add wave -noupdate -expand -group FIFO -group write -radix unsigned /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/data_addr_w +add wave -noupdate -expand -group FIFO -group write /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/wen +add wave -noupdate -radix hexadecimal -subitemconfig {/tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(0) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(1) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(2) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(3) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(4) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(5) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(6) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(7) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(8) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(9) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(10) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(11) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(12) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(13) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(14) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(15) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(16) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(17) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(18) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(19) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(20) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(21) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(22) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(23) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(24) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(25) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(26) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(27) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(28) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(29) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(30) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(31) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(32) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(33) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(34) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(35) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(36) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(37) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(38) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(39) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(40) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(41) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(42) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(43) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(44) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(45) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(46) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(47) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(48) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(49) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(50) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(51) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(52) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(53) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(54) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(55) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(56) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(57) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(58) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(59) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(60) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(61) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(62) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(63) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(64) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(65) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(66) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(67) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(68) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(69) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(70) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(71) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(72) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(73) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(74) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(75) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(76) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(77) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(78) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(79) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(80) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(81) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(82) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(83) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(84) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(85) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(86) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(87) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(88) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(89) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(90) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(91) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(92) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(93) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(94) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(95) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(96) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(97) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(98) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(99) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(100) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(101) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(102) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(103) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(104) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(105) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(106) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(107) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(108) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(109) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(110) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(111) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(112) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(113) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(114) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(115) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(116) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(117) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(118) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(119) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(120) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(121) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(122) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(123) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(124) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(125) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(126) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(127) {-height 15 -radix hexadecimal}} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd +add wave -noupdate -expand -group DMA -expand -group INOUT /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/pp_waveform_dma_1/hclk +add wave -noupdate -expand -group DMA -expand -group INOUT /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/pp_waveform_dma_1/hresetn +add wave -noupdate -expand -group DMA -expand -group INOUT /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/pp_waveform_dma_1/ahb_master_in +add wave -noupdate -expand -group DMA -expand -group INOUT -subitemconfig {/tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/pp_waveform_dma_1/ahb_master_out.haddr {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/pp_waveform_dma_1/ahb_master_out.hwdata {-height 15 -radix hexadecimal}} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/pp_waveform_dma_1/ahb_master_out +add wave -noupdate -expand -group DMA -expand -group INOUT -expand -group FIFO_interface /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/pp_waveform_dma_1/data_ready +add wave -noupdate -expand -group DMA -expand -group INOUT -expand -group FIFO_interface /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/pp_waveform_dma_1/data +add wave -noupdate -expand -group DMA -expand -group INOUT -expand -group FIFO_interface /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/pp_waveform_dma_1/data_data_ren +add wave -noupdate -expand -group DMA -expand -group INOUT -expand -group FIFO_interface /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/pp_waveform_dma_1/data_time_ren +add wave -noupdate -expand -group DMA -expand -group INOUT -expand -group REG_CONFIG -radix unsigned /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/pp_waveform_dma_1/nb_burst_available +add wave -noupdate -expand -group DMA -expand -group INOUT -expand -group REG_CONFIG /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/pp_waveform_dma_1/addr_data_f0 +add wave -noupdate -expand -group DMA -expand -group INOUT -expand -group REG_CONFIG /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/pp_waveform_dma_1/addr_data_f1 +add wave -noupdate -expand -group DMA -expand -group INOUT -expand -group REG_CONFIG /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/pp_waveform_dma_1/addr_data_f2 +add wave -noupdate -expand -group DMA -expand -group INOUT -expand -group REG_CONFIG /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/pp_waveform_dma_1/addr_data_f3 +add wave -noupdate -expand -group DMA -expand -group INOUT /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/pp_waveform_dma_1/status_full +add wave -noupdate -expand -group DMA -expand -group INOUT /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/pp_waveform_dma_1/status_full_ack +add wave -noupdate -expand -group DMA -expand -group INOUT /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/pp_waveform_dma_1/status_full_err +add wave -noupdate -expand -group DMA /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/pp_waveform_dma_1/dmain +add wave -noupdate -expand -group DMA /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/pp_waveform_dma_1/dmaout +add wave -noupdate -expand -group DMA /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/pp_waveform_dma_1/state +add wave -noupdate -expand -group DMA /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/pp_waveform_dma_1/sel_data_s +add wave -noupdate -expand -group DMA /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/pp_waveform_dma_1/sel_data +add wave -noupdate -expand -group DMA /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/pp_waveform_dma_1/update +add wave -noupdate -expand -group DMA /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/pp_waveform_dma_1/time_select +add wave -noupdate -expand -group DMA /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/pp_waveform_dma_1/time_write +add wave -noupdate -expand -group DMA /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/pp_waveform_dma_1/time_already_send +add wave -noupdate -expand -group DMA /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/pp_waveform_dma_1/time_already_send_s +add wave -noupdate -expand -group DMA /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/pp_waveform_dma_1/time_dmai +add wave -noupdate -expand -group DMA /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/pp_waveform_dma_1/time_send +add wave -noupdate -expand -group DMA /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/pp_waveform_dma_1/time_send_ok +add wave -noupdate -expand -group DMA /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/pp_waveform_dma_1/time_send_ko +add wave -noupdate -expand -group DMA /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/pp_waveform_dma_1/time_fifo_ren +add wave -noupdate -expand -group DMA /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/pp_waveform_dma_1/time_ren +add wave -noupdate -expand -group DMA /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/pp_waveform_dma_1/data_dmai +add wave -noupdate -expand -group DMA /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/pp_waveform_dma_1/data_send +add wave -noupdate -expand -group DMA /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/pp_waveform_dma_1/data_send_ok +add wave -noupdate -expand -group DMA /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/pp_waveform_dma_1/data_send_ko +add wave -noupdate -expand -group DMA /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/pp_waveform_dma_1/data_fifo_ren +add wave -noupdate -expand -group DMA /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/pp_waveform_dma_1/data_ren +add wave -noupdate -expand -group DMA /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/pp_waveform_dma_1/data_address +add wave -noupdate -expand -group DMA /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/pp_waveform_dma_1/update_and_sel +add wave -noupdate -expand -group DMA /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/pp_waveform_dma_1/addr_data_reg_vector +add wave -noupdate -expand -group DMA /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/pp_waveform_dma_1/addr_data_vector +add wave -noupdate -expand -group DMA /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/pp_waveform_dma_1/send_16_3_time +add wave -noupdate -expand -group DMA /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/pp_waveform_dma_1/count_send_time +add wave -noupdate /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/ren +add wave -noupdate /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/wen +add wave -noupdate -group fifo_ctrl_time_3 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_time(3)/lpp_waveform_fifo_ctrl_time/clk +add wave -noupdate -group fifo_ctrl_time_3 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_time(3)/lpp_waveform_fifo_ctrl_time/rstn +add wave -noupdate -group fifo_ctrl_time_3 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_time(3)/lpp_waveform_fifo_ctrl_time/ren +add wave -noupdate -group fifo_ctrl_time_3 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_time(3)/lpp_waveform_fifo_ctrl_time/wen +add wave -noupdate -group fifo_ctrl_time_3 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_time(3)/lpp_waveform_fifo_ctrl_time/mem_re +add wave -noupdate -group fifo_ctrl_time_3 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_time(3)/lpp_waveform_fifo_ctrl_time/mem_we +add wave -noupdate -group fifo_ctrl_time_3 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_time(3)/lpp_waveform_fifo_ctrl_time/mem_addr_ren +add wave -noupdate -group fifo_ctrl_time_3 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_time(3)/lpp_waveform_fifo_ctrl_time/mem_addr_wen +add wave -noupdate -group fifo_ctrl_time_3 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_time(3)/lpp_waveform_fifo_ctrl_time/ready +add wave -noupdate -expand -group fifo_ctrl_time_2 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_time(2)/lpp_waveform_fifo_ctrl_time/clk +add wave -noupdate -expand -group fifo_ctrl_time_2 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_time(2)/lpp_waveform_fifo_ctrl_time/rstn +add wave -noupdate -expand -group fifo_ctrl_time_2 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_time(2)/lpp_waveform_fifo_ctrl_time/ren +add wave -noupdate -expand -group fifo_ctrl_time_2 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_time(2)/lpp_waveform_fifo_ctrl_time/wen +add wave -noupdate -expand -group fifo_ctrl_time_2 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_time(2)/lpp_waveform_fifo_ctrl_time/mem_re +add wave -noupdate -expand -group fifo_ctrl_time_2 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_time(2)/lpp_waveform_fifo_ctrl_time/mem_we +add wave -noupdate -expand -group fifo_ctrl_time_2 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_time(2)/lpp_waveform_fifo_ctrl_time/mem_addr_ren +add wave -noupdate -expand -group fifo_ctrl_time_2 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_time(2)/lpp_waveform_fifo_ctrl_time/mem_addr_wen +add wave -noupdate -expand -group fifo_ctrl_time_2 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_time(2)/lpp_waveform_fifo_ctrl_time/ready +add wave -noupdate -expand -group fifo_ctrl_time_1 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_time(1)/lpp_waveform_fifo_ctrl_time/clk +add wave -noupdate -expand -group fifo_ctrl_time_1 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_time(1)/lpp_waveform_fifo_ctrl_time/rstn +add wave -noupdate -expand -group fifo_ctrl_time_1 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_time(1)/lpp_waveform_fifo_ctrl_time/ren +add wave -noupdate -expand -group fifo_ctrl_time_1 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_time(1)/lpp_waveform_fifo_ctrl_time/wen +add wave -noupdate -expand -group fifo_ctrl_time_1 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_time(1)/lpp_waveform_fifo_ctrl_time/mem_re +add wave -noupdate -expand -group fifo_ctrl_time_1 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_time(1)/lpp_waveform_fifo_ctrl_time/mem_we +add wave -noupdate -expand -group fifo_ctrl_time_1 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_time(1)/lpp_waveform_fifo_ctrl_time/mem_addr_ren +add wave -noupdate -expand -group fifo_ctrl_time_1 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_time(1)/lpp_waveform_fifo_ctrl_time/mem_addr_wen +add wave -noupdate -expand -group fifo_ctrl_time_1 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_time(1)/lpp_waveform_fifo_ctrl_time/ready +add wave -noupdate -group fifo_ctrl_time_0 -group IN /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_time(0)/lpp_waveform_fifo_ctrl_time/clk +add wave -noupdate -group fifo_ctrl_time_0 -group IN /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_time(0)/lpp_waveform_fifo_ctrl_time/rstn +add wave -noupdate -group fifo_ctrl_time_0 -group IN /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_time(0)/lpp_waveform_fifo_ctrl_time/ren +add wave -noupdate -group fifo_ctrl_time_0 -group IN /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_time(0)/lpp_waveform_fifo_ctrl_time/wen +add wave -noupdate -group fifo_ctrl_time_0 -group OUT /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_time(0)/lpp_waveform_fifo_ctrl_time/mem_re +add wave -noupdate -group fifo_ctrl_time_0 -group OUT /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_time(0)/lpp_waveform_fifo_ctrl_time/mem_we +add wave -noupdate -group fifo_ctrl_time_0 -group OUT /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_time(0)/lpp_waveform_fifo_ctrl_time/mem_addr_ren +add wave -noupdate -group fifo_ctrl_time_0 -group OUT /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_time(0)/lpp_waveform_fifo_ctrl_time/mem_addr_wen +add wave -noupdate -group fifo_ctrl_time_0 -group OUT /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_time(0)/lpp_waveform_fifo_ctrl_time/ready +add wave -noupdate -group fifo_ctrl_time_0 -group internal /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_time(0)/lpp_waveform_fifo_ctrl_time/sfull +add wave -noupdate -group fifo_ctrl_time_0 -group internal /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_time(0)/lpp_waveform_fifo_ctrl_time/sfull_s +add wave -noupdate -group fifo_ctrl_time_0 -group internal /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_time(0)/lpp_waveform_fifo_ctrl_time/sempty_s +add wave -noupdate -group fifo_ctrl_time_0 -group internal /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_time(0)/lpp_waveform_fifo_ctrl_time/sempty +add wave -noupdate -group fifo_ctrl_time_0 -group internal /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_time(0)/lpp_waveform_fifo_ctrl_time/sren +add wave -noupdate -group fifo_ctrl_time_0 -group internal /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_time(0)/lpp_waveform_fifo_ctrl_time/swen +add wave -noupdate -group fifo_ctrl_time_0 -group internal /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_time(0)/lpp_waveform_fifo_ctrl_time/sre +add wave -noupdate -group fifo_ctrl_time_0 -group internal /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_time(0)/lpp_waveform_fifo_ctrl_time/swe +add wave -noupdate -group fifo_ctrl_time_0 -group internal /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_time(0)/lpp_waveform_fifo_ctrl_time/waddr_vect +add wave -noupdate -group fifo_ctrl_time_0 -group internal /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_time(0)/lpp_waveform_fifo_ctrl_time/raddr_vect +add wave -noupdate -group fifo_ctrl_time_0 -group internal /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_time(0)/lpp_waveform_fifo_ctrl_time/waddr_vect_s +add wave -noupdate -group fifo_ctrl_time_0 -group internal /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_time(0)/lpp_waveform_fifo_ctrl_time/raddr_vect_s +add wave -noupdate -group fifo_ctrl_time_0 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_time(0)/lpp_waveform_fifo_ctrl_time/clk +add wave -noupdate -group fifo_ctrl_time_0 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_time(0)/lpp_waveform_fifo_ctrl_time/rstn +add wave -noupdate -group fifo_ctrl_time_0 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_time(0)/lpp_waveform_fifo_ctrl_time/ren +add wave -noupdate -group fifo_ctrl_time_0 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_time(0)/lpp_waveform_fifo_ctrl_time/wen +add wave -noupdate -group fifo_ctrl_time_0 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_time(0)/lpp_waveform_fifo_ctrl_time/mem_re +add wave -noupdate -group fifo_ctrl_time_0 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_time(0)/lpp_waveform_fifo_ctrl_time/mem_we +add wave -noupdate -group fifo_ctrl_time_0 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_time(0)/lpp_waveform_fifo_ctrl_time/mem_addr_ren +add wave -noupdate -group fifo_ctrl_time_0 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_time(0)/lpp_waveform_fifo_ctrl_time/mem_addr_wen +add wave -noupdate -group fifo_ctrl_time_0 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_time(0)/lpp_waveform_fifo_ctrl_time/ready +add wave -noupdate -group fifo_ctrl_data_3 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_data(3)/lpp_waveform_fifo_ctrl_data/clk +add wave -noupdate -group fifo_ctrl_data_3 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_data(3)/lpp_waveform_fifo_ctrl_data/rstn +add wave -noupdate -group fifo_ctrl_data_3 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_data(3)/lpp_waveform_fifo_ctrl_data/ren +add wave -noupdate -group fifo_ctrl_data_3 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_data(3)/lpp_waveform_fifo_ctrl_data/wen +add wave -noupdate -group fifo_ctrl_data_3 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_data(3)/lpp_waveform_fifo_ctrl_data/mem_re +add wave -noupdate -group fifo_ctrl_data_3 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_data(3)/lpp_waveform_fifo_ctrl_data/mem_we +add wave -noupdate -group fifo_ctrl_data_3 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_data(3)/lpp_waveform_fifo_ctrl_data/mem_addr_ren +add wave -noupdate -group fifo_ctrl_data_3 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_data(3)/lpp_waveform_fifo_ctrl_data/mem_addr_wen +add wave -noupdate -group fifo_ctrl_data_3 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_data(3)/lpp_waveform_fifo_ctrl_data/ready +add wave -noupdate -expand -group fifo_ctrl_data_2 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_data(2)/lpp_waveform_fifo_ctrl_data/clk +add wave -noupdate -expand -group fifo_ctrl_data_2 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_data(2)/lpp_waveform_fifo_ctrl_data/rstn +add wave -noupdate -expand -group fifo_ctrl_data_2 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_data(2)/lpp_waveform_fifo_ctrl_data/ren +add wave -noupdate -expand -group fifo_ctrl_data_2 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_data(2)/lpp_waveform_fifo_ctrl_data/wen +add wave -noupdate -expand -group fifo_ctrl_data_2 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_data(2)/lpp_waveform_fifo_ctrl_data/mem_re +add wave -noupdate -expand -group fifo_ctrl_data_2 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_data(2)/lpp_waveform_fifo_ctrl_data/mem_we +add wave -noupdate -expand -group fifo_ctrl_data_2 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_data(2)/lpp_waveform_fifo_ctrl_data/mem_addr_ren +add wave -noupdate -expand -group fifo_ctrl_data_2 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_data(2)/lpp_waveform_fifo_ctrl_data/mem_addr_wen +add wave -noupdate -expand -group fifo_ctrl_data_2 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_data(2)/lpp_waveform_fifo_ctrl_data/ready +add wave -noupdate -group fifo_ctrl_data_1 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_data(1)/lpp_waveform_fifo_ctrl_data/clk +add wave -noupdate -group fifo_ctrl_data_1 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_data(1)/lpp_waveform_fifo_ctrl_data/rstn +add wave -noupdate -group fifo_ctrl_data_1 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_data(1)/lpp_waveform_fifo_ctrl_data/ren +add wave -noupdate -group fifo_ctrl_data_1 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_data(1)/lpp_waveform_fifo_ctrl_data/wen +add wave -noupdate -group fifo_ctrl_data_1 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_data(1)/lpp_waveform_fifo_ctrl_data/mem_re +add wave -noupdate -group fifo_ctrl_data_1 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_data(1)/lpp_waveform_fifo_ctrl_data/mem_we +add wave -noupdate -group fifo_ctrl_data_1 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_data(1)/lpp_waveform_fifo_ctrl_data/mem_addr_ren +add wave -noupdate -group fifo_ctrl_data_1 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_data(1)/lpp_waveform_fifo_ctrl_data/mem_addr_wen +add wave -noupdate -group fifo_ctrl_data_1 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_data(1)/lpp_waveform_fifo_ctrl_data/ready +add wave -noupdate -group fifo_ctrl_data_0 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_data(0)/lpp_waveform_fifo_ctrl_data/clk +add wave -noupdate -group fifo_ctrl_data_0 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_data(0)/lpp_waveform_fifo_ctrl_data/rstn +add wave -noupdate -group fifo_ctrl_data_0 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_data(0)/lpp_waveform_fifo_ctrl_data/ren +add wave -noupdate -group fifo_ctrl_data_0 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_data(0)/lpp_waveform_fifo_ctrl_data/wen +add wave -noupdate -group fifo_ctrl_data_0 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_data(0)/lpp_waveform_fifo_ctrl_data/mem_re +add wave -noupdate -group fifo_ctrl_data_0 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_data(0)/lpp_waveform_fifo_ctrl_data/mem_we +add wave -noupdate -group fifo_ctrl_data_0 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_data(0)/lpp_waveform_fifo_ctrl_data/mem_addr_ren +add wave -noupdate -group fifo_ctrl_data_0 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_data(0)/lpp_waveform_fifo_ctrl_data/mem_addr_wen +add wave -noupdate -group fifo_ctrl_data_0 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_data(0)/lpp_waveform_fifo_ctrl_data/ready +TreeUpdate [SetDefaultTree] +WaveRestoreCursors {{Cursor 1} {70458134452 ps} 0} +configure wave -namecolwidth 842 +configure wave -valuecolwidth 100 +configure wave -justifyvalue left +configure wave -signalnamewidth 0 +configure wave -snapdistance 10 +configure wave -datasetprefix 0 +configure wave -rowmargin 4 +configure wave -childrowmargin 2 +configure wave -gridoffset 0 +configure wave -gridperiod 1 +configure wave -griddelta 40 +configure wave -timeline 0 +configure wave -timelineunits ns +update +WaveRestoreZoom {70455153866 ps} {70464281299 ps} diff --git a/lib/lpp/lfr_time_management/apb_lfr_time_management.vhd b/lib/lpp/lfr_time_management/apb_lfr_time_management.vhd --- a/lib/lpp/lfr_time_management/apb_lfr_time_management.vhd +++ b/lib/lpp/lfr_time_management/apb_lfr_time_management.vhd @@ -17,158 +17,158 @@ -- Additional Comments: -- ---------------------------------------------------------------------------------- -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.NUMERIC_STD.ALL; -library grlib; -use grlib.amba.all; -use grlib.stdlib.all; -use grlib.devices.all; -library lpp; -use lpp.apb_devices_list.all; -use lpp.lpp_lfr_time_management.all; +LIBRARY IEEE; +USE IEEE.STD_LOGIC_1164.ALL; +USE IEEE.NUMERIC_STD.ALL; +LIBRARY grlib; +USE grlib.amba.ALL; +USE grlib.stdlib.ALL; +USE grlib.devices.ALL; +LIBRARY lpp; +USE lpp.apb_devices_list.ALL; +USE lpp.lpp_lfr_time_management.ALL; -entity apb_lfr_time_management is +ENTITY apb_lfr_time_management IS -generic( - pindex : integer := 0; --! APB slave index - paddr : integer := 0; --! ADDR field of the APB BAR - pmask : integer := 16#fff#; --! MASK field of the APB BAR - pirq : integer := 0; --! 2 consecutive IRQ lines are used - masterclk : integer := 25000000; --! master clock in Hz - otherclk : integer := 49152000; --! other clock in Hz - finetimeclk : integer := 65536 --! divided clock used for the fine time counter - ); + GENERIC( + pindex : INTEGER := 0; --! APB slave index + paddr : INTEGER := 0; --! ADDR field of the APB BAR + pmask : INTEGER := 16#fff#; --! MASK field of the APB BAR + pirq : INTEGER := 0; --! 2 consecutive IRQ lines are used + masterclk : INTEGER := 25000000; --! master clock in Hz + otherclk : INTEGER := 49152000; --! other clock in Hz + finetimeclk : INTEGER := 65536 --! divided clock used for the fine time counter + ); -Port ( - clk25MHz : in STD_LOGIC; --! Clock - clk49_152MHz : in STD_LOGIC; --! secondary clock - resetn : in STD_LOGIC; --! Reset - grspw_tick : in STD_LOGIC; --! grspw signal asserted when a valid time-code is received - apbi : in apb_slv_in_type; --! APB slave input signals - apbo : out apb_slv_out_type; --! APB slave output signals - coarse_time : out std_logic_vector(31 downto 0); --! coarse time - fine_time : out std_logic_vector(31 downto 0) --! fine time - ); - -end apb_lfr_time_management; + PORT ( + clk25MHz : IN STD_LOGIC; --! Clock + clk49_152MHz : IN STD_LOGIC; --! secondary clock + resetn : IN STD_LOGIC; --! Reset + grspw_tick : IN STD_LOGIC; --! grspw signal asserted when a valid time-code is received + apbi : IN apb_slv_in_type; --! APB slave input signals + apbo : OUT apb_slv_out_type; --! APB slave output signals + coarse_time : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); --! coarse time + fine_time : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) --! fine time + ); -architecture Behavioral of apb_lfr_time_management is +END apb_lfr_time_management; -constant REVISION : integer := 1; +ARCHITECTURE Behavioral OF apb_lfr_time_management IS + + CONSTANT REVISION : INTEGER := 1; --! the following types are defined in the grlib amba package --! subtype amba_config_word is std_logic_vector(31 downto 0); --! type apb_config_type is array (0 to NAPBCFG-1) of amba_config_word; -constant pconfig : apb_config_type := ( + CONSTANT pconfig : apb_config_type := ( --! 0 => ahb_device_reg (VENDOR_LPP, LPP_ROTARY, 0, REVISION, 0), - 0 => ahb_device_reg (19, 14, 0, REVISION, pirq), - 1 => apb_iobar(paddr, pmask)); + 0 => ahb_device_reg (19, 14, 0, REVISION, pirq), + 1 => apb_iobar(paddr, pmask)); -type apb_lfr_time_management_Reg is record - ctrl : std_logic_vector(31 downto 0); - coarse_time_load : std_logic_vector(31 downto 0); - coarse_time : std_logic_vector(31 downto 0); - fine_time : std_logic_vector(31 downto 0); - next_commutation : std_logic_vector(31 downto 0); -end record; + TYPE apb_lfr_time_management_Reg IS RECORD + ctrl : STD_LOGIC_VECTOR(31 DOWNTO 0); + coarse_time_load : STD_LOGIC_VECTOR(31 DOWNTO 0); + coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0); + fine_time : STD_LOGIC_VECTOR(31 DOWNTO 0); + next_commutation : STD_LOGIC_VECTOR(31 DOWNTO 0); + END RECORD; -signal r : apb_lfr_time_management_Reg; -signal Rdata : std_logic_vector(31 downto 0); -signal force_tick : std_logic; -signal previous_force_tick : std_logic; -signal soft_tick : std_logic; -signal reset_next_commutation : std_logic; + SIGNAL r : apb_lfr_time_management_Reg; + SIGNAL Rdata : STD_LOGIC_VECTOR(31 DOWNTO 0); + SIGNAL force_tick : STD_LOGIC; + SIGNAL previous_force_tick : STD_LOGIC; + SIGNAL soft_tick : STD_LOGIC; + SIGNAL reset_next_commutation : STD_LOGIC; -begin +BEGIN -lfrtimemanagement0: lfr_time_management -generic map(masterclk => masterclk, timeclk => otherclk, finetimeclk => finetimeclk) -Port map( master_clock => clk25MHz, time_clock => clk49_152MHz, resetn => resetn, - grspw_tick => grspw_tick, soft_tick => soft_tick, - coarse_time_load => r.coarse_time_load, coarse_time => r.coarse_time, fine_time => r.fine_time, - next_commutation => r.next_commutation, reset_next_commutation => reset_next_commutation, - irq1 => apbo.pirq(pirq), irq2 => apbo.pirq(pirq+1) ); + lfrtimemanagement0 : lfr_time_management + GENERIC MAP(masterclk => masterclk, timeclk => otherclk, finetimeclk => finetimeclk) + PORT MAP(master_clock => clk25MHz, time_clock => clk49_152MHz, resetn => resetn, + grspw_tick => grspw_tick, soft_tick => soft_tick, + coarse_time_load => r.coarse_time_load, coarse_time => r.coarse_time, fine_time => r.fine_time, + next_commutation => r.next_commutation, reset_next_commutation => reset_next_commutation, + irq1 => apbo.pirq(pirq), irq2 => apbo.pirq(pirq+1)); -process(resetn,clk25MHz, reset_next_commutation) -begin + PROCESS(resetn, clk25MHz, reset_next_commutation) + BEGIN - if resetn = '0' then - r.coarse_time_load <= x"80000000"; - r.ctrl <= x"00000000"; - r.next_commutation <= x"ffffffff"; - force_tick <= '0'; - previous_force_tick <= '0'; - soft_tick <= '0'; + IF resetn = '0' THEN + r.coarse_time_load <= x"80000000"; + r.ctrl <= x"00000000"; + r.next_commutation <= x"ffffffff"; + force_tick <= '0'; + previous_force_tick <= '0'; + soft_tick <= '0'; - elsif reset_next_commutation = '1' then - r.next_commutation <= x"ffffffff"; + ELSIF reset_next_commutation = '1' THEN + r.next_commutation <= x"ffffffff"; - elsif clk25MHz'event and clk25MHz = '1' then + ELSIF clk25MHz'EVENT AND clk25MHz = '1' THEN - previous_force_tick <= force_tick; - force_tick <= r.ctrl(0); - if (previous_force_tick = '0') and (force_tick = '1') then - soft_tick <= '1'; - else - soft_tick <= '0'; - end if; - + previous_force_tick <= force_tick; + force_tick <= r.ctrl(0); + IF (previous_force_tick = '0') AND (force_tick = '1') THEN + soft_tick <= '1'; + ELSE + soft_tick <= '0'; + END IF; + --APB Write OP - if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then - case apbi.paddr(7 downto 2) is - when "000000" => - r.ctrl <= apbi.pwdata(31 downto 0); - when "000001" => - r.coarse_time_load <= apbi.pwdata(31 downto 0); - when "000100" => - r.next_commutation <= apbi.pwdata(31 downto 0); - when others => - r.coarse_time_load <= x"00000000"; - end case; - elsif r.ctrl(0) = '1' then - r.ctrl(0) <= '0'; - end if; + IF (apbi.psel(pindex) AND apbi.penable AND apbi.pwrite) = '1' THEN + CASE apbi.paddr(7 DOWNTO 2) IS + WHEN "000000" => + r.ctrl <= apbi.pwdata(31 DOWNTO 0); + WHEN "000001" => + r.coarse_time_load <= apbi.pwdata(31 DOWNTO 0); + WHEN "000100" => + r.next_commutation <= apbi.pwdata(31 DOWNTO 0); + WHEN OTHERS => + r.coarse_time_load <= x"00000000"; + END CASE; + ELSIF r.ctrl(0) = '1' THEN + r.ctrl(0) <= '0'; + END IF; --APB READ OP - if (apbi.psel(pindex) and (not apbi.pwrite)) = '1' then - case apbi.paddr(7 downto 2) is - when "000000" => - Rdata(31 downto 24) <= r.ctrl(31 downto 24); - Rdata(23 downto 16) <= r.ctrl(23 downto 16); - Rdata(15 downto 8) <= r.ctrl(15 downto 8); - Rdata(7 downto 0) <= r.ctrl(7 downto 0); - when "000001" => - Rdata(31 downto 24) <= r.coarse_time_load(31 downto 24); - Rdata(23 downto 16) <= r.coarse_time_load(23 downto 16); - Rdata(15 downto 8) <= r.coarse_time_load(15 downto 8); - Rdata(7 downto 0) <= r.coarse_time_load(7 downto 0); - when "000010" => - Rdata(31 downto 24) <= r.coarse_time(31 downto 24); - Rdata(23 downto 16) <= r.coarse_time(23 downto 16); - Rdata(15 downto 8) <= r.coarse_time(15 downto 8); - Rdata(7 downto 0) <= r.coarse_time(7 downto 0); - when "000011" => - Rdata(31 downto 24) <= r.fine_time(31 downto 24); - Rdata(23 downto 16) <= r.fine_time(23 downto 16); - Rdata(15 downto 8) <= r.fine_time(15 downto 8); - Rdata(7 downto 0) <= r.fine_time(7 downto 0); - when "000100" => - Rdata(31 downto 24) <= r.next_commutation(31 downto 24); - Rdata(23 downto 16) <= r.next_commutation(23 downto 16); - Rdata(15 downto 8) <= r.next_commutation(15 downto 8); - Rdata(7 downto 0) <= r.next_commutation(7 downto 0); - when others => - Rdata(31 downto 0) <= x"00000000"; - end case; - end if; + IF (apbi.psel(pindex) AND (NOT apbi.pwrite)) = '1' THEN + CASE apbi.paddr(7 DOWNTO 2) IS + WHEN "000000" => + Rdata(31 DOWNTO 24) <= r.ctrl(31 DOWNTO 24); + Rdata(23 DOWNTO 16) <= r.ctrl(23 DOWNTO 16); + Rdata(15 DOWNTO 8) <= r.ctrl(15 DOWNTO 8); + Rdata(7 DOWNTO 0) <= r.ctrl(7 DOWNTO 0); + WHEN "000001" => + Rdata(31 DOWNTO 24) <= r.coarse_time_load(31 DOWNTO 24); + Rdata(23 DOWNTO 16) <= r.coarse_time_load(23 DOWNTO 16); + Rdata(15 DOWNTO 8) <= r.coarse_time_load(15 DOWNTO 8); + Rdata(7 DOWNTO 0) <= r.coarse_time_load(7 DOWNTO 0); + WHEN "000010" => + Rdata(31 DOWNTO 24) <= r.coarse_time(31 DOWNTO 24); + Rdata(23 DOWNTO 16) <= r.coarse_time(23 DOWNTO 16); + Rdata(15 DOWNTO 8) <= r.coarse_time(15 DOWNTO 8); + Rdata(7 DOWNTO 0) <= r.coarse_time(7 DOWNTO 0); + WHEN "000011" => + Rdata(31 DOWNTO 24) <= r.fine_time(31 DOWNTO 24); + Rdata(23 DOWNTO 16) <= r.fine_time(23 DOWNTO 16); + Rdata(15 DOWNTO 8) <= r.fine_time(15 DOWNTO 8); + Rdata(7 DOWNTO 0) <= r.fine_time(7 DOWNTO 0); + WHEN "000100" => + Rdata(31 DOWNTO 24) <= r.next_commutation(31 DOWNTO 24); + Rdata(23 DOWNTO 16) <= r.next_commutation(23 DOWNTO 16); + Rdata(15 DOWNTO 8) <= r.next_commutation(15 DOWNTO 8); + Rdata(7 DOWNTO 0) <= r.next_commutation(7 DOWNTO 0); + WHEN OTHERS => + Rdata(31 DOWNTO 0) <= x"00000000"; + END CASE; + END IF; - end if; - apbo.pconfig <= pconfig; -end process; + END IF; + apbo.pconfig <= pconfig; + END PROCESS; -apbo.prdata <= Rdata when apbi.penable = '1' ; -coarse_time <= r.coarse_time; -fine_time <= r.fine_time; + apbo.prdata <= Rdata WHEN apbi.penable = '1'; + coarse_time <= r.coarse_time; + fine_time <= r.fine_time; -end Behavioral; \ No newline at end of file +END Behavioral; diff --git a/lib/lpp/lpp_top_lfr/lpp_top_acq.vhd b/lib/lpp/lpp_top_lfr/lpp_top_acq.vhd --- a/lib/lpp/lpp_top_lfr/lpp_top_acq.vhd +++ b/lib/lpp/lpp_top_lfr/lpp_top_acq.vhd @@ -245,7 +245,7 @@ BEGIN GENERIC MAP ( ChanelCount => ChanelCount, SampleSize => 18, - DivideParam => 256) + DivideParam => 96) PORT MAP ( clk => clk, rstn => rstn, @@ -275,7 +275,7 @@ BEGIN GENERIC MAP ( ChanelCount => ChanelCount, SampleSize => 18, - DivideParam => 96) + DivideParam => 256) PORT MAP ( clk => clk, rstn => rstn, diff --git a/lib/lpp/lpp_top_lfr/lpp_top_lfr.vhd b/lib/lpp/lpp_top_lfr/lpp_top_lfr.vhd --- a/lib/lpp/lpp_top_lfr/lpp_top_lfr.vhd +++ b/lib/lpp/lpp_top_lfr/lpp_top_lfr.vhd @@ -14,7 +14,8 @@ USE lpp.lpp_top_lfr_pkg.ALL; USE lpp.lpp_dma_pkg.ALL; USE lpp.lpp_demux.ALL; USE lpp.lpp_fft.ALL; -use lpp.lpp_matrix.all; +USE lpp.lpp_matrix.ALL; +USE lpp.lpp_waveform_pkg.ALL; LIBRARY techmap; USE techmap.gencomp.ALL; @@ -46,6 +47,10 @@ ENTITY lpp_top_lfr IS -- AMBA AHB Master Interface AHB_DMA_SpectralMatrix_In : IN AHB_Mst_In_Type; AHB_DMA_SpectralMatrix_Out : OUT AHB_Mst_Out_Type + + -- Time + coarse_time : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); --! coarse time + fine_time : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) --! fine time ); END lpp_top_lfr; @@ -53,8 +58,7 @@ ARCHITECTURE tb OF lpp_top_lfr IS ----------------------------------------------------------------------------- -- f0 - SIGNAL sample_f0_0_wen : STD_LOGIC_VECTOR(4 DOWNTO 0); - SIGNAL sample_f0_1_wen : STD_LOGIC_VECTOR(4 DOWNTO 0); + SIGNAL sample_f0_wen : STD_LOGIC_VECTOR(4 DOWNTO 0); SIGNAL sample_f0_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); -- SIGNAL sample_f0_0_ren : STD_LOGIC_VECTOR(4 DOWNTO 0); @@ -104,9 +108,9 @@ ARCHITECTURE tb OF lpp_top_lfr IS SIGNAL fft_fifo_wen : STD_LOGIC_VECTOR(4 DOWNTO 0); SIGNAL fft_fifo_reuse : STD_LOGIC_VECTOR(4 DOWNTO 0); - SIGNAL SP_fifo_data : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); - SIGNAL SP_fifo_ren : STD_LOGIC_VECTOR(4 DOWNTO 0); - + SIGNAL SP_fifo_data : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); + SIGNAL SP_fifo_ren : STD_LOGIC_VECTOR(4 DOWNTO 0); + SIGNAL fifo_data : STD_LOGIC_VECTOR(31 DOWNTO 0); SIGNAL fifo_empty : STD_LOGIC; SIGNAL fifo_ren : STD_LOGIC; @@ -136,6 +140,35 @@ ARCHITECTURE tb OF lpp_top_lfr IS SIGNAL addr_matrix_f0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0); SIGNAL addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0); SIGNAL addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0); + + ----------------------------------------------------------------------------- + -- + ----------------------------------------------------------------------------- + + CONSTANT nb_snapshot_param_size : INTEGER := 11; + CONSTANT delta_snapshot_size : INTEGER := 16; + CONSTANT delta_f2_f0_size : INTEGER := 10; + CONSTANT delta_f2_f1_size : INTEGER := 10; + + SIGNAL waveform_enable_f0 : STD_LOGIC; + SIGNAL waveform_enable_f1 : STD_LOGIC; + SIGNAL waveform_enable_f2 : STD_LOGIC; + SIGNAL waveform_enable_f3 : STD_LOGIC; + + SIGNAL waveform_burst_f0 : STD_LOGIC; + SIGNAL waveform_burst_f1 : STD_LOGIC; + SIGNAL waveform_burst_f2 : STD_LOGIC; + + SIGNAL waveform_nb_snapshot_param : STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0); + SIGNAL waveform_delta_snapshot : STD_LOGIC_VECTOR(delta_snapshot_size-1 DOWNTO 0); + SIGNAL waveform_delta_f2_f1 : STD_LOGIC_VECTOR(delta_f2_f1_size-1 DOWNTO 0); + SIGNAL waveform_delta_f2_f0 : STD_LOGIC_VECTOR(delta_f2_f0_size-1 DOWNTO 0); + + SIGNAL data_f0_in_valid : STD_LOGIC; + SIGNAL data_f0_in_valid_r : STD_LOGIC; + SIGNAL data_f1_in_valid : STD_LOGIC; + SIGNAL data_f2_in_valid : STD_LOGIC; + SIGNAL data_f3_in_valid : STD_LOGIC; BEGIN @@ -155,8 +188,7 @@ BEGIN clk => clk, rstn => rstn, - sample_f0_0_wen => sample_f0_0_wen, - sample_f0_1_wen => sample_f0_1_wen, + sample_f0_wen => sample_f0_wen, sample_f0_wdata => sample_f0_wdata, sample_f1_wen => sample_f1_wen, sample_f1_wdata => sample_f1_wdata, @@ -169,7 +201,7 @@ BEGIN -- FIFO ----------------------------------------------------------------------------- - lppFIFO_f0_0 : lppFIFOxN + lppFIFO_f0 : lppFIFOxN GENERIC MAP ( tech => tech, Data_sz => 16, @@ -181,31 +213,12 @@ BEGIN rclk => clk, ReUse => (OTHERS => '0'), - wen => sample_f0_0_wen, - ren => sample_f0_0_ren, + wen => sample_f0_wen, + ren => sample_f0_ren, wdata => sample_f0_wdata, - rdata => sample_f0_0_rdata, - full => sample_f0_0_full, - empty => sample_f0_0_empty); - - lppFIFO_f0_1 : lppFIFOxN - GENERIC MAP ( - tech => tech, - Data_sz => 16, - FifoCnt => 5, - Enable_ReUse => '0') - PORT MAP ( - rst => rstn, - wclk => clk, - rclk => clk, - ReUse => (OTHERS => '0'), - - wen => sample_f0_1_wen, - ren => sample_f0_1_ren, - wdata => sample_f0_wdata, - rdata => sample_f0_1_rdata, - full => sample_f0_1_full, - empty => sample_f0_1_empty); + rdata => sample_f0_rdata, + full => sample_f0_full, + empty => sample_f0_empty); lppFIFO_f1 : lppFIFOxN GENERIC MAP ( @@ -226,7 +239,7 @@ BEGIN full => sample_f1_full, empty => sample_f1_empty); - lppFIFO_f3 : lppFIFOxN + lppFIFO_f2 : lppFIFOxN GENERIC MAP ( tech => tech, Data_sz => 16, @@ -238,92 +251,91 @@ BEGIN rclk => clk, ReUse => (OTHERS => '0'), - wen => sample_f3_wen, - ren => sample_f3_ren, - wdata => sample_f3_wdata, - rdata => sample_f3_rdata, - full => sample_f3_full, - empty => sample_f3_empty); + wen => sample_f2_wen, + ren => sample_f2_ren, + wdata => sample_f2_wdata, + rdata => sample_f2_rdata, + full => sample_f2_full, + empty => sample_f2_empty); ----------------------------------------------------------------------------- -- SPECTRAL MATRIX ----------------------------------------------------------------------------- - sample_f0_0_ren <= sample_ren(4 DOWNTO 0); - sample_f0_1_ren <= sample_ren(9 DOWNTO 5); - sample_f1_ren <= sample_ren(14 DOWNTO 10); - sample_f3_ren <= sample_ren(19 DOWNTO 15); + --sample_f0_ren <= sample_ren(4 DOWNTO 0); + --sample_f1_ren <= sample_ren(14 DOWNTO 10); + --sample_f2_ren <= sample_ren(19 DOWNTO 15); - Demultiplex_1 : Demultiplex - GENERIC MAP ( - Data_sz => 16) - PORT MAP ( - clk => clk, - rstn => rstn, + --Demultiplex_1 : Demultiplex + -- GENERIC MAP ( + -- Data_sz => 16) + -- PORT MAP ( + -- clk => clk, + -- rstn => rstn, - Read => demux_ren, - EmptyF0a => sample_f0_0_empty, - EmptyF0b => sample_f0_0_empty, - EmptyF1 => sample_f1_empty, - EmptyF2 => sample_f3_empty, - DataF0a => sample_f0_0_rdata, - DataF0b => sample_f0_1_rdata, - DataF1 => sample_f1_rdata, - DataF2 => sample_f3_rdata, - Read_DEMUX => sample_ren, - Empty => demux_empty, - Data => demux_data); + -- Read => demux_ren, + -- EmptyF0a => sample_f0_0_empty, + -- EmptyF0b => sample_f0_0_empty, + -- EmptyF1 => sample_f1_empty, + -- EmptyF2 => sample_f3_empty, + -- DataF0a => sample_f0_0_rdata, + -- DataF0b => sample_f0_1_rdata, + -- DataF1 => sample_f1_rdata, + -- DataF2 => sample_f3_rdata, + -- Read_DEMUX => sample_ren, + -- Empty => demux_empty, + -- Data => demux_data); - FFT_1 : FFT - GENERIC MAP ( - Data_sz => 16, - NbData => 256) - PORT MAP ( - clkm => clk, - rstn => rstn, - FifoIN_Empty => demux_empty, - FifoIN_Data => demux_data, - FifoOUT_Full => fft_fifo_full, - Read => demux_ren, - Write => fft_fifo_wen, - ReUse => fft_fifo_reuse, - Data => fft_fifo_data); + --FFT_1 : FFT + -- GENERIC MAP ( + -- Data_sz => 16, + -- NbData => 256) + -- PORT MAP ( + -- clkm => clk, + -- rstn => rstn, + -- FifoIN_Empty => demux_empty, + -- FifoIN_Data => demux_data, + -- FifoOUT_Full => fft_fifo_full, + -- Read => demux_ren, + -- Write => fft_fifo_wen, + -- ReUse => fft_fifo_reuse, + -- Data => fft_fifo_data); - lppFIFO_fft : lppFIFOxN - GENERIC MAP ( - tech => tech, - Data_sz => 16, - FifoCnt => 5, - Enable_ReUse => '1') - PORT MAP ( - rst => rstn, - wclk => clk, - rclk => clk, - ReUse => fft_fifo_reuse, - wen => fft_fifo_wen, - ren => SP_fifo_ren, - wdata => fft_fifo_data, - rdata => SP_fifo_data, - full => fft_fifo_full, - empty => OPEN); + --lppFIFO_fft : lppFIFOxN + -- GENERIC MAP ( + -- tech => tech, + -- Data_sz => 16, + -- FifoCnt => 5, + -- Enable_ReUse => '1') + -- PORT MAP ( + -- rst => rstn, + -- wclk => clk, + -- rclk => clk, + -- ReUse => fft_fifo_reuse, + -- wen => fft_fifo_wen, + -- ren => SP_fifo_ren, + -- wdata => fft_fifo_data, + -- rdata => SP_fifo_data, + -- full => fft_fifo_full, + -- empty => OPEN); - MatriceSpectrale_1: MatriceSpectrale - GENERIC MAP ( - Input_SZ => 16, - Result_SZ => 32) - PORT MAP ( - clkm => clk, - rstn => rstn, - - FifoIN_Full => fft_fifo_full, - FifoOUT_Full => , -- TODO - Data_IN => SP_fifo_data, - ACQ => , -- TODO - FlagError => , -- TODO - Pong => , -- TODO - Write => , -- TODO - Read => SP_fifo_ren, - Data_OUT => ); -- TODO - + --MatriceSpectrale_1 : MatriceSpectrale + -- GENERIC MAP ( + -- Input_SZ => 16, + -- Result_SZ => 32) + -- PORT MAP ( + -- clkm => clk, + -- rstn => rstn, + + -- FifoIN_Full => fft_fifo_full, + -- FifoOUT_Full => , -- TODO + -- Data_IN => SP_fifo_data, + -- ACQ => , -- TODO + -- FlagError => , -- TODO + -- Pong => , -- TODO + -- Write => , -- TODO + -- Read => SP_fifo_ren, + -- Data_OUT => ); -- TODO + ----------------------------------------------------------------------------- -- DMA SPECTRAL MATRIX @@ -401,11 +413,73 @@ BEGIN addr_matrix_f2 => addr_matrix_f2); + ----------------------------------------------------------------------------- + -- WAVEFORM + ----------------------------------------------------------------------------- + + ----------------------------------------------------------------------------- + delay_valid_waveform : PROCESS (clk, rstn) + BEGIN + IF rstn = '0' THEN + data_f0_in_valid <= '0'; + data_f1_in_valid <= '0'; + ELSIF clk'EVENT AND clk = '1' THEN + data_f0_in_valid_r <= NOT sample_f0_wen; + data_f0_in_valid <= NOT data_f0_in_valid_r; + data_f1_in_valid <= NOT sample_f1_wen; + END IF; + END PROCESS delay_valid_waveform; + + data_f2_in_valid <= NOT sample_f2_wen; + data_f3_in_valid <= NOT sample_f3_wen; + + ----------------------------------------------------------------------------- + lpp_waveform_1 : lpp_waveform + GENERIC MAP ( + data_size => 16, + nb_snapshot_param_size => nb_snapshot_param_size, + delta_snapshot_size => delta_snapshot_size, + delta_f2_f0_size => delta_f2_f0_size, + delta_f2_f1_size => delta_f2_f1_size) + PORT MAP ( + clk => clk, + rstn => rstn, + + coarse_time_0 => coarse_time(0), + delta_snapshot => waveform_delta_snapshot, + delta_f2_f1 => waveform_delta_f2_f1, + delta_f2_f0 => waveform_delta_f2_f0, + + enable_f0 => waveform_enable_f0, + enable_f1 => waveform_enable_f1, + enable_f2 => waveform_enable_f2, + enable_f3 => waveform_enable_f3, + + burst_f0 => waveform_burst_f0, + burst_f1 => waveform_burst_f1, + burst_f2 => waveform_burst_f2, + + nb_snapshot_param => waveform_nb_snapshot_param, + + data_f0_in => sample_f0_wdata, + data_f1_in => sample_f1_wdata, + data_f2_in => sample_f2_wdata, + data_f3_in => sample_f3_wdata, + + data_f0_in_valid => data_f0_in_valid, + data_f1_in_valid => data_f1_in_valid, + data_f2_in_valid => data_f2_in_valid, + data_f3_in_valid => data_f3_in_valid); + + ----------------------------------------------------------------------------- + -- + ----------------------------------------------------------------------------- + --DONE : add the irq alert for DMA matrix transfert ending - + --TODO : add 5 bit register into APB to control the DATA SHIPING --TODO : data shiping - + --TODO : add Spectral Matrix (FFT + SP) --TODO : add DMA for WaveForms Picker --TODO : add APB Reg to control WaveForms Picker diff --git a/lib/lpp/lpp_waveform/lpp_waveform.vhd b/lib/lpp/lpp_waveform/lpp_waveform.vhd new file mode 100644 --- /dev/null +++ b/lib/lpp/lpp_waveform/lpp_waveform.vhd @@ -0,0 +1,277 @@ +LIBRARY IEEE; +USE IEEE.STD_LOGIC_1164.ALL; +USE ieee.numeric_std.ALL; + +LIBRARY grlib; +USE grlib.amba.ALL; +USE grlib.stdlib.ALL; +USE grlib.devices.ALL; +USE GRLIB.DMA2AHB_Package.ALL; + +LIBRARY lpp; +USE lpp.lpp_waveform_pkg.ALL; + +LIBRARY techmap; +USE techmap.gencomp.ALL; + +ENTITY lpp_waveform IS + + GENERIC ( + hindex : INTEGER := 2; + tech : INTEGER := inferred; + data_size : INTEGER := 160; + nb_burst_available_size : INTEGER := 11; + nb_snapshot_param_size : INTEGER := 11; + delta_snapshot_size : INTEGER := 16; + delta_f2_f0_size : INTEGER := 10; + delta_f2_f1_size : INTEGER := 10); + + PORT ( + clk : IN STD_LOGIC; + rstn : IN STD_LOGIC; + + -- AMBA AHB Master Interface + AHB_Master_In : IN AHB_Mst_In_Type; + AHB_Master_Out : OUT AHB_Mst_Out_Type; + + coarse_time_0 : IN STD_LOGIC; + + --config + delta_snapshot : IN STD_LOGIC_VECTOR(delta_snapshot_size-1 DOWNTO 0); + delta_f2_f1 : IN STD_LOGIC_VECTOR(delta_f2_f1_size-1 DOWNTO 0); + delta_f2_f0 : IN STD_LOGIC_VECTOR(delta_f2_f0_size-1 DOWNTO 0); + + enable_f0 : IN STD_LOGIC; + enable_f1 : IN STD_LOGIC; + enable_f2 : IN STD_LOGIC; + enable_f3 : IN STD_LOGIC; + + burst_f0 : IN STD_LOGIC; + burst_f1 : IN STD_LOGIC; + burst_f2 : IN STD_LOGIC; + + nb_burst_available : IN STD_LOGIC_VECTOR(nb_burst_available_size-1 DOWNTO 0); + nb_snapshot_param : IN STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0); + status_full : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + status_full_ack : IN STD_LOGIC_VECTOR(3 DOWNTO 0); + status_full_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + status_new_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); -- New data f(i) before the current data is write by dma + addr_data_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + addr_data_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + addr_data_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + addr_data_f3 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + + data_f0_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); + data_f1_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); + data_f2_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); + data_f3_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); + + data_f0_in_valid : IN STD_LOGIC; + data_f1_in_valid : IN STD_LOGIC; + data_f2_in_valid : IN STD_LOGIC; + data_f3_in_valid : IN STD_LOGIC + ); + +END lpp_waveform; + +ARCHITECTURE beh OF lpp_waveform IS + SIGNAL start_snapshot_f0 : STD_LOGIC; + SIGNAL start_snapshot_f1 : STD_LOGIC; + SIGNAL start_snapshot_f2 : STD_LOGIC; + + SIGNAL data_f0_out : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); + SIGNAL data_f1_out : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); + SIGNAL data_f2_out : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); + SIGNAL data_f3_out : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); + + SIGNAL data_f0_out_valid : STD_LOGIC; + SIGNAL data_f1_out_valid : STD_LOGIC; + SIGNAL data_f2_out_valid : STD_LOGIC; + SIGNAL data_f3_out_valid : STD_LOGIC; + SIGNAL nb_snapshot_param_more_one : STD_LOGIC_VECTOR(nb_snapshot_param_size DOWNTO 0); + + -- + SIGNAL valid_in : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL valid_out : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL valid_ack : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL ready : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL ready_arb : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL data_wen : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL time_wen : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL wdata : STD_LOGIC_VECTOR(31 DOWNTO 0); + -- + SIGNAL data_ren : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL time_ren : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL rdata : STD_LOGIC_VECTOR(31 DOWNTO 0); + +BEGIN -- beh + + lpp_waveform_snapshot_controler_1: lpp_waveform_snapshot_controler + GENERIC MAP ( + delta_snapshot_size => delta_snapshot_size, + delta_f2_f0_size => delta_f2_f0_size, + delta_f2_f1_size => delta_f2_f1_size) + PORT MAP ( + clk => clk, + rstn => rstn, + delta_snapshot => delta_snapshot, + delta_f2_f1 => delta_f2_f1, + delta_f2_f0 => delta_f2_f0, + coarse_time_0 => coarse_time_0, + data_f0_in_valid => data_f0_in_valid, + data_f2_in_valid => data_f2_in_valid, + start_snapshot_f0 => start_snapshot_f0, + start_snapshot_f1 => start_snapshot_f1, + start_snapshot_f2 => start_snapshot_f2); + + lpp_waveform_snapshot_f0 : lpp_waveform_snapshot + GENERIC MAP ( + data_size => data_size, + nb_snapshot_param_size => nb_snapshot_param_size) + PORT MAP ( + clk => clk, + rstn => rstn, + enable => enable_f0, + burst_enable => burst_f0, + nb_snapshot_param => nb_snapshot_param, + start_snapshot => start_snapshot_f0, + data_in => data_f0_in, + data_in_valid => data_f0_in_valid, + data_out => data_f0_out, + data_out_valid => data_f0_out_valid); + + nb_snapshot_param_more_one <= ('0' & nb_snapshot_param) + 1; + + lpp_waveform_snapshot_f1 : lpp_waveform_snapshot + GENERIC MAP ( + data_size => data_size, + nb_snapshot_param_size => nb_snapshot_param_size+1) + PORT MAP ( + clk => clk, + rstn => rstn, + enable => enable_f1, + burst_enable => burst_f1, + nb_snapshot_param => nb_snapshot_param_more_one, + start_snapshot => start_snapshot_f1, + data_in => data_f1_in, + data_in_valid => data_f1_in_valid, + data_out => data_f1_out, + data_out_valid => data_f1_out_valid); + + lpp_waveform_snapshot_f2 : lpp_waveform_snapshot + GENERIC MAP ( + data_size => data_size, + nb_snapshot_param_size => nb_snapshot_param_size+1) + PORT MAP ( + clk => clk, + rstn => rstn, + enable => enable_f2, + burst_enable => burst_f2, + nb_snapshot_param => nb_snapshot_param_more_one, + start_snapshot => start_snapshot_f2, + data_in => data_f2_in, + data_in_valid => data_f2_in_valid, + data_out => data_f2_out, + data_out_valid => data_f2_out_valid); + + lpp_waveform_burst_f3: lpp_waveform_burst + GENERIC MAP ( + data_size => data_size) + PORT MAP ( + clk => clk, + rstn => rstn, + enable => enable_f3, + data_in => data_f3_in, + data_in_valid => data_f3_in_valid, + data_out => data_f3_out, + data_out_valid => data_f3_out_valid); + + + valid_in <= data_f3_out_valid & data_f2_out_valid & data_f1_out_valid & data_f0_out_valid; + + all_input_valid: FOR i IN 3 DOWNTO 0 GENERATE + lpp_waveform_dma_gen_valid_I: lpp_waveform_dma_gen_valid + PORT MAP ( + HCLK => clk, + HRESETn => rstn, + valid_in => valid_in(I), + ack_in => valid_ack(I), + valid_out => valid_out(I), + error => status_new_err(I)); + END GENERATE all_input_valid; + + lpp_waveform_fifo_arbiter_1: lpp_waveform_fifo_arbiter + GENERIC MAP (tech => tech) + PORT MAP ( + clk => clk, + rstn => rstn, + data_f0_valid => valid_out(0), + data_f1_valid => valid_out(1), + data_f2_valid => valid_out(2), + data_f3_valid => valid_out(3), + + data_valid_ack => valid_ack, + + data_f0 => data_f0_out, + data_f1 => data_f1_out, + data_f2 => data_f2_out, + data_f3 => data_f3_out, + + ready => ready_arb, + time_wen => time_wen, + data_wen => data_wen, + data => wdata); + + ready_arb <= NOT ready; + + lpp_waveform_fifo_1: lpp_waveform_fifo + GENERIC MAP (tech => tech) + PORT MAP ( + clk => clk, + rstn => rstn, + ready => ready, + time_ren => time_ren, -- todo + data_ren => data_ren, -- todo + rdata => rdata, -- todo + + time_wen => time_wen, + data_wen => data_wen, + wdata => wdata); + + --time_ren <= (OTHERS => '1'); + --data_ren <= (OTHERS => '1'); + + pp_waveform_dma_1: lpp_waveform_dma + GENERIC MAP ( + data_size => data_size, + tech => tech, + hindex => hindex, + nb_burst_available_size => nb_burst_available_size) + PORT MAP ( + HCLK => clk, + HRESETn => rstn, + AHB_Master_In => AHB_Master_In, + AHB_Master_Out => AHB_Master_Out, + data_ready => ready, + data => rdata, + data_data_ren => data_ren, + data_time_ren => time_ren, + --data_f0_in => data_f0_out, + --data_f1_in => data_f1_out, + --data_f2_in => data_f2_out, + --data_f3_in => data_f3_out, + --data_f0_in_valid => data_f0_out_valid, + --data_f1_in_valid => data_f1_out_valid, + --data_f2_in_valid => data_f2_out_valid, + --data_f3_in_valid => data_f3_out_valid, + nb_burst_available => nb_burst_available, + status_full => status_full, + status_full_ack => status_full_ack, + status_full_err => status_full_err, +-- status_new_err => status_new_err, + addr_data_f0 => addr_data_f0, + addr_data_f1 => addr_data_f1, + addr_data_f2 => addr_data_f2, + addr_data_f3 => addr_data_f3); + +END beh; diff --git a/lib/lpp/lpp_waveform/lpp_waveform_burst.vhd b/lib/lpp/lpp_waveform/lpp_waveform_burst.vhd new file mode 100644 --- /dev/null +++ b/lib/lpp/lpp_waveform/lpp_waveform_burst.vhd @@ -0,0 +1,42 @@ +LIBRARY IEEE; +USE IEEE.STD_LOGIC_1164.ALL; + +ENTITY lpp_waveform_burst IS + + GENERIC ( + data_size : INTEGER := 16); + + PORT ( + clk : IN STD_LOGIC; + rstn : IN STD_LOGIC; + + enable : IN STD_LOGIC; + + data_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); + data_in_valid : IN STD_LOGIC; + + data_out : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); + data_out_valid : OUT STD_LOGIC + ); + +END lpp_waveform_burst; + +ARCHITECTURE beh OF lpp_waveform_burst IS +BEGIN -- beh + + PROCESS (clk, rstn) + BEGIN + IF rstn = '0' THEN + data_out <= (OTHERS => '0'); + data_out_valid <= '0'; + ELSIF clk'EVENT AND clk = '1' THEN + data_out <= data_in; + IF enable = '0' THEN + data_out_valid <= '0'; + ELSE + data_out_valid <= data_in_valid; + END IF; + END IF; + END PROCESS; + +END beh; diff --git a/lib/lpp/lpp_waveform/lpp_waveform_dma.vhd b/lib/lpp/lpp_waveform/lpp_waveform_dma.vhd new file mode 100644 --- /dev/null +++ b/lib/lpp/lpp_waveform/lpp_waveform_dma.vhd @@ -0,0 +1,363 @@ + +------------------------------------------------------------------------------ +-- This file is a part of the LPP VHDL IP LIBRARY +-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 3 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +------------------------------------------------------------------------------- +-- Author : Jean-christophe Pellion +-- Mail : jean-christophe.pellion@lpp.polytechnique.fr +-- jean-christophe.pellion@easii-ic.com +------------------------------------------------------------------------------- +-- 1.0 - initial version +-- 1.1 - (01/11/2013) FIX boundary error (1kB address should not be crossed by BURSTS) +------------------------------------------------------------------------------- +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.numeric_std.ALL; +LIBRARY grlib; +USE grlib.amba.ALL; +USE grlib.stdlib.ALL; +USE grlib.devices.ALL; +USE GRLIB.DMA2AHB_Package.ALL; +LIBRARY lpp; +USE lpp.lpp_amba.ALL; +USE lpp.apb_devices_list.ALL; +USE lpp.lpp_memory.ALL; +USE lpp.lpp_dma_pkg.ALL; +USE lpp.lpp_waveform_pkg.ALL; +LIBRARY techmap; +USE techmap.gencomp.ALL; + + +ENTITY lpp_waveform_dma IS + GENERIC ( + data_size : INTEGER := 160; + tech : INTEGER := inferred; + hindex : INTEGER := 2; + nb_burst_available_size : INTEGER := 11 + ); + PORT ( + -- AMBA AHB system signals + HCLK : IN STD_ULOGIC; + HRESETn : IN STD_ULOGIC; + -- AMBA AHB Master Interface + AHB_Master_In : IN AHB_Mst_In_Type; + AHB_Master_Out : OUT AHB_Mst_Out_Type; + -- + data_ready : IN STD_LOGIC_VECTOR(3 DOWNTO 0); -- todo + data : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- todo + data_data_ren : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); -- todo + data_time_ren : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); -- todo + -- Reg + nb_burst_available : IN STD_LOGIC_VECTOR(nb_burst_available_size-1 DOWNTO 0); + status_full : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + status_full_ack : IN STD_LOGIC_VECTOR(3 DOWNTO 0); + status_full_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); +-- status_new_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); -- New data f(i) before the current data is write by dma + addr_data_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + addr_data_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + addr_data_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + addr_data_f3 : IN STD_LOGIC_VECTOR(31 DOWNTO 0) + ); +END; + +ARCHITECTURE Behavioral OF lpp_waveform_dma IS + ----------------------------------------------------------------------------- + SIGNAL DMAIn : DMA_In_Type; + SIGNAL DMAOut : DMA_OUt_Type; + ----------------------------------------------------------------------------- + TYPE state_DMAWriteBurst IS (IDLE, + SEND_TIME_0, WAIT_TIME_0, + SEND_TIME_1, WAIT_TIME_1, + SEND_5_TIME, + SEND_DATA, WAIT_DATA); + SIGNAL state : state_DMAWriteBurst := IDLE; + ----------------------------------------------------------------------------- + -- CONTROL + SIGNAL sel_data_s : STD_LOGIC_VECTOR(1 DOWNTO 0); + SIGNAL sel_data : STD_LOGIC_VECTOR(1 DOWNTO 0); + SIGNAL update : STD_LOGIC_VECTOR(1 DOWNTO 0); + SIGNAL time_select : STD_LOGIC; + SIGNAL time_write : STD_LOGIC; + SIGNAL time_already_send : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL time_already_send_s : STD_LOGIC; + ----------------------------------------------------------------------------- + -- SEND TIME MODULE + SIGNAL time_dmai : DMA_In_Type; + SIGNAL time_send : STD_LOGIC; + SIGNAL time_send_ok : STD_LOGIC; + SIGNAL time_send_ko : STD_LOGIC; + SIGNAL time_fifo_ren : STD_LOGIC; + SIGNAL time_ren : STD_LOGIC; + ----------------------------------------------------------------------------- + -- SEND DATA MODULE + SIGNAL data_dmai : DMA_In_Type; + SIGNAL data_send : STD_LOGIC; + SIGNAL data_send_ok : STD_LOGIC; + SIGNAL data_send_ko : STD_LOGIC; + SIGNAL data_fifo_ren : STD_LOGIC; + SIGNAL data_ren : STD_LOGIC; + ----------------------------------------------------------------------------- + -- SELECT ADDRESS + SIGNAL data_address : STD_LOGIC_VECTOR(31 DOWNTO 0); + SIGNAL update_and_sel : STD_LOGIC_VECTOR(7 DOWNTO 0); + SIGNAL addr_data_reg_vector : STD_LOGIC_VECTOR(32*4-1 DOWNTO 0); + SIGNAL addr_data_vector : STD_LOGIC_VECTOR(32*4-1 DOWNTO 0); + ----------------------------------------------------------------------------- + SIGNAL send_16_3_time : STD_LOGIC_VECTOR(2 DOWNTO 0); + SIGNAL count_send_time : INTEGER; +BEGIN + + ----------------------------------------------------------------------------- + -- DMA to AHB interface + DMA2AHB_1 : DMA2AHB + GENERIC MAP ( + hindex => hindex, + vendorid => VENDOR_LPP, + deviceid => 0, + version => 0, + syncrst => 1, + boundary => 1) -- FIX 11/01/2013 + PORT MAP ( + HCLK => HCLK, + HRESETn => HRESETn, + DMAIn => DMAIn, + DMAOut => DMAOut, + AHBIn => AHB_Master_In, + AHBOut => AHB_Master_Out); + ----------------------------------------------------------------------------- + + ----------------------------------------------------------------------------- + -- This module memorises when the Times info are write. When FSM send + -- the Times info, the "reg" is set and when a full_ack is received the "reg" is reset. + all_time_write: FOR I IN 3 DOWNTO 0 GENERATE + PROCESS (HCLK, HRESETn) + BEGIN -- PROCESS + IF HRESETn = '0' THEN -- asynchronous reset (active low) + time_already_send(I) <= '0'; + ELSIF HCLK'EVENT AND HCLK = '1' THEN -- rising clock edge + IF time_write = '1' AND UNSIGNED(sel_data) = I THEN + time_already_send(I) <= '1'; + ELSIF status_full_ack(I) = '1' THEN + time_already_send(I) <= '0'; + END IF; + END IF; + END PROCESS; + END GENERATE all_time_write; + + ----------------------------------------------------------------------------- + sel_data_s <= "00" WHEN data_ready(0) = '1' ELSE + "01" WHEN data_ready(1) = '1' ELSE + "10" WHEN data_ready(2) = '1' ELSE + "11"; + + time_already_send_s <= time_already_send(0) WHEN data_ready(0) = '1' ELSE + time_already_send(1) WHEN data_ready(1) = '1' ELSE + time_already_send(2) WHEN data_ready(2) = '1' ELSE + time_already_send(3); + + -- DMA control + DMAWriteFSM_p : PROCESS (HCLK, HRESETn) + BEGIN -- PROCESS DMAWriteBurst_p + IF HRESETn = '0' THEN + state <= IDLE; + + sel_data <= "00"; + update <= "00"; + time_select <= '0'; + time_fifo_ren <= '1'; + data_send <= '0'; + time_send <= '0'; + time_write <= '0'; + send_16_3_time <= "001"; + + ELSIF HCLK'EVENT AND HCLK = '1' THEN + + CASE state IS + WHEN IDLE => + count_send_time <= 0; + sel_data <= "00"; + update <= "00"; + time_select <= '0'; + time_fifo_ren <= '1'; + data_send <= '0'; + time_send <= '0'; + time_write <= '0'; + + IF data_ready = "0000" THEN + state <= IDLE; + ELSE + sel_data <= sel_data_s; + send_16_3_time <= send_16_3_time(1 DOWNTO 0) & send_16_3_time(2); + IF send_16_3_time(0) = '1' THEN + state <= SEND_TIME_0; + ELSE + state <= SEND_5_TIME; + END IF; + END IF; + + WHEN SEND_TIME_0 => + time_select <= '1'; + IF time_already_send_s = '0' THEN + time_send <= '1'; + state <= WAIT_TIME_0; + ELSE + time_send <= '0'; + state <= SEND_TIME_1; + END IF; + time_fifo_ren <= '0'; + + WHEN WAIT_TIME_0 => + time_fifo_ren <= '1'; + update <= "00"; + time_send <= '0'; + IF time_send_ok = '1' OR time_send_ko = '1' THEN + update <= "01"; + state <= SEND_TIME_1; + END IF; + + WHEN SEND_TIME_1 => + time_select <= '1'; + IF time_already_send_s = '0' THEN + time_send <= '1'; + state <= WAIT_TIME_1; + ELSE + time_send <= '0'; + state <= SEND_5_TIME; + END IF; + time_fifo_ren <= '0'; + + WHEN WAIT_TIME_1 => + time_fifo_ren <= '1'; + update <= "00"; + time_send <= '0'; + IF time_send_ok = '1' OR time_send_ko = '1' THEN + time_write <= '1'; + update <= "01"; + state <= SEND_5_TIME; + END IF; + + WHEN SEND_5_TIME => + update <= "00"; + time_select <= '1'; + time_fifo_ren <= '0'; + count_send_time <= count_send_time + 1; + IF count_send_time = 10 THEN + state <= SEND_DATA; + END IF; + + WHEN SEND_DATA => + time_fifo_ren <= '1'; + time_write <= '0'; + time_send <= '0'; + + time_select <= '0'; + data_send <= '1'; + update <= "00"; + state <= WAIT_DATA; + + WHEN WAIT_DATA => + data_send <= '0'; + + IF data_send_ok = '1' OR data_send_ko = '1' THEN + state <= IDLE; + update <= "10"; + END IF; + + WHEN OTHERS => NULL; + END CASE; + + END IF; + END PROCESS DMAWriteFSM_p; + ----------------------------------------------------------------------------- + + + + ----------------------------------------------------------------------------- + -- SEND 1 word by DMA + ----------------------------------------------------------------------------- + lpp_dma_send_1word_1 : lpp_dma_send_1word + PORT MAP ( + HCLK => HCLK, + HRESETn => HRESETn, + DMAIn => time_dmai, + DMAOut => DMAOut, + + send => time_send, + address => data_address, + data => data, + send_ok => time_send_ok, + send_ko => time_send_ko + ); + + ----------------------------------------------------------------------------- + -- SEND 16 word by DMA (in burst mode) + ----------------------------------------------------------------------------- + lpp_dma_send_16word_1 : lpp_dma_send_16word + PORT MAP ( + HCLK => HCLK, + HRESETn => HRESETn, + DMAIn => data_dmai, + DMAOut => DMAOut, + + send => data_send, + address => data_address, + data => data, + ren => data_fifo_ren, + send_ok => data_send_ok, + send_ko => data_send_ko); + + DMAIn <= time_dmai WHEN time_select = '1' ELSE data_dmai; + data_ren <= '1' WHEN time_select = '1' ELSE data_fifo_ren; + time_ren <= time_fifo_ren WHEN time_select = '1' ELSE '1'; + + all_data_ren : FOR I IN 3 DOWNTO 0 GENERATE + data_data_ren(I) <= data_ren WHEN UNSIGNED(sel_data) = I ELSE '1'; + data_time_ren(I) <= time_ren WHEN UNSIGNED(sel_data) = I ELSE '1'; + END GENERATE all_data_ren; + + ----------------------------------------------------------------------------- + -- SELECT ADDRESS + addr_data_reg_vector <= addr_data_f3 & addr_data_f2 & addr_data_f1 & addr_data_f0; + + gen_select_address : FOR I IN 3 DOWNTO 0 GENERATE + + update_and_sel((2*I)+1 DOWNTO 2*I) <= update WHEN UNSIGNED(sel_data) = I ELSE "00"; + + lpp_waveform_dma_selectaddress_I : lpp_waveform_dma_selectaddress + GENERIC MAP ( + nb_burst_available_size => nb_burst_available_size) + PORT MAP ( + HCLK => HCLK, + HRESETn => HRESETn, + update => update_and_sel((2*I)+1 DOWNTO 2*I), + nb_burst_available => nb_burst_available, + addr_data_reg => addr_data_reg_vector(32*I+31 DOWNTO 32*I), + addr_data => addr_data_vector(32*I+31 DOWNTO 32*I), + status_full => status_full(I), + status_full_ack => status_full_ack(I), + status_full_err => status_full_err(I)); + + END GENERATE gen_select_address; + + data_address <= addr_data_vector(31 DOWNTO 0) WHEN UNSIGNED(sel_data) = 0 ELSE + addr_data_vector(32*1+31 DOWNTO 32*1) WHEN UNSIGNED(sel_data) = 1 ELSE + addr_data_vector(32*2+31 DOWNTO 32*2) WHEN UNSIGNED(sel_data) = 2 ELSE + addr_data_vector(32*3+31 DOWNTO 32*3); + ----------------------------------------------------------------------------- + + +END Behavioral; diff --git a/lib/lpp/lpp_waveform/lpp_waveform_dma_genvalid.vhd b/lib/lpp/lpp_waveform/lpp_waveform_dma_genvalid.vhd new file mode 100644 --- /dev/null +++ b/lib/lpp/lpp_waveform/lpp_waveform_dma_genvalid.vhd @@ -0,0 +1,88 @@ + +------------------------------------------------------------------------------ +-- This file is a part of the LPP VHDL IP LIBRARY +-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 3 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +------------------------------------------------------------------------------- +-- Author : Jean-christophe Pellion +-- Mail : jean-christophe.pellion@lpp.polytechnique.fr +-- jean-christophe.pellion@easii-ic.com +------------------------------------------------------------------------------- +-- 1.0 - initial version +------------------------------------------------------------------------------- + +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.numeric_std.ALL; + + +ENTITY lpp_waveform_dma_gen_valid IS + PORT ( + HCLK : IN STD_LOGIC; + HRESETn : IN STD_LOGIC; + + valid_in : IN STD_LOGIC; + ack_in : IN STD_LOGIC; + + valid_out : OUT STD_LOGIC; + error : OUT STD_LOGIC + ); +END; + +ARCHITECTURE Behavioral OF lpp_waveform_dma_gen_valid IS + TYPE state_fsm IS (IDLE, VALID); + SIGNAL state : state_fsm; +BEGIN + + FSM_SELECT_ADDRESS : PROCESS (HCLK, HRESETn) + BEGIN + IF HRESETn = '0' THEN + state <= IDLE; + valid_out <= '0'; + error <= '0'; + ELSIF HCLK'EVENT AND HCLK = '1' THEN + CASE state IS + WHEN IDLE => + valid_out <= '0'; + error <= '0'; + IF valid_in = '1' THEN + state <= VALID; + valid_out <= '1'; + END IF; + + WHEN VALID => + valid_out <= '1'; + error <= '0'; + IF valid_in = '1' THEN + IF ack_in = '1' THEN + state <= VALID; + valid_out <= '1'; + ELSE + state <= IDLE; + error <= '1'; + valid_out <= '0'; + END IF; + ELSIF ack_in = '1' THEN + state <= IDLE; + valid_out <= '0'; + END IF; + + WHEN OTHERS => NULL; + END CASE; + END IF; + END PROCESS FSM_SELECT_ADDRESS; + +END Behavioral; diff --git a/lib/lpp/lpp_waveform/lpp_waveform_dma_selectaddress.vhd b/lib/lpp/lpp_waveform/lpp_waveform_dma_selectaddress.vhd new file mode 100644 --- /dev/null +++ b/lib/lpp/lpp_waveform/lpp_waveform_dma_selectaddress.vhd @@ -0,0 +1,129 @@ + +------------------------------------------------------------------------------ +-- This file is a part of the LPP VHDL IP LIBRARY +-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 3 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +------------------------------------------------------------------------------- +-- Author : Jean-christophe Pellion +-- Mail : jean-christophe.pellion@lpp.polytechnique.fr +-- jean-christophe.pellion@easii-ic.com +------------------------------------------------------------------------------- +-- 1.0 - initial version +------------------------------------------------------------------------------- + +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.numeric_std.ALL; + + +ENTITY lpp_waveform_dma_selectaddress IS + GENERIC ( + nb_burst_available_size : INTEGER := 11 + ); + PORT ( + HCLK : IN STD_ULOGIC; + HRESETn : IN STD_ULOGIC; + + update : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + + nb_burst_available : IN STD_LOGIC_VECTOR(nb_burst_available_size-1 DOWNTO 0); + addr_data_reg : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + + addr_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + + status_full : OUT STD_LOGIC; + status_full_ack : IN STD_LOGIC; + status_full_err : OUT STD_LOGIC + ); +END; + +ARCHITECTURE Behavioral OF lpp_waveform_dma_selectaddress IS + TYPE state_fsm_select_data IS (IDLE, ADD, FULL, ERR, UPDATED); + SIGNAL state : state_fsm_select_data; + + SIGNAL address : STD_LOGIC_VECTOR(31 DOWNTO 0); + SIGNAL nb_send : STD_LOGIC_VECTOR(nb_burst_available_size-1 DOWNTO 0); + SIGNAL nb_send_next : STD_LOGIC_VECTOR(nb_burst_available_size-1 DOWNTO 0); + + SIGNAL update_s : STD_LOGIC; +BEGIN + + update_s <= update(0) OR update(1); + + addr_data <= address; + nb_send_next <= std_logic_vector(unsigned(nb_send) + 1); + + FSM_SELECT_ADDRESS : PROCESS (HCLK, HRESETn) + BEGIN + IF HRESETn = '0' THEN + state <= IDLE; + address <= (OTHERS => '0'); + nb_send <= (OTHERS => '0'); + status_full <= '0'; + status_full_err <= '0'; + ELSIF HCLK'EVENT AND HCLK = '1' THEN + CASE state IS + WHEN IDLE => + IF update_s = '1' THEN + state <= ADD; + END IF; + + WHEN ADD => + IF UNSIGNED(nb_send_next) < UNSIGNED(nb_burst_available) THEN + state <= IDLE; + IF update = "10" THEN + address <= std_logic_vector(unsigned(address) + 16); + nb_send <= nb_send_next; + ELSIF update = "01" THEN + address <= std_logic_vector(unsigned(address) + 1); + END IF; + ELSE + state <= FULL; + nb_send <= (OTHERS => '0'); + status_full <= '1'; + END IF; + + WHEN FULL => + status_full <= '0'; + IF status_full_ack = '1' THEN + IF update_s = '1' THEN + status_full_err <= '1'; + END IF; + state <= UPDATED; + ELSE + IF update_s = '1' THEN + status_full_err <= '1'; + state <= ERR; + END IF; + END IF; + + WHEN ERR => + status_full_err <= '0'; + IF status_full_ack = '1' THEN + state <= UPDATED; + END IF; + + WHEN UPDATED => + status_full_err <= '0'; + state <= IDLE; + address <= addr_data_reg; + + WHEN OTHERS => NULL; + END CASE; + END IF; + END PROCESS FSM_SELECT_ADDRESS; + +END Behavioral; diff --git a/lib/lpp/lpp_waveform/lpp_waveform_dma_send_Nword.vhd b/lib/lpp/lpp_waveform/lpp_waveform_dma_send_Nword.vhd new file mode 100644 --- /dev/null +++ b/lib/lpp/lpp_waveform/lpp_waveform_dma_send_Nword.vhd @@ -0,0 +1,173 @@ +------------------------------------------------------------------------------ +-- This file is a part of the LPP VHDL IP LIBRARY +-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 3 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +------------------------------------------------------------------------------- +-- Author : Jean-christophe Pellion +-- Mail : jean-christophe.pellion@lpp.polytechnique.fr +-- jean-christophe.pellion@easii-ic.com +---------------------------------------------------------------------------- + +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.numeric_std.ALL; +LIBRARY grlib; +USE grlib.amba.ALL; +USE grlib.stdlib.ALL; +USE grlib.devices.ALL; +USE GRLIB.DMA2AHB_Package.ALL; +LIBRARY lpp; +USE lpp.lpp_amba.ALL; +USE lpp.apb_devices_list.ALL; +USE lpp.lpp_memory.ALL; +LIBRARY techmap; +USE techmap.gencomp.ALL; + +ENTITY lpp_waveform_dma_send_Nword IS + PORT ( + -- AMBA AHB system signals + HCLK : IN STD_ULOGIC; + HRESETn : IN STD_ULOGIC; + + -- DMA + DMAIn : OUT DMA_In_Type; + DMAOut : IN DMA_OUt_Type; + + -- + Nb_word_less1 : IN STD_LOGIC_VECTOR(3 DOWNTO 0); + -- + send : IN STD_LOGIC; + address : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + data : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + ren : OUT STD_LOGIC; + -- + send_ok : OUT STD_LOGIC; + send_ko : OUT STD_LOGIC + ); +END lpp_waveform_dma_send_Nword; + +ARCHITECTURE beh OF lpp_waveform_dma_send_Nword IS + + TYPE state_fsm_send_Nword IS (IDLE, REQUEST_BUS, SEND_DATA, ERROR0, ERROR1, WAIT_LAST_READY); + SIGNAL state : state_fsm_send_Nword; + + SIGNAL data_counter : INTEGER; + SIGNAL grant_counter : INTEGER; + +BEGIN -- beh + + DMAIn.Beat <= HINCR16; + DMAIn.Size <= HSIZE32; + + PROCESS (HCLK, HRESETn) + BEGIN -- PROCESS + IF HRESETn = '0' THEN -- asynchronous reset (active low) + state <= IDLE; + send_ok <= '0'; + send_ko <= '0'; + + DMAIn.Reset <= '0'; + DMAIn.Address <= (OTHERS => '0'); + DMAIn.Request <= '0'; + DMAIn.Store <= '0'; + DMAIn.Burst <= '1'; + DMAIn.Lock <= '0'; + data_counter <= 0; + ELSIF HCLK'EVENT AND HCLK = '1' THEN -- rising clock edge + + CASE state IS + WHEN IDLE => + DMAIn.Store <= '1'; + DMAIn.Request <= '0'; + send_ok <= '0'; + send_ko <= '0'; + DMAIn.Address <= address; + data_counter <= 0; + DMAIn.Lock <= '0'; -- FIX test + IF send = '1' THEN + state <= REQUEST_BUS; + DMAIn.Request <= '1'; + DMAIn.Lock <= '1'; -- FIX test + DMAIn.Store <= '1'; + END IF; + WHEN REQUEST_BUS => + IF DMAOut.Grant = '1' THEN + data_counter <= 1; + grant_counter <= 1; + state <= SEND_DATA; + END IF; + WHEN SEND_DATA => + + IF DMAOut.Fault = '1' THEN + DMAIn.Reset <= '0'; + DMAIn.Address <= (OTHERS => '0'); + DMAIn.Request <= '0'; + DMAIn.Store <= '0'; + DMAIn.Burst <= '0'; + state <= ERROR0; + ELSE + + IF DMAOut.Grant = '1' THEN + IF grant_counter = UNSIGNED(Nb_word_less1) THEN -- + DMAIn.Reset <= '0'; + DMAIn.Request <= '0'; + DMAIn.Store <= '0'; + DMAIn.Burst <= '0'; + ELSE + grant_counter <= grant_counter+1; + END IF; + END IF; + + IF DMAOut.OKAY = '1' THEN + IF data_counter = UNSIGNED(Nb_word_less1) THEN + DMAIn.Address <= (OTHERS => '0'); + state <= WAIT_LAST_READY; + ELSE + data_counter <= data_counter + 1; + END IF; + END IF; + END IF; + + + WHEN WAIT_LAST_READY => + IF DMAOut.Ready = '1' THEN + IF grant_counter = UNSIGNED(Nb_word_less1) THEN + state <= IDLE; + send_ok <= '1'; + send_ko <= '0'; + ELSE + state <= ERROR0; + END IF; + END IF; + + WHEN ERROR0 => + state <= ERROR1; + WHEN ERROR1 => + send_ok <= '0'; + send_ko <= '1'; + state <= IDLE; + WHEN OTHERS => NULL; + END CASE; + END IF; + END PROCESS; + + DMAIn.Data <= data; + + ren <= '0' WHEN DMAOut.OKAY = '1' AND state = SEND_DATA ELSE + '0' WHEN state = REQUEST_BUS AND DMAOut.Grant = '1' ELSE + '1'; + +END beh; diff --git a/lib/lpp/lpp_waveform/lpp_waveform_fifo.vhd b/lib/lpp/lpp_waveform/lpp_waveform_fifo.vhd new file mode 100644 --- /dev/null +++ b/lib/lpp/lpp_waveform/lpp_waveform_fifo.vhd @@ -0,0 +1,176 @@ +------------------------------------------------------------------------------ +-- This file is a part of the LPP VHDL IP LIBRARY +-- Copyright (C) 2009 - 2012, Laboratory of Plasmas Physic - CNRS +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 3 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +------------------------------------------------------------------------------ +-- Author : Jean-christophe PELLION +-- Mail : jean-christophe.pellion@lpp.polytechnique.fr +------------------------------------------------------------------------------ +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; +USE IEEE.numeric_std.ALL; +LIBRARY lpp; +USE lpp.lpp_memory.ALL; +USE lpp.iir_filter.ALL; +USE lpp.lpp_waveform_pkg.ALL; + +LIBRARY techmap; +USE techmap.gencomp.ALL; + +ENTITY lpp_waveform_fifo IS + GENERIC( + tech : INTEGER := 0 + ); + PORT( + clk : IN STD_LOGIC; + rstn : IN STD_LOGIC; + + --------------------------------------------------------------------------- + ready : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); -- FIFO_DATA occupancy is greater than 16 * 32b + + --------------------------------------------------------------------------- + time_ren : IN STD_LOGIC_VECTOR(3 DOWNTO 0); + data_ren : IN STD_LOGIC_VECTOR(3 DOWNTO 0); + + rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + + --------------------------------------------------------------------------- + time_wen : IN STD_LOGIC_VECTOR(3 DOWNTO 0); + data_wen : IN STD_LOGIC_VECTOR(3 DOWNTO 0); + + wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0) + ); +END ENTITY; + + +ARCHITECTURE ar_lpp_waveform_fifo OF lpp_waveform_fifo IS + + + SIGNAL time_mem_addr_r : LPP_TYPE_ADDR_FIFO_WAVEFORM(3 DOWNTO 0); + SIGNAL time_mem_addr_w : LPP_TYPE_ADDR_FIFO_WAVEFORM(3 DOWNTO 0); + SIGNAL time_mem_ren : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL time_mem_wen : STD_LOGIC_VECTOR(3 DOWNTO 0); + + SIGNAL data_mem_addr_r : LPP_TYPE_ADDR_FIFO_WAVEFORM(3 DOWNTO 0); + SIGNAL data_mem_addr_w : LPP_TYPE_ADDR_FIFO_WAVEFORM(3 DOWNTO 0); + SIGNAL data_mem_ren : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL data_mem_wen : STD_LOGIC_VECTOR(3 DOWNTO 0); + + SIGNAL data_addr_r : STD_LOGIC_VECTOR(6 DOWNTO 0); + SIGNAL data_addr_w : STD_LOGIC_VECTOR(6 DOWNTO 0); + SIGNAL ren : STD_LOGIC; + SIGNAL wen : STD_LOGIC; + +BEGIN + + SRAM : syncram_2p + GENERIC MAP(tech, 7, 32) + PORT MAP(clk, ren, data_addr_r, rdata, + clk, wen, data_addr_w, wdata); + + + ren <= time_mem_ren(3) OR data_mem_ren(3) OR + time_mem_ren(2) OR data_mem_ren(2) OR + time_mem_ren(1) OR data_mem_ren(1) OR + time_mem_ren(0) OR data_mem_ren(0); + + wen <= time_mem_wen(3) OR data_mem_wen(3) OR + time_mem_wen(2) OR data_mem_wen(2) OR + time_mem_wen(1) OR data_mem_wen(1) OR + time_mem_wen(0) OR data_mem_wen(0); + + data_addr_r <= time_mem_addr_r(0) WHEN time_mem_ren(0) = '1' ELSE + time_mem_addr_r(1) WHEN time_mem_ren(1) = '1' ELSE + time_mem_addr_r(2) WHEN time_mem_ren(2) = '1' ELSE + time_mem_addr_r(3) WHEN time_mem_ren(3) = '1' ELSE + data_mem_addr_r(0) WHEN data_mem_ren(0) = '1' ELSE + data_mem_addr_r(1) WHEN data_mem_ren(1) = '1' ELSE + data_mem_addr_r(2) WHEN data_mem_ren(2) = '1' ELSE + data_mem_addr_r(3); + + data_addr_w <= time_mem_addr_w(0) WHEN time_mem_wen(0) = '1' ELSE + time_mem_addr_w(1) WHEN time_mem_wen(1) = '1' ELSE + time_mem_addr_w(2) WHEN time_mem_wen(2) = '1' ELSE + time_mem_addr_w(3) WHEN time_mem_wen(3) = '1' ELSE + data_mem_addr_w(0) WHEN data_mem_wen(0) = '1' ELSE + data_mem_addr_w(1) WHEN data_mem_wen(1) = '1' ELSE + data_mem_addr_w(2) WHEN data_mem_wen(2) = '1' ELSE + data_mem_addr_w(3); + + gen_fifo_ctrl_time: FOR I IN 3 DOWNTO 0 GENERATE + lpp_waveform_fifo_ctrl_time: lpp_waveform_fifo_ctrl + GENERIC MAP ( + offset => 32*I + 20, + length => 10, + enable_ready => '0') + PORT MAP ( + clk => clk, + rstn => rstn, + ren => time_ren(I), + wen => time_wen(I), + mem_re => time_mem_ren(I), + mem_we => time_mem_wen(I), + mem_addr_ren => time_mem_addr_r(I), + mem_addr_wen => time_mem_addr_w(I), + ready => OPEN); + END GENERATE gen_fifo_ctrl_time; + + gen_fifo_ctrl_data: FOR I IN 3 DOWNTO 0 GENERATE + lpp_waveform_fifo_ctrl_data: lpp_waveform_fifo_ctrl + GENERIC MAP ( + offset => 32*I, + length => 20, + enable_ready => '1') + PORT MAP ( + clk => clk, + rstn => rstn, + ren => data_ren(I), + wen => data_wen(I), + mem_re => data_mem_ren(I), + mem_we => data_mem_wen(I), + mem_addr_ren => data_mem_addr_r(I), + mem_addr_wen => data_mem_addr_w(I), + ready => ready(I)); + END GENERATE gen_fifo_ctrl_data; + + +END ARCHITECTURE; + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/lib/lpp/lpp_waveform/lpp_waveform_fifo_arbiter.vhd b/lib/lpp/lpp_waveform/lpp_waveform_fifo_arbiter.vhd new file mode 100644 --- /dev/null +++ b/lib/lpp/lpp_waveform/lpp_waveform_fifo_arbiter.vhd @@ -0,0 +1,177 @@ +------------------------------------------------------------------------------ +-- This file is a part of the LPP VHDL IP LIBRARY +-- Copyright (C) 2009 - 2012, Laboratory of Plasmas Physic - CNRS +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 3 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +------------------------------------------------------------------------------ +-- Author : Jean-christophe PELLION +-- Mail : jean-christophe.pellion@lpp.polytechnique.fr +------------------------------------------------------------------------------ +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; +USE IEEE.numeric_std.ALL; + +LIBRARY lpp; +USE lpp.lpp_waveform_pkg.ALL; + +ENTITY lpp_waveform_fifo_arbiter IS + GENERIC( + tech : INTEGER := 0 + ); + PORT( + clk : IN STD_LOGIC; + rstn : IN STD_LOGIC; + + --------------------------------------------------------------------------- + data_f0_valid : IN STD_LOGIC; + data_f1_valid : IN STD_LOGIC; + data_f2_valid : IN STD_LOGIC; + data_f3_valid : IN STD_LOGIC; + + data_valid_ack : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + + data_f0 : IN STD_LOGIC_VECTOR(159 DOWNTO 0); + data_f1 : IN STD_LOGIC_VECTOR(159 DOWNTO 0); + data_f2 : IN STD_LOGIC_VECTOR(159 DOWNTO 0); + data_f3 : IN STD_LOGIC_VECTOR(159 DOWNTO 0); + + --------------------------------------------------------------------------- + ready : IN STD_LOGIC_VECTOR(3 DOWNTO 0); + + --------------------------------------------------------------------------- + time_wen : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + data_wen : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) + + ); +END ENTITY; + + +ARCHITECTURE ar_lpp_waveform_fifo_arbiter OF lpp_waveform_fifo_arbiter IS + TYPE state_fsm IS (IDLE, T1, T2, D1, D2); + SIGNAL state : state_fsm; + + SIGNAL data_valid_and_ready : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL data_selected : STD_LOGIC_VECTOR(159 DOWNTO 0); + SIGNAL data_valid_selected : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL data_ready_to_go : STD_LOGIC; + + SIGNAL data_temp : STD_LOGIC_VECTOR(32*4-1 DOWNTO 0); + SIGNAL time_en_temp : STD_LOGIC_VECTOR(3 DOWNTO 0); +BEGIN + + data_valid_and_ready(0) <= ready(0) AND data_f0_valid; + data_valid_and_ready(1) <= ready(1) AND data_f1_valid; + data_valid_and_ready(2) <= ready(2) AND data_f2_valid; + data_valid_and_ready(3) <= ready(3) AND data_f3_valid; + + data_selected <= data_f0 WHEN data_valid_and_ready(0) = '1' ELSE + data_f1 WHEN data_valid_and_ready(1) = '1' ELSE + data_f2 WHEN data_valid_and_ready(2) = '1' ELSE + data_f3; + + data_valid_selected <= "0001" WHEN data_valid_and_ready(0) = '1' ELSE + "0010" WHEN data_valid_and_ready(1) = '1' ELSE + "0100" WHEN data_valid_and_ready(2) = '1' ELSE + "1000" WHEN data_valid_and_ready(3) = '1' ELSE + "0000"; + + data_ready_to_go <= data_valid_and_ready(0) OR + data_valid_and_ready(1) OR + data_valid_and_ready(2) OR + data_valid_and_ready(3); + + PROCESS (clk, rstn) + BEGIN + IF rstn = '0' THEN + state <= IDLE; + data_valid_ack <= (OTHERS => '0'); + data_wen <= (OTHERS => '1'); + time_wen <= (OTHERS => '1'); + data <= (OTHERS => '0'); + data_temp <= (OTHERS => '0'); + time_en_temp <= (OTHERS => '0'); + ELSIF clk'EVENT AND clk = '1' THEN + CASE state IS + WHEN IDLE => + data_valid_ack <= (OTHERS => '0'); + time_wen <= (OTHERS => '1'); + data_wen <= (OTHERS => '1'); + data <= (OTHERS => '0'); + data_temp <= (OTHERS => '0'); + IF data_ready_to_go = '1' THEN + state <= T1; + data_valid_ack <= data_valid_selected; + time_wen <= NOT data_valid_selected; + time_en_temp <= NOT data_valid_selected; + data <= data_selected(31 DOWNTO 0); + data_temp <= data_selected(159 DOWNTO 32); + END IF; + WHEN T1 => + state <= T2; + data_valid_ack <= (OTHERS => '0'); + data <= data_temp(31 DOWNTO 0); + data_temp(32*3-1 DOWNTO 0) <= data_temp(32*4-1 DOWNTO 32); + + WHEN T2 => + state <= D1; + time_wen <= (OTHERS => '1'); + data_wen <= time_en_temp; + data <= data_temp(31 DOWNTO 0); + data_temp(32*3-1 DOWNTO 0) <= data_temp(32*4-1 DOWNTO 32); + + WHEN D1 => + state <= D2; + data <= data_temp(31 DOWNTO 0); + data_temp(32*3-1 DOWNTO 0) <= data_temp(32*4-1 DOWNTO 32); + + WHEN D2 => + state <= IDLE; + data <= data_temp(31 DOWNTO 0); + data_temp(32*3-1 DOWNTO 0) <= data_temp(32*4-1 DOWNTO 32); + + WHEN OTHERS => NULL; + END CASE; + + END IF; + END PROCESS; + +END ARCHITECTURE; + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/lib/lpp/lpp_waveform/lpp_waveform_fifo_ctrl.vhd b/lib/lpp/lpp_waveform/lpp_waveform_fifo_ctrl.vhd new file mode 100644 --- /dev/null +++ b/lib/lpp/lpp_waveform/lpp_waveform_fifo_ctrl.vhd @@ -0,0 +1,171 @@ +------------------------------------------------------------------------------ +-- This file is a part of the LPP VHDL IP LIBRARY +-- Copyright (C) 2009 - 2012, Laboratory of Plasmas Physic - CNRS +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 3 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +------------------------------------------------------------------------------ +-- Author : Jean-christophe PELLION +-- Mail : jean-christophe.pellion@lpp.polytechnique.fr +------------------------------------------------------------------------------ +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; +USE IEEE.numeric_std.ALL; +LIBRARY lpp; +USE lpp.lpp_memory.ALL; +USE lpp.iir_filter.ALL; +USE lpp.lpp_waveform_pkg.ALL; + +LIBRARY techmap; +USE techmap.gencomp.ALL; + +ENTITY lpp_waveform_fifo_ctrl IS + generic( + offset : INTEGER := 0; + length : INTEGER := 20; + enable_ready : STD_LOGIC := '1' + ); + PORT( + clk : IN STD_LOGIC; + rstn : IN STD_LOGIC; + + ren : IN STD_LOGIC; + wen : IN STD_LOGIC; + + mem_re : OUT STD_LOGIC; + mem_we : OUT STD_LOGIC; + + mem_addr_ren : out STD_LOGIC_VECTOR(6 DOWNTO 0); + mem_addr_wen : out STD_LOGIC_VECTOR(6 DOWNTO 0); + + ready : OUT STD_LOGIC + ); +END ENTITY; + + +ARCHITECTURE ar_lpp_waveform_fifo_ctrl OF lpp_waveform_fifo_ctrl IS + + SIGNAL sFull : STD_LOGIC; + SIGNAL sFull_s : STD_LOGIC; + SIGNAL sEmpty_s : STD_LOGIC; + + SIGNAL sEmpty : STD_LOGIC; + SIGNAL sREN : STD_LOGIC; + SIGNAL sWEN : STD_LOGIC; + SIGNAL sRE : STD_LOGIC; + SIGNAL sWE : STD_LOGIC; + + SIGNAL Waddr_vect : INTEGER RANGE 0 TO length := 0; + SIGNAL Raddr_vect : INTEGER RANGE 0 TO length := 0; + SIGNAL Waddr_vect_s : INTEGER RANGE 0 TO length := 0; + SIGNAL Raddr_vect_s : INTEGER RANGE 0 TO length := 0; + +BEGIN + mem_re <= sRE; + mem_we <= sWE; +--============================= +-- Read section +--============================= + sREN <= REN OR sEmpty; + sRE <= NOT sREN; + + sEmpty_s <= '1' WHEN sEmpty = '1' AND Wen = '1' ELSE + '1' WHEN sEmpty = '0' AND (Wen = '1' AND Ren = '0' AND Raddr_vect_s = Waddr_vect) ELSE + '0'; + + Raddr_vect_s <= Raddr_vect +1 WHEN Raddr_vect < length -1 ELSE 0 ; + + PROCESS (clk, rstn) + BEGIN + IF(rstn = '0')then + Raddr_vect <= 0; + sempty <= '1'; + ELSIF(clk'EVENT AND clk = '1')then + sEmpty <= sempty_s; + + IF(sREN = '0' and sempty = '0')then + Raddr_vect <= Raddr_vect_s; + END IF; + + END IF; + END PROCESS; + +--============================= +-- Write section +--============================= + sWEN <= WEN OR sFull; + sWE <= NOT sWEN; + + sFull_s <= '1' WHEN Waddr_vect_s = Raddr_vect AND REN = '1' AND WEN = '0' ELSE + '1' WHEN sFull = '1' AND REN = '1' ELSE + '0'; + + Waddr_vect_s <= Waddr_vect +1 WHEN Waddr_vect < length -1 ELSE 0 ; + + PROCESS (clk, rstn) + BEGIN + IF(rstn = '0')then + Waddr_vect <= 0; + sfull <= '0'; + ELSIF(clk'EVENT AND clk = '1')then + sfull <= sfull_s; + + IF(sWEN = '0' and sfull = '0')THEN + Waddr_vect <= Waddr_vect_s; + END IF; + + END IF; + END PROCESS; + + + mem_addr_wen <= std_logic_vector(to_unsigned((Waddr_vect + offset), mem_addr_wen'length)); + mem_addr_ren <= std_logic_vector(to_unsigned((Raddr_vect + offset), mem_addr_ren'length)); + + ready_gen: IF enable_ready = '1' GENERATE + ready <= '1' WHEN Waddr_vect > Raddr_vect AND (Waddr_vect - Raddr_vect) > 15 ELSE + '1' WHEN Waddr_vect < Raddr_vect AND (length + Waddr_vect - Raddr_vect) > 15 ELSE + '0'; + END GENERATE ready_gen; + + ready_not_gen: IF enable_ready = '0' GENERATE + ready <= '0'; + END GENERATE ready_not_gen; + +END ARCHITECTURE; + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/lib/lpp/lpp_waveform/lpp_waveform_pkg.vhd b/lib/lpp/lpp_waveform/lpp_waveform_pkg.vhd new file mode 100644 --- /dev/null +++ b/lib/lpp/lpp_waveform/lpp_waveform_pkg.vhd @@ -0,0 +1,243 @@ +LIBRARY IEEE; +USE IEEE.STD_LOGIC_1164.ALL; + +LIBRARY grlib; +USE grlib.amba.ALL; +USE grlib.stdlib.ALL; +USE grlib.devices.ALL; +USE GRLIB.DMA2AHB_Package.ALL; + +LIBRARY techmap; +USE techmap.gencomp.ALL; + +PACKAGE lpp_waveform_pkg IS + + TYPE LPP_TYPE_ADDR_FIFO_WAVEFORM IS ARRAY (NATURAL RANGE <>) OF STD_LOGIC_VECTOR(6 DOWNTO 0); + + COMPONENT lpp_waveform_snapshot + GENERIC ( + data_size : INTEGER; + nb_snapshot_param_size : INTEGER); + PORT ( + clk : IN STD_LOGIC; + rstn : IN STD_LOGIC; + enable : IN STD_LOGIC; + burst_enable : IN STD_LOGIC; + nb_snapshot_param : IN STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0); + start_snapshot : IN STD_LOGIC; + data_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); + data_in_valid : IN STD_LOGIC; + data_out : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); + data_out_valid : OUT STD_LOGIC); + END COMPONENT; + + COMPONENT lpp_waveform_burst + GENERIC ( + data_size : INTEGER); + PORT ( + clk : IN STD_LOGIC; + rstn : IN STD_LOGIC; + enable : IN STD_LOGIC; + data_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); + data_in_valid : IN STD_LOGIC; + data_out : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); + data_out_valid : OUT STD_LOGIC); + END COMPONENT; + + COMPONENT lpp_waveform_snapshot_controler + GENERIC ( + delta_snapshot_size : INTEGER; + delta_f2_f0_size : INTEGER; + delta_f2_f1_size : INTEGER); + PORT ( + clk : IN STD_LOGIC; + rstn : IN STD_LOGIC; + delta_snapshot : IN STD_LOGIC_VECTOR(delta_snapshot_size-1 DOWNTO 0); + delta_f2_f1 : IN STD_LOGIC_VECTOR(delta_f2_f1_size-1 DOWNTO 0); + delta_f2_f0 : IN STD_LOGIC_VECTOR(delta_f2_f0_size-1 DOWNTO 0); + coarse_time_0 : IN STD_LOGIC; + data_f0_in_valid : IN STD_LOGIC; + data_f2_in_valid : IN STD_LOGIC; + start_snapshot_f0 : OUT STD_LOGIC; + start_snapshot_f1 : OUT STD_LOGIC; + start_snapshot_f2 : OUT STD_LOGIC); + END COMPONENT; + + + + COMPONENT lpp_waveform + GENERIC ( + hindex : INTEGER; + tech : INTEGER; + data_size : INTEGER; + nb_burst_available_size : INTEGER; + nb_snapshot_param_size : INTEGER; + delta_snapshot_size : INTEGER; + delta_f2_f0_size : INTEGER; + delta_f2_f1_size : INTEGER); + PORT ( + clk : IN STD_LOGIC; + rstn : IN STD_LOGIC; + AHB_Master_In : IN AHB_Mst_In_Type; + AHB_Master_Out : OUT AHB_Mst_Out_Type; + coarse_time_0 : IN STD_LOGIC; + delta_snapshot : IN STD_LOGIC_VECTOR(delta_snapshot_size-1 DOWNTO 0); + delta_f2_f1 : IN STD_LOGIC_VECTOR(delta_f2_f1_size-1 DOWNTO 0); + delta_f2_f0 : IN STD_LOGIC_VECTOR(delta_f2_f0_size-1 DOWNTO 0); + enable_f0 : IN STD_LOGIC; + enable_f1 : IN STD_LOGIC; + enable_f2 : IN STD_LOGIC; + enable_f3 : IN STD_LOGIC; + burst_f0 : IN STD_LOGIC; + burst_f1 : IN STD_LOGIC; + burst_f2 : IN STD_LOGIC; + nb_burst_available : IN STD_LOGIC_VECTOR(nb_burst_available_size-1 DOWNTO 0); + nb_snapshot_param : IN STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0); + status_full : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + status_full_ack : IN STD_LOGIC_VECTOR(3 DOWNTO 0); + status_full_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + status_new_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + addr_data_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + addr_data_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + addr_data_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + addr_data_f3 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + data_f0_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); + data_f1_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); + data_f2_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); + data_f3_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); + data_f0_in_valid : IN STD_LOGIC; + data_f1_in_valid : IN STD_LOGIC; + data_f2_in_valid : IN STD_LOGIC; + data_f3_in_valid : IN STD_LOGIC); + END COMPONENT; + + COMPONENT lpp_waveform_dma_send_Nword + PORT ( + HCLK : IN STD_ULOGIC; + HRESETn : IN STD_ULOGIC; + DMAIn : OUT DMA_In_Type; + DMAOut : IN DMA_OUt_Type; + Nb_word_less1 : IN STD_LOGIC_VECTOR(3 DOWNTO 0); + send : IN STD_LOGIC; + address : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + data : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + ren : OUT STD_LOGIC; + send_ok : OUT STD_LOGIC; + send_ko : OUT STD_LOGIC); + END COMPONENT; + + COMPONENT lpp_waveform_dma_selectaddress + GENERIC ( + nb_burst_available_size : INTEGER); + PORT ( + HCLK : IN STD_ULOGIC; + HRESETn : IN STD_ULOGIC; + update : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + nb_burst_available : IN STD_LOGIC_VECTOR(nb_burst_available_size-1 DOWNTO 0); + addr_data_reg : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + addr_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + status_full : OUT STD_LOGIC; + status_full_ack : IN STD_LOGIC; + status_full_err : OUT STD_LOGIC); + END COMPONENT; + + COMPONENT lpp_waveform_dma_gen_valid + PORT ( + HCLK : IN STD_LOGIC; + HRESETn : IN STD_LOGIC; + valid_in : IN STD_LOGIC; + ack_in : IN STD_LOGIC; + valid_out : OUT STD_LOGIC; + error : OUT STD_LOGIC); + END COMPONENT; + + COMPONENT lpp_waveform_dma + GENERIC ( + data_size : INTEGER; + tech : INTEGER; + hindex : INTEGER; + nb_burst_available_size : INTEGER); + PORT ( + HCLK : IN STD_ULOGIC; + HRESETn : IN STD_ULOGIC; + AHB_Master_In : IN AHB_Mst_In_Type; + AHB_Master_Out : OUT AHB_Mst_Out_Type; + data_ready : IN STD_LOGIC_VECTOR(3 DOWNTO 0); + data : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + data_data_ren : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + data_time_ren : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + --data_f0_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); + --data_f1_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); + --data_f2_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); + --data_f3_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); + --data_f0_in_valid : IN STD_LOGIC; + --data_f1_in_valid : IN STD_LOGIC; + --data_f2_in_valid : IN STD_LOGIC; + --data_f3_in_valid : IN STD_LOGIC; + nb_burst_available : IN STD_LOGIC_VECTOR(nb_burst_available_size-1 DOWNTO 0); + status_full : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + status_full_ack : IN STD_LOGIC_VECTOR(3 DOWNTO 0); + status_full_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); +-- status_new_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + addr_data_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + addr_data_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + addr_data_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + addr_data_f3 : IN STD_LOGIC_VECTOR(31 DOWNTO 0)); + END COMPONENT; + + COMPONENT lpp_waveform_fifo_ctrl + GENERIC ( + offset : INTEGER; + length : INTEGER; + enable_ready : STD_LOGIC); + PORT ( + clk : IN STD_LOGIC; + rstn : IN STD_LOGIC; + ren : IN STD_LOGIC; + wen : IN STD_LOGIC; + mem_re : OUT STD_LOGIC; + mem_we : OUT STD_LOGIC; + mem_addr_ren : out STD_LOGIC_VECTOR(6 DOWNTO 0); + mem_addr_wen : out STD_LOGIC_VECTOR(6 DOWNTO 0); + ready : OUT STD_LOGIC); + END COMPONENT; + + COMPONENT lpp_waveform_fifo_arbiter + GENERIC ( + tech : INTEGER); + PORT ( + clk : IN STD_LOGIC; + rstn : IN STD_LOGIC; + data_f0_valid : IN STD_LOGIC; + data_f1_valid : IN STD_LOGIC; + data_f2_valid : IN STD_LOGIC; + data_f3_valid : IN STD_LOGIC; + data_valid_ack : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + data_f0 : IN STD_LOGIC_VECTOR(159 DOWNTO 0); + data_f1 : IN STD_LOGIC_VECTOR(159 DOWNTO 0); + data_f2 : IN STD_LOGIC_VECTOR(159 DOWNTO 0); + data_f3 : IN STD_LOGIC_VECTOR(159 DOWNTO 0); + ready : IN STD_LOGIC_VECTOR(3 DOWNTO 0); + time_wen : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + data_wen : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)); + END COMPONENT; + + COMPONENT lpp_waveform_fifo + GENERIC ( + tech : INTEGER); + PORT ( + clk : IN STD_LOGIC; + rstn : IN STD_LOGIC; + ready : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + time_ren : IN STD_LOGIC_VECTOR(3 DOWNTO 0); + data_ren : IN STD_LOGIC_VECTOR(3 DOWNTO 0); + rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + time_wen : IN STD_LOGIC_VECTOR(3 DOWNTO 0); + data_wen : IN STD_LOGIC_VECTOR(3 DOWNTO 0); + wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0)); + END COMPONENT; + + + +END lpp_waveform_pkg; diff --git a/lib/lpp/lpp_waveform/lpp_waveform_snapshot.vhd b/lib/lpp/lpp_waveform/lpp_waveform_snapshot.vhd new file mode 100644 --- /dev/null +++ b/lib/lpp/lpp_waveform/lpp_waveform_snapshot.vhd @@ -0,0 +1,80 @@ +LIBRARY IEEE; +USE IEEE.STD_LOGIC_1164.ALL; +USE ieee.numeric_std.ALL; + +ENTITY lpp_waveform_snapshot IS + + GENERIC ( + data_size : INTEGER := 16; + nb_snapshot_param_size : INTEGER := 11); + + PORT ( + clk : IN STD_LOGIC; + rstn : IN STD_LOGIC; + + enable : IN STD_LOGIC; + burst_enable : IN STD_LOGIC; + nb_snapshot_param : IN STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0); + + start_snapshot : IN STD_LOGIC; + + data_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); + data_in_valid : IN STD_LOGIC; + + data_out : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); + data_out_valid : OUT STD_LOGIC + ); + +END lpp_waveform_snapshot; + +ARCHITECTURE beh OF lpp_waveform_snapshot IS + SIGNAL counter_points_snapshot : INTEGER; +BEGIN -- beh + + PROCESS (clk, rstn) + BEGIN + IF rstn = '0' THEN + data_out <= (OTHERS => '0'); + data_out_valid <= '0'; + counter_points_snapshot <= 0; + ELSIF clk'EVENT AND clk = '1' THEN + data_out <= data_in; + IF enable = '0' THEN + data_out_valid <= '0'; + counter_points_snapshot <= 0; + ELSE + IF burst_enable = '1' THEN + -- BURST ModE -- + data_out_valid <= data_in_valid; + counter_points_snapshot <= 0; + ELSE + -- SNAPShOT MODE -- + IF start_snapshot = '1' THEN + IF data_in_valid = '1' THEN + counter_points_snapshot <= to_integer(unsigned(nb_snapshot_param)) - 1; + data_out_valid <= '1'; + ELSE + counter_points_snapshot <= to_integer(unsigned(nb_snapshot_param)); + data_out_valid <= '0'; + END IF; + ELSE + IF data_in_valid = '1' THEN + IF counter_points_snapshot > 0 THEN + counter_points_snapshot <= counter_points_snapshot - 1; + data_out_valid <= '1'; + ELSE + counter_points_snapshot <= counter_points_snapshot; + data_out_valid <= '0'; + END IF; + ELSE + counter_points_snapshot <= counter_points_snapshot; + data_out_valid <= '0'; + END IF; + END IF; + + END IF; + END IF; + END IF; + END PROCESS; + +END beh; diff --git a/lib/lpp/lpp_waveform/lpp_waveform_snapshot_controler.vhd b/lib/lpp/lpp_waveform/lpp_waveform_snapshot_controler.vhd new file mode 100644 --- /dev/null +++ b/lib/lpp/lpp_waveform/lpp_waveform_snapshot_controler.vhd @@ -0,0 +1,116 @@ +LIBRARY IEEE; +USE IEEE.STD_LOGIC_1164.ALL; +USE ieee.numeric_std.ALL; + +ENTITY lpp_waveform_snapshot_controler IS + + GENERIC ( + delta_snapshot_size : INTEGER := 16; + delta_f2_f0_size : INTEGER := 10; + delta_f2_f1_size : INTEGER := 10); + + PORT ( + clk : IN STD_LOGIC; + rstn : IN STD_LOGIC; + --config + delta_snapshot : IN STD_LOGIC_VECTOR(delta_snapshot_size-1 DOWNTO 0); + delta_f2_f1 : IN STD_LOGIC_VECTOR(delta_f2_f1_size-1 DOWNTO 0); + delta_f2_f0 : IN STD_LOGIC_VECTOR(delta_f2_f0_size-1 DOWNTO 0); + + --input + coarse_time_0 : IN STD_LOGIC; + data_f0_in_valid : IN STD_LOGIC; + data_f2_in_valid : IN STD_LOGIC; + --output + start_snapshot_f0 : OUT STD_LOGIC; + start_snapshot_f1 : OUT STD_LOGIC; + start_snapshot_f2 : OUT STD_LOGIC + ); + +END lpp_waveform_snapshot_controler; + +ARCHITECTURE beh OF lpp_waveform_snapshot_controler IS + SIGNAL counter_delta_snapshot : INTEGER; + SIGNAL counter_delta_f0 : INTEGER; + + SIGNAL coarse_time_0_r : STD_LOGIC; + SIGNAL start_snapshot_f2_temp : STD_LOGIC; + SIGNAL start_snapshot_fothers_temp : STD_LOGIC; + SIGNAL start_snapshot_fothers_temp2 : STD_LOGIC; +BEGIN -- beh + + PROCESS (clk, rstn) + BEGIN + IF rstn = '0' THEN + start_snapshot_f0 <= '0'; + start_snapshot_f1 <= '0'; + start_snapshot_f2 <= '0'; + counter_delta_snapshot <= 0; + counter_delta_f0 <= 0; + coarse_time_0_r <= '0'; + start_snapshot_f2_temp <= '0'; + start_snapshot_fothers_temp <= '0'; + start_snapshot_fothers_temp2 <= '0'; + ELSIF clk'EVENT AND clk = '1' THEN + IF counter_delta_snapshot = UNSIGNED(delta_snapshot) THEN + start_snapshot_f2_temp <= '1'; + ELSE + start_snapshot_f2_temp <= '0'; + END IF; + ------------------------------------------------------------------------- + IF counter_delta_snapshot = UNSIGNED(delta_snapshot) AND start_snapshot_f2_temp = '0' THEN + start_snapshot_f2 <= '1'; + ELSE + start_snapshot_f2 <= '0'; + END IF; + ------------------------------------------------------------------------- + coarse_time_0_r <= coarse_time_0; + IF coarse_time_0 = NOT coarse_time_0_r AND coarse_time_0 = '1' THEN + IF counter_delta_snapshot = 0 THEN + counter_delta_snapshot <= to_integer(UNSIGNED(delta_snapshot)); + ELSE + counter_delta_snapshot <= counter_delta_snapshot - 1; + END IF; + END IF; + + + ------------------------------------------------------------------------- + + + + IF counter_delta_f0 = UNSIGNED(delta_f2_f1) THEN + start_snapshot_f1 <= '1'; + ELSE + start_snapshot_f1 <= '0'; + END IF; + + IF counter_delta_f0 = 1 THEN --UNSIGNED(delta_f2_f0) THEN + start_snapshot_f0 <= '1'; + ELSE + start_snapshot_f0 <= '0'; + END IF; + + IF counter_delta_snapshot = UNSIGNED(delta_snapshot) + AND start_snapshot_f2_temp = '0' + THEN -- + start_snapshot_fothers_temp <= '1'; + ELSIF counter_delta_f0 > 0 THEN + start_snapshot_fothers_temp <= '0'; + END IF; + + + ------------------------------------------------------------------------- + IF (start_snapshot_fothers_temp = '1' OR (counter_delta_snapshot = UNSIGNED(delta_snapshot) AND start_snapshot_f2_temp = '0')) AND data_f2_in_valid = '1' THEN + --counter_delta_snapshot = UNSIGNED(delta_snapshot) AND start_snapshot_f2_temp = '0' THEN -- + --counter_delta_snapshot = UNSIGNED(delta_snapshot) THEN + counter_delta_f0 <= to_integer(UNSIGNED(delta_f2_f0)); --0; + ELSE + IF (( counter_delta_f0 > 0 ) AND ( data_f0_in_valid = '1' )) THEN --<= UNSIGNED(delta_f2_f0) THEN + counter_delta_f0 <= counter_delta_f0 - 1;--counter_delta_f0 + 1; + END IF; + END IF; + ------------------------------------------------------------------------- + END IF; + END PROCESS; + +END beh; diff --git a/lib/lpp/lpp_waveform/lpp_waveform_valid_ack.vhd b/lib/lpp/lpp_waveform/lpp_waveform_valid_ack.vhd new file mode 100644 --- /dev/null +++ b/lib/lpp/lpp_waveform/lpp_waveform_valid_ack.vhd @@ -0,0 +1,88 @@ +------------------------------------------------------------------------------ +-- This file is a part of the LPP VHDL IP LIBRARY +-- Copyright (C) 2009 - 2012, Laboratory of Plasmas Physic - CNRS +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 3 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +------------------------------------------------------------------------------ +-- Author : Jean-christophe PELLION +-- Mail : jean-christophe.pellion@lpp.polytechnique.fr +------------------------------------------------------------------------------ +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; +USE IEEE.numeric_std.ALL; + +LIBRARY lpp; +USE lpp.lpp_waveform_pkg.ALL; + +ENTITY lpp_waveform_valid_ack IS + PORT( + clk : IN STD_LOGIC; + rstn : IN STD_LOGIC; + + data_valid_in : IN STD_LOGIC_VECTOR(3 DOWNTO 0); + data_valid_out : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + error_valid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0) + ); +END ENTITY; + + +ARCHITECTURE ar_lpp_waveform_valid_ack OF lpp_waveform_valid_ack IS + + SIGNAL data_valid_temp : STD_LOGIC_VECTOR(3 DOWNTO 0); + +BEGIN + + all_input: FOR I IN 3 DOWNTO 0 GENERATE + + PROCESS (clk, rstn) + BEGIN + IF rstn = '0' THEN + data_valid_temp(I) <= '0'; + ELSIF clk'event AND clk = '1' THEN + data_valid_temp(I) <= data_valid_in(I); + data_valid_out(I) <= data_valid_in(I) AND ; + + END IF; + END PROCESS; + + END GENERATE all_input; + +END ARCHITECTURE; + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/lib/lpp/lpp_waveform/vhdlsyn.txt b/lib/lpp/lpp_waveform/vhdlsyn.txt new file mode 100644 --- /dev/null +++ b/lib/lpp/lpp_waveform/vhdlsyn.txt @@ -0,0 +1,9 @@ +lpp_waveform_pkg.vhd +lpp_waveform.vhd +lpp_waveform_snapshot_controler.vhd +lpp_waveform_snapshot.vhd +lpp_waveform_burst.vhd +lpp_waveform_dma.vhd +lpp_waveform_dma_send_Nword.vhd +lpp_waveform_dma_selectaddress.vhd +lpp_waveform_dma_genvalid.vhd