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1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2012, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2012, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 ------------------------------------------------------------------------------
18 ------------------------------------------------------------------------------
19 -- Author : Martin Morlot
19 -- Author : Martin Morlot
20 -- Mail : martin.morlot@lpp.polytechnique.fr
20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 ------------------------------------------------------------------------------
21 ------------------------------------------------------------------------------
22 library IEEE;
22 library IEEE;
23 use IEEE.std_logic_1164.all;
23 use IEEE.std_logic_1164.all;
24 use IEEE.numeric_std.all;
24 use IEEE.numeric_std.all;
25
25
26 entity HeaderBuilder is
26 entity HeaderBuilder is
27 generic(
27 generic(
28 Data_sz : integer := 32);
28 Data_sz : integer := 32);
29 port(
29 port(
30 clkm : in std_logic;
30 clkm : in std_logic;
31 rstn : in std_logic;
31 rstn : in std_logic;
32
32
33 pong : in std_logic;
33 pong : in std_logic;
34 Statu : in std_logic_vector(3 downto 0);
34 Statu : in std_logic_vector(3 downto 0);
35 Matrix_Type : in std_logic_vector(1 downto 0);
35 Matrix_Type : in std_logic_vector(1 downto 0);
36 Matrix_Write : in std_logic;
36 Matrix_Write : in std_logic;
37 Valid : out std_logic;
37 Valid : out std_logic;
38
38
39 dataIN : in std_logic_vector((2*Data_sz)-1 downto 0);
39 dataIN : in std_logic_vector((2*Data_sz)-1 downto 0);
40 emptyIN : in std_logic_vector(1 downto 0);
40 emptyIN : in std_logic_vector(1 downto 0);
41 RenOUT : out std_logic_vector(1 downto 0);
41 RenOUT : out std_logic_vector(1 downto 0);
42
42
43 dataOUT : out std_logic_vector(Data_sz-1 downto 0);
43 dataOUT : out std_logic_vector(Data_sz-1 downto 0);
44 emptyOUT : out std_logic;
44 emptyOUT : out std_logic;
45 RenIN : in std_logic;
45 RenIN : in std_logic;
46
46
47 header : out std_logic_vector(Data_sz-1 DOWNTO 0);
47 header : out std_logic_vector(Data_sz-1 DOWNTO 0);
48 header_val : out std_logic;
48 header_val : out std_logic;
49 header_ack : in std_logic
49 header_ack : in std_logic
50 );
50 );
51 end entity;
51 end entity;
52
52
53
53
54 architecture ar_HeaderBuilder of HeaderBuilder is
54 architecture ar_HeaderBuilder of HeaderBuilder is
55
55
56 signal Matrix_Param : std_logic_vector(3 downto 0);
56 signal Matrix_Param : std_logic_vector(3 downto 0);
57 signal Write_reg : std_logic;
57 signal Write_reg : std_logic;
58 signal Data_cpt : integer;
58 signal Data_cpt : integer;
59 signal MAX : integer;
59 signal MAX : integer;
60
60
61
61
62 begin
62 begin
63
63
64 process (clkm,rstn)
64 process (clkm,rstn)
65 begin
65 begin
66 if(rstn='0')then
66 if(rstn='0')then
67 Valid <= '0';
67 Valid <= '0';
68 Write_reg <= '0';
68 Write_reg <= '0';
69 Data_cpt <= 0;
69 Data_cpt <= 0;
70 MAX <= 0;
70 MAX <= 0;
71
71
72
72
73 elsif(clkm' event and clkm='1')then
73 elsif(clkm' event and clkm='1')then
74 Write_reg <= Matrix_Write;
74 Write_reg <= Matrix_Write;
75
75
76 if(Statu="0001" or Statu="0011" or Statu="0110" or Statu="1010" or Statu="1111")then
76 if(Statu="0001" or Statu="0011" or Statu="0110" or Statu="1010" or Statu="1111")then
77 MAX <= 128;
77 MAX <= 128;
78 else
78 else
79 MAX <= 256;
79 MAX <= 256;
80 end if;
80 end if;
81
81
82 if(Write_reg = '0' and Matrix_Write = '1')then
82 if(Write_reg = '0' and Matrix_Write = '1')then
83 if(Data_cpt = MAX)then
83 if(Data_cpt = MAX)then
84 Data_cpt <= 0;
84 Data_cpt <= 0;
85 Valid <= '1';
85 Valid <= '1';
86 header_val <= '1';
86 header_val <= '1';
87 else
87 else
88 Data_cpt <= Data_cpt + 1;
88 Data_cpt <= Data_cpt + 1;
89 Valid <= '0';
89 Valid <= '0';
90 end if;
90 end if;
91 end if;
91 end if;
92
92
93 if(header_ack = '1')then
93 if(header_ack = '1')then
94 header_val <= '0';
94 header_val <= '0';
95 end if;
95 end if;
96
96
97 end if;
97 end if;
98 end process;
98 end process;
99
99
100 Matrix_Param <= std_logic_vector(to_unsigned(to_integer(unsigned(Statu))-1,4));
100 Matrix_Param <= std_logic_vector(to_unsigned(to_integer(unsigned(Statu))-1,4));
101
101
102 header(1 downto 0) <= Matrix_Type;
102 header(1 downto 0) <= Matrix_Type;
103 header(5 downto 2) <= Matrix_Param;
103 header(5 downto 2) <= Matrix_Param;
104
104
105 dataOUT <= dataIN(Data_sz-1 downto 0) when pong = '0' else dataIN((2*Data_sz)-1 downto Data_sz);
105 dataOUT <= dataIN(Data_sz-1 downto 0) when pong = '0' else dataIN((2*Data_sz)-1 downto Data_sz);
106 emptyOUT <= emptyIN(0) when pong = '0' else emptyIN(1);
106 emptyOUT <= emptyIN(0) when pong = '0' else emptyIN(1);
107
107
108 RenOUT <= '1' & RenIN when pong = '0' else RenIN & '1';
108 RenOUT <= '1' & RenIN when pong = '0' else RenIN & '1';
109
109
110 end architecture; No newline at end of file
110 end architecture;
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