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r598:a4da461dd67d
LFR-EQM 2.1.81 > all is ok, the ADC data are sampled at 500M.sample.Hz
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r597:ec6fbc748101
save
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r596:04687799528c
ok
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r595:eb603d70d051
register the data outputed by ADC_driver
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r594:a9702b7364d2
temp : update ADC driver - conversion part clocked by clk_49 (49.152 MHz) - cnv_clk = clk_49.152/100 with duty cycle of 50% - 3 period for each Ren, - Data sampling during the 2nd cycle of Ren, - each 2 data input, 1 data output (@)
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r593:173a643f1c9c
temp
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r589:ebd290519818
update ok ??
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r588:86f47bdf2a6e
force ADC output to constant or ramp.
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r587:f2c158b74433
global reset delayed in function of ram_nbusy signal (waiting 16 falling edge).
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r586:e44412efb127
temp JC
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r585:fd7ec3818c5e
temp Alexis
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r584:e4c118ae5ff2
update version
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r583:3d475eacd91a
LFR-EQM 2.1.71
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r582:3fed66e2161d
Simulation without RAM_CEL
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r581:006d69890bba
custom dma : update lock generation into LPP_DMA's FSM state (Just for test)
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r580:f4e8c3120b82
custom dma : update transition's condition between FSM state "ARBITER" and "CTRL"
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