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global reset delayed in function of ram_nbusy signal (waiting 16 falling edge).
pellion -
r587:f2c158b74433 simu_with_Leon3
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@@ -169,14 +169,41 ARCHITECTURE beh OF LFR_EQM IS
169 SIGNAL clk_25_int : STD_LOGIC := '0';
169 SIGNAL clk_25_int : STD_LOGIC := '0';
170
170
171 component clkint port(A : in std_ulogic; Y :out std_ulogic); end component;
171 component clkint port(A : in std_ulogic; Y :out std_ulogic); end component;
172
172
173 SIGNAL rstn_50 : STD_LOGIC;
174 SIGNAL clk_lock : STD_LOGIC;
175 SIGNAL clk_busy_counter : STD_LOGIC_VECTOR(3 DOWNTO 0);
176 SIGNAL nSRAM_BUSY_reg : STD_LOGIC;
173 BEGIN -- beh
177 BEGIN -- beh
174
178
175 -----------------------------------------------------------------------------
179 -----------------------------------------------------------------------------
180 -- CLK_LOCK
181 -----------------------------------------------------------------------------
182 rst_gen_global : rstgen PORT MAP (reset, clk_50, '1', rstn_50, OPEN);
183
184 PROCESS (clk50MHz_int, rstn_50)
185 BEGIN -- PROCESS
186 IF rstn_50 = '0' THEN -- asynchronous reset (active low)
187 clk_lock <= '0';
188 clk_busy_counter <= (OTHERS => '0');
189 nSRAM_BUSY_reg <= '0';
190 ELSIF clk50MHz_int'event AND clk50MHz_int = '1' THEN -- rising clock edge
191 nSRAM_BUSY_reg <= nSRAM_BUSY;
192 IF nSRAM_BUSY_reg = '1' AND nSRAM_BUSY = '0' THEN
193 IF clk_busy_counter = "1111" THEN
194 clk_lock = '1';
195 ELSE
196 clk_busy_counter <= STD_LOGIC_VECTOR(to_unsigned(to_integer(UNSIGNED(clk_busy_counter))+1,4));
197 END IF;
198 END IF;
199 END IF;
200 END PROCESS;
201
202 -----------------------------------------------------------------------------
176 -- CLK
203 -- CLK
177 -----------------------------------------------------------------------------
204 -----------------------------------------------------------------------------
178 rst_domain25 : rstgen PORT MAP (reset, clk_25, '1', rstn_25, OPEN);
205 rst_domain25 : rstgen PORT MAP (reset, clk_25, clk_lock, rstn_25, OPEN);
179 rst_domain24 : rstgen PORT MAP (reset, clk_24, '1', rstn_24, OPEN);
206 rst_domain24 : rstgen PORT MAP (reset, clk_24, clk_lock, rstn_24, OPEN);
180
207
181 --clk_pad : clkint port map (A => clk50MHz, Y => clk50MHz_int );
208 --clk_pad : clkint port map (A => clk50MHz, Y => clk50MHz_int );
182 clk50MHz_int <= clk50MHz;
209 clk50MHz_int <= clk50MHz;
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