HG_REPOSITORIES/LPP/INSTRUMENTATION/USERS/PELLION/VHD_Lib Commit - r582:3fed66e2161d

Simulation without RAM_CEL

pellion -

r582:3fed66e2161d simu_with_Leon3

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r582:3fed66e2161d

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lib/lpp/lpp_dma/lpp_dma_SEND16B_FIFO2DMA.vhd +22 -3

               SIGNAL bus_request : STD_LOGIC;
               SIGNAL bus_lock : STD_LOGIC;
+              SIGNAL data_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
             BEGIN
               -----------------------------------------------------------------------------
               AHB_Master_Out.HADDR  <= address(31 DOWNTO 6) & address_counter_reg & "00";
-              AHB_Master_Out.HWDATA <= ahbdrivedata(data);
+              AHB_Master_Out.HWDATA <= ahbdrivedata(data) WHEN AHB_Master_In.HREADY = '1' ELSE ahbdrivedata(data_reg);
               -----------------------------------------------------------------------------
               --ren <= NOT ((AHB_Master_In.HGRANT(hindex) OR LAST_READ ) AND AHB_Master_In.HREADY );
               --ren <= NOT beat;
                 IF rstn = '0' THEN                  -- asynchronous reset (active low)
                   state <= IDLE;
                   done <= '0';
+                  ren <= '1';
                   address_counter_reg <= (OTHERS => '0');
                   AHB_Master_Out.HTRANS  <= HTRANS_IDLE;
                   AHB_Master_Out.HBUSREQ <= '0';
                   AHB_Master_Out.HLOCK   <= '0';
+                  data_reg <= (OTHERS => '0');
                 ELSIF clk'event AND clk = '1' THEN  -- rising clock edge
+                  IF AHB_Master_In.HREADY = '1' AND AHB_Master_In.HGRANT(hindex) = '1'  THEN
+                    data_reg <= data;
+                  END IF;
                   done <= '0';
+                  ren <= '1';
                   CASE state IS
                     WHEN IDLE =>
                       AHB_Master_Out.HBUSREQ <= '0';
                       IF AHB_Master_In.HREADY = '1' AND AHB_Master_In.HGRANT(hindex) = '1' THEN
                         AHB_Master_Out.HTRANS  <= HTRANS_SEQ;
                         state <= s_CTRL_DATA;
+                        ren <= '0';
                       END IF;
                     WHEN s_CTRL_DATA =>
                         state <= s_DATA;
                       END IF;
+                      IF AHB_Master_In.HREADY = '1' AND AHB_Master_In.HGRANT(hindex) = '1' AND address_counter_reg /= "1111" THEN
+                        ren <= '0';
+                      END IF;
                     WHEN s_DATA =>
                       AHB_Master_Out.HBUSREQ <= '0';
                       --AHB_Master_Out.HLOCK   <= '0';
               ctrl_window <= '1' WHEN state = s_CTRL OR state = s_CTRL_DATA ELSE '0';
               data_window <= '1' WHEN state = s_CTRL_DATA OR state = s_DATA ELSE '0';
               -----------------------------------------------------------------------------
-              ren <= NOT(AHB_Master_In.HREADY) WHEN state = s_CTRL_DATA ELSE '1';
+              --ren <= NOT(AHB_Master_In.HREADY) WHEN state = s_CTRL_DATA ELSE '1';
               -----------------------------------------------------------------------------
               --PROCESS (clk, rstn)

lib/lpp/lpp_leon3_soc/leon3_soc.vhd +1 -1

                     --Aeroflex memory generics:
                     mbpedac  => BYPASS_EDAC_MEMCTRLR,
                     mprog    => 1,          -- program memory by default values after reset
-                    mpsrate  => 15,                 -- default scrub rate period
+                    mpsrate  => 5,                 -- default scrub rate period
                     mpb2s    => 14,                  -- default busy to scrub delay
                     mpapb    => 1,                  -- instantiate apb register
                     mchipcnt => 2,

lib/lpp/lpp_top_lfr/lpp_lfr.vhd +58 -9

@@ -83,6 +83,9 ARCHITECTURE beh OF lpp_lfr IS
83	SIGNAL sample_f2_val : STD_LOGIC;	83	SIGNAL sample_f2_val : STD_LOGIC;
84	SIGNAL sample_f3_val : STD_LOGIC;	84	SIGNAL sample_f3_val : STD_LOGIC;
85	--	85	--
		86	SIGNAL sample_f_val : STD_LOGIC_VECTOR(3 DOWNTO 0);
		87	SIGNAL sample_f_data : STD_LOGIC_VECTOR((616)4-1 DOWNTO 0);
		88	--
86	SIGNAL sample_f0_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);	89	SIGNAL sample_f0_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
87	SIGNAL sample_f1_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);	90	SIGNAL sample_f1_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
88	SIGNAL sample_f2_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);	91	SIGNAL sample_f2_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
@@ -262,20 +265,66 BEGIN
262	data_shaping_R0 => data_shaping_R0,	265	data_shaping_R0 => data_shaping_R0,
263	data_shaping_R1 => data_shaping_R1,	266	data_shaping_R1 => data_shaping_R1,
264	data_shaping_R2 => data_shaping_R2,	267	data_shaping_R2 => data_shaping_R2,
265	sample_f0_val => sample_f0_val,	268	sample_f0_val => sample_f_val(0),
266	sample_f1_val => sample_f1_val,	269	sample_f1_val => sample_f_val(1),
267	sample_f2_val => sample_f2_val,	270	sample_f2_val => sample_f_val(2),
268	sample_f3_val => sample_f3_val,	271	sample_f3_val => sample_f_val(3),
269	sample_f0_wdata => ~~sample_f0_data~~,	272	sample_f0_wdata => OPEN,
270	sample_f1_wdata => ~~sample_f1_data~~,	273	sample_f1_wdata => OPEN,
271	sample_f2_wdata => ~~sample_f2_data~~,	274	sample_f2_wdata => OPEN,
272	sample_f3_wdata => ~~sample_f3_data~~,	275	sample_f3_wdata => OPEN,
273	sample_f0_time => sample_f0_time,	276	sample_f0_time => sample_f0_time,
274	sample_f1_time => sample_f1_time,	277	sample_f1_time => sample_f1_time,
275	sample_f2_time => sample_f2_time,	278	sample_f2_time => sample_f2_time,
276	sample_f3_time => sample_f3_time	279	sample_f3_time => sample_f3_time
277	);	280	);
		281	-----------------------------------------------------------------------------
		282	ALL_lane: FOR J IN 0 TO 3 GENERATE
		283	ALL_channel: FOR I IN 0 TO 5 GENERATE
		284	sample_f_data(15 + I16 + J616 DOWNTO 14 + I16 + J616) <= STD_LOGIC_VECTOR(to_unsigned(J,2));
		285	sample_f_data(13 + I16 + J616 DOWNTO 11 + I16 + J616) <= STD_LOGIC_VECTOR(to_unsigned(I,3));
278		286
		287	PROCESS (clk, rstn)
		288	BEGIN -- PROCESS
		289	IF rstn = '0' THEN -- asynchronous reset (active low)
		290	sample_f_data(10 + I16 + J616 DOWNTO 0 + I16 + J616 ) <= STD_LOGIC_VECTOR(to_unsigned(2*11/6I,11));
		291	ELSIF clk'event AND clk = '1' THEN -- rising clock edge
		292	IF sample_f_val(J) = '1' THEN
		293	sample_f_data(10 + I16 + J616 DOWNTO 0 + I16 + J616) <= STD_LOGIC_VECTOR(to_unsigned(
		294	to_integer(UNSIGNED(sample_f_data(10 + I16 + J616 DOWNTO 0 + I16 + J616))) + 1,
		295	11));
		296	END IF;
		297	END IF;
		298	END PROCESS;
		299
		300	END GENERATE ALL_channel;
		301	END GENERATE ALL_lane;
		302
		303	PROCESS (clk, rstn)
		304	BEGIN -- PROCESS
		305	IF rstn = '0' THEN -- asynchronous reset (active low)
		306	sample_f0_val <= '0';
		307	sample_f1_val <= '0';
		308	sample_f2_val <= '0';
		309	sample_f3_val <= '0';
		310	ELSIF clk'event AND clk = '1' THEN -- rising clock edge
		311	sample_f0_val <= sample_f_val(0);
		312	sample_f1_val <= sample_f_val(1);
		313	sample_f2_val <= sample_f_val(2);
		314	sample_f3_val <= sample_f_val(3);
		315	END IF;
		316	END PROCESS;
		317
		318
		319	sample_f0_data <= sample_f_data(1616-1 DOWNTO 0616);
		320	sample_f1_data <= sample_f_data(2616-1 DOWNTO 1616);
		321	sample_f2_data <= sample_f_data(3616-1 DOWNTO 2616);
		322	sample_f3_data <= sample_f_data(4616-1 DOWNTO 3616);
		323
		324	--sample_f0_data <= X"0020" & X"0010" & X"0008" & X"0004" & X"0002" & X"0001";
		325	--sample_f1_data <= X"1020" & X"1010" & X"1008" & X"1004" & X"1002" & X"1001";
		326	--sample_f2_data <= X"2020" & X"2010" & X"2008" & X"2004" & X"2002" & X"2001";
		327	--sample_f3_data <= X"4020" & X"4010" & X"4008" & X"4004" & X"4002" & X"4001";
279	-----------------------------------------------------------------------------	328	-----------------------------------------------------------------------------
280	lpp_lfr_apbreg_1 : lpp_lfr_apbreg	329	lpp_lfr_apbreg_1 : lpp_lfr_apbreg
281	GENERIC MAP (	330	GENERIC MAP (
@@ -539,4 +588,4 BEGIN
539	buffer_full_err => dma_buffer_full_err, --buffer_full_err,	588	buffer_full_err => dma_buffer_full_err, --buffer_full_err,
540	grant_error => dma_grant_error); --grant_error);	589	grant_error => dma_grant_error); --grant_error);
541		590
542	END beh; No newline at end of file	591	END beh;

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