diff --git a/lib/lpp/lpp_dma/lpp_dma_SEND16B_FIFO2DMA.vhd b/lib/lpp/lpp_dma/lpp_dma_SEND16B_FIFO2DMA.vhd --- a/lib/lpp/lpp_dma/lpp_dma_SEND16B_FIFO2DMA.vhd +++ b/lib/lpp/lpp_dma/lpp_dma_SEND16B_FIFO2DMA.vhd @@ -85,6 +85,8 @@ ARCHITECTURE Behavioral OF lpp_dma_SEND1 SIGNAL bus_request : STD_LOGIC; SIGNAL bus_lock : STD_LOGIC; + + SIGNAL data_reg : STD_LOGIC_VECTOR(31 DOWNTO 0); BEGIN @@ -111,8 +113,8 @@ BEGIN ----------------------------------------------------------------------------- AHB_Master_Out.HADDR <= address(31 DOWNTO 6) & address_counter_reg & "00"; - AHB_Master_Out.HWDATA <= ahbdrivedata(data); - + AHB_Master_Out.HWDATA <= ahbdrivedata(data) WHEN AHB_Master_In.HREADY = '1' ELSE ahbdrivedata(data_reg); + ----------------------------------------------------------------------------- --ren <= NOT ((AHB_Master_In.HGRANT(hindex) OR LAST_READ ) AND AHB_Master_In.HREADY ); --ren <= NOT beat; @@ -122,12 +124,21 @@ BEGIN IF rstn = '0' THEN -- asynchronous reset (active low) state <= IDLE; done <= '0'; + ren <= '1'; address_counter_reg <= (OTHERS => '0'); AHB_Master_Out.HTRANS <= HTRANS_IDLE; AHB_Master_Out.HBUSREQ <= '0'; AHB_Master_Out.HLOCK <= '0'; + + data_reg <= (OTHERS => '0'); ELSIF clk'event AND clk = '1' THEN -- rising clock edge + + IF AHB_Master_In.HREADY = '1' AND AHB_Master_In.HGRANT(hindex) = '1' THEN + data_reg <= data; + END IF; + done <= '0'; + ren <= '1'; CASE state IS WHEN IDLE => AHB_Master_Out.HBUSREQ <= '0'; @@ -159,6 +170,7 @@ BEGIN IF AHB_Master_In.HREADY = '1' AND AHB_Master_In.HGRANT(hindex) = '1' THEN AHB_Master_Out.HTRANS <= HTRANS_SEQ; state <= s_CTRL_DATA; + ren <= '0'; END IF; WHEN s_CTRL_DATA => @@ -176,6 +188,11 @@ BEGIN state <= s_DATA; END IF; + IF AHB_Master_In.HREADY = '1' AND AHB_Master_In.HGRANT(hindex) = '1' AND address_counter_reg /= "1111" THEN + ren <= '0'; + END IF; + + WHEN s_DATA => AHB_Master_Out.HBUSREQ <= '0'; --AHB_Master_Out.HLOCK <= '0'; @@ -194,7 +211,9 @@ BEGIN ctrl_window <= '1' WHEN state = s_CTRL OR state = s_CTRL_DATA ELSE '0'; data_window <= '1' WHEN state = s_CTRL_DATA OR state = s_DATA ELSE '0'; ----------------------------------------------------------------------------- - ren <= NOT(AHB_Master_In.HREADY) WHEN state = s_CTRL_DATA ELSE '1'; + + + --ren <= NOT(AHB_Master_In.HREADY) WHEN state = s_CTRL_DATA ELSE '1'; ----------------------------------------------------------------------------- --PROCESS (clk, rstn) diff --git a/lib/lpp/lpp_leon3_soc/leon3_soc.vhd b/lib/lpp/lpp_leon3_soc/leon3_soc.vhd --- a/lib/lpp/lpp_leon3_soc/leon3_soc.vhd +++ b/lib/lpp/lpp_leon3_soc/leon3_soc.vhd @@ -422,7 +422,7 @@ BEGIN --Aeroflex memory generics: mbpedac => BYPASS_EDAC_MEMCTRLR, mprog => 1, -- program memory by default values after reset - mpsrate => 15, -- default scrub rate period + mpsrate => 5, -- default scrub rate period mpb2s => 14, -- default busy to scrub delay mpapb => 1, -- instantiate apb register mchipcnt => 2, diff --git a/lib/lpp/lpp_top_lfr/lpp_lfr.vhd b/lib/lpp/lpp_top_lfr/lpp_lfr.vhd --- a/lib/lpp/lpp_top_lfr/lpp_lfr.vhd +++ b/lib/lpp/lpp_top_lfr/lpp_lfr.vhd @@ -83,6 +83,9 @@ ARCHITECTURE beh OF lpp_lfr IS SIGNAL sample_f2_val : STD_LOGIC; SIGNAL sample_f3_val : STD_LOGIC; -- + SIGNAL sample_f_val : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL sample_f_data : STD_LOGIC_VECTOR((6*16)*4-1 DOWNTO 0); + -- SIGNAL sample_f0_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); SIGNAL sample_f1_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); SIGNAL sample_f2_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); @@ -262,20 +265,66 @@ BEGIN data_shaping_R0 => data_shaping_R0, data_shaping_R1 => data_shaping_R1, data_shaping_R2 => data_shaping_R2, - sample_f0_val => sample_f0_val, - sample_f1_val => sample_f1_val, - sample_f2_val => sample_f2_val, - sample_f3_val => sample_f3_val, - sample_f0_wdata => sample_f0_data, - sample_f1_wdata => sample_f1_data, - sample_f2_wdata => sample_f2_data, - sample_f3_wdata => sample_f3_data, + sample_f0_val => sample_f_val(0), + sample_f1_val => sample_f_val(1), + sample_f2_val => sample_f_val(2), + sample_f3_val => sample_f_val(3), + sample_f0_wdata => OPEN, + sample_f1_wdata => OPEN, + sample_f2_wdata => OPEN, + sample_f3_wdata => OPEN, sample_f0_time => sample_f0_time, sample_f1_time => sample_f1_time, sample_f2_time => sample_f2_time, sample_f3_time => sample_f3_time ); + ----------------------------------------------------------------------------- + ALL_lane: FOR J IN 0 TO 3 GENERATE + ALL_channel: FOR I IN 0 TO 5 GENERATE + sample_f_data(15 + I*16 + J*6*16 DOWNTO 14 + I*16 + J*6*16) <= STD_LOGIC_VECTOR(to_unsigned(J,2)); + sample_f_data(13 + I*16 + J*6*16 DOWNTO 11 + I*16 + J*6*16) <= STD_LOGIC_VECTOR(to_unsigned(I,3)); + PROCESS (clk, rstn) + BEGIN -- PROCESS + IF rstn = '0' THEN -- asynchronous reset (active low) + sample_f_data(10 + I*16 + J*6*16 DOWNTO 0 + I*16 + J*6*16 ) <= STD_LOGIC_VECTOR(to_unsigned(2**11/6*I,11)); + ELSIF clk'event AND clk = '1' THEN -- rising clock edge + IF sample_f_val(J) = '1' THEN + sample_f_data(10 + I*16 + J*6*16 DOWNTO 0 + I*16 + J*6*16) <= STD_LOGIC_VECTOR(to_unsigned( + to_integer(UNSIGNED(sample_f_data(10 + I*16 + J*6*16 DOWNTO 0 + I*16 + J*6*16))) + 1, + 11)); + END IF; + END IF; + END PROCESS; + + END GENERATE ALL_channel; + END GENERATE ALL_lane; + + PROCESS (clk, rstn) + BEGIN -- PROCESS + IF rstn = '0' THEN -- asynchronous reset (active low) + sample_f0_val <= '0'; + sample_f1_val <= '0'; + sample_f2_val <= '0'; + sample_f3_val <= '0'; + ELSIF clk'event AND clk = '1' THEN -- rising clock edge + sample_f0_val <= sample_f_val(0); + sample_f1_val <= sample_f_val(1); + sample_f2_val <= sample_f_val(2); + sample_f3_val <= sample_f_val(3); + END IF; + END PROCESS; + + + sample_f0_data <= sample_f_data(1*6*16-1 DOWNTO 0*6*16); + sample_f1_data <= sample_f_data(2*6*16-1 DOWNTO 1*6*16); + sample_f2_data <= sample_f_data(3*6*16-1 DOWNTO 2*6*16); + sample_f3_data <= sample_f_data(4*6*16-1 DOWNTO 3*6*16); + + --sample_f0_data <= X"0020" & X"0010" & X"0008" & X"0004" & X"0002" & X"0001"; + --sample_f1_data <= X"1020" & X"1010" & X"1008" & X"1004" & X"1002" & X"1001"; + --sample_f2_data <= X"2020" & X"2010" & X"2008" & X"2004" & X"2002" & X"2001"; + --sample_f3_data <= X"4020" & X"4010" & X"4008" & X"4004" & X"4002" & X"4001"; ----------------------------------------------------------------------------- lpp_lfr_apbreg_1 : lpp_lfr_apbreg GENERIC MAP ( @@ -539,4 +588,4 @@ BEGIN buffer_full_err => dma_buffer_full_err, --buffer_full_err, grant_error => dma_grant_error); --grant_error); -END beh; \ No newline at end of file +END beh;