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LFR-EQM-2.1.63
pellion -
r545:fddf2234482f (LFR-EQM) 2-1-63 JC
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1 # Top Level Design Parameters
2
3 # Clocks
4
5 create_clock -period 10.000000 -waveform {0.000000 5.000000} clk50MHz
6 create_clock -period 20.344999 -waveform {0.000000 10.172500} clk49_152MHz
7 create_clock -period 40.000000 -waveform {0.000000 20.000000} clk_25:Q
8 create_clock -period 40.690000 -waveform {0.000000 20.345100} clk_24:Q
9 create_clock -name SPW_CLOCK -period 100.000000 -waveform {0.000000 50.000000} {spw1_din spw1_sin spw2_din spw2_sin}
10
11
12 # False Paths Between Clocks
13
14
15 # False Path Constraints
16
17
18 # Maximum Delay Constraints
19
20
21 # Multicycle Constraints
22
23
24 # Virtual Clocks
25 # Output Load Constraints
26 # Driving Cell Constraints
27 # Wire Loads
28 # set_wire_load_mode top
29
30 # Other Constraints
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1 set_io clk49_152MHz -pinname D5 -fixed yes -DIRECTION Inout
2 set_io clk50MHz -pinname B3 -fixed yes -DIRECTION Inout
3 set_io reset -pinname R4 -fixed yes -DIRECTION Inout
4
5 set_io {address[0]} -pinname U3 -fixed yes -DIRECTION Inout
6 set_io {address[1]} -pinname V14 -fixed yes -DIRECTION Inout
7 set_io {address[2]} -pinname V13 -fixed yes -DIRECTION Inout
8 set_io {address[3]} -pinname V16 -fixed yes -DIRECTION Inout
9 set_io {address[4]} -pinname N9 -fixed yes -DIRECTION Inout
10 set_io {address[5]} -pinname T11 -fixed yes -DIRECTION Inout
11 set_io {address[6]} -pinname U13 -fixed yes -DIRECTION Inout
12 set_io {address[7]} -pinname R5 -fixed yes -DIRECTION Inout
13 set_io {address[8]} -pinname U2 -fixed yes -DIRECTION Inout
14 set_io {address[9]} -pinname N11 -fixed yes -DIRECTION Inout
15 set_io {address[10]} -pinname R13 -fixed yes -DIRECTION Inout
16 set_io {address[11]} -pinname R12 -fixed yes -DIRECTION Inout
17 set_io {address[12]} -pinname M15 -fixed yes -DIRECTION Inout
18 set_io {address[13]} -pinname T12 -fixed yes -DIRECTION Inout
19 set_io {address[14]} -pinname M13 -fixed yes -DIRECTION Inout
20 set_io {address[15]} -pinname T13 -fixed yes -DIRECTION Inout
21 set_io {address[16]} -pinname L13 -fixed yes -DIRECTION Inout
22 set_io {address[17]} -pinname V17 -fixed yes -DIRECTION Inout
23 set_io {address[18]} -pinname V15 -fixed yes -DIRECTION Inout
24
25 set_io {data[0]} -pinname V4 -fixed yes -DIRECTION Inout
26 set_io {data[1]} -pinname V3 -fixed yes -DIRECTION Inout
27 set_io {data[2]} -pinname V2 -fixed yes -DIRECTION Inout
28 set_io {data[3]} -pinname T3 -fixed yes -DIRECTION Inout
29 set_io {data[4]} -pinname N6 -fixed yes -DIRECTION Inout
30 set_io {data[5]} -pinname P6 -fixed yes -DIRECTION Inout
31 set_io {data[6]} -pinname R6 -fixed yes -DIRECTION Inout
32 set_io {data[7]} -pinname T4 -fixed yes -DIRECTION Inout
33 set_io {data[8]} -pinname T1 -fixed yes -DIRECTION Inout
34 set_io {data[9]} -pinname R1 -fixed yes -DIRECTION Inout
35 set_io {data[10]} -pinname P1 -fixed yes -DIRECTION Inout
36 set_io {data[11]} -pinname N2 -fixed yes -DIRECTION Inout
37 set_io {data[12]} -pinname R3 -fixed yes -DIRECTION Inout
38 set_io {data[13]} -pinname P4 -fixed yes -DIRECTION Inout
39 set_io {data[14]} -pinname N4 -fixed yes -DIRECTION Inout
40 set_io {data[15]} -pinname N3 -fixed yes -DIRECTION Inout
41 set_io {data[16]} -pinname G12 -fixed yes -DIRECTION Inout
42 set_io {data[17]} -pinname G15 -fixed yes -DIRECTION Inout
43 set_io {data[18]} -pinname H15 -fixed yes -DIRECTION Inout
44 set_io {data[19]} -pinname F17 -fixed yes -DIRECTION Inout
45 set_io {data[20]} -pinname F18 -fixed yes -DIRECTION Inout
46 set_io {data[21]} -pinname G17 -fixed yes -DIRECTION Inout
47 set_io {data[22]} -pinname H18 -fixed yes -DIRECTION Inout
48 set_io {data[23]} -pinname J18 -fixed yes -DIRECTION Inout
49 set_io {data[24]} -pinname R18 -fixed yes -DIRECTION Inout
50 set_io {data[25]} -pinname N18 -fixed yes -DIRECTION Inout
51 set_io {data[26]} -pinname P17 -fixed yes -DIRECTION Inout
52 set_io {data[27]} -pinname N17 -fixed yes -DIRECTION Inout
53 set_io {data[28]} -pinname T18 -fixed yes -DIRECTION Inout
54 set_io {data[29]} -pinname M17 -fixed yes -DIRECTION Inout
55 set_io {data[30]} -pinname U18 -fixed yes -DIRECTION Inout
56 set_io {data[31]} -pinname L18 -fixed yes -DIRECTION Inout
57
58 set_io nSRAM_MBE -pinname E4 -fixed yes -DIRECTION Inout
59 set_io nSRAM_E1 -pinname D1 -fixed yes -DIRECTION Inout
60 set_io nSRAM_E2 -pinname C1 -fixed yes -DIRECTION Inout
61 #set_io nSRAM_SCRUB -pinname C2 -fixed yes -DIRECTION Inout
62 set_io nSRAM_W -pinname D4 -fixed yes -DIRECTION Inout
63 set_io nSRAM_G -pinname E1 -fixed yes -DIRECTION Inout
64 set_io nSRAM_BUSY -pinname F4 -fixed yes -DIRECTION Inout
65
66 set_io spw1_en -pinname G4 -fixed yes -DIRECTION Inout
67 set_io spw1_din -pinname D13 -fixed yes -DIRECTION Inout
68 set_io spw1_sin -pinname D14 -fixed yes -DIRECTION Inout
69 set_io spw1_dout -pinname C16 -fixed yes -DIRECTION Inout
70 set_io spw1_sout -pinname C4 -fixed yes -DIRECTION Inout
71
72 set_io spw2_en -pinname G3 -fixed yes -DIRECTION Inout
73 set_io spw2_din -pinname E6 -fixed yes -DIRECTION Inout
74 set_io spw2_sin -pinname C15 -fixed yes -DIRECTION Inout
75 set_io spw2_dout -pinname B7 -fixed yes -DIRECTION Inout
76 set_io spw2_sout -pinname D7 -fixed yes -DIRECTION Inout
77
78 set_io TAG1 -pinname J12 -fixed yes -DIRECTION Inout
79 set_io TAG2 -pinname K12 -fixed yes -DIRECTION Inout
80 set_io TAG3 -pinname K13 -fixed yes -DIRECTION Inout
81 set_io TAG4 -pinname L16 -fixed yes -DIRECTION Inout
82 #set_io TAG5 -pinname L15 -fixed yes -DIRECTION Inout
83 #set_io TAG6 -pinname M16 -fixed yes -DIRECTION Inout
84 #set_io TAG7 -pinname J14 -fixed yes -DIRECTION Inout
85 set_io TAG8 -pinname K15 -fixed yes -DIRECTION Inout
86 #set_io TAG9 -pinname J17 -fixed yes -DIRECTION Inout
87
88 set_io bias_fail_sw -pinname A3 -fixed yes -DIRECTION Inout
89
90 set_io {ADC_OEB_bar_CH[0]} -pinname A10 -fixed yes -DIRECTION Inout
91 set_io {ADC_OEB_bar_CH[1]} -pinname B10 -fixed yes -DIRECTION Inout
92 set_io {ADC_OEB_bar_CH[2]} -pinname B12 -fixed yes -DIRECTION Inout
93 set_io {ADC_OEB_bar_CH[3]} -pinname A11 -fixed yes -DIRECTION Inout
94 set_io {ADC_OEB_bar_CH[4]} -pinname B13 -fixed yes -DIRECTION Inout
95 set_io {ADC_OEB_bar_CH[5]} -pinname C6 -fixed yes -DIRECTION Inout
96 set_io {ADC_OEB_bar_CH[6]} -pinname A13 -fixed yes -DIRECTION Inout
97 set_io {ADC_OEB_bar_CH[7]} -pinname A14 -fixed yes -DIRECTION Inout
98
99 set_io ADC_smpclk -pinname A15 -fixed yes -DIRECTION Inout
100
101 set_io HK_smpclk -pinname R11 -fixed yes -DIRECTION Inout
102 set_io ADC_OEB_bar_HK -pinname D6 -fixed yes -DIRECTION Inout
103 set_io {HK_SEL[0]} -pinname C3 -fixed yes -DIRECTION Inout
104 set_io {HK_SEL[1]} -pinname A2 -fixed yes -DIRECTION Inout
105
106 set_io {ADC_data[0]} -pinname G13 -fixed yes -DIRECTION Inout
107 set_io {ADC_data[1]} -pinname G16 -fixed yes -DIRECTION Inout
108 set_io {ADC_data[2]} -pinname F16 -fixed yes -DIRECTION Inout
109 set_io {ADC_data[3]} -pinname E15 -fixed yes -DIRECTION Inout
110 set_io {ADC_data[4]} -pinname F13 -fixed yes -DIRECTION Inout
111 set_io {ADC_data[5]} -pinname F15 -fixed yes -DIRECTION Inout
112 set_io {ADC_data[6]} -pinname D16 -fixed yes -DIRECTION Inout
113 set_io {ADC_data[7]} -pinname D15 -fixed yes -DIRECTION Inout
114 set_io {ADC_data[8]} -pinname B17 -fixed yes -DIRECTION Inout
115 set_io {ADC_data[9]} -pinname A17 -fixed yes -DIRECTION Inout
116 set_io {ADC_data[10]} -pinname A16 -fixed yes -DIRECTION Inout
117 set_io {ADC_data[11]} -pinname B16 -fixed yes -DIRECTION Inout
118 set_io {ADC_data[12]} -pinname C12 -fixed yes -DIRECTION Inout
119 set_io {ADC_data[13]} -pinname C13 -fixed yes -DIRECTION Inout
120
121 set_io DAC_SDO -pinname A4 -fixed yes -DIRECTION Inout
122 set_io DAC_SCK -pinname A5 -fixed yes -DIRECTION Inout
123 set_io DAC_SYNC -pinname B6 -fixed yes -DIRECTION Inout
124 set_io DAC_CAL_EN -pinname A6 -fixed yes -DIRECTION Inout
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1 set_io clk49_152MHz -pinname 314 -fixed yes -DIRECTION Inout
2 set_io clk50MHz -pinname 318 -fixed yes -DIRECTION Inout
3 set_io reset -pinname 128 -fixed yes -DIRECTION Inout
4
5 set_io {address[0]} -pinname 124 -fixed yes -DIRECTION Inout
6 set_io {address[1]} -pinname 156 -fixed yes -DIRECTION Inout
7 set_io {address[2]} -pinname 154 -fixed yes -DIRECTION Inout
8 set_io {address[3]} -pinname 160 -fixed yes -DIRECTION Inout
9 set_io {address[4]} -pinname 162 -fixed yes -DIRECTION Inout
10 set_io {address[5]} -pinname 165 -fixed yes -DIRECTION Inout
11 set_io {address[6]} -pinname 155 -fixed yes -DIRECTION Inout
12 set_io {address[7]} -pinname 127 -fixed yes -DIRECTION Inout
13 set_io {address[8]} -pinname 123 -fixed yes -DIRECTION Inout
14 set_io {address[9]} -pinname 137 -fixed yes -DIRECTION Inout
15 set_io {address[10]} -pinname 141 -fixed yes -DIRECTION Inout
16 set_io {address[11]} -pinname 166 -fixed yes -DIRECTION Inout
17 set_io {address[12]} -pinname 182 -fixed yes -DIRECTION Inout
18 set_io {address[13]} -pinname 167 -fixed yes -DIRECTION Inout
19 set_io {address[14]} -pinname 181 -fixed yes -DIRECTION Inout
20 set_io {address[15]} -pinname 171 -fixed yes -DIRECTION Inout
21 set_io {address[16]} -pinname 183 -fixed yes -DIRECTION Inout
22 set_io {address[17]} -pinname 161 -fixed yes -DIRECTION Inout
23 set_io {address[18]} -pinname 159 -fixed yes -DIRECTION Inout
24
25 set_io {data[0]} -pinname 103 -fixed yes -DIRECTION Inout
26 set_io {data[1]} -pinname 100 -fixed yes -DIRECTION Inout
27 set_io {data[2]} -pinname 99 -fixed yes -DIRECTION Inout
28 set_io {data[3]} -pinname 98 -fixed yes -DIRECTION Inout
29 set_io {data[4]} -pinname 97 -fixed yes -DIRECTION Inout
30 set_io {data[5]} -pinname 94 -fixed yes -DIRECTION Inout
31 set_io {data[6]} -pinname 93 -fixed yes -DIRECTION Inout
32 set_io {data[7]} -pinname 92 -fixed yes -DIRECTION Inout
33 set_io {data[8]} -pinname 82 -fixed yes -DIRECTION Inout
34 set_io {data[9]} -pinname 79 -fixed yes -DIRECTION Inout
35 set_io {data[10]} -pinname 78 -fixed yes -DIRECTION Inout
36 set_io {data[11]} -pinname 77 -fixed yes -DIRECTION Inout
37 set_io {data[12]} -pinname 71 -fixed yes -DIRECTION Inout
38 set_io {data[13]} -pinname 70 -fixed yes -DIRECTION Inout
39 set_io {data[14]} -pinname 67 -fixed yes -DIRECTION Inout
40 set_io {data[15]} -pinname 66 -fixed yes -DIRECTION Inout
41 set_io {data[16]} -pinname 246 -fixed yes -DIRECTION Inout
42 set_io {data[17]} -pinname 242 -fixed yes -DIRECTION Inout
43 set_io {data[18]} -pinname 241 -fixed yes -DIRECTION Inout
44 set_io {data[19]} -pinname 229 -fixed yes -DIRECTION Inout
45 set_io {data[20]} -pinname 228 -fixed yes -DIRECTION Inout
46 set_io {data[21]} -pinname 227 -fixed yes -DIRECTION Inout
47 set_io {data[22]} -pinname 224 -fixed yes -DIRECTION Inout
48 set_io {data[23]} -pinname 223 -fixed yes -DIRECTION Inout
49 set_io {data[24]} -pinname 206 -fixed yes -DIRECTION Inout
50 set_io {data[25]} -pinname 212 -fixed yes -DIRECTION Inout
51 set_io {data[26]} -pinname 207 -fixed yes -DIRECTION Inout
52 set_io {data[27]} -pinname 211 -fixed yes -DIRECTION Inout
53 set_io {data[28]} -pinname 205 -fixed yes -DIRECTION Inout
54 set_io {data[29]} -pinname 213 -fixed yes -DIRECTION Inout
55 set_io {data[30]} -pinname 202 -fixed yes -DIRECTION Inout
56 set_io {data[31]} -pinname 214 -fixed yes -DIRECTION Inout
57
58 set_io nSRAM_MBE -pinname 9 -fixed yes -DIRECTION Inout
59 set_io nSRAM_E1 -pinname 20 -fixed yes -DIRECTION Inout
60 set_io nSRAM_E2 -pinname 15 -fixed yes -DIRECTION Inout
61 set_io nSRAM_SCRUB -pinname 14 -fixed yes -DIRECTION Inout
62 set_io nSRAM_W -pinname 8 -fixed yes -DIRECTION Inout
63 set_io nSRAM_G -pinname 21 -fixed yes -DIRECTION Inout
64 set_io nSRAM_BUSY -pinname 24 -fixed yes -DIRECTION Inout
65
66 set_io spw1_en -pinname 31 -fixed yes -DIRECTION Inout
67 set_io spw1_din -pinname 300 -fixed yes -DIRECTION Inout
68 set_io spw1_sin -pinname 299 -fixed yes -DIRECTION Inout
69 set_io spw1_dout -pinname 303 -fixed yes -DIRECTION Inout
70 set_io spw1_sout -pinname 317 -fixed yes -DIRECTION Inout
71
72 set_io spw2_en -pinname 30 -fixed yes -DIRECTION Inout
73 set_io spw2_din -pinname 313 -fixed yes -DIRECTION Inout
74 set_io spw2_sin -pinname 304 -fixed yes -DIRECTION Inout
75 set_io spw2_dout -pinname 335 -fixed yes -DIRECTION Inout
76 set_io spw2_sout -pinname 330 -fixed yes -DIRECTION Inout
77
78 set_io TAG1 -pinname 195 -fixed yes -DIRECTION Inout
79 set_io TAG2 -pinname 190 -fixed yes -DIRECTION Inout
80 set_io TAG3 -pinname 189 -fixed yes -DIRECTION Inout
81 set_io TAG4 -pinname 188 -fixed yes -DIRECTION Inout
82 #set_io TAG5 -pinname 187 -fixed yes -DIRECTION Inout
83 #set_io TAG6 -pinname 184 -fixed yes -DIRECTION Inout
84 #set_io TAG7 -pinname 200 -fixed yes -DIRECTION Inout
85 set_io TAG8 -pinname 199 -fixed yes -DIRECTION Inout
86 #set_io TAG9 -pinname 196 -fixed yes -DIRECTION Inout
87
88 set_io bias_fail_sw -pinname 342 -fixed yes -DIRECTION Inout
89
90 set_io {ADC_OEB_bar_CH[0]} -pinname 288 -fixed yes -DIRECTION Inout
91 set_io {ADC_OEB_bar_CH[1]} -pinname 287 -fixed yes -DIRECTION Inout
92 set_io {ADC_OEB_bar_CH[2]} -pinname 285 -fixed yes -DIRECTION Inout
93 set_io {ADC_OEB_bar_CH[3]} -pinname 286 -fixed yes -DIRECTION Inout
94 set_io {ADC_OEB_bar_CH[4]} -pinname 281 -fixed yes -DIRECTION Inout
95 set_io {ADC_OEB_bar_CH[5]} -pinname 332 -fixed yes -DIRECTION Inout
96 set_io {ADC_OEB_bar_CH[6]} -pinname 282 -fixed yes -DIRECTION Inout
97 set_io {ADC_OEB_bar_CH[7]} -pinname 280 -fixed yes -DIRECTION Inout
98
99 set_io ADC_smpclk -pinname 279 -fixed yes -DIRECTION Inout
100
101 set_io HK_smpclk -pinname 172 -fixed yes -DIRECTION Inout
102 set_io ADC_OEB_bar_HK -pinname 331 -fixed yes -DIRECTION Inout
103 set_io {HK_SEL[0]} -pinname 6 -fixed yes -DIRECTION Inout
104 set_io {HK_SEL[1]} -pinname 343 -fixed yes -DIRECTION Inout
105
106 set_io {ADC_data[0]} -pinname 251 -fixed yes -DIRECTION Inout
107 set_io {ADC_data[1]} -pinname 253 -fixed yes -DIRECTION Inout
108 set_io {ADC_data[2]} -pinname 257 -fixed yes -DIRECTION Inout
109 set_io {ADC_data[3]} -pinname 259 -fixed yes -DIRECTION Inout
110 set_io {ADC_data[4]} -pinname 252 -fixed yes -DIRECTION Inout
111 set_io {ADC_data[5]} -pinname 254 -fixed yes -DIRECTION Inout
112 set_io {ADC_data[6]} -pinname 258 -fixed yes -DIRECTION Inout
113 set_io {ADC_data[7]} -pinname 260 -fixed yes -DIRECTION Inout
114 set_io {ADC_data[8]} -pinname 270 -fixed yes -DIRECTION Inout
115 set_io {ADC_data[9]} -pinname 274 -fixed yes -DIRECTION Inout
116 set_io {ADC_data[10]} -pinname 276 -fixed yes -DIRECTION Inout
117 set_io {ADC_data[11]} -pinname 275 -fixed yes -DIRECTION Inout
118 set_io {ADC_data[12]} -pinname 273 -fixed yes -DIRECTION Inout
119 set_io {ADC_data[13]} -pinname 269 -fixed yes -DIRECTION Inout
120
121 set_io DAC_SDO -pinname 341 -fixed yes -DIRECTION Inout
122 set_io DAC_SCK -pinname 338 -fixed yes -DIRECTION Inout
123 set_io DAC_SYNC -pinname 337 -fixed yes -DIRECTION Inout
124 set_io DAC_CAL_EN -pinname 336 -fixed yes -DIRECTION Inout
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1 PACKAGE=\"\"
2 SPEED=Std
3 SYNFREQ=50
4
5 TECHNOLOGY=ProASIC3E
6 LIBERO_DIE=IT14X14M4
7 PART=A3PE3000
8
9 DESIGNER_VOLTAGE=COM
10 DESIGNER_TEMP=COM
11 DESIGNER_PACKAGE=FBGA
12 DESIGNER_PINS=324
13
14 MANUFACTURER=Actel
15 MGCTECHNOLOGY=Proasic3
16 MGCPART=$(PART)
17 MGCPACKAGE= {$(DESIGNER_PINS) $(DESIGNER_PACKAGE)}
18 LIBERO_PACKAGE=fg$(DESIGNER_PINS)
19
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1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
19 -- Author : Jean-christophe Pellion
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 -------------------------------------------------------------------------------
22 LIBRARY IEEE;
23 USE IEEE.numeric_std.ALL;
24 USE IEEE.std_logic_1164.ALL;
25 LIBRARY grlib;
26 USE grlib.amba.ALL;
27 USE grlib.stdlib.ALL;
28 LIBRARY techmap;
29 USE techmap.gencomp.ALL;
30 LIBRARY gaisler;
31 USE gaisler.memctrl.ALL;
32 USE gaisler.leon3.ALL;
33 USE gaisler.uart.ALL;
34 USE gaisler.misc.ALL;
35 USE gaisler.spacewire.ALL;
36 LIBRARY esa;
37 USE esa.memoryctrl.ALL;
38 LIBRARY lpp;
39 USE lpp.lpp_memory.ALL;
40 USE lpp.lpp_ad_conv.ALL;
41 USE lpp.lpp_lfr_pkg.ALL; -- contains lpp_lfr, not in the 206 rev of the VHD_Lib
42 USE lpp.lpp_top_lfr_pkg.ALL; -- contains top_wf_picker
43 USE lpp.iir_filter.ALL;
44 USE lpp.general_purpose.ALL;
45 USE lpp.lpp_lfr_management.ALL;
46 USE lpp.lpp_leon3_soc_pkg.ALL;
47
48 ENTITY LFR_EQM IS
49
50 PORT (
51 clk50MHz : IN STD_ULOGIC;
52 clk49_152MHz : IN STD_ULOGIC;
53 reset : IN STD_ULOGIC;
54
55 -- TAG --------------------------------------------------------------------
56 TAG1 : IN STD_ULOGIC; -- DSU rx data
57 TAG3 : OUT STD_ULOGIC; -- DSU tx data
58 -- UART APB ---------------------------------------------------------------
59 TAG2 : IN STD_ULOGIC; -- UART1 rx data
60 TAG4 : OUT STD_ULOGIC; -- UART1 tx data
61 -- RAM --------------------------------------------------------------------
62 address : OUT STD_LOGIC_VECTOR(18 DOWNTO 0);
63 data : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0);
64
65 nSRAM_MBE : INOUT STD_LOGIC; -- new
66 nSRAM_E1 : OUT STD_LOGIC; -- new
67 nSRAM_E2 : OUT STD_LOGIC; -- new
68 -- nSRAM_SCRUB : OUT STD_LOGIC; -- new
69 nSRAM_W : OUT STD_LOGIC; -- new
70 nSRAM_G : OUT STD_LOGIC; -- new
71 nSRAM_BUSY : IN STD_LOGIC; -- new
72 -- SPW --------------------------------------------------------------------
73 spw1_en : OUT STD_LOGIC; -- new
74 spw1_din : IN STD_LOGIC;
75 spw1_sin : IN STD_LOGIC;
76 spw1_dout : OUT STD_LOGIC;
77 spw1_sout : OUT STD_LOGIC;
78 spw2_en : OUT STD_LOGIC; -- new
79 spw2_din : IN STD_LOGIC;
80 spw2_sin : IN STD_LOGIC;
81 spw2_dout : OUT STD_LOGIC;
82 spw2_sout : OUT STD_LOGIC;
83 -- ADC --------------------------------------------------------------------
84 bias_fail_sw : OUT STD_LOGIC;
85 ADC_OEB_bar_CH : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
86 ADC_smpclk : OUT STD_LOGIC;
87 ADC_data : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
88 -- DAC --------------------------------------------------------------------
89 DAC_SDO : OUT STD_LOGIC;
90 DAC_SCK : OUT STD_LOGIC;
91 DAC_SYNC : OUT STD_LOGIC;
92 DAC_CAL_EN : OUT STD_LOGIC;
93 -- HK ---------------------------------------------------------------------
94 HK_smpclk : OUT STD_LOGIC;
95 ADC_OEB_bar_HK : OUT STD_LOGIC;
96 HK_SEL : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
97 ---------------------------------------------------------------------------
98 TAG8 : OUT STD_LOGIC
99 );
100
101 END LFR_EQM;
102
103
104 ARCHITECTURE beh OF LFR_EQM IS
105
106 SIGNAL clk_25 : STD_LOGIC := '0';
107 SIGNAL clk_24 : STD_LOGIC := '0';
108 -----------------------------------------------------------------------------
109 SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
110 SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0);
111
112 -- CONSTANTS
113 CONSTANT CFG_PADTECH : INTEGER := inferred;
114 CONSTANT NB_APB_SLAVE : INTEGER := 11; -- 3 = grspw + waveform picker + time manager, 11 allows pindex = f
115 CONSTANT NB_AHB_SLAVE : INTEGER := 1;
116 CONSTANT NB_AHB_MASTER : INTEGER := 2; -- 2 = grspw + waveform picker
117
118 SIGNAL apbi_ext : apb_slv_in_type;
119 SIGNAL apbo_ext : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5) := (OTHERS => apb_none);
120 SIGNAL ahbi_s_ext : ahb_slv_in_type;
121 SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3) := (OTHERS => ahbs_none);
122 SIGNAL ahbi_m_ext : AHB_Mst_In_Type;
123 SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1) := (OTHERS => ahbm_none);
124
125 -- Spacewire signals
126 SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
127 SIGNAL stmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
128 SIGNAL spw_rxclk : STD_LOGIC_VECTOR(1 DOWNTO 0);
129 SIGNAL spw_rxtxclk : STD_ULOGIC;
130 SIGNAL spw_rxclkn : STD_ULOGIC;
131 SIGNAL spw_clk : STD_LOGIC;
132 SIGNAL swni : grspw_in_type;
133 SIGNAL swno : grspw_out_type;
134
135 --GPIO
136 SIGNAL gpioi : gpio_in_type;
137 SIGNAL gpioo : gpio_out_type;
138
139 -- AD Converter ADS7886
140 SIGNAL sample : Samples14v(8 DOWNTO 0);
141 SIGNAL sample_s : Samples(8 DOWNTO 0);
142 SIGNAL sample_val : STD_LOGIC;
143 SIGNAL ADC_OEB_bar_CH_s : STD_LOGIC_VECTOR(8 DOWNTO 0);
144
145 -----------------------------------------------------------------------------
146 SIGNAL observation_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
147
148 -----------------------------------------------------------------------------
149 SIGNAL rstn : STD_LOGIC;
150
151 SIGNAL LFR_soft_rstn : STD_LOGIC;
152 SIGNAL LFR_rstn : STD_LOGIC;
153
154 SIGNAL ADC_smpclk_s : STD_LOGIC;
155
156 SIGNAL nSRAM_CE : STD_LOGIC_VECTOR(1 DOWNTO 0);
157
158 BEGIN -- beh
159
160 -----------------------------------------------------------------------------
161 -- CLK
162 -----------------------------------------------------------------------------
163 rst0 : rstgen PORT MAP (reset, clk_25, '1', rstn, OPEN);
164
165 PROCESS(clk50MHz)
166 BEGIN
167 IF clk50MHz'EVENT AND clk50MHz = '1' THEN
168 clk_25 <= NOT clk_25;
169 END IF;
170 END PROCESS;
171
172 PROCESS(clk49_152MHz)
173 BEGIN
174 IF clk49_152MHz'EVENT AND clk49_152MHz = '1' THEN
175 clk_24 <= NOT clk_24;
176 END IF;
177 END PROCESS;
178
179 -----------------------------------------------------------------------------
180 --
181 leon3_soc_1 : leon3_soc
182 GENERIC MAP (
183 fabtech => apa3e,
184 memtech => apa3e,
185 padtech => inferred,
186 clktech => inferred,
187 disas => 0,
188 dbguart => 0,
189 pclow => 2,
190 clk_freq => 25000,
191 IS_RADHARD => 0,
192 NB_CPU => 1,
193 ENABLE_FPU => 1,
194 FPU_NETLIST => 0,
195 ENABLE_DSU => 1,
196 ENABLE_AHB_UART => 1,
197 ENABLE_APB_UART => 1,
198 ENABLE_IRQMP => 1,
199 ENABLE_GPT => 1,
200 NB_AHB_MASTER => NB_AHB_MASTER,
201 NB_AHB_SLAVE => NB_AHB_SLAVE,
202 NB_APB_SLAVE => NB_APB_SLAVE,
203 ADDRESS_SIZE => 19,
204 USES_IAP_MEMCTRLR => 1)
205 PORT MAP (
206 clk => clk_25,
207 reset => rstn,
208 errorn => OPEN,
209
210 ahbrxd => TAG1,
211 ahbtxd => TAG3,
212 urxd1 => TAG2,
213 utxd1 => TAG4,
214
215 address => address,
216 data => data,
217 nSRAM_BE0 => OPEN,
218 nSRAM_BE1 => OPEN,
219 nSRAM_BE2 => OPEN,
220 nSRAM_BE3 => OPEN,
221 nSRAM_WE => nSRAM_W,
222 nSRAM_CE => nSRAM_CE,
223 nSRAM_OE => nSRAM_G,
224 nSRAM_READY => nSRAM_BUSY,
225 SRAM_MBE => nSRAM_MBE,
226
227 apbi_ext => apbi_ext,
228 apbo_ext => apbo_ext,
229 ahbi_s_ext => ahbi_s_ext,
230 ahbo_s_ext => ahbo_s_ext,
231 ahbi_m_ext => ahbi_m_ext,
232 ahbo_m_ext => ahbo_m_ext);
233
234
235 nSRAM_E1 <= nSRAM_CE(0);
236 nSRAM_E2 <= nSRAM_CE(1);
237
238 -------------------------------------------------------------------------------
239 -- APB_LFR_TIME_MANAGEMENT ----------------------------------------------------
240 -------------------------------------------------------------------------------
241 apb_lfr_management_1 : apb_lfr_management
242 GENERIC MAP (
243 tech => apa3e,
244 pindex => 6,
245 paddr => 6,
246 pmask => 16#fff#,
247 FIRST_DIVISION => 374, -- ((49.152/2) /2^16) - 1 = 375 - 1 = 374
248 NB_SECOND_DESYNC => 60) -- 60 secondes of desynchronization before CoarseTime's MSB is Set
249 PORT MAP (
250 clk25MHz => clk_25,
251 clk24_576MHz => clk_24, -- 49.152MHz/2
252 resetn => rstn,
253 grspw_tick => swno.tickout,
254 apbi => apbi_ext,
255 apbo => apbo_ext(6),
256
257 HK_sample => sample_s(8),
258 HK_val => sample_val,
259 HK_sel => HK_SEL,
260
261 DAC_SDO => DAC_SDO,
262 DAC_SCK => DAC_SCK,
263 DAC_SYNC => DAC_SYNC,
264 DAC_CAL_EN => DAC_CAL_EN,
265
266 coarse_time => coarse_time,
267 fine_time => fine_time,
268 LFR_soft_rstn => LFR_soft_rstn
269 );
270
271 -----------------------------------------------------------------------
272 --- SpaceWire --------------------------------------------------------
273 -----------------------------------------------------------------------
274
275 ------------------------------------------------------------------------------
276 -- \/\/\/\/ TODO : spacewire enable should be controled by the SPW IP \/\/\/\/
277 ------------------------------------------------------------------------------
278 spw1_en <= '1';
279 spw2_en <= '1';
280 ------------------------------------------------------------------------------
281 -- /\/\/\/\ --------------------------------------------------------- /\/\/\/\
282 ------------------------------------------------------------------------------
283
284 spw_clk <= clk50MHz;
285 spw_rxtxclk <= spw_clk;
286 spw_rxclkn <= NOT spw_rxtxclk;
287
288 -- PADS for SPW1
289 spw1_rxd_pad : inpad GENERIC MAP (tech => inferred)
290 PORT MAP (spw1_din, dtmp(0));
291 spw1_rxs_pad : inpad GENERIC MAP (tech => inferred)
292 PORT MAP (spw1_sin, stmp(0));
293 spw1_txd_pad : outpad GENERIC MAP (tech => inferred)
294 PORT MAP (spw1_dout, swno.d(0));
295 spw1_txs_pad : outpad GENERIC MAP (tech => inferred)
296 PORT MAP (spw1_sout, swno.s(0));
297 -- PADS FOR SPW2
298 spw2_rxd_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
299 PORT MAP (spw2_din, dtmp(1));
300 spw2_rxs_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
301 PORT MAP (spw2_sin, stmp(1));
302 spw2_txd_pad : outpad GENERIC MAP (tech => inferred)
303 PORT MAP (spw2_dout, swno.d(1));
304 spw2_txs_pad : outpad GENERIC MAP (tech => inferred)
305 PORT MAP (spw2_sout, swno.s(1));
306
307 -- GRSPW PHY
308 --spw1_input: if CFG_SPW_GRSPW = 1 generate
309 spw_inputloop : FOR j IN 0 TO 1 GENERATE
310 spw_phy0 : grspw_phy
311 GENERIC MAP(
312 tech => apa3e,
313 rxclkbuftype => 1,
314 scantest => 0)
315 PORT MAP(
316 rxrst => swno.rxrst,
317 di => dtmp(j),
318 si => stmp(j),
319 rxclko => spw_rxclk(j),
320 do => swni.d(j),
321 ndo => swni.nd(j*5+4 DOWNTO j*5),
322 dconnect => swni.dconnect(j*2+1 DOWNTO j*2));
323 END GENERATE spw_inputloop;
324
325 -- SPW core
326 sw0 : grspwm GENERIC MAP(
327 tech => apa3e,
328 hindex => 1,
329 pindex => 5,
330 paddr => 5,
331 pirq => 11,
332 sysfreq => 25000, -- CPU_FREQ
333 rmap => 1,
334 rmapcrc => 1,
335 fifosize1 => 16,
336 fifosize2 => 16,
337 rxclkbuftype => 1,
338 rxunaligned => 0,
339 rmapbufs => 4,
340 ft => 0,
341 netlist => 0,
342 ports => 2,
343 --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1
344 memtech => apa3e,
345 destkey => 2,
346 spwcore => 1
347 --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1
348 --output_type => CFG_SPW_OUTPUT, -- not used byt the spw core 1
349 --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1
350 )
351 PORT MAP(rstn, clk_25, spw_rxclk(0),
352 spw_rxclk(1), spw_rxtxclk, spw_rxtxclk,
353 ahbi_m_ext, ahbo_m_ext(1), apbi_ext, apbo_ext(5),
354 swni, swno);
355
356 swni.tickin <= '0';
357 swni.rmapen <= '1';
358 swni.clkdiv10 <= "00000100"; -- 10 MHz / (4 + 1) = 10 MHz
359 swni.tickinraw <= '0';
360 swni.timein <= (OTHERS => '0');
361 swni.dcrstval <= (OTHERS => '0');
362 swni.timerrstval <= (OTHERS => '0');
363
364 -------------------------------------------------------------------------------
365 -- LFR ------------------------------------------------------------------------
366 -------------------------------------------------------------------------------
367 LFR_rstn <= LFR_soft_rstn AND rstn;
368
369 lpp_lfr_1 : lpp_lfr
370 GENERIC MAP (
371 Mem_use => use_RAM,
372 nb_data_by_buffer_size => 32,
373 --nb_word_by_buffer_size => 30,
374 nb_snapshot_param_size => 32,
375 delta_vector_size => 32,
376 delta_vector_size_f0_2 => 7, -- log2(96)
377 pindex => 15,
378 paddr => 15,
379 pmask => 16#fff#,
380 pirq_ms => 6,
381 pirq_wfp => 14,
382 hindex => 2,
383 top_lfr_version => X"02013F") -- aa.bb.cc version
384 -- AA : BOARD NUMBER
385 -- 0 => MINI_LFR
386 -- 1 => EM
387 -- 1 => EQM (with A3PE3000)
388 PORT MAP (
389 clk => clk_25,
390 rstn => LFR_rstn,
391 sample_B => sample_s(2 DOWNTO 0),
392 sample_E => sample_s(7 DOWNTO 3),
393 sample_val => sample_val,
394 apbi => apbi_ext,
395 apbo => apbo_ext(15),
396 ahbi => ahbi_m_ext,
397 ahbo => ahbo_m_ext(2),
398 coarse_time => coarse_time,
399 fine_time => fine_time,
400 data_shaping_BW => bias_fail_sw,
401 debug_vector => OPEN,
402 debug_vector_ms => OPEN); --,
403 --observation_vector_0 => OPEN,
404 --observation_vector_1 => OPEN,
405 --observation_reg => observation_reg);
406
407
408 all_sample : FOR I IN 7 DOWNTO 0 GENERATE
409 sample_s(I) <= sample(I) & '0' & '0';
410 END GENERATE all_sample;
411 sample_s(8) <= sample(8)(13) & sample(8)(13) & sample(8);
412
413 -----------------------------------------------------------------------------
414 --
415 -----------------------------------------------------------------------------
416 top_ad_conv_RHF1401_withFilter_1 : top_ad_conv_RHF1401_withFilter
417 GENERIC MAP (
418 ChanelCount => 9,
419 ncycle_cnv_high => 13,
420 ncycle_cnv => 25,
421 FILTER_ENABLED => 16#FF#)
422 PORT MAP (
423 cnv_clk => clk_24,
424 cnv_rstn => rstn,
425 cnv => ADC_smpclk_s,
426 clk => clk_25,
427 rstn => rstn,
428 ADC_data => ADC_data,
429 ADC_nOE => ADC_OEB_bar_CH_s,
430 sample => sample,
431 sample_val => sample_val);
432
433 ADC_OEB_bar_CH <= ADC_OEB_bar_CH_s(7 DOWNTO 0);
434
435 ADC_smpclk <= ADC_smpclk_s;
436 HK_smpclk <= ADC_smpclk_s;
437
438 TAG8 <= ADC_smpclk_s;
439
440 -----------------------------------------------------------------------------
441 -- HK
442 -----------------------------------------------------------------------------
443 ADC_OEB_bar_HK <= ADC_OEB_bar_CH_s(8);
444
445 END beh;
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1 #GRLIB=../..
2 VHDLIB=../..
3 SCRIPTSDIR=$(VHDLIB)/scripts/
4 GRLIB := $(shell sh $(VHDLIB)/scripts/lpp_relpath.sh)
5 TOP=LFR_EQM
6 BOARD=LFR-EQM
7 include $(VHDLIB)/boards/$(BOARD)/Makefile.inc
8 DEVICE=$(PART)-$(PACKAGE)$(SPEED)
9 UCF=$(GRLIB)/boards/$(BOARD)/$(TOP).ucf
10 QSF=$(GRLIB)/boards/$(BOARD)/$(TOP).qsf
11 EFFORT=high
12 XSTOPT=
13 SYNPOPT="set_option -pipe 0; set_option -retiming 0; set_option -write_apr_constraint 0"
14 #VHDLSYNFILES=config.vhd ahbrom.vhd leon3mp.vhd
15 #VHDLSYNFILES=config.vhd leon3mp.vhd
16 VHDLSYNFILES=LFR-EQM.vhd
17 VHDLSIMFILES=testbench.vhd
18 #SIMTOP=testbench
19 PDC=$(VHDLIB)/boards/$(BOARD)/LFR_EQM_A3PE3000.pdc
20 SDC=$(VHDLIB)/boards/$(BOARD)/LFR_EQM.sdc
21
22 BITGEN=$(VHDLIB)/boards/$(BOARD)/default.ut
23 CLEAN=soft-clean
24
25 TECHLIBS = proasic3e
26
27 LIBSKIP = core1553bbc core1553brm core1553brt gr1553 corePCIF \
28 tmtc openchip hynix ihp gleichmann micron usbhc
29
30 DIRSKIP = b1553 pcif leon2 leon2ft crypto satcan ddr usb ata i2c \
31 pci grusbhc haps slink ascs pwm coremp7 spi ac97 \
32 ./amba_lcd_16x2_ctrlr \
33 ./general_purpose/lpp_AMR \
34 ./general_purpose/lpp_balise \
35 ./general_purpose/lpp_delay \
36 ./lpp_bootloader \
37 ./dsp/lpp_fft_rtax \
38 ./lpp_uart \
39 ./lpp_usb \
40 ./lpp_sim/CY7C1061DV33 \
41
42 FILESKIP = i2cmst.vhd \
43 APB_MULTI_DIODE.vhd \
44 APB_MULTI_DIODE.vhd \
45 Top_MatrixSpec.vhd \
46 APB_FFT.vhd\
47 CoreFFT_simu.vhd \
48 lpp_lfr_apbreg_simu.vhd
49
50 include $(GRLIB)/bin/Makefile
51 include $(GRLIB)/software/leon3/Makefile
52
53 ################## project specific targets ##########################
54
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