# HG changeset patch # User pellion # Date 2015-03-03 09:44:51 # Node ID fddf2234482fd7d31ae35c25fe06d703a5f56812 # Parent 7527baf4377d6b7d44498a207ed2b1f7aecb1886 LFR-EQM-2.1.63 diff --git a/boards/LFR-EQM/LFR_EQM.sdc b/boards/LFR-EQM/LFR_EQM.sdc new file mode 100644 --- /dev/null +++ b/boards/LFR-EQM/LFR_EQM.sdc @@ -0,0 +1,30 @@ +# Top Level Design Parameters + +# Clocks + +create_clock -period 10.000000 -waveform {0.000000 5.000000} clk50MHz +create_clock -period 20.344999 -waveform {0.000000 10.172500} clk49_152MHz +create_clock -period 40.000000 -waveform {0.000000 20.000000} clk_25:Q +create_clock -period 40.690000 -waveform {0.000000 20.345100} clk_24:Q +create_clock -name SPW_CLOCK -period 100.000000 -waveform {0.000000 50.000000} {spw1_din spw1_sin spw2_din spw2_sin} + + +# False Paths Between Clocks + + +# False Path Constraints + + +# Maximum Delay Constraints + + +# Multicycle Constraints + + +# Virtual Clocks +# Output Load Constraints +# Driving Cell Constraints +# Wire Loads +# set_wire_load_mode top + +# Other Constraints diff --git a/boards/LFR-EQM/LFR_EQM_A3PE3000.pdc b/boards/LFR-EQM/LFR_EQM_A3PE3000.pdc new file mode 100644 --- /dev/null +++ b/boards/LFR-EQM/LFR_EQM_A3PE3000.pdc @@ -0,0 +1,124 @@ +set_io clk49_152MHz -pinname D5 -fixed yes -DIRECTION Inout +set_io clk50MHz -pinname B3 -fixed yes -DIRECTION Inout +set_io reset -pinname R4 -fixed yes -DIRECTION Inout + +set_io {address[0]} -pinname U3 -fixed yes -DIRECTION Inout +set_io {address[1]} -pinname V14 -fixed yes -DIRECTION Inout +set_io {address[2]} -pinname V13 -fixed yes -DIRECTION Inout +set_io {address[3]} -pinname V16 -fixed yes -DIRECTION Inout +set_io {address[4]} -pinname N9 -fixed yes -DIRECTION Inout +set_io {address[5]} -pinname T11 -fixed yes -DIRECTION Inout +set_io {address[6]} -pinname U13 -fixed yes -DIRECTION Inout +set_io {address[7]} -pinname R5 -fixed yes -DIRECTION Inout +set_io {address[8]} -pinname U2 -fixed yes -DIRECTION Inout +set_io {address[9]} -pinname N11 -fixed yes -DIRECTION Inout +set_io {address[10]} -pinname R13 -fixed yes -DIRECTION Inout +set_io {address[11]} -pinname R12 -fixed yes -DIRECTION Inout +set_io {address[12]} -pinname M15 -fixed yes -DIRECTION Inout +set_io {address[13]} -pinname T12 -fixed yes -DIRECTION Inout +set_io {address[14]} -pinname M13 -fixed yes -DIRECTION Inout +set_io {address[15]} -pinname T13 -fixed yes -DIRECTION Inout +set_io {address[16]} -pinname L13 -fixed yes -DIRECTION Inout +set_io {address[17]} -pinname V17 -fixed yes -DIRECTION Inout +set_io {address[18]} -pinname V15 -fixed yes -DIRECTION Inout + +set_io {data[0]} -pinname V4 -fixed yes -DIRECTION Inout +set_io {data[1]} -pinname V3 -fixed yes -DIRECTION Inout +set_io {data[2]} -pinname V2 -fixed yes -DIRECTION Inout +set_io {data[3]} -pinname T3 -fixed yes -DIRECTION Inout +set_io {data[4]} -pinname N6 -fixed yes -DIRECTION Inout +set_io {data[5]} -pinname P6 -fixed yes -DIRECTION Inout +set_io {data[6]} -pinname R6 -fixed yes -DIRECTION Inout +set_io {data[7]} -pinname T4 -fixed yes -DIRECTION Inout +set_io {data[8]} -pinname T1 -fixed yes -DIRECTION Inout +set_io {data[9]} -pinname R1 -fixed yes -DIRECTION Inout +set_io {data[10]} -pinname P1 -fixed yes -DIRECTION Inout +set_io {data[11]} -pinname N2 -fixed yes -DIRECTION Inout +set_io {data[12]} -pinname R3 -fixed yes -DIRECTION Inout +set_io {data[13]} -pinname P4 -fixed yes -DIRECTION Inout +set_io {data[14]} -pinname N4 -fixed yes -DIRECTION Inout +set_io {data[15]} -pinname N3 -fixed yes -DIRECTION Inout +set_io {data[16]} -pinname G12 -fixed yes -DIRECTION Inout +set_io {data[17]} -pinname G15 -fixed yes -DIRECTION Inout +set_io {data[18]} -pinname H15 -fixed yes -DIRECTION Inout +set_io {data[19]} -pinname F17 -fixed yes -DIRECTION Inout +set_io {data[20]} -pinname F18 -fixed yes -DIRECTION Inout +set_io {data[21]} -pinname G17 -fixed yes -DIRECTION Inout +set_io {data[22]} -pinname H18 -fixed yes -DIRECTION Inout +set_io {data[23]} -pinname J18 -fixed yes -DIRECTION Inout +set_io {data[24]} -pinname R18 -fixed yes -DIRECTION Inout +set_io {data[25]} -pinname N18 -fixed yes -DIRECTION Inout +set_io {data[26]} -pinname P17 -fixed yes -DIRECTION Inout +set_io {data[27]} -pinname N17 -fixed yes -DIRECTION Inout +set_io {data[28]} -pinname T18 -fixed yes -DIRECTION Inout +set_io {data[29]} -pinname M17 -fixed yes -DIRECTION Inout +set_io {data[30]} -pinname U18 -fixed yes -DIRECTION Inout +set_io {data[31]} -pinname L18 -fixed yes -DIRECTION Inout + +set_io nSRAM_MBE -pinname E4 -fixed yes -DIRECTION Inout +set_io nSRAM_E1 -pinname D1 -fixed yes -DIRECTION Inout +set_io nSRAM_E2 -pinname C1 -fixed yes -DIRECTION Inout +#set_io nSRAM_SCRUB -pinname C2 -fixed yes -DIRECTION Inout +set_io nSRAM_W -pinname D4 -fixed yes -DIRECTION Inout +set_io nSRAM_G -pinname E1 -fixed yes -DIRECTION Inout +set_io nSRAM_BUSY -pinname F4 -fixed yes -DIRECTION Inout + +set_io spw1_en -pinname G4 -fixed yes -DIRECTION Inout +set_io spw1_din -pinname D13 -fixed yes -DIRECTION Inout +set_io spw1_sin -pinname D14 -fixed yes -DIRECTION Inout +set_io spw1_dout -pinname C16 -fixed yes -DIRECTION Inout +set_io spw1_sout -pinname C4 -fixed yes -DIRECTION Inout + +set_io spw2_en -pinname G3 -fixed yes -DIRECTION Inout +set_io spw2_din -pinname E6 -fixed yes -DIRECTION Inout +set_io spw2_sin -pinname C15 -fixed yes -DIRECTION Inout +set_io spw2_dout -pinname B7 -fixed yes -DIRECTION Inout +set_io spw2_sout -pinname D7 -fixed yes -DIRECTION Inout + +set_io TAG1 -pinname J12 -fixed yes -DIRECTION Inout +set_io TAG2 -pinname K12 -fixed yes -DIRECTION Inout +set_io TAG3 -pinname K13 -fixed yes -DIRECTION Inout +set_io TAG4 -pinname L16 -fixed yes -DIRECTION Inout +#set_io TAG5 -pinname L15 -fixed yes -DIRECTION Inout +#set_io TAG6 -pinname M16 -fixed yes -DIRECTION Inout +#set_io TAG7 -pinname J14 -fixed yes -DIRECTION Inout +set_io TAG8 -pinname K15 -fixed yes -DIRECTION Inout +#set_io TAG9 -pinname J17 -fixed yes -DIRECTION Inout + +set_io bias_fail_sw -pinname A3 -fixed yes -DIRECTION Inout + +set_io {ADC_OEB_bar_CH[0]} -pinname A10 -fixed yes -DIRECTION Inout +set_io {ADC_OEB_bar_CH[1]} -pinname B10 -fixed yes -DIRECTION Inout +set_io {ADC_OEB_bar_CH[2]} -pinname B12 -fixed yes -DIRECTION Inout +set_io {ADC_OEB_bar_CH[3]} -pinname A11 -fixed yes -DIRECTION Inout +set_io {ADC_OEB_bar_CH[4]} -pinname B13 -fixed yes -DIRECTION Inout +set_io {ADC_OEB_bar_CH[5]} -pinname C6 -fixed yes -DIRECTION Inout +set_io {ADC_OEB_bar_CH[6]} -pinname A13 -fixed yes -DIRECTION Inout +set_io {ADC_OEB_bar_CH[7]} -pinname A14 -fixed yes -DIRECTION Inout + +set_io ADC_smpclk -pinname A15 -fixed yes -DIRECTION Inout + +set_io HK_smpclk -pinname R11 -fixed yes -DIRECTION Inout +set_io ADC_OEB_bar_HK -pinname D6 -fixed yes -DIRECTION Inout +set_io {HK_SEL[0]} -pinname C3 -fixed yes -DIRECTION Inout +set_io {HK_SEL[1]} -pinname A2 -fixed yes -DIRECTION Inout + +set_io {ADC_data[0]} -pinname G13 -fixed yes -DIRECTION Inout +set_io {ADC_data[1]} -pinname G16 -fixed yes -DIRECTION Inout +set_io {ADC_data[2]} -pinname F16 -fixed yes -DIRECTION Inout +set_io {ADC_data[3]} -pinname E15 -fixed yes -DIRECTION Inout +set_io {ADC_data[4]} -pinname F13 -fixed yes -DIRECTION Inout +set_io {ADC_data[5]} -pinname F15 -fixed yes -DIRECTION Inout +set_io {ADC_data[6]} -pinname D16 -fixed yes -DIRECTION Inout +set_io {ADC_data[7]} -pinname D15 -fixed yes -DIRECTION Inout +set_io {ADC_data[8]} -pinname B17 -fixed yes -DIRECTION Inout +set_io {ADC_data[9]} -pinname A17 -fixed yes -DIRECTION Inout +set_io {ADC_data[10]} -pinname A16 -fixed yes -DIRECTION Inout +set_io {ADC_data[11]} -pinname B16 -fixed yes -DIRECTION Inout +set_io {ADC_data[12]} -pinname C12 -fixed yes -DIRECTION Inout +set_io {ADC_data[13]} -pinname C13 -fixed yes -DIRECTION Inout + +set_io DAC_SDO -pinname A4 -fixed yes -DIRECTION Inout +set_io DAC_SCK -pinname A5 -fixed yes -DIRECTION Inout +set_io DAC_SYNC -pinname B6 -fixed yes -DIRECTION Inout +set_io DAC_CAL_EN -pinname A6 -fixed yes -DIRECTION Inout diff --git a/boards/LFR-EQM/LFR_EQM_RTAX.pdc b/boards/LFR-EQM/LFR_EQM_RTAX.pdc new file mode 100644 --- /dev/null +++ b/boards/LFR-EQM/LFR_EQM_RTAX.pdc @@ -0,0 +1,124 @@ +set_io clk49_152MHz -pinname 314 -fixed yes -DIRECTION Inout +set_io clk50MHz -pinname 318 -fixed yes -DIRECTION Inout +set_io reset -pinname 128 -fixed yes -DIRECTION Inout + +set_io {address[0]} -pinname 124 -fixed yes -DIRECTION Inout +set_io {address[1]} -pinname 156 -fixed yes -DIRECTION Inout +set_io {address[2]} -pinname 154 -fixed yes -DIRECTION Inout +set_io {address[3]} -pinname 160 -fixed yes -DIRECTION Inout +set_io {address[4]} -pinname 162 -fixed yes -DIRECTION Inout +set_io {address[5]} -pinname 165 -fixed yes -DIRECTION Inout +set_io {address[6]} -pinname 155 -fixed yes -DIRECTION Inout +set_io {address[7]} -pinname 127 -fixed yes -DIRECTION Inout +set_io {address[8]} -pinname 123 -fixed yes -DIRECTION Inout +set_io {address[9]} -pinname 137 -fixed yes -DIRECTION Inout +set_io {address[10]} -pinname 141 -fixed yes -DIRECTION Inout +set_io {address[11]} -pinname 166 -fixed yes -DIRECTION Inout +set_io {address[12]} -pinname 182 -fixed yes -DIRECTION Inout +set_io {address[13]} -pinname 167 -fixed yes -DIRECTION Inout +set_io {address[14]} -pinname 181 -fixed yes -DIRECTION Inout +set_io {address[15]} -pinname 171 -fixed yes -DIRECTION Inout +set_io {address[16]} -pinname 183 -fixed yes -DIRECTION Inout +set_io {address[17]} -pinname 161 -fixed yes -DIRECTION Inout +set_io {address[18]} -pinname 159 -fixed yes -DIRECTION Inout + +set_io {data[0]} -pinname 103 -fixed yes -DIRECTION Inout +set_io {data[1]} -pinname 100 -fixed yes -DIRECTION Inout +set_io {data[2]} -pinname 99 -fixed yes -DIRECTION Inout +set_io {data[3]} -pinname 98 -fixed yes -DIRECTION Inout +set_io {data[4]} -pinname 97 -fixed yes -DIRECTION Inout +set_io {data[5]} -pinname 94 -fixed yes -DIRECTION Inout +set_io {data[6]} -pinname 93 -fixed yes -DIRECTION Inout +set_io {data[7]} -pinname 92 -fixed yes -DIRECTION Inout +set_io {data[8]} -pinname 82 -fixed yes -DIRECTION Inout +set_io {data[9]} -pinname 79 -fixed yes -DIRECTION Inout +set_io {data[10]} -pinname 78 -fixed yes -DIRECTION Inout +set_io {data[11]} -pinname 77 -fixed yes -DIRECTION Inout +set_io {data[12]} -pinname 71 -fixed yes -DIRECTION Inout +set_io {data[13]} -pinname 70 -fixed yes -DIRECTION Inout +set_io {data[14]} -pinname 67 -fixed yes -DIRECTION Inout +set_io {data[15]} -pinname 66 -fixed yes -DIRECTION Inout +set_io {data[16]} -pinname 246 -fixed yes -DIRECTION Inout +set_io {data[17]} -pinname 242 -fixed yes -DIRECTION Inout +set_io {data[18]} -pinname 241 -fixed yes -DIRECTION Inout +set_io {data[19]} -pinname 229 -fixed yes -DIRECTION Inout +set_io {data[20]} -pinname 228 -fixed yes -DIRECTION Inout +set_io {data[21]} -pinname 227 -fixed yes -DIRECTION Inout +set_io {data[22]} -pinname 224 -fixed yes -DIRECTION Inout +set_io {data[23]} -pinname 223 -fixed yes -DIRECTION Inout +set_io {data[24]} -pinname 206 -fixed yes -DIRECTION Inout +set_io {data[25]} -pinname 212 -fixed yes -DIRECTION Inout +set_io {data[26]} -pinname 207 -fixed yes -DIRECTION Inout +set_io {data[27]} -pinname 211 -fixed yes -DIRECTION Inout +set_io {data[28]} -pinname 205 -fixed yes -DIRECTION Inout +set_io {data[29]} -pinname 213 -fixed yes -DIRECTION Inout +set_io {data[30]} -pinname 202 -fixed yes -DIRECTION Inout +set_io {data[31]} -pinname 214 -fixed yes -DIRECTION Inout + +set_io nSRAM_MBE -pinname 9 -fixed yes -DIRECTION Inout +set_io nSRAM_E1 -pinname 20 -fixed yes -DIRECTION Inout +set_io nSRAM_E2 -pinname 15 -fixed yes -DIRECTION Inout +set_io nSRAM_SCRUB -pinname 14 -fixed yes -DIRECTION Inout +set_io nSRAM_W -pinname 8 -fixed yes -DIRECTION Inout +set_io nSRAM_G -pinname 21 -fixed yes -DIRECTION Inout +set_io nSRAM_BUSY -pinname 24 -fixed yes -DIRECTION Inout + +set_io spw1_en -pinname 31 -fixed yes -DIRECTION Inout +set_io spw1_din -pinname 300 -fixed yes -DIRECTION Inout +set_io spw1_sin -pinname 299 -fixed yes -DIRECTION Inout +set_io spw1_dout -pinname 303 -fixed yes -DIRECTION Inout +set_io spw1_sout -pinname 317 -fixed yes -DIRECTION Inout + +set_io spw2_en -pinname 30 -fixed yes -DIRECTION Inout +set_io spw2_din -pinname 313 -fixed yes -DIRECTION Inout +set_io spw2_sin -pinname 304 -fixed yes -DIRECTION Inout +set_io spw2_dout -pinname 335 -fixed yes -DIRECTION Inout +set_io spw2_sout -pinname 330 -fixed yes -DIRECTION Inout + +set_io TAG1 -pinname 195 -fixed yes -DIRECTION Inout +set_io TAG2 -pinname 190 -fixed yes -DIRECTION Inout +set_io TAG3 -pinname 189 -fixed yes -DIRECTION Inout +set_io TAG4 -pinname 188 -fixed yes -DIRECTION Inout +#set_io TAG5 -pinname 187 -fixed yes -DIRECTION Inout +#set_io TAG6 -pinname 184 -fixed yes -DIRECTION Inout +#set_io TAG7 -pinname 200 -fixed yes -DIRECTION Inout +set_io TAG8 -pinname 199 -fixed yes -DIRECTION Inout +#set_io TAG9 -pinname 196 -fixed yes -DIRECTION Inout + +set_io bias_fail_sw -pinname 342 -fixed yes -DIRECTION Inout + +set_io {ADC_OEB_bar_CH[0]} -pinname 288 -fixed yes -DIRECTION Inout +set_io {ADC_OEB_bar_CH[1]} -pinname 287 -fixed yes -DIRECTION Inout +set_io {ADC_OEB_bar_CH[2]} -pinname 285 -fixed yes -DIRECTION Inout +set_io {ADC_OEB_bar_CH[3]} -pinname 286 -fixed yes -DIRECTION Inout +set_io {ADC_OEB_bar_CH[4]} -pinname 281 -fixed yes -DIRECTION Inout +set_io {ADC_OEB_bar_CH[5]} -pinname 332 -fixed yes -DIRECTION Inout +set_io {ADC_OEB_bar_CH[6]} -pinname 282 -fixed yes -DIRECTION Inout +set_io {ADC_OEB_bar_CH[7]} -pinname 280 -fixed yes -DIRECTION Inout + +set_io ADC_smpclk -pinname 279 -fixed yes -DIRECTION Inout + +set_io HK_smpclk -pinname 172 -fixed yes -DIRECTION Inout +set_io ADC_OEB_bar_HK -pinname 331 -fixed yes -DIRECTION Inout +set_io {HK_SEL[0]} -pinname 6 -fixed yes -DIRECTION Inout +set_io {HK_SEL[1]} -pinname 343 -fixed yes -DIRECTION Inout + +set_io {ADC_data[0]} -pinname 251 -fixed yes -DIRECTION Inout +set_io {ADC_data[1]} -pinname 253 -fixed yes -DIRECTION Inout +set_io {ADC_data[2]} -pinname 257 -fixed yes -DIRECTION Inout +set_io {ADC_data[3]} -pinname 259 -fixed yes -DIRECTION Inout +set_io {ADC_data[4]} -pinname 252 -fixed yes -DIRECTION Inout +set_io {ADC_data[5]} -pinname 254 -fixed yes -DIRECTION Inout +set_io {ADC_data[6]} -pinname 258 -fixed yes -DIRECTION Inout +set_io {ADC_data[7]} -pinname 260 -fixed yes -DIRECTION Inout +set_io {ADC_data[8]} -pinname 270 -fixed yes -DIRECTION Inout +set_io {ADC_data[9]} -pinname 274 -fixed yes -DIRECTION Inout +set_io {ADC_data[10]} -pinname 276 -fixed yes -DIRECTION Inout +set_io {ADC_data[11]} -pinname 275 -fixed yes -DIRECTION Inout +set_io {ADC_data[12]} -pinname 273 -fixed yes -DIRECTION Inout +set_io {ADC_data[13]} -pinname 269 -fixed yes -DIRECTION Inout + +set_io DAC_SDO -pinname 341 -fixed yes -DIRECTION Inout +set_io DAC_SCK -pinname 338 -fixed yes -DIRECTION Inout +set_io DAC_SYNC -pinname 337 -fixed yes -DIRECTION Inout +set_io DAC_CAL_EN -pinname 336 -fixed yes -DIRECTION Inout diff --git a/boards/LFR-EQM/Makefile.inc b/boards/LFR-EQM/Makefile.inc new file mode 100644 --- /dev/null +++ b/boards/LFR-EQM/Makefile.inc @@ -0,0 +1,19 @@ +PACKAGE=\"\" +SPEED=Std +SYNFREQ=50 + +TECHNOLOGY=ProASIC3E +LIBERO_DIE=IT14X14M4 +PART=A3PE3000 + +DESIGNER_VOLTAGE=COM +DESIGNER_TEMP=COM +DESIGNER_PACKAGE=FBGA +DESIGNER_PINS=324 + +MANUFACTURER=Actel +MGCTECHNOLOGY=Proasic3 +MGCPART=$(PART) +MGCPACKAGE= {$(DESIGNER_PINS) $(DESIGNER_PACKAGE)} +LIBERO_PACKAGE=fg$(DESIGNER_PINS) + diff --git a/designs/LFR-EQM-WFP_MS/LFR-EQM.vhd b/designs/LFR-EQM-WFP_MS/LFR-EQM.vhd new file mode 100644 --- /dev/null +++ b/designs/LFR-EQM-WFP_MS/LFR-EQM.vhd @@ -0,0 +1,445 @@ +------------------------------------------------------------------------------ +-- This file is a part of the LPP VHDL IP LIBRARY +-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 3 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +------------------------------------------------------------------------------- +-- Author : Jean-christophe Pellion +-- Mail : jean-christophe.pellion@lpp.polytechnique.fr +------------------------------------------------------------------------------- +LIBRARY IEEE; +USE IEEE.numeric_std.ALL; +USE IEEE.std_logic_1164.ALL; +LIBRARY grlib; +USE grlib.amba.ALL; +USE grlib.stdlib.ALL; +LIBRARY techmap; +USE techmap.gencomp.ALL; +LIBRARY gaisler; +USE gaisler.memctrl.ALL; +USE gaisler.leon3.ALL; +USE gaisler.uart.ALL; +USE gaisler.misc.ALL; +USE gaisler.spacewire.ALL; +LIBRARY esa; +USE esa.memoryctrl.ALL; +LIBRARY lpp; +USE lpp.lpp_memory.ALL; +USE lpp.lpp_ad_conv.ALL; +USE lpp.lpp_lfr_pkg.ALL; -- contains lpp_lfr, not in the 206 rev of the VHD_Lib +USE lpp.lpp_top_lfr_pkg.ALL; -- contains top_wf_picker +USE lpp.iir_filter.ALL; +USE lpp.general_purpose.ALL; +USE lpp.lpp_lfr_management.ALL; +USE lpp.lpp_leon3_soc_pkg.ALL; + +ENTITY LFR_EQM IS + + PORT ( + clk50MHz : IN STD_ULOGIC; + clk49_152MHz : IN STD_ULOGIC; + reset : IN STD_ULOGIC; + + -- TAG -------------------------------------------------------------------- + TAG1 : IN STD_ULOGIC; -- DSU rx data + TAG3 : OUT STD_ULOGIC; -- DSU tx data + -- UART APB --------------------------------------------------------------- + TAG2 : IN STD_ULOGIC; -- UART1 rx data + TAG4 : OUT STD_ULOGIC; -- UART1 tx data + -- RAM -------------------------------------------------------------------- + address : OUT STD_LOGIC_VECTOR(18 DOWNTO 0); + data : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0); + + nSRAM_MBE : INOUT STD_LOGIC; -- new + nSRAM_E1 : OUT STD_LOGIC; -- new + nSRAM_E2 : OUT STD_LOGIC; -- new +-- nSRAM_SCRUB : OUT STD_LOGIC; -- new + nSRAM_W : OUT STD_LOGIC; -- new + nSRAM_G : OUT STD_LOGIC; -- new + nSRAM_BUSY : IN STD_LOGIC; -- new + -- SPW -------------------------------------------------------------------- + spw1_en : OUT STD_LOGIC; -- new + spw1_din : IN STD_LOGIC; + spw1_sin : IN STD_LOGIC; + spw1_dout : OUT STD_LOGIC; + spw1_sout : OUT STD_LOGIC; + spw2_en : OUT STD_LOGIC; -- new + spw2_din : IN STD_LOGIC; + spw2_sin : IN STD_LOGIC; + spw2_dout : OUT STD_LOGIC; + spw2_sout : OUT STD_LOGIC; + -- ADC -------------------------------------------------------------------- + bias_fail_sw : OUT STD_LOGIC; + ADC_OEB_bar_CH : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); + ADC_smpclk : OUT STD_LOGIC; + ADC_data : IN STD_LOGIC_VECTOR(13 DOWNTO 0); + -- DAC -------------------------------------------------------------------- + DAC_SDO : OUT STD_LOGIC; + DAC_SCK : OUT STD_LOGIC; + DAC_SYNC : OUT STD_LOGIC; + DAC_CAL_EN : OUT STD_LOGIC; + -- HK --------------------------------------------------------------------- + HK_smpclk : OUT STD_LOGIC; + ADC_OEB_bar_HK : OUT STD_LOGIC; + HK_SEL : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); + --------------------------------------------------------------------------- + TAG8 : OUT STD_LOGIC + ); + +END LFR_EQM; + + +ARCHITECTURE beh OF LFR_EQM IS + + SIGNAL clk_25 : STD_LOGIC := '0'; + SIGNAL clk_24 : STD_LOGIC := '0'; + ----------------------------------------------------------------------------- + SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0); + SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0); + + -- CONSTANTS + CONSTANT CFG_PADTECH : INTEGER := inferred; + CONSTANT NB_APB_SLAVE : INTEGER := 11; -- 3 = grspw + waveform picker + time manager, 11 allows pindex = f + CONSTANT NB_AHB_SLAVE : INTEGER := 1; + CONSTANT NB_AHB_MASTER : INTEGER := 2; -- 2 = grspw + waveform picker + + SIGNAL apbi_ext : apb_slv_in_type; + SIGNAL apbo_ext : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5) := (OTHERS => apb_none); + SIGNAL ahbi_s_ext : ahb_slv_in_type; + SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3) := (OTHERS => ahbs_none); + SIGNAL ahbi_m_ext : AHB_Mst_In_Type; + SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1) := (OTHERS => ahbm_none); + +-- Spacewire signals + SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0); + SIGNAL stmp : STD_LOGIC_VECTOR(1 DOWNTO 0); + SIGNAL spw_rxclk : STD_LOGIC_VECTOR(1 DOWNTO 0); + SIGNAL spw_rxtxclk : STD_ULOGIC; + SIGNAL spw_rxclkn : STD_ULOGIC; + SIGNAL spw_clk : STD_LOGIC; + SIGNAL swni : grspw_in_type; + SIGNAL swno : grspw_out_type; + +--GPIO + SIGNAL gpioi : gpio_in_type; + SIGNAL gpioo : gpio_out_type; + +-- AD Converter ADS7886 + SIGNAL sample : Samples14v(8 DOWNTO 0); + SIGNAL sample_s : Samples(8 DOWNTO 0); + SIGNAL sample_val : STD_LOGIC; + SIGNAL ADC_OEB_bar_CH_s : STD_LOGIC_VECTOR(8 DOWNTO 0); + + ----------------------------------------------------------------------------- + SIGNAL observation_reg : STD_LOGIC_VECTOR(31 DOWNTO 0); + + ----------------------------------------------------------------------------- + SIGNAL rstn : STD_LOGIC; + + SIGNAL LFR_soft_rstn : STD_LOGIC; + SIGNAL LFR_rstn : STD_LOGIC; + + SIGNAL ADC_smpclk_s : STD_LOGIC; + + SIGNAL nSRAM_CE : STD_LOGIC_VECTOR(1 DOWNTO 0); + +BEGIN -- beh + + ----------------------------------------------------------------------------- + -- CLK + ----------------------------------------------------------------------------- + rst0 : rstgen PORT MAP (reset, clk_25, '1', rstn, OPEN); + + PROCESS(clk50MHz) + BEGIN + IF clk50MHz'EVENT AND clk50MHz = '1' THEN + clk_25 <= NOT clk_25; + END IF; + END PROCESS; + + PROCESS(clk49_152MHz) + BEGIN + IF clk49_152MHz'EVENT AND clk49_152MHz = '1' THEN + clk_24 <= NOT clk_24; + END IF; + END PROCESS; + + ----------------------------------------------------------------------------- + -- + leon3_soc_1 : leon3_soc + GENERIC MAP ( + fabtech => apa3e, + memtech => apa3e, + padtech => inferred, + clktech => inferred, + disas => 0, + dbguart => 0, + pclow => 2, + clk_freq => 25000, + IS_RADHARD => 0, + NB_CPU => 1, + ENABLE_FPU => 1, + FPU_NETLIST => 0, + ENABLE_DSU => 1, + ENABLE_AHB_UART => 1, + ENABLE_APB_UART => 1, + ENABLE_IRQMP => 1, + ENABLE_GPT => 1, + NB_AHB_MASTER => NB_AHB_MASTER, + NB_AHB_SLAVE => NB_AHB_SLAVE, + NB_APB_SLAVE => NB_APB_SLAVE, + ADDRESS_SIZE => 19, + USES_IAP_MEMCTRLR => 1) + PORT MAP ( + clk => clk_25, + reset => rstn, + errorn => OPEN, + + ahbrxd => TAG1, + ahbtxd => TAG3, + urxd1 => TAG2, + utxd1 => TAG4, + + address => address, + data => data, + nSRAM_BE0 => OPEN, + nSRAM_BE1 => OPEN, + nSRAM_BE2 => OPEN, + nSRAM_BE3 => OPEN, + nSRAM_WE => nSRAM_W, + nSRAM_CE => nSRAM_CE, + nSRAM_OE => nSRAM_G, + nSRAM_READY => nSRAM_BUSY, + SRAM_MBE => nSRAM_MBE, + + apbi_ext => apbi_ext, + apbo_ext => apbo_ext, + ahbi_s_ext => ahbi_s_ext, + ahbo_s_ext => ahbo_s_ext, + ahbi_m_ext => ahbi_m_ext, + ahbo_m_ext => ahbo_m_ext); + + + nSRAM_E1 <= nSRAM_CE(0); + nSRAM_E2 <= nSRAM_CE(1); + +------------------------------------------------------------------------------- +-- APB_LFR_TIME_MANAGEMENT ---------------------------------------------------- +------------------------------------------------------------------------------- + apb_lfr_management_1 : apb_lfr_management + GENERIC MAP ( + tech => apa3e, + pindex => 6, + paddr => 6, + pmask => 16#fff#, + FIRST_DIVISION => 374, -- ((49.152/2) /2^16) - 1 = 375 - 1 = 374 + NB_SECOND_DESYNC => 60) -- 60 secondes of desynchronization before CoarseTime's MSB is Set + PORT MAP ( + clk25MHz => clk_25, + clk24_576MHz => clk_24, -- 49.152MHz/2 + resetn => rstn, + grspw_tick => swno.tickout, + apbi => apbi_ext, + apbo => apbo_ext(6), + + HK_sample => sample_s(8), + HK_val => sample_val, + HK_sel => HK_SEL, + + DAC_SDO => DAC_SDO, + DAC_SCK => DAC_SCK, + DAC_SYNC => DAC_SYNC, + DAC_CAL_EN => DAC_CAL_EN, + + coarse_time => coarse_time, + fine_time => fine_time, + LFR_soft_rstn => LFR_soft_rstn + ); + +----------------------------------------------------------------------- +--- SpaceWire -------------------------------------------------------- +----------------------------------------------------------------------- + + ------------------------------------------------------------------------------ + -- \/\/\/\/ TODO : spacewire enable should be controled by the SPW IP \/\/\/\/ + ------------------------------------------------------------------------------ + spw1_en <= '1'; + spw2_en <= '1'; + ------------------------------------------------------------------------------ + -- /\/\/\/\ --------------------------------------------------------- /\/\/\/\ + ------------------------------------------------------------------------------ + + spw_clk <= clk50MHz; + spw_rxtxclk <= spw_clk; + spw_rxclkn <= NOT spw_rxtxclk; + + -- PADS for SPW1 + spw1_rxd_pad : inpad GENERIC MAP (tech => inferred) + PORT MAP (spw1_din, dtmp(0)); + spw1_rxs_pad : inpad GENERIC MAP (tech => inferred) + PORT MAP (spw1_sin, stmp(0)); + spw1_txd_pad : outpad GENERIC MAP (tech => inferred) + PORT MAP (spw1_dout, swno.d(0)); + spw1_txs_pad : outpad GENERIC MAP (tech => inferred) + PORT MAP (spw1_sout, swno.s(0)); + -- PADS FOR SPW2 + spw2_rxd_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\ + PORT MAP (spw2_din, dtmp(1)); + spw2_rxs_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\ + PORT MAP (spw2_sin, stmp(1)); + spw2_txd_pad : outpad GENERIC MAP (tech => inferred) + PORT MAP (spw2_dout, swno.d(1)); + spw2_txs_pad : outpad GENERIC MAP (tech => inferred) + PORT MAP (spw2_sout, swno.s(1)); + + -- GRSPW PHY + --spw1_input: if CFG_SPW_GRSPW = 1 generate + spw_inputloop : FOR j IN 0 TO 1 GENERATE + spw_phy0 : grspw_phy + GENERIC MAP( + tech => apa3e, + rxclkbuftype => 1, + scantest => 0) + PORT MAP( + rxrst => swno.rxrst, + di => dtmp(j), + si => stmp(j), + rxclko => spw_rxclk(j), + do => swni.d(j), + ndo => swni.nd(j*5+4 DOWNTO j*5), + dconnect => swni.dconnect(j*2+1 DOWNTO j*2)); + END GENERATE spw_inputloop; + + -- SPW core + sw0 : grspwm GENERIC MAP( + tech => apa3e, + hindex => 1, + pindex => 5, + paddr => 5, + pirq => 11, + sysfreq => 25000, -- CPU_FREQ + rmap => 1, + rmapcrc => 1, + fifosize1 => 16, + fifosize2 => 16, + rxclkbuftype => 1, + rxunaligned => 0, + rmapbufs => 4, + ft => 0, + netlist => 0, + ports => 2, + --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1 + memtech => apa3e, + destkey => 2, + spwcore => 1 + --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1 + --output_type => CFG_SPW_OUTPUT, -- not used byt the spw core 1 + --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1 + ) + PORT MAP(rstn, clk_25, spw_rxclk(0), + spw_rxclk(1), spw_rxtxclk, spw_rxtxclk, + ahbi_m_ext, ahbo_m_ext(1), apbi_ext, apbo_ext(5), + swni, swno); + + swni.tickin <= '0'; + swni.rmapen <= '1'; + swni.clkdiv10 <= "00000100"; -- 10 MHz / (4 + 1) = 10 MHz + swni.tickinraw <= '0'; + swni.timein <= (OTHERS => '0'); + swni.dcrstval <= (OTHERS => '0'); + swni.timerrstval <= (OTHERS => '0'); + +------------------------------------------------------------------------------- +-- LFR ------------------------------------------------------------------------ +------------------------------------------------------------------------------- + LFR_rstn <= LFR_soft_rstn AND rstn; + + lpp_lfr_1 : lpp_lfr + GENERIC MAP ( + Mem_use => use_RAM, + nb_data_by_buffer_size => 32, + --nb_word_by_buffer_size => 30, + nb_snapshot_param_size => 32, + delta_vector_size => 32, + delta_vector_size_f0_2 => 7, -- log2(96) + pindex => 15, + paddr => 15, + pmask => 16#fff#, + pirq_ms => 6, + pirq_wfp => 14, + hindex => 2, + top_lfr_version => X"02013F") -- aa.bb.cc version + -- AA : BOARD NUMBER + -- 0 => MINI_LFR + -- 1 => EM + -- 1 => EQM (with A3PE3000) + PORT MAP ( + clk => clk_25, + rstn => LFR_rstn, + sample_B => sample_s(2 DOWNTO 0), + sample_E => sample_s(7 DOWNTO 3), + sample_val => sample_val, + apbi => apbi_ext, + apbo => apbo_ext(15), + ahbi => ahbi_m_ext, + ahbo => ahbo_m_ext(2), + coarse_time => coarse_time, + fine_time => fine_time, + data_shaping_BW => bias_fail_sw, + debug_vector => OPEN, + debug_vector_ms => OPEN); --, + --observation_vector_0 => OPEN, + --observation_vector_1 => OPEN, + --observation_reg => observation_reg); + + + all_sample : FOR I IN 7 DOWNTO 0 GENERATE + sample_s(I) <= sample(I) & '0' & '0'; + END GENERATE all_sample; + sample_s(8) <= sample(8)(13) & sample(8)(13) & sample(8); + + ----------------------------------------------------------------------------- + -- + ----------------------------------------------------------------------------- + top_ad_conv_RHF1401_withFilter_1 : top_ad_conv_RHF1401_withFilter + GENERIC MAP ( + ChanelCount => 9, + ncycle_cnv_high => 13, + ncycle_cnv => 25, + FILTER_ENABLED => 16#FF#) + PORT MAP ( + cnv_clk => clk_24, + cnv_rstn => rstn, + cnv => ADC_smpclk_s, + clk => clk_25, + rstn => rstn, + ADC_data => ADC_data, + ADC_nOE => ADC_OEB_bar_CH_s, + sample => sample, + sample_val => sample_val); + + ADC_OEB_bar_CH <= ADC_OEB_bar_CH_s(7 DOWNTO 0); + + ADC_smpclk <= ADC_smpclk_s; + HK_smpclk <= ADC_smpclk_s; + + TAG8 <= ADC_smpclk_s; + + ----------------------------------------------------------------------------- + -- HK + ----------------------------------------------------------------------------- + ADC_OEB_bar_HK <= ADC_OEB_bar_CH_s(8); + +END beh; diff --git a/designs/LFR-EQM-WFP_MS/Makefile b/designs/LFR-EQM-WFP_MS/Makefile new file mode 100644 --- /dev/null +++ b/designs/LFR-EQM-WFP_MS/Makefile @@ -0,0 +1,54 @@ +#GRLIB=../.. +VHDLIB=../.. +SCRIPTSDIR=$(VHDLIB)/scripts/ +GRLIB := $(shell sh $(VHDLIB)/scripts/lpp_relpath.sh) +TOP=LFR_EQM +BOARD=LFR-EQM +include $(VHDLIB)/boards/$(BOARD)/Makefile.inc +DEVICE=$(PART)-$(PACKAGE)$(SPEED) +UCF=$(GRLIB)/boards/$(BOARD)/$(TOP).ucf +QSF=$(GRLIB)/boards/$(BOARD)/$(TOP).qsf +EFFORT=high +XSTOPT= +SYNPOPT="set_option -pipe 0; set_option -retiming 0; set_option -write_apr_constraint 0" +#VHDLSYNFILES=config.vhd ahbrom.vhd leon3mp.vhd +#VHDLSYNFILES=config.vhd leon3mp.vhd +VHDLSYNFILES=LFR-EQM.vhd +VHDLSIMFILES=testbench.vhd +#SIMTOP=testbench +PDC=$(VHDLIB)/boards/$(BOARD)/LFR_EQM_A3PE3000.pdc +SDC=$(VHDLIB)/boards/$(BOARD)/LFR_EQM.sdc + +BITGEN=$(VHDLIB)/boards/$(BOARD)/default.ut +CLEAN=soft-clean + +TECHLIBS = proasic3e + +LIBSKIP = core1553bbc core1553brm core1553brt gr1553 corePCIF \ + tmtc openchip hynix ihp gleichmann micron usbhc + +DIRSKIP = b1553 pcif leon2 leon2ft crypto satcan ddr usb ata i2c \ + pci grusbhc haps slink ascs pwm coremp7 spi ac97 \ + ./amba_lcd_16x2_ctrlr \ + ./general_purpose/lpp_AMR \ + ./general_purpose/lpp_balise \ + ./general_purpose/lpp_delay \ + ./lpp_bootloader \ + ./dsp/lpp_fft_rtax \ + ./lpp_uart \ + ./lpp_usb \ + ./lpp_sim/CY7C1061DV33 \ + +FILESKIP = i2cmst.vhd \ + APB_MULTI_DIODE.vhd \ + APB_MULTI_DIODE.vhd \ + Top_MatrixSpec.vhd \ + APB_FFT.vhd\ + CoreFFT_simu.vhd \ + lpp_lfr_apbreg_simu.vhd + +include $(GRLIB)/bin/Makefile +include $(GRLIB)/software/leon3/Makefile + +################## project specific targets ########################## +